JP6942549B2 - Power supply and image forming equipment - Google Patents

Description

The present invention relates to a power supply device and an image forming device, and more particularly to a power supply device having a digital control unit that operates with a clock signal.

In a switching power supply device that converts an AC voltage input from a commercial power supply or the like into a DC voltage, it is required to improve the efficiency of the switching power supply device in order to reduce power consumption. In particular, an image forming apparatus such as a laser beam printer (LBP) has a wide load range during use from a heavy load to a light load. Therefore, the switching power supply device mounted on the image forming device is required to have power supply efficiency in a wide load range. For example, Patent Document 1 proposes a method of utilizing digital control by a microprocessor in a switching power supply device that is efficient in a wide load range from a heavy load to a light load. Here, the efficiency of the switching power supply device is expressed by the ratio of the power supplied to the switching power supply device and the power output by the switching power supply device.

JP-A-2017-017846

However, the control unit of the switching power supply may be affected by noise. For example, if the operation of the control unit is stopped due to noise and the switching element is held in the ON state, an overcurrent may flow and the overcurrent protection circuit may operate. As a result, when the output of the switching power supply device is stopped and the power supply to the load is stopped, the operation of the load is stopped and the usability is deteriorated.

The present invention has been made under such circumstances, and an object of the present invention is to protect the circuit from overcurrent even when the operation of the control unit is stopped, and not to stop the output of the power supply voltage to the load.

In order to solve the above-mentioned problems, the present invention includes the following configurations.

(1) A transformer having a primary winding and a secondary winding, a first switching element connected in series with the primary winding of the transformer, and a first switching element connected in parallel with the primary winding of the transformer. A second switching element, a capacitor connected in series with the second switching element and connected in parallel with the first winding of the transformer together with the second switching element, and the secondary winding of the transformer. Based on the feedback means that outputs information according to the induced voltage and the information input from the feedback means, the first control signal controls the on or off of the first switching element, and the second The control means includes a control means for controlling the on / off of the second switching element by the control signal of the above, and the control means sandwiches a dead time for turning off both the first switching element and the second switching element. A power supply device that performs a switching operation in which the first switching element and the second switching element are alternately turned on or off, and the first current detecting means for detecting the current flowing through the first switching element. When an overcurrent is detected based on the detection result of the first current detecting means, the first holding means that turns off the first switching element and holds the first switching element in the off state. The first holding means is characterized in that the off state of the first switching element is released at the timing when the control means turns on the second switching element by the second control signal. Power supply.

(2) A transformer having a primary winding and a secondary winding, a first switching element connected in series with the primary winding of the transformer, and a first switching element connected in parallel with the primary winding of the transformer. A second switching element, a capacitor connected in series with the second switching element and connected in parallel with the first winding of the transformer together with the second switching element, and the secondary winding of the transformer. Based on the feedback means that outputs information according to the induced voltage and the information input from the feedback means, the first control signal controls the on or off of the first switching element, and the second The control means includes a control means for controlling the on / off of the second switching element by the control signal of the above, and the control means sandwiches a dead time for turning off both the first switching element and the second switching element. A power supply device that performs a switching operation in which the first switching element and the second switching element are alternately turned on or off, and the control means outputs a state signal indicating the state of the control means, and the control means outputs a state signal indicating the state of the control means. Based on the state signal output by the control means, the detection means for detecting the operation stop of the control means, and when the detection means detects the operation stop of the control means, the first switching element is turned off and the first switching element is turned off. The holding means includes a holding means for holding the first switching element in an off state, and the holding means is said to be the first when the state signal is switched from a state in which the operation of the control means is stopped to a state in which the control means indicates a normal operation. A power supply device characterized by releasing the off state of a switching element.

(3) A transformer having a primary winding and a secondary winding, a first switching element connected in series with the primary winding of the transformer, and a first switching element connected in parallel with the primary winding of the transformer. A second switching element, a capacitor connected in series with the second switching element and connected in parallel with the first winding of the transformer together with the second switching element, and the secondary winding of the transformer. Based on the feedback means that outputs information according to the induced voltage and the information input from the feedback means, the first control signal controls the on or off of the first switching element, and the second The control means includes a control means for controlling the on / off of the second switching element by the control signal of the above, and the control means sandwiches a dead time for turning off both the first switching element and the second switching element. A power supply device that performs a switching operation in which the first switching element and the second switching element are alternately turned on or off, and a current detecting means for detecting a current flowing through the first switching element, and the current. When an overcurrent is detected based on the detection result of the detection means, the control means includes a holding means for turning off the first switching element and holding the first switching element in the off state, and the control means is a clock signal. When the clock signal is output, a state signal indicating a normal operation state is output, and when the clock signal is stopped, the state signal indicating an operation stop state is output. The holding means is a power supply device characterized in that when the state signal is switched from the stopped state of the control means to the normal operation state, the off state of the first switching element is released.

(4) A transformer having a primary winding and a secondary winding, a switching element connected in series with the primary winding of the transformer, and a snubber circuit connected in parallel with the primary winding of the transformer. The on / off of the switching element is controlled by a control signal based on the feedback means that outputs information according to the voltage induced in the secondary winding of the transformer and the information input from the feedback means. A power supply device including a control means for controlling, which turns off the switching element when an overcurrent is detected based on the detection result of the current detecting means for detecting the current flowing through the switching element and the detection result of the current detecting means. The control means operates by a clock signal, and outputs a state signal indicating a normal operation state when the clock signal is output. Then, when the clock signal is stopped, the state signal indicating the state of operation stop is output, and the holding means changes the state signal from the state of stop of operation of the control means to the state of normal operation. A power supply device characterized by releasing the off state of a switching element.

(5) An image forming apparatus comprising: an image forming means for forming an image on a recording material, and a power supply device according to any one of (1) to (4).

According to the present invention, the circuit can be protected from overcurrent even when the operation of the control unit is stopped, and the output of the power supply voltage to the load can not be stopped.

Schematic diagram of the power supply circuit of the first embodiment Schematic diagram showing the configuration of the control unit of the first embodiment Schematic diagram showing the configuration of the control unit of the first embodiment Explanatory drawing of control method of Example 1 A simple circuit diagram for explaining the control method of the first embodiment. Schematic diagram of the power supply circuit of the second embodiment Schematic diagram showing the configuration of the control unit of the second embodiment Explanatory drawing of control method of Example 2 Schematic diagram of the power supply circuit of the first embodiment and the second embodiment The figure which shows the image forming apparatus of Example 3.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Power supply configuration]
FIG. 1 is a circuit diagram showing an outline of a switching power supply circuit using the active clamp method of the first embodiment. The AC power supply 10 such as a commercial power supply outputs an AC voltage, and the voltage rectified by the bridge diode BD1 which is a full-wave rectifying means is input to the switching power supply circuit 100. The smoothing capacitor C3 is used as a means for smoothing the rectified voltage, and the potential on the low side of the smoothing capacitor C3 is the potential DCL, and the potential on the high side is the potential DCH. The switching power supply circuit 100 outputs a power supply voltage V11 (also referred to as an output voltage V11) from the input voltage Vin charged in the smoothing capacitor C3 to the insulated secondary side. In this embodiment, the switching power supply circuit 100 outputs a constant voltage of, for example, 5V as an example of the power supply voltage V11.

The switching power supply circuit 100 has an insulated transformer T1 having a primary winding P1 and an auxiliary winding P2 on the primary side and a secondary winding S1 on the secondary side. Energy is supplied to the primary winding P1 to the secondary winding S1 of the transformer T1 by the switching operation described later with reference to FIG. 4 (A). The auxiliary winding P2 of the transformer T1 is used to rectify and smooth the forward voltage of the input voltage Vin applied to the primary winding P1 by the diode D4 and the capacitor C4 to supply the power supply voltage V1.

On the primary side of the switching power supply circuit 100, a field effect transistor (hereinafter referred to as FET) FET1, which is a first switching element, is connected in series to the primary winding P1 of the transformer T1. The capacitor C2 for voltage clamping and the FET 2 which is the second switching element are connected in series. The voltage clamp capacitors C2 and FET2 connected in series are connected in parallel to the primary winding P1 of the transformer T1. On the primary side of the switching power supply circuit 100, a control unit 101 and an FET drive unit 102 are provided as control means for the FET 1 and the FET 2. The voltage resonance capacitor C1 connected in parallel with the FET 1 is provided in order to reduce the loss when the FET 1 and the FET 2 are switched off. The capacitance between the drain terminal and the source terminal of the FET 1 may be used without providing the capacitor C1 for voltage resonance. In order to facilitate the operation of turning on the switching element at zero voltage, which will be described later, the capacitor C1 for voltage resonance is selected to have a smaller capacitance than the capacitor C2 for voltage clamping. The diode D1 of this embodiment is a body diode of FET1. Similarly, the diode D2 is the body diode of the FET 2.

On the secondary side of the switching power supply circuit 100, a diode D11 and a capacitor C11, which are rectifying and smoothing means on the secondary side of the flyback voltage generated in the secondary winding S1 of the transformer T1, are provided. The voltage induced in the secondary winding S1 of the transformer T1 is rectified and smoothed by the diode D11 and the capacitor C11, and is output as the power supply voltage V11. Further, the secondary side of the switching power supply circuit 100 has a feedback unit 115 as a feedback means for feeding back information according to the power supply voltage V11 output to the secondary side to the primary side (dotted line in the figure). Frame part). The control unit 101 of this embodiment uses arithmetic control elements such as a CPU and an ASIC that operate with a clock signal generated by an oscillator or the like. Details of the control unit 101 will be described with reference to FIG. As a result, complicated waveform control of the control signal DRV1 (first control signal) and the control signal DRV2 (second control signal) can be realized with a simple and inexpensive circuit configuration.

The power supply voltage V2 generated by the DC / DC converter 104 is supplied from the OUT terminal of the DC / DC converter 104 between the VC terminal and the G terminal of the control unit 101. The control unit 101 outputs the control signal DRV1 and the control signal DRV2 based on the voltage signal input from the feedback unit 115 to the FB terminal, and controls the FET1 and the FET2 via the FET drive unit 102. Here, the control signal DRV1 is a signal for driving the FET1, and the control signal DRV2 is a signal for driving the FET2.

The FET drive unit 102 is a circuit that generates a gate drive signal DL of the FET 1 in response to the control signal DRV1 input from the control unit 101, and generates a gate drive signal DH of the FET 2 in response to the control signal DRV2. The power supply voltage V1 generated by the auxiliary winding P2 is supplied between the VC terminal and the G terminal of the FET drive unit 102. Further, in order to drive the FET 2, a power supply voltage V1 is supplied between the VH terminal and the GH terminal by a charge pump circuit composed of a capacitor C5 and a diode D5. When the high level control signal DRV1 is input, the FET drive unit 102 sets the gate drive signal DL of the FET 1 to a high level, whereby the FET 1 is turned on. Similarly, when the high-level control signal DRV2 is input, the FET drive unit 102 sets the gate drive signal DH of the FET 2 to a high level, whereby the FET 2 is turned on.

The DC / DC converter 104 is a 3-terminal regulator or a step-down switching power supply circuit, which converts the power supply voltage V1 input between the VC terminal and the G terminal and outputs the power supply voltage V2 from the OUT terminal. The start-up circuit 103 is a 3-terminal regulator or a step-down switching power supply, converts the input voltage Vin input between the VC terminal and the G terminal, and outputs the power supply voltage V1 from the OUT terminal. The start circuit 103 is a circuit that operates only when the power supply voltage V1 supplied from the auxiliary winding P2 is equal to or lower than a predetermined voltage value, and is used to supply the power supply voltage V1 when the switching power supply circuit 100 is started.

[Feedback section]
The feedback unit 115 is used to control the power supply voltage V11 to a predetermined constant voltage. The voltage value of the power supply voltage V11 is set by the reference voltage of the reference terminal REF of the shunt regulator IC5, the resistor R52, and the resistor R53. When the power supply voltage V11 becomes higher than a predetermined voltage (5V in this case), a current flows from the cathode terminal K of the shunt regulator IC5, and the secondary diode of the photocoupler PC5 becomes conductive via the pull-up resistor R51. As a result, the primary phototransistor of the photocoupler PC5 operates to discharge the electric charge from the capacitor C6. Therefore, the voltage of the FB terminal of the control unit 101 (hereinafter referred to as the FB terminal voltage) drops. On the other hand, when the power supply voltage V11 becomes lower than 5V, the secondary diode becomes non-conducting. As a result, the primary phototransistor of the photocoupler PC5 is turned off, and a current for charging the capacitor C6 flows from the power supply voltage V2 via the resistor R2. Therefore, the FB terminal voltage of the control unit 101 rises. In this way, the feedback unit 115 changes the FB terminal voltage of the control unit 101 according to the fluctuation of the power supply voltage V11.

The control unit 101 detects the FB terminal voltage input from the feedback unit 115 to perform feedback control for controlling the power supply voltage V11 to a predetermined constant voltage. In this way, the control unit 101 can indirectly feedback-control the power supply voltage V11 by monitoring the FB terminal voltage.

[Structure of control unit 101]
FIG. 2A is a block diagram showing an internal configuration of the control unit 101. The control unit 101 is a one-chip microcomputer including a clock oscillation unit 131, a PWM output unit 133, an arithmetic control unit 136, a storage unit 137, a storage unit 138, and an AD conversion unit 139, which are generation units. The storage unit 137 is a RAM, and the storage unit 138 is composed of a ROM and a flash memory (FLASH). The calculation control unit 136 operates based on the clock signal of the clock oscillation unit 131, and is a control unit that reads the instructions and data stored in the storage unit 138 into the storage unit 137 and then performs sequential calculations. The arithmetic control unit 136 controls the set values (control start timing, cycle, duty) of the two control signals DRV1 and DRV2 of the PWM output unit 133 based on the AD_FB signal input from the FB terminal detected by the AD conversion unit 139. do. Thereby, on / off control of FET1 and FET2 is performed.

By the way, as an example of the above-mentioned malfunction state of the control unit 101, the operation of the clock oscillation unit 131 is stopped due to external noise or the like, so that the clock signal is not output, and as a result, the processing of the arithmetic control unit 136 is stopped. (It may not be possible to continue). The clock oscillation unit 131 of the control unit 101 of FIG. 2A has a function of automatically recovering after a lapse of a predetermined time even if the output of the clock signal is stopped due to noise or the like. Therefore, after the clock signal is stopped and the processing of the arithmetic control unit 136 is stopped (cannot be continued), the clock oscillating unit 131 reoscillates and the clock signal is output, so that the arithmetic control unit 136 is output. Can resume the stopped processing.

FIG. 2B shows a control unit including a clock recovery unit 141, which is a detection unit that monitors the clock signal output by the clock oscillation unit 131 internally and outputs a recovery signal when it detects that the clock signal has stopped. It is a block diagram which shows the internal structure of 107. When the return signal is input, the clock oscillation unit 131 reoscillates and outputs the clock signal. Further, FIG. 2C includes an external monitoring unit 142 which is a detection unit that monitors the clock signal output by the clock oscillation unit 131 to the outside and outputs a return signal when the clock signal is detected to have stopped. It is a block diagram which shows the internal structure of the control part 108. When the return signal is input, the clock oscillation unit 131 reoscillates and outputs the clock signal. As described above, instead of the control unit 101, a configuration such as the control unit 107 shown in FIG. 2B or the control unit 108 shown in FIG. 2C may be used.

[Current detector]
The current detection unit 120 surrounded by the alternate long and short dash line will be described with reference to FIG. 1 (A). The current detection unit 120 includes an overcurrent detection circuit for instantaneous current (hereinafter referred to as OCP circuit) and an overcurrent detection circuit for average current (hereinafter referred to as OLP circuit). The OCP circuit, which is the first current detecting means, is composed of the comparator IC1 and the voltage dividing resistors R22 and R23, and the output terminal of the comparator IC1 is connected to the latch portion 105, which is the first holding means. On the other hand, the OLP circuit, which is the second current detecting means, is composed of an average current detecting unit 119 for detecting the average current value, a comparator IC2, and voltage dividing resistors R24 and R25, and the output terminal of the comparator IC2 is held in the second position. It is connected to the latch portion 106 which is a means.

FIG. 1B is a circuit diagram showing the internal configuration of the latch portion 105. The latch portion 105 is composed of a PNP type transistor Tr1, an NPN type transistor Tr2, a Tr3 (hereinafter, simply referred to as transistors Tr1, Tr2, Tr3), a capacitor Cr1, a diode D23, a resistor and the like. FIG. 1C is a circuit diagram showing the internal configuration of the latch portion 106, wherein the latch portion 106 includes a PNP type transistor Tr4, an NPN type transistor Tr5 (hereinafter, simply referred to as transistors Tr4 and Tr5), a capacitor Cr2, and a diode D24. It is composed of resistors and the like. The circuit configurations of the OCP circuit and the OLP circuit shown in FIG. 1 (A) and the latch portions 105 and 106 shown in FIGS. 1 (B) and 1 (C) are examples, and the present invention is limited to these circuit configurations. However, a configuration using other elements may be used. Further, instead of the control unit 101 shown in FIG. 2 (A), the current detection unit 120 shown in FIG. 1 (A) is provided inside the control unit 109, for example, as in the control unit 109 shown in FIG. May be good. Then, the current detection unit 120 may be configured to stop the output of the control signal DRV1 and the control signal DRV2 output from the PWM output unit 133 according to the current Ip flowing through the current detection resistor R21.

[Control method of switching power supply circuit]
FIG. 4 is an explanatory diagram of a control method of the switching power supply circuit 100 using the active clamp method by the control unit 101. In FIG. 4, (i) shows the waveform of the control signal DRV1 corresponding to the gate drive signal DL of the FET 1, and (ii) shows the waveform of the control signal DRV2 corresponding to the gate drive signal DH of the FET 2. Further, in FIG. 4, (iii) shows the waveform of the drain current of the FET 1, (iv) shows the waveform of the voltage between the drain terminal and the source terminal of the FET 1, and (v) shows the clock signal of the clock oscillator 131. The waveform is shown. FIG. 4B shows the waveform of the latch voltage Vr1, which is the charging potential of the capacitor Cr1 of the latch portion 105, which will be described later. The horizontal axis indicates time. FIG. 5 shows the current flow during a plurality of periods ([1] to [3]) shown in FIG. 4 together with a simple circuit diagram. The operation of each period will be described below. In FIG. 5, the transformer T1 is divided into a leakage inductance Lr, a coupling inductance Ls, and an ideal transformer Ti. Further, in the circuit of FIG. 5, the currents flowing in each of the periods [1] to [3] are indicated by dark solid arrows.

[Switching period]
First, a normal switching operation will be described with reference to FIG. 4 (A). As shown in (v) of FIG. 4A, the clock signal continues to be output when the clock oscillator 131 inside the control unit 101 is operating normally. The switching period is a period in which the control unit 101 repeatedly controls the FET 1 and the FET 2 by alternately turning them on and off with a dead time for turning off the FET 1 and the FET 2 together. The operation using the FET 2 and the capacitor C2 for voltage clamping during the switching period (hereinafter referred to as active clamping operation) will be described with reference to FIGS. 4 (A) and 5 [1] to [3].

While the FET 1 is in the ON state, a current flows through the leakage inductance Lr and the coupling inductance Ls of the transformer T1 (see FIGS. 4 (A) and 4 (iii)). The period [1] shown in FIG. 5 is a period in which the FET 1 is turned on for the time TL1 and then turned off, and the FET 2 is turned on after the dead time. The current flowing while the FET 1 is on causes the transformer T1 to charge the + terminal side of the voltage clamping capacitor C2 via the FET 2 or the diode D2. Since the kickback voltage due to the leakage inductance Lr can be absorbed by the capacitor C2 for voltage clamping, the surge voltage applied between the drain terminal and the source terminal of the FET 1 can be suppressed. When the voltage of the voltage clamping capacitor C2 rises, the diode D11 is turned on, and power is supplied to the secondary side of the switching power supply circuit 100 via the secondary winding S1 of the transformer T1.

In the period of [2] shown in FIG. 5, a current flows from the + terminal side of the capacitor C2 to the transformer T1 via the FET 2 due to resonance between the capacitor C2 for voltage clamping and the leakage inductance Lr and the coupling inductance Ls of the transformer T1. It will be in a flowing state. When the voltage of the voltage clamping capacitor C2 drops, the diode D11 on the secondary side becomes non-conducting, and power is not supplied to the secondary side of the switching power supply circuit 100. Further, by maintaining the conduction state of the FET 2, the current flowing from the voltage clamping capacitor C2 to the leakage inductance Lr and the coupling inductance Ls of the transformer T1 increases.

The period [3] shown in FIG. 5 is a dead time period in which both FET 1 and FET 2 are in the off state. In the period of [3] of FIG. 5, by turning off the FET 2, the capacitance of the capacitor connected to the primary winding P1 of the transformer T1 is the combined capacitance of the capacitor C2 for voltage clamping and the capacitor C1 for voltage resonance. From the value of, it decreases to the capacitance of the capacitor C1 for voltage resonance. Therefore, the electric charge charged in the voltage resonance capacitor C1 can be regenerated into the smoothing capacitor C3 by the current flowing through the leakage inductance Lr and the coupling inductance Ls of the transformer T1. When the above-described regeneration operation is completed, the diode D1 is in a conductive state. When the period of [3] shown in FIG. 5 is completed and the diode D1 is conducting, the FET 1 is turned on, so that the FET 1 performs a switching operation of shifting from the off state to the on state in the zero volt state. Can be done. The switching operation in which the FET 1 shifts from the off state to the on state in the zero volt state is hereinafter referred to as zero volt switching. The operation from when the FET 2 is turned on to when the operation of regeneration to the smoothing capacitor C3 is completed is called an active clamp operation. FET1 is then turned on for time TL2.

As described above, the surge voltage of the FET 1 can be suppressed by the action of the voltage clamping capacitors C2 and the FET 2 in the active clamping operation described in FIGS. 4 (A) and 5 [1] to [3]. Further, the electric charge of the voltage resonance capacitor C1 can be regenerated into the smoothing capacitor C3, and the FET 1 can be zero-volt switched. Therefore, by using the active clamp method, the efficiency of the switching power supply circuit 100 can be improved during the switching period shown in FIG. 4 (A).

[Operation of OLP circuit]
Next, the operation of the OLP circuit will be described with reference to FIG. 1 (A). The current flowing through the FET 1 is detected as an average current voltage Iav by the current detection resistor R21 and the average current detection unit 119, and is input to the − terminal of the comparator IC2. The comparator IC2 compares the reference voltage Iavo, which is set by the power supply voltage V2, the voltage dividing resistors R24, and R25, and is input to the + terminal, with the average current voltage Iav, which is the detection result of the average current detection unit 119. Then, when the average current voltage Iav is larger than the reference voltage Iavo, the comparator IC2 outputs a low level IavOff signal to the latch unit 106. The reference voltage Iavo is set to a value larger than the average current voltage Iav during normal operation so that the OLP circuit does not operate during normal operation. Therefore, during normal operation, the output terminal of the comparator IC2 is in a high impedance state (open collector).

Next, the operation of the latch portion 106 will be described. As shown in FIGS. 1A and 1C, the power supply voltage V2, the potential DCL, and the IavOff signal are input to the latch unit 106, and the DRVOff signal is output from the latch unit 106. During normal operation, the output terminal of the comparator IC2 is in a high impedance state, so that the base terminal voltage of the transistor Tr4 is at the same potential as the emitter terminal, and the transistor Tr4 is in an off state. As a result, the base-emitter voltage of the transistor Tr5 becomes lower than the threshold voltage at which the transistor Tr5 is turned on, so that the transistor Tr5 is turned off and the collector terminal of the transistor Tr5 is in a high impedance state. Therefore, the DRVOff signal is in a high impedance state.

At the time of abnormal operation such as a load short circuit, the value of the average current voltage Iav becomes larger than that of the reference voltage Iavo, and a low-level IavOff signal is output from the output terminal of the comparator IC2. Therefore, the base terminal voltage of the transistor Tr4 becomes low level, and the transistor Tr4 is turned on. Then, when the transistor Tr4 is turned on, the power supply voltage V2 is applied to the base terminals of the capacitor Cr2 and the transistor Tr5 via the transistor Tr4. When the power supply voltage V2 is charged to the capacitor Cr2, the base-emitter voltage of the transistor Tr5 continues to be higher than the threshold voltage due to the latch voltage Vr2 which is the charging potential of the capacitor Cr2, so that the transistor Tr5 is turned on. It becomes a state. As a result, the collector terminal of the transistor Tr5 becomes low level, and the DRVOff signal becomes low level.

The base terminal voltage of the transistor Tr4 is higher than the collector terminal voltage of the transistor Tr5 by the forward voltage Vf of the diode D24, and the base-emitter voltage of the transistor Tr4 is a voltage that can be sufficiently turned on by the transistor Tr4. Since the base-emitter voltage of the transistor Tr5 is kept higher than the threshold voltage due to the potential charged in the capacitor Cr2, the transistor Tr5 is kept in the on state and the DRVOff signal is also held at a low level. Therefore, the control signal DRV1 becomes a low level via the diode D22 regardless of whether the control signal DRV1 output from the control unit 101 has a high level or a low level. As a result, the gate drive signal DL of the FET 1 output from the FET drive unit 102 is forcibly lowered to a low level. Similarly, the control signal DRV2 also has a low level via the diode D20 regardless of whether the control signal DRV2 output from the control unit 101 has a high level or a low level. As a result, the gate drive signal DH of the FET 2 output from the FET drive unit 102 is forcibly lowered to a low level. By detecting the average current and stopping the switching power supply in this way, the switching power supply can be safely stopped even if a rare short circuit at the output end or an unrated load is drawn.

[Operation of OCP circuit]
Next, the operation of the OCP circuit will be described with reference to FIG. 1 (A). The current flowing through the FET 1 is converted into a detection voltage Ip by the current detection resistor R21 and input to the − terminal of the comparator IC1. The comparator IC1 divides the power supply voltage V2 by the voltage dividing resistors R22 and R23, compares the reference voltage Ipo input to the + terminal with the detection voltage Ip, and if the detection voltage Ip is larger than the reference voltage Ipo, it is low. The level IpOff signal is output to the latch unit 105. The reference voltage Ipo is set to a value larger than the detection voltage Ip in the normal operation so that the OCP circuit does not operate in the normal operation. Therefore, during normal operation, the output terminal of the comparator IC1 is in a high impedance state.

Next, the operation of the latch portion 105 will be described. As shown in FIGS. 1A and 1B, the power supply voltage V2, the potential DCL, the IpOff signal, and the control signal DRV2 are input to the latch portion 105, and the DRV1Off signal is output from the latch portion 105. Will be done. During normal operation, the output terminal of the comparator IC1 is in a high impedance state, so that the base terminal voltage of the transistor Tr1 is at the same potential as the emitter terminal, and the transistor Tr1 is in an off state. Therefore, since the base-emitter voltage of the transistor Tr2 is lower than the threshold voltage, the transistor Tr2 is turned off and the collector terminal of the transistor Tr2 is in a high impedance state. Therefore, the DRV1Off signal is in a high impedance state.

[Operation when the control unit 101 is abnormal]
Next, the operation of protecting the switching power supply circuit 100 in the event of a malfunction of the control unit 101, which is a feature of this embodiment, will be described in detail. When noise or the like is applied from the outside, the control unit 101 may malfunction and the PWM output of the PWM output unit 133 may be temporarily stopped. As an example of the case where the PWM output of the PWM output unit 133 is stopped, a malfunction state of the control unit 101 in which the clock signal output from the clock oscillation unit 131 is stopped will be described as an example. The details of the operation of the clock oscillator 131 when the clock signal is stopped are shown in FIG. 4 (B). When the clock signal is stopped, the control signal DRV1 and the control signal DRV2, which are PWM signals output from the PWM output unit 133, cannot be controlled, and the state of the control signal DRV1 and the control signal DRV2 at the time when the clock signal is stopped. Will be retained. (A) to (e) in FIG. 4 (B) show the timing (time). Hereinafter, the circuit operation at each timing will be described with reference to FIG. 4 (B).

(Timing a) Switching operation The timing (a) is the time when the control signal DRV2 is output at a high level and the control signal DRV1 is output at a low level from the control unit 101 (FIGS. 4B and 4i). (Ii)). At this time, the FET 1 is in the off state and the FET 2 is in the on state, and the switching operation is performed.

(Timing b) Clock signal stop The timing (b) indicates the time when the clock signal output from the clock oscillator 131 of the control unit 101 is stopped due to disturbance noise or the like (FIGS. 4B and 4v). .. When the clock signal is stopped, the arithmetic control unit 136 of the control unit 101 also stops its operation. As a result, the control signal DRV1 and the control signal DRV2 output from the PWM output unit 133 are held in the state at the time when the clock signal is stopped, that is, the control signal DRV1 is held at a high level and the control signal DRV2 is held at a low level. Therefore, when the PWM output of the PWM output unit 133 is held in the high level state of the control signal DRV1, the period of the high level state of the control signal DRV1 becomes long (FIGS. 4B and 4i), and during that time, The FET 1 continues to be kept on. As a result, the drain current of the FET 1 continues to flow (FIGS. 4 (B) and (iii)). As shown in FIG. 1A, the drain current of the FET 1 is current-voltage converted by the current detection resistor R21 and detected as the detection voltage Ip. Further, in the signal waveform of the control signal DRV1 of FIG. 4B (i), the broken line between the timing (b) and the timing (c) indicates that the control signal DRV1 has a high level unless the clock signal is stopped. It shows the timing of falling to the low level from.

(Timing c) Operation of OCP circuit Timing (c) indicates the time point at which the above-mentioned OCP circuit operates. The operation of the OCP circuit and the latch portion 105 will be described with reference to FIGS. 1 (A) and 1 (B). When the detection voltage Ip becomes larger than the reference voltage Ipo due to the continuous flow of the drain current of the FET 1, a low-level IpOff signal is output from the output terminal of the comparator IC1. As a result, the base terminal voltage of the transistor Tr1 of the latch portion 105 becomes low level, and the transistor Tr1 is turned on. When the transistor Tr1 is turned on, the power supply voltage V2 is applied to the base terminals of the capacitor Cr1 and the transistor Tr2 via the transistor Tr1. Due to the potential charged in the capacitor Cr1, the base-emitter voltage of the transistor Tr2 becomes higher than the threshold voltage, so that the transistor Tr2 is turned on. As a result, the collector terminal of the transistor Tr2 becomes low level, and the DRV1Off signal becomes low level. The base terminal of the transistor Tr1 is higher than the collector terminal voltage of the transistor Tr2 by the forward voltage Vf of the diode D23, and the base-emitter voltage of the transistor Tr1 is a voltage that the transistor Tr1 can sufficiently turn on. Since the base-emitter voltage of the transistor Tr2 is held higher than the threshold voltage by the latch potential Vr1, which is the potential charged in the capacitor Cr1, the transistor Tr2 is held in the on state and the DRV1Off signal is also at a low level. It is held at.

Since the DRV1OFF signal has a low level, the control signal DRV1 output from the control unit 101 has a low level regardless of whether it has a high level or a low level, and the control signal DRV1 input to the FET drive unit 102 has a low level via the diode D21. .. As a result, the gate drive signal DL of the FET 1 output from the FET drive unit 102 is forcibly lowered to a low level. As a result, the FET 1 is turned off and the drain current does not flow (FIGS. 4B (iii)). This timing is the timing (c) shown in FIG. 4 (B).

As described above, after the control signal DRV1 is held at a low level by the OCP circuit and the latch portion 105, the FET1 is turned off, so that the drain current of the FET1 does not flow. Therefore, the detection voltage Ip detected by the current detection resistor R21 drops, and when the voltage drops below the reference voltage Ipo, the IpOff signal output from the output terminal of the comparator IC1 also changes from a low level to a high impedance state. In this way, even if the clock signal is stopped due to noise or the like, the FET 1 is turned off by the OCP circuit, so that the switching operation can be stopped without the FET 1 being destroyed by the overcurrent.

(Timing d) Clock signal re-oscillation The timing (d) indicates the time when the clock oscillating unit 131 automatically recovers and re-oscillates to output the clock signal after the disturbance noise or the like disappears. The recovery of the clock oscillator 131 may be the automatic recovery of FIG. 2A described above or the recovery by the recovery signals of FIGS. 2B and 2C. Since the operation of the control unit 101 is restarted from the state at the time when the clock signal is stopped (timing (b)), the control signal DRV1 is held in a high level state. However, even if the operation of the control unit 101 is restarted by the operation of the latch unit 105 of the OCP circuit described above (latch voltage Vr1 shown in FIGS. 4 (B) and 4 (vi)), the FET 1 is held in the off state. There is. As a result, it is possible to prevent the FET 1 from turning on at the time when the clock signal reoscillates (timing (d)) and entering a hard switching state. Since the operation of the control unit 101 is restarted from the state when the clock signal is stopped (timing (b)), the control signal DRV1 is set when a predetermined time elapses after the clock signal reoscillates. It becomes a low level. That is, when the time from the timing (b) to the timing at which the control signal DRV1 falls to the low level (broken line portion in FIGS. , Low level.

(Timing e) Release of the latch portion The timing (e) indicates the time when the latch state of the latch portion 105 is released. The circuit operation when the latch state is released will be described with reference to FIGS. 1 (A), 1 (B) and 4 (B). When a high-level control signal DRV2 is output from the control unit 101 (FIGS. 4B and 4ii) and input to the latch unit 105, the base-emitter voltage of the transistor Tr3 becomes higher than the threshold voltage. The transistor Tr3 is turned on. When the transistor Tr3 is turned on, the electric charge charged in the capacitor Cr1 is discharged via the transistor Tr3 (FIGS. 4 (B) and 4 (vi)). As a result, the base-emitter voltage of the transistor Tr2 becomes lower than the threshold voltage, and the transistor Tr2 is turned off. Further, the base terminal voltage of the transistor Tr1 becomes the same potential as the emitter terminal, and the transistor Tr1 is turned off. When the transistor Tr1 is turned off, the power supply voltage V2 is not supplied to the capacitor Cr1, so that the base-emitter voltage of the transistor Tr2 remains lower than the threshold voltage. As a result, the low level holding of the control signal DRV1 by the DRV1 Off signal of the latch portion 105 is released.

Here, the circuit operation for preventing the FET 1 from being destroyed by holding the FET 1 in the ON state by the OCP circuit when the clock signal is stopped when the control signal DRV1 is at a high level has been described. When the control signal DRV1 is at a low level, the FET1 is not turned on regardless of whether the control signal DRV2 is at a high level or a low level. Therefore, the description of the circuit operation here will be omitted. Further, in this embodiment, the timing (d) at which the operation of the control unit 101 is restarted cannot be detected. In order to detect the timing (d) at which the operation of the control unit 101 is restarted, a circuit that detects that the operation of the control unit 101 is restarted, as in the determination unit 202 of the switching power supply circuit 200 of FIG. It is necessary to provide.

In the switching power supply circuit 100 of this embodiment, when the control signal DRV2 reaches a high level, the low level state of the control signal DRV1 is released by the DRV1Off signal output from the latch unit 105. Therefore, it is not necessary to provide a circuit for detecting that the operation of the control unit 101 is restarted by the reoscillation of the clock signal, and the switching operation can be restarted at the optimum timing. As a result, the control unit 101 malfunctions due to disturbance noise or the like, and even when the overcurrent protection is performed by the OCP circuit as described in FIG. 4 (B), the output of the output voltage V11 can be maintained, and usability is achieved. And the reliability of the switching power supply circuit 100 can be compatible with each other.

Further, in this embodiment, an OCP circuit that detects an overcurrent of the drain current of the FET 1 and stops the switching of the FET 1 for each switching, and an OLP circuit that detects the average current of the drain current and stops the switching of the FET 1 and the FET 2. Is used together. As a result, the destruction of the FET 1 due to the short-term overcurrent can be protected by the OCP circuit, and the thermal destruction of the FET 1 and the FET 2 due to the long-term overcurrent can be protected by the OLP circuit. Reliability can be increased. Further, the OCP circuit can be used as a protection operation when the load of the output voltage V11 is short-circuited, in addition to the protection operation when the operation of the control unit 101 is stopped as described in FIG. 4 (B).

By the way, in the first embodiment, the malfunction of the clock signal has been described as an example, but the present invention is not limited to this. In addition to stopping the clock signal, the PWM output of the PWM output unit 133 is temporarily stopped due to an internal malfunction of the control unit 101, resulting in a malfunction in which the ON period of the FET 1 is longer than during normal control. It is effective against it.

As described above, according to the present embodiment, it is possible to protect the circuit from overcurrent and not stop the output of the power supply voltage to the load even when the operation of the control unit is stopped.

In the first embodiment, when the clock signal is stopped due to disturbance noise or the like, the OCP circuit detects that an overcurrent flows through the FET 1, and sets the control signal DRV1 to a low level to forcibly turn the FET 1 off. The circuit operation to be performed was explained. In the second embodiment, a circuit operation for forcibly turning off the FET 1 when an abnormality of the control unit is performed based on a signal indicating an operation state output from the control unit will be described.

[Configuration of switching power supply]
FIG. 6 is a circuit diagram showing an outline of a switching power supply circuit 200 using the active clamp method of the second embodiment. In FIG. 6 (A), the control unit 101 and the current detection unit 120 of FIG. 1 (A) are deleted as compared with the circuit diagram of FIG. 1 (A) of the first embodiment, and the control unit 201, the determination unit 202, and the latch are deleted. Part 203 has been added. The same components as those in FIG. 1 (A) of the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

[Control unit configuration]
FIG. 7A is a block diagram showing an internal configuration of the control unit 201 of this embodiment. In the control unit 201, a state transmission unit 231 that outputs a high-level or low-level STATUS signal (state signal) according to the operating state of the control unit 201 is added to the configuration of the control unit 101 described in the first embodiment. There is. Since the other configurations other than the state transmission unit 231 are the same as the control unit 101 of the first embodiment, the description thereof will be omitted here.

The state transmission unit 231 monitors the output of the clock signal of the clock oscillation unit 131. Then, as shown in FIGS. 8 (v) and 8 (v') described later, when the clock signal output from the clock oscillator 131 is stopped due to noise or the like from the outside (timing (b) in FIG. 8), the state is reached. The transmitter 231 sets the STATUS signal to a low level. Then, when the clock signal from the clock oscillator 131 is output again (timing (c) in FIG. 8), the state transmission unit 231 sets the STATUS signal to a high level (FIG. 8 (v')). The STATUS signal is not limited to the waveform shown in FIG. 8 (v'), and the STATUS signal is set to a high level when the clock signal output from the clock oscillator 131 stops, and the clock signal returns to normal. At that time, it may be set to a low level. Further, when the clock signal output from the clock oscillator 131 is stopped, the output of the STATUS signal may be stopped, and when the clock signal returns to normal, the STATUS signal may be output. Further, as shown in FIG. 7B, the state transmission unit 231 is provided in the control unit 101 provided with the external monitoring unit 142 for the clock signal, which has an internal configuration shown in FIG. 2C of the first embodiment. The control unit 201 may be configured.

[Structure of latch part]
As shown in FIG. 6A, the switching power supply circuit 200 has a latch portion 203 which is a holding means. FIG. 6B is a circuit diagram showing the internal configuration of the latch portion 203. A STATUS signal, a STATUSOff signal, and a potential DCL are input to the latch unit 203, and a DRVOff signal is output. In the latch unit 203, as compared with the latch unit 105 shown in FIG. 1 (B) of the first embodiment, the STATUS signal is used instead of the control signal DRV2, the STATUSOff signal is used instead of the IpOff signal, and the DRVOff signal is used instead of the DRV1Off signal. It is used. The circuit configuration of the latch portion 203 is the same as that of the latch portion 105 of the first embodiment, and the same reference numerals are given to the same circuit elements, and the description thereof will be omitted here. Therefore, in the latch portion 203, similarly to the latch portion 105 of the first embodiment, when the STATUSOff signal becomes low level, the transistors Tr1 and TR2 are turned on. Then, when the transistors Tr1 and TR2 are turned on, the control signal DRV1 and the control signal DRV2 become low level via the diodes D21 and D25. In this way, the DRVOff signal can be controlled by the STATUSOff signal. Further, when the STATUS signal changes from a low level to a high level, the transistor Tr3 is turned on and the electric charge charged in the capacitor Cr1 is discharged. As a result, the transistor Tr2 is turned off, the DRVOff signal is brought into a high impedance state, and the latch state is released.

[Configuration and operation of the judgment unit]
As shown in FIG. 6A, the switching power supply circuit 200 has a determination unit 202 which is a detection means. Further, as shown in FIG. 6C, the determination unit 202 receives the power supply voltage V2, the DCL potential, and the STATUS signal, and outputs the STATUSOff signal. The determination unit 202 controls the STATUSOff signal based on the STATUS signal output from the control unit 201, and the STATUSOff signal output from the determination unit 202 is input to the latch unit 203. As an example of the determination unit 202, FIG. 6C shows a circuit composed of a plurality of resistors and NPN-type transistors Tr21 and Tr22 (hereinafter, simply referred to as transistors Tr21 and Tr22). The determination unit 202 is not limited to the circuit configuration shown in FIG. 6C, and may be a configuration using an IC such as an FET, an operational amplifier, or a comparator, or a configuration having the determination unit 202 inside the control unit 201. good.

Next, the operation of the determination unit 202 will be described with reference to FIGS. 6 (B) and 6 (C). When the clock signal is output from the clock oscillator 131, the STATUS signal output from the control unit 201 is at a high level. Therefore, the base-emitter voltage of the transistor Tr21 of the determination unit 202 is higher than the threshold voltage, and the transistor Tr21 is turned on. The power supply voltage V2 is applied to the collector terminal of the transistor Tr21 and the base terminal of the transistor Tr23 via a resistor. When the transistor Tr21 is on, the base-emitter voltage of the transistor Tr22 is lower than the threshold voltage, and the transistor Tr22 is off. Therefore, the collector terminal of the transistor Tr22 is in a high impedance state, and the STATUSOff signal is also in a high impedance state.

In the latch portion 203, when the input STATUSOff signal is in the high impedance state, the base terminal voltage of the transistor Tr1 becomes the same potential as the emitter terminal, and the transistor Tr1 is in the off state. Therefore, the base-emitter voltage of the transistor Tr2 is lower than the threshold voltage, and the transistor Tr2 is turned off. Therefore, the DRVOff signal is in a high impedance state.

On the other hand, when the output of the clock signal from the clock oscillator 131 is stopped, the STATUS signal output from the control unit 201 becomes low level. Therefore, the base-emitter voltage of the transistor Tr21 of the determination unit 202 is lower than the threshold voltage, and the transistor Tr21 is turned off. As a result, since the power supply voltage V2 is applied to the base terminal of the transistor Tr22 via a resistor, the base-emitter voltage of the transistor Tr22 becomes higher than the threshold voltage, and the transistor Tr22 turns on. Therefore, the STATUSOff signal connected to the collector terminal of the transistor Tr22 becomes low level.

When the STATUSOff signal becomes low level in the latch portion 203, the transistor Tr1 is turned on, so that the base-emitter voltage of the transistor Tr2 is higher than the threshold voltage and the transistor Tr2 is turned on. As a result, the DRVOff signal becomes low level. Since the DRVOFF signal becomes low level, the control signal DRV1 output from the control unit 201 becomes low level regardless of whether the control signal DRV1 is high level or low level. Therefore, the gate drive signal DL of the FET 1 output from the FET drive unit 102 is forcibly lowered to a low level. Similarly, the control signal DRV2 also becomes a low level via the diode D25, and the gate drive signal DH of the FET 2 output from the FET drive unit 102 is forcibly lowered to a low level. In this way, the point that the determination unit 202 can control the FET 1 according to the STATUS signal indicating whether or not the clock signal of the control unit 201 is in the normal state is that the control unit 101 controls the FET 1 according to the output of the OCP circuit. It is different from the configuration of the first embodiment.

[Operation when the control unit 201 is abnormal]
Next, the operation of protecting the switching power supply circuit 200 when the control unit 201 malfunctions, which is a feature of this embodiment, will be described in detail. In this embodiment as well, as in the first embodiment, as an example of the case where the PWM output of the PWM output unit 133 of the control unit 201 is stopped, the control unit 201 in which the clock signal output from the clock oscillation unit 131 is stopped is stopped. The malfunction state of is described as an example. FIG. 8 shows details of the operation of the clock oscillator 131 when the clock signal is stopped. In FIG. 8, (i) shows the waveform of the control signal DRV1 corresponding to the gate drive signal DL of the FET 1, and (ii) shows the waveform of the control signal DRV2 corresponding to the gate drive signal DH of the FET 2. Further, in FIG. 8, (iii) shows the waveform of the drain current of the FET 1, (iv) shows the waveform of the voltage between the drain terminal and the source terminal of the FET 1, and (v) shows the clock signal of the clock oscillator 131. The waveform is shown. Further, in FIG. 8, (v') shows the state of the STATUS signal, and (vi) shows the waveform of the latch voltage Vr1. The horizontal axis indicates time.

Similar to the switching power supply circuit 100 of FIG. 1A of the first embodiment, the switching power supply circuit 200 shown in FIG. 6A is a control signal DRV1 output from the PWM output unit 133 when the clock signal is stopped. And the control signal DRV2 cannot be controlled. As a result, the states of the control signal DRV1 and the control signal DRV2 at the time when the clock signal is stopped are maintained. (A) to (c) in FIG. 8 indicate timing (time). Hereinafter, the circuit operation at each timing will be described with reference to FIG.

(Timing a) Switching operation The timing (a) is the time when the high-level control signal DRV2 is output from the control unit 201 and the control signal DRV1 is output at the low level (FIGS. 8 (i) and 8 (ii)). ). At this time, the FET 1 is in the off state and the FET 2 is in the on state, and the switching operation is performed. Further, as shown in FIG. 8 (v'), the STATUS signal is at a high level during the period in which the clock signal of the control unit 201 is operating normally.

(Timing b) Clock signal stop The timing (b) indicates the time when the clock signal output from the clock oscillator 131 of the control unit 201 is stopped due to disturbance noise or the like (FIG. 8 (v)). When the clock signal is stopped, the arithmetic control unit 136 of the control unit 101 also stops its operation. As a result, the control signal DRV1 and the control signal DRV2 output from the PWM output unit 133 are held in the state at the time when the clock signal is stopped, that is, the control signal DRV1 is held at a high level and the control signal DRV2 is held at a low level. In the signal waveform of the control signal DRV1 of FIG. 8 (i), the broken line between the timing (b) and the timing (c) indicates that the control signal DRV1 has a high level to a low level unless the clock signal is stopped. It shows the timing of falling down.

Further, as shown in the STATUS signal, when the clock signal is stopped, the STATUS signal becomes low level (FIG. 8 (v')). In FIG. 6C, since the STATUS signal is at a low level, the base-emitter voltage of the transistor Tr21 of the determination unit 202 is lower than the threshold voltage, and the transistor Tr21 is turned off. As a result, the power supply voltage V2 is applied to the base terminal of the transistor Tr22 via a resistor, so that the base-emitter voltage of the transistor Tr22 is higher than the threshold voltage and the transistor Tr22 is turned on. As a result, the STATUSOff signal connected to the collector terminal of the transistor Tr22 becomes low level.

In FIG. 6B, when the STATUSOff signal becomes low level, the transistors Tr1 and Tr2 of the latch portion 203 are turned on, and the DRVOff signal becomes low level. As a result, both the control signal DRV1 and the control signal DRV2 output from the control unit 201 are at a low level (FIGS. 8 (i) and 8 (ii)). As a result, both the gate drive signal DL of the FET 1 and the gate drive signal DH of the FET 2 output from the FET drive unit 102 are forcibly lowered to a low level (FIG. 8 (iii)). In this way, even if the clock signal is stopped due to noise or the like, the STATUS signal (FIG. 8 (v')) and the determination unit 202 can safely stop the switching operation without destroying the switching element FET1. can. Further, in FIG. 8 (iii), the current waveform of the drain current shown by the broken line is the waveform of the drain current of the FET 1 that flows until the overcurrent is detected by the OCP circuit in the first embodiment (FIGS. 4 (B) and (iii)). ) Is shown. The present embodiment is different from the case of the first embodiment in that the switching operation of the FET 1 can be stopped before the overcurrent flows through the FET 1.

(Timing c) Clock signal reoscillation The timing (c) indicates the time when the clock oscillation unit 131 automatically recovers and reoscillates to output the clock signal after the disturbance noise or the like disappears. When the control unit 201 operates normally, the STATUS signal becomes high level (FIG. 8 (v')). As a result, the transistor Tr21 of the determination unit 202 is turned on, the transistor Tr22 is turned off, and the STATUSOff signal is changed from the low level to the high impedance state. Further, in the latch portion 203, when the STATUS signal becomes high level, the transistor Tr3 is turned on, the transistors Tr1 and Tr2 are turned off, and the DRVOff signal is put into a high impedance state. As a result, the switching stop of the FET 1 by the latch portion 203 is released.

Since the operation of the control unit 201 is restarted from the state at the time when the clock signal is stopped (timing (b)), the control signal DRV1 is held in a high level state. Therefore, when the clock signal reoscillates (timing (c)), the FET 1 is turned on, a hard switching state occurs, and a surge current is generated (FIG. 8 (iii)). Since the operation of the control unit 201 is restarted from the state when the clock signal is stopped (timing (b)), the control signal DRV1 is set when a predetermined time elapses after the clock signal reoscillates. It becomes a low level. That is, when the time from the timing (b) to the timing at which the control signal DRV1 falls to the low level (broken line portion in FIG. 8 (i)) has elapsed unless the clock signal is stopped, the control signal DRV1 is at the low level. It becomes.

As described above, according to the present embodiment, even if the clock signal unexpectedly stops during the switching period, the determination unit 202 stops the switching operation of the FET 1 based on the STATUS signal indicating the state of the control unit 201. do. As a result, the switching operation can be stopped earlier than in the first embodiment. Further, when the control unit 201 returns to the normal state, the power supply circuit can be restored by canceling the switching stop of the FET 1 by the determination unit 202. As a result, the output voltage can be maintained without stopping the power supply from the switching power supply circuit to the load.

As described above, in this embodiment, when the clock signal is stopped, the STATUS signal changes from high level to low level. As a result, the latch unit 203 is in the latch state, the gate drive signal DL of the FET 1 output from the FET drive unit 102 becomes low level, the switching operation of the FET 1 is stopped, and the overcurrent of the FET 1 is prevented. However, when the clock signal is output, the STATUS signal changes from low level to high level, and the latch state of the latch portion 203 is released. At that time, since the control signal DRV1 is held in a high level state, the FET1 is turned on when the clock signal reoscillates, and a hard switching state occurs. Therefore, the timing at which the state transmission unit 231 of the control unit 201 switches the STATUS signal from the low level to the high level is changed from the timing at which the clock signal is output to the timing at which the clock output is output and the DRV2 signal is turned on. do. As a result, similarly to the first embodiment, the above-mentioned hard switching can be prevented, the generation of the surge current of the FET 1 can be prevented, and the generation of the overcurrent of the FET 1 can be prevented.

As described above, according to the present embodiment, it is possible to protect the circuit from overcurrent and not stop the output of the power supply voltage to the load even when the operation of the control unit is stopped.

[Other Examples]
By the way, the switching power supply circuits 100 and 200 described in the first and second embodiments are flyback type power supply circuits, but the above-mentioned circuit configuration can also be applied to a forward type power supply circuit or a switching power supply circuit that is not an active clamp type. Can be applied. FIG. 9A is a circuit diagram showing a circuit configuration of a switching power supply circuit 701 using an active clamp method in which a forward voltage is used for the secondary output of the transformer T1. In FIG. 9 (A), the control unit 703 is a control unit having the functions of the control unit 201 and the FET drive unit 102 of FIG. 6 (A) of the second embodiment, and controls the on / off of the FET 1 and the FET 2. , Outputs a STATUS signal according to the output state of the clock signal. The timing at which the STATUS signal is switched from the low level to the high level is the timing at which the clock output is output and the gate drive signal DH that drives the FET 2 is turned on. Further, the OCP circuit composed of the comparator IC1, the voltage dividing resistors R22 and R23 for dividing the power supply voltage V2, the current detection resistor R21 and the like is the same as in FIG. 1 (A) of the first embodiment, and the description thereof will be described here. Omit. Although the circuit configuration of the latch portion 705 is not shown, it is the same as the latch portion 203 shown in FIG. 6 (B) of the second embodiment. The IpOff signal of the latch portion 705 of FIG. 9A corresponds to the STATUSOff signal of FIG. 8B, and the signal output to the cathode terminal of the diode 706 corresponds to the DRVOff signal of FIG. 8B. Further, the secondary side of the transformer T1 has diodes D91 and D92, a capacitor C11, and a coil L91 which are rectifying and smoothing means on the secondary side of the forward voltage generated in the secondary winding S1 of the transformer T1. In FIG. 9A, the AC power supply 10, the bridge diode BD1, the start circuit 103, the DC / DC converter 104, and the feedback unit shown in FIG. 1 (A) of the first embodiment and FIG. 6 (A) of the second embodiment are shown. The description of 115 etc. is omitted.

In the switching power supply circuit 701, similarly to the first and second embodiments, even if the clock signal unexpectedly stops during the switching period of the FET 1, the OCP circuit and the latch portion 705 operate to stop the switching operation of the FET 1. .. As a result, switching can be safely stopped. Further, after the clock signal reoscillates normally, the switching operation is restarted in synchronization with the STATUS signal and the gate drive signal DH of the FET 2, so that the switching operation of the switching power supply circuit 701 is restored without damaging the FET 1. be able to.

Further, FIG. 9B is a switching power supply circuit 702 in which the active clamp circuit portion is deleted from FIG. 9A and the snubber circuit SK1 is added. FIG. 9B is the same as the circuit configuration of FIG. 9A except that the snubber circuit SK1 and the control unit 704 control only FET1 on / off, and the description thereof will be omitted here. In the switching power supply circuit 702, similarly to the switching power supply circuit 701 of FIG. 9A, the OCP circuit and the latch portion 705 prevent damage to the FET 1 due to overcurrent. Further, in the switching power supply circuit 702, when the clock signal is normally output from the clock oscillation unit of the control unit 704, the switching operation of the switching power supply circuit 702 is restored to normal.

As described above, also in the other embodiments, the circuit can be protected from overcurrent even when the operation of the control unit is stopped, and the output of the power supply voltage to the load can not be stopped.

The switching power supply circuit, which is the power supply device described in Examples 1 and 2, can be applied as, for example, a low-voltage power supply of an image forming device, that is, a power supply that supplies power to a drive unit such as a controller (control unit) or a motor. The configuration of the image forming apparatus to which the power supply apparatus having the switching power supply circuits of Examples 1 and 2 is applied will be described below.

[Configuration of image forming apparatus]
As an example of the image forming apparatus, a laser beam printer will be described as an example. FIG. 10 shows a schematic configuration of a laser beam printer, which is an example of an electrophotographic printer. The laser beam printer 300 includes a photosensitive drum 311 as an image carrier on which an electrostatic latent image is formed, a charging unit 317 (charging means) that uniformly charges the photosensitive drum 311, and an electrostatic latent image formed on the photosensitive drum 311. A developing unit 312 (developing means) for developing an image with toner is provided. Then, the toner image developed on the photosensitive drum 311 is transferred to a sheet (not shown) as a recording material supplied from the cassette 316 by a transfer unit 318 (transfer means), and the toner image transferred to the sheet is transferred to the fixing device 314. And discharge to tray 315. The photosensitive drum 311, the charging unit 317, the developing unit 312, and the transfer unit 318 are image forming units. Further, the laser beam printer 300 includes a power supply device 500 having the switching power supply circuits 100 and 200 described in the first and second embodiments. The image forming apparatus to which the power supply device 500 can be applied is not limited to the one illustrated in FIG. 10, and may be, for example, an image forming apparatus including a plurality of image forming portions. Further, the image forming apparatus may include a primary transfer unit that transfers the toner image on the photosensitive drum 311 to the intermediate transfer belt and a secondary transfer unit that transfers the toner image on the intermediate transfer belt to the sheet.

The laser beam printer 300 includes a controller 320 that controls an image forming operation by the image forming unit and a sheet conveying operation, and the switching power supply circuits 100 and 200 according to the first and second embodiments power the controller 320, for example. To supply. Further, the switching power supply circuits 100 and 200 according to the first and second embodiments supply electric power to a driving unit such as a motor for rotating the photosensitive drum 311 or for driving various rollers and the like for conveying a sheet.

When the power supply device 500 of the present embodiment includes the switching power supply circuit 100 of the first embodiment, the OCP circuit and the latch portion 105 operate even if the clock signal is unexpectedly stopped during the switching period. The switching operation can be stopped. As a result, the power supply device 500 can be safely stopped. Further, after the clock signal reoscillates normally, the power supply device 500 can be restored without damaging the FET 1 by restarting the switching in synchronization with the control signal DRV2, and then the image forming apparatus can be automatically restored. can.

Further, when the power supply device 500 of the present embodiment includes the switching power supply circuit 200 of the second embodiment, the STATUS signal indicating the state of the control unit 201 and the determination unit even when the clock signal is unexpectedly stopped. 202 operates and stops the switching operation. As a result, the switching operation of the FET 1 can be stopped faster than in the case of the power supply device 500 including the switching power supply circuit 100. Further, when the control unit 201 becomes a normal state, the determination unit 202 releases the stop of the switching operation of the FET 1, so that the power supply device 500 can be restored, and then the image forming apparatus can be automatically restored.

As described above, according to the present embodiment, it is possible to protect the circuit from overcurrent and not stop the output of the power supply voltage to the load even when the operation of the control unit is stopped.

DRV2 Control signal FET1 Field effect transistor FET2 Field effect transistor IC1 Comparator 101 Control unit 105 Latch unit

Claims (15)

A transformer with primary and secondary windings,
A first switching element connected in series with the primary winding of the transformer,
A second switching element connected in parallel to the primary winding of the transformer,
A capacitor connected in series with the second switching element and connected in parallel with the primary winding of the transformer together with the second switching element.
A feedback means that outputs information according to the voltage induced in the secondary winding of the transformer, and
Based on the information input from the feedback means, the first control signal controls the on or off of the first switching element, and the second control signal controls the on or off of the second switching element. Control means to control and
With
The control means performs a switching operation in which the first switching element and the second switching element are alternately turned on or off with a dead time for turning off both the first switching element and the second switching element. It is a power supply device to perform
The first current detecting means for detecting the current flowing through the first switching element, and
When an overcurrent is detected based on the detection result of the first current detecting means, the first holding means for turning off the first switching element and holding the first switching element in the off state, and the first holding means.
With
The first holding means is a power supply device characterized in that the off state of the first switching element is released at the timing when the control means turns on the second switching element by the second control signal. .. The first holding means turns the first switching element off by setting the first control signal that turns on the first switching element to a state in which the first switching element is turned off. The power supply device according to claim 1, wherein the power supply device is held. A second current detecting means for detecting the average current value flowing through the first switching element, and
When the overcurrent of the first switching element is detected based on the detection result of the second current detecting means, the first switching element and the second switching element are turned off and the first switching element is turned off. and power supply device according to claim 2, characterized in that and a second holding means that holds the oFF state the second switching element. The power supply device according to claim 3, wherein the second holding means does not release the off state setting of the first switching element and the second switching element. The control means has a generation unit that generates a clock signal for operating the control means.
The power supply device according to any one of claims 1 to 4, wherein the generation unit reoscillates and outputs the clock signal when a predetermined time elapses even if the clock signal is stopped. .. The control means includes a generation unit that generates a clock signal for operating the control means, and a detection unit that detects a stop of the clock signal output from the generation unit.
Claims 1 to 4, wherein when the detection unit detects that the clock signal has stopped, it reoscillates to the generation unit and outputs a return signal for outputting the clock signal. The power supply device according to any one item. A transformer with primary and secondary windings,
A first switching element connected in series with the primary winding of the transformer,
A second switching element connected in parallel to the primary winding of the transformer,
A capacitor connected in series with the second switching element and connected in parallel with the primary winding of the transformer together with the second switching element.
A feedback means that outputs information according to the voltage induced in the secondary winding of the transformer, and
Based on the information input from the feedback means, the first control signal controls the on or off of the first switching element, and the second control signal controls the on or off of the second switching element. Control means to control and
With
The control means performs a switching operation in which the first switching element and the second switching element are alternately turned on or off with a dead time for turning off both the first switching element and the second switching element. It is a power supply device to perform
The control means outputs a state signal indicating the state of the control means, and outputs a state signal.
A detection means for detecting the stoppage of operation of the control means based on the state signal output by the control means, and a detection means.
When the detection means detects that the control means has stopped operating, the first switching element is turned off, and the holding means for holding the first switching element in the off state is used.
With
The holding means is a power supply device characterized in that when the state signal is switched from a state in which the operation of the control means is stopped to a state indicating a normal operation, the off state of the first switching element is released. The control means operates by a clock signal, outputs the state signal indicating a normal operation state when the clock signal is output, and indicates an operation stop state when the clock signal is stopped. The power supply device according to claim 7, wherein the status signal is output. The control means is characterized in that the state signal is switched from the stopped state of the control means to the normal operation state at the timing when the control means turns on the second switching element by the second control signal. The power supply device according to claim 8. The control means has a generation unit that generates the clock signal.
The power supply device according to claim 8 or 9, wherein even if the clock signal is stopped, the generation unit reoscillates and outputs the clock signal when a predetermined time elapses. The control means includes a generation unit that generates the clock signal and a detection unit that detects the stop of the clock signal output from the generation unit.
8. The power supply described. A transformer with primary and secondary windings,
A first switching element connected in series with the primary winding of the transformer,
A second switching element connected in parallel to the primary winding of the transformer,
A capacitor connected in series with the second switching element and connected in parallel with the primary winding of the transformer together with the second switching element.
A feedback means that outputs information according to the voltage induced in the secondary winding of the transformer, and
Based on the information input from the feedback means, the first control signal controls the on or off of the first switching element, and the second control signal controls the on or off of the second switching element. Control means to control and
With
The control means performs a switching operation in which the first switching element and the second switching element are alternately turned on or off with a dead time for turning off both the first switching element and the second switching element. It is a power supply device to perform
A current detecting means for detecting the current flowing through the first switching element, and
When an overcurrent is detected based on the detection result of the current detecting means, the first switching element is turned off and the holding means for holding the first switching element in the off state is used.
With
The control means operates by a clock signal, outputs a state signal indicating a normal operation state when the clock signal is output, and indicates an operation stop state when the clock signal is stopped. Outputs a status signal and
The holding means is a power supply device characterized in that when the state signal is switched from the stopped state of the control means to the normal operation state, the off state of the first switching element is released. The control means is characterized in that the state signal is switched from the stopped state of the control means to the normal operation state at the timing when the control means turns on the second switching element by the second control signal. The power supply device according to claim 12. A transformer with primary and secondary windings,
A switching element connected in series with the primary winding of the transformer,
A snubber circuit connected in parallel to the primary winding of the transformer,
A feedback means that outputs information according to the voltage induced in the secondary winding of the transformer, and
A control means that controls on or off of the switching element by a control signal based on the information input from the feedback means.
It is a power supply device equipped with
A current detecting means for detecting the current flowing through the switching element, and
When an overcurrent is detected based on the detection result of the current detecting means, the switching element is turned off and the holding means for holding the switching element in the off state is used.
With
The control means operates by a clock signal, outputs a state signal indicating a normal operation state when the clock signal is output, and indicates an operation stop state when the clock signal is stopped. Outputs a status signal and
The holding means is a power supply device characterized in that when the state signal is switched from the stopped state of the control means to the normal operation state, the off state of the switching element is released. An image forming means for forming an image on a recording material,
The power supply device according to any one of claims 1 to 14.
An image forming apparatus comprising.

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