JP6941981B2

JP6941981B2 - Piezoelectric thin film resonators, filters and multiplexers

Info

Publication number: JP6941981B2
Application number: JP2017124887A
Authority: JP
Inventors: 耕平伊藤; 英行関根
Original assignee: Taiyo Yuden Co Ltd
Current assignee: Taiyo Yuden Co Ltd
Priority date: 2017-06-27
Filing date: 2017-06-27
Publication date: 2021-09-29
Anticipated expiration: 2037-06-27
Also published as: JP2019009671A

Description

本発明は、圧電薄膜共振器、フィルタおよびマルチプレクサに関し、例えば基板と下部電極との間に空隙が設けられた圧電薄膜共振器、フィルタおよびマルチプレクサに関する。 The present invention relates to piezoelectric thin film resonators, filters and multiplexers, for example, piezoelectric thin film resonators, filters and multiplexers in which a gap is provided between a substrate and a lower electrode.

圧電薄膜共振器は、例えば携帯電話等の無線機器のフィルタおよびデュプレクサとして用いられている。圧電薄膜共振器では、基板上に空隙を介し下部電極、圧電膜および上部電極が積層されている。基板と下部電極との間に空隙を形成する方法として、基板上に犠牲層を形成し犠牲層上に下部電極を形成する。その後、下部電極に形成された貫通孔を介し犠牲層にエッチング液を導入し、犠牲層を除去することで空隙を形成することが知られている（例えば特許文献１）。 Piezoelectric thin film resonators are used as filters and duplexers for wireless devices such as mobile phones. In the piezoelectric thin film resonator, a lower electrode, a piezoelectric film, and an upper electrode are laminated on a substrate via a gap. As a method of forming a gap between the substrate and the lower electrode, a sacrificial layer is formed on the substrate and a lower electrode is formed on the sacrificial layer. After that, it is known that an etching solution is introduced into the sacrificial layer through a through hole formed in the lower electrode to remove the sacrificial layer to form a void (for example, Patent Document 1).

特開２００５−３４７８９８号公報Japanese Unexamined Patent Publication No. 2005-347988

エッチング液を導入するためには、下部電極に設けられた貫通孔の面積を大きくすることが好ましい。しかしながら、貫通孔を大きくするとチップ面積が大きくなる。 In order to introduce the etching solution, it is preferable to increase the area of the through hole provided in the lower electrode. However, increasing the through hole increases the chip area.

本発明は、上記課題に鑑みなされたものであり、圧電薄膜共振器を小型化することを目的とする。 The present invention has been made in view of the above problems, and an object of the present invention is to reduce the size of a piezoelectric thin film resonator.

本発明は、基板と、前記基板上に設けられた圧電膜と、前記圧電膜上に設けられた上部電極と、前記上部電極とで前記圧電膜の少なくとも一部を挟む共振領域を形成するように、前記基板と前記圧電膜との間に、前記基板との間に空隙を介し設けられ、前記空隙とつながる第１貫通孔および第２貫通孔を前記共振領域外に有する下部電極と、を具備し、前記共振領域の外周のうち前記第１貫通孔に最も近い箇所における前記外周に沿った第１方向における前記第１貫通孔の第１幅は、前記第１方向に直交する第１直交方向における前記第１貫通孔の第２幅より大きく、前記外周のうち前記第２貫通孔に最も近い箇所における前記外周に沿った第２方向における前記第２貫通孔の第３幅は前記第１幅より小さく、前記第２方向に直交する第２直交方向における前記第２貫通孔の第４幅は前記第２幅より大きい圧電薄膜共振器である。 The present invention forms a resonance region in which at least a part of the piezoelectric film is sandwiched between the substrate, the piezoelectric film provided on the substrate, the upper electrode provided on the piezoelectric film, and the upper electrode. in, between the substrate and the piezoelectric film, provided through a gap between the substrate, a lower electrode having a first through-hole and the second through-hole leads the space outside the resonance region, the The first width of the first through hole in the first direction along the outer circumference at the portion of the outer circumference of the resonance region closest to the first through hole is the first orthogonality orthogonal to the first direction. The third width of the second through hole in the second direction along the outer circumference at a portion of the outer circumference closest to the second through hole, which is larger than the second width of the first through hole in the direction, is the first. The fourth width of the second through hole in the second orthogonal direction smaller than the width and orthogonal to the second direction is a piezoelectric thin film resonator larger than the second width.

上記構成において、前記第３幅と前記第４幅は等しい構成とすることができる。 In the above configuration, the third width and the fourth width can be equal to each other.

上記構成において、前記第１貫通孔および前記第２貫通孔は前記共振領域の中心を挟んで設けられている構成とすることができる。 In the above configuration, the first through hole and the second through hole may be provided with the center of the resonance region interposed therebetween.

上記構成において、前記共振領域は長手方向と短手方向を有し、前記第１貫通孔と前記第２貫通孔は前記長手方向に設けられている構成とすることができる。 In the above configuration, the resonance region has a longitudinal direction and a lateral direction, and the first through hole and the second through hole may be provided in the longitudinal direction.

上記構成において、前記第１貫通孔は前記共振領域に最も近い前記基板の端部と前記共振領域との間に設けられ、前記基板の端部と前記共振領域との間には、他の圧電薄膜共振器は設けられておらず、前記第２貫通孔と、前記第２貫通孔に対し前記共振領域と反対側の前記基板の端部と、の間には、他の圧電薄膜共振器が設けられている構成とすることができる。 In the above configuration, the first through hole is provided between the end of the substrate closest to the resonance region and the resonance region, and another piezoelectric is provided between the end of the substrate and the resonance region. A thin film resonator is not provided, and another piezoelectric thin film resonator is provided between the second through hole and the end portion of the substrate opposite to the resonance region with respect to the second through hole. It can be configured to be provided.

上記構成において、前記第１貫通孔は隣接する第１他の圧電薄膜共振器との間に設けられ、前記第１貫通孔と、前記第１他の圧電薄膜共振器が有する貫通孔のうち前記第１貫通孔に最も近い貫通孔と、の第１距離は、前記第２貫通孔と、前記第２貫通孔に最も近い第２他の圧電薄膜共振器が有する貫通孔のうち前記第２貫通孔に最も近い貫通孔と、の第２距離より短い構成とすることができる。
In the above structure, the first through-hole is found interposed between the first other piezoelectric thin-film resonators adjacent one of the the first through-hole, the first other through holes piezoelectric thin-film resonator has The first distance between the through hole closest to the first through hole is the second of the through holes of the second through hole and the second other piezoelectric thin film resonator closest to the second through hole. The configuration may be shorter than the second distance between the through hole closest to the through hole and the through hole.

上記構成において、前記第１貫通孔と前記第２貫通孔の面積は略同じである構成とすることができる。 In the above configuration, the areas of the first through hole and the second through hole can be substantially the same.

本発明は、上記圧電薄膜共振器を含むフィルタである。 The present invention is a filter including the piezoelectric thin film resonator.

本発明は、上記フィルタを含むマルチプレクサである。 The present invention is a multiplexer including the above filter.

本発明によれば、圧電薄膜共振器を小型化することができる。 According to the present invention, the piezoelectric thin film resonator can be miniaturized.

図１（ａ）は、実施例１における圧電薄膜共振器の平面図、図１（ｂ）は、図１（ａ）のＡ−Ａ断面図である。1 (a) is a plan view of the piezoelectric thin film resonator according to the first embodiment, and FIG. 1 (b) is a cross-sectional view taken along the line AA of FIG. 1 (a). 図２（ａ）から図２（ｄ）は、実施例１に係る圧電薄膜共振器の製造方法を示す断面図である。2 (a) to 2 (d) are cross-sectional views showing a method of manufacturing the piezoelectric thin film resonator according to the first embodiment. 図３は、比較例１に係る圧電薄膜共振器の平面図である。FIG. 3 is a plan view of the piezoelectric thin film resonator according to Comparative Example 1. 図４（ａ）および図４（ｂ）は、実施例２に係る圧電薄膜共振器の平面図である。4 (a) and 4 (b) are plan views of the piezoelectric thin film resonator according to the second embodiment. 図５は、実施例３に係るフィルタの平面図である。FIG. 5 is a plan view of the filter according to the third embodiment. 図６（ａ）および図６（ｂ）は、図５の領域ＡおよびＢの拡大図である。6 (a) and 6 (b) are enlarged views of regions A and B of FIG. 図７は、実施例４に係る圧電薄膜共振器の断面図である。FIG. 7 is a cross-sectional view of the piezoelectric thin film resonator according to the fourth embodiment. 図８は、実施例５に係るデュプレクサの回路図である。FIG. 8 is a circuit diagram of the duplexer according to the fifth embodiment.

以下、図面を参照し実施例について説明する。 Hereinafter, examples will be described with reference to the drawings.

図１（ａ）は、実施例１における圧電薄膜共振器の平面図、図１（ｂ）は、図１（ａ）のＡ−Ａ断面図である。共振領域５０の長軸方向および短軸方向をＸ方向およびＹ方向、基板の法線方向をＺ方向とすする。 1 (a) is a plan view of the piezoelectric thin film resonator according to the first embodiment, and FIG. 1 (b) is a cross-sectional view taken along the line AA of FIG. 1 (a). The major axis direction and the minor axis direction of the resonance region 50 are the X direction and the Y direction, and the normal direction of the substrate is the Z direction.

図１（ａ）および図１（ｂ）に示すように、基板１０上に、下部電極１２が設けられている。基板１０の平坦主面と下部電極１２との間にドーム状の膨らみを有する空隙３０が形成されている。ドーム状の膨らみとは、例えば空隙３０の周辺では空隙３０の高さが小さく、空隙３０の内部ほど空隙３０の高さが大きくなるような形状の膨らみである。 As shown in FIGS. 1A and 1B, a lower electrode 12 is provided on the substrate 10. A gap 30 having a dome-shaped bulge is formed between the flat main surface of the substrate 10 and the lower electrode 12. The dome-shaped bulge is, for example, a bulge having a shape in which the height of the void 30 is small around the void 30 and the height of the void 30 is increased toward the inside of the void 30.

下部電極１２上に、圧電膜１４が設けられている。圧電膜１４上に上部電極１６が設けられている。圧電膜１４を挟み下部電極１２と上部電極１６とが対向する領域は共振領域５０である。共振領域５０の平面形状は、長軸５２と短軸５４を有する楕円形状である。長軸長はＬ１である。共振領域５０は厚み縦振動モードの弾性波が共振する領域である。下部電極１２上に配線２６が設けられている。平面視において、共振領域５０は空隙３０に含まれている。 A piezoelectric film 14 is provided on the lower electrode 12. The upper electrode 16 is provided on the piezoelectric film 14. The region where the lower electrode 12 and the upper electrode 16 face each other with the piezoelectric film 14 interposed therebetween is the resonance region 50. The planar shape of the resonance region 50 is an elliptical shape having a major axis 52 and a minor axis 54. The major axis length is L1. The resonance region 50 is a region in which elastic waves in the thickness longitudinal vibration mode resonate. Wiring 26 is provided on the lower electrode 12. In a plan view, the resonance region 50 is included in the void 30.

空隙３０は共振領域５０の外まで設けられている。下部電極１２は、共振領域５０の外において空隙３０につながる貫通孔３５ａを有している。貫通孔３５ａは共振領域５０の長軸５２の延長線上に共振領域５０を挟み一対設けられている。貫通孔３５ａの平面形状は、共振領域５０に沿った方向（Ｙ方向）の幅Ｒ１がＸ方向の幅Ｒ２より大きい細長である。貫通孔３５ａは後述するように、犠牲層をエッチングするためのエッチング剤を導入するための導入路である。貫通孔３５ａを含む圧電薄膜共振器のＸ方向の長さはＬ０である。長さＬ０は長軸長Ｌ１と幅Ｒ２の２倍にその他の領域αを加えたＬ０＝Ｌ１＋２×Ｒ２＋αである。 The gap 30 is provided to the outside of the resonance region 50. The lower electrode 12 has a through hole 35a connected to the gap 30 outside the resonance region 50. A pair of through holes 35a are provided on the extension line of the long axis 52 of the resonance region 50 with the resonance region 50 interposed therebetween. The planar shape of the through hole 35a is elongated in that the width R1 in the direction (Y direction) along the resonance region 50 is larger than the width R2 in the X direction. The through hole 35a is an introduction path for introducing an etching agent for etching the sacrificial layer, as will be described later. The length of the piezoelectric thin film resonator including the through hole 35a in the X direction is L0. The length L0 is L0 = L1 + 2 × R2 + α, which is twice the major axis length L1 and the width R2 plus the other region α.

基板１０は、例えば膜厚が２８０μｍのＳｉ（シリコン）基板である。基板１０としては、Ｓｉ基板以外に、サファイア基板、スピネル基板、アルミナ基板、石英基板、ガラス基板、セラミック基板またはＧａＡｓ基板等を用いることができる。 The substrate 10 is, for example, a Si (silicon) substrate having a film thickness of 280 μm. As the substrate 10, in addition to the Si substrate, a sapphire substrate, a spinel substrate, an alumina substrate, a quartz substrate, a glass substrate, a ceramic substrate, a GaAs substrate, or the like can be used.

下部電極１２は、例えば合計の膜厚が２００ｎｍであり、基板１０側からＣｒ（クロム）膜およびＲｕ（ルテニウム）膜である。上部電極１６は、例えば合計の膜厚が２００ｎｍであり、圧電膜１４側からＲｕ膜およびＣｒ膜である。下部電極１２および上部電極１６としては、ＲｕおよびＣｒ以外にもＡｌ（アルミニウム）、Ｔｉ（チタン）、Ｃｕ（銅）、Ｍｏ（モリブデン）、Ｗ（タングステン）、Ｔａ（タンタル）、Ｐｔ（白金）、Ｒｈ（ロジウム）またはＩｒ（イリジウム）等の単層膜またはこれらの積層膜を用いることができる。 The lower electrode 12 has, for example, a total film thickness of 200 nm, and is a Cr (chromium) film and a Ru (ruthenium) film from the substrate 10 side. The upper electrode 16 has, for example, a total film thickness of 200 nm, and is a Ru film and a Cr film from the piezoelectric film 14 side. In addition to Ru and Cr, the lower electrode 12 and the upper electrode 16 include Al (aluminum), Ti (titanium), Cu (copper), Mo (molybdenum), W (tungsten), Ta (tantalum), and Pt (platinum). , Rh (lodium) or Ir (iridium) or the like, or a laminated film thereof can be used.

圧電膜１４は、例えば膜厚が１０００ｎｍの（００２）方向を主軸とする窒化アルミニウム（ＡｌＮ）を主成分とする窒化アルミニウム膜である。圧電膜１４は、窒化アルミニウム以外にも、ＺｎＯ（酸化亜鉛）、ＰＺＴ（チタン酸ジルコン酸鉛）、ＰｂＴｉＯ₃（チタン酸鉛）等を用いることができる。また、例えば、圧電膜１４は、窒化アルミニウムを主成分とし、共振特性の向上または圧電性の向上のため他の元素を含んでもよい。例えば、添加元素として、Ｓｃ（スカンジウム）、２族または１２族の元素と４族の元素との２つの元素、または２族または１２族と５族との２つの元素を用いることにより、圧電膜１４の圧電性が向上する。このため、圧電薄膜共振器の実効的電気機械結合係数を向上できる。２族の元素は、例えばＣａ（カルシウム）、Ｍｇ（マグネシウム）、Ｓｒ（ストロンチウム）であり１２族元素は例えばＺｎ（亜鉛）である。４族の元素は、例えばＴｉ、Ｚｒ（ジルコニウム）またはＨｆ（ハフニウム）である。５族の元素は、例えばＴａ、Ｎｂ（ニオブ）またはＶ（バナジウム）である。さらに、圧電膜１４は、窒化アルミニウムを主成分とし、Ｂ（ボロン）を含んでもよい。 The piezoelectric film 14 is, for example, an aluminum nitride film containing aluminum nitride (AlN) as a main component having a film thickness of 1000 nm in the (002) direction as a main axis. In addition to aluminum nitride, ZnO (zinc oxide), PZT (lead zirconate titanate), PbTiO ₃ (lead titanate) and the like can be used as the piezoelectric film 14. Further, for example, the piezoelectric film 14 may contain aluminum nitride as a main component and may contain other elements in order to improve the resonance characteristics or the piezoelectricity. For example, by using Sc (scandium), two elements of Group 2 or Group 12 and Group 4 elements, or two elements of Group 2 or Group 12 and Group 5, as the additive element, a piezoelectric film is used. The piezoelectricity of 14 is improved. Therefore, the effective electromechanical coupling coefficient of the piezoelectric thin film resonator can be improved. Group 2 elements are, for example, Ca (calcium), Mg (magnesium), Sr (strontium), and Group 12 elements are, for example, Zn (zinc). Group 4 elements are, for example, Ti, Zr (zirconium) or Hf (hafnium). Group 5 elements are, for example, Ta, Nb (niobium) or V (vanadium). Further, the piezoelectric film 14 contains aluminum nitride as a main component and may contain B (boron).

配線２６は、例えば下部電極１２側から膜厚が１００ｎｍのＴｉ膜および膜厚が６００ｎｍのＡｕ（金）膜である。配線２６は、Ｃｕ（銅）膜およびＡｌ（アルミニウム）膜等の低抵抗の膜が含まれればよい。空隙３０の高さは例えば数１０ｎｍから数１００ｎｍである。貫通孔３５ａの幅Ｒ１およびＲ２は例えばそれぞれ１６μｍおよび４μｍである。各層の膜厚は、所望の共振特性を得るため適宜設定することができる。 The wiring 26 is, for example, a Ti film having a film thickness of 100 nm and an Au (gold) film having a film thickness of 600 nm from the lower electrode 12 side. The wiring 26 may include a low resistance film such as a Cu (copper) film and an Al (aluminum) film. The height of the void 30 is, for example, several tens of nm to several hundred nm. The widths R1 and R2 of the through hole 35a are, for example, 16 μm and 4 μm, respectively. The film thickness of each layer can be appropriately set in order to obtain desired resonance characteristics.

［実施例１の製造方法］
図２（ａ）から図２（ｄ）は、実施例１に係る圧電薄膜共振器の製造方法を示す断面図である。図２（ａ）に示すように、基板１０上に、犠牲層３８を例えばスパッタリング法、真空蒸着法またはＣＶＤ（Chemical Vapor Deposition）法を用い形成する。犠牲層３８は、例えば膜厚が６０ｎｍのＭｇＯ（酸化マグネシウム）膜である。犠牲層３８は、例えばＺｎＯ膜、Ｇｅ膜または酸化シリコン膜でもよい。犠牲層３８の膜厚は例えば１０ｎｍから１００ｎｍでもよい。犠牲層３８を例えばフォトリソグラフィ法およびエッチング法を用い所望の形状にパターニングする。犠牲層３８は空隙３０となる領域に設けられる。 [Manufacturing method of Example 1]
2 (a) to 2 (d) are cross-sectional views showing a method of manufacturing the piezoelectric thin film resonator according to the first embodiment. As shown in FIG. 2A, the sacrificial layer 38 is formed on the substrate 10 by using, for example, a sputtering method, a vacuum deposition method, or a CVD (Chemical Vapor Deposition) method. The sacrificial layer 38 is, for example, an MgO (magnesium oxide) film having a film thickness of 60 nm. The sacrificial layer 38 may be, for example, a ZnO film, a Ge film, or a silicon oxide film. The film thickness of the sacrificial layer 38 may be, for example, 10 nm to 100 nm. The sacrificial layer 38 is patterned into a desired shape using, for example, a photolithography method and an etching method. The sacrificial layer 38 is provided in a region that becomes a gap 30.

図２（ｂ）に示すように、基板１０上に犠牲層３８を覆うように下部電極１２を例えばスパッタリング法、真空蒸着法またはＣＶＤ法を用い形成する。下部電極１２を例えばフォトリソグラフィ法およびエッチング法を用い所望の形状にパターニングする。これにより下部電極１２に貫通孔３５ａが形成される。下部電極１２は、リフトオフ法により形成してもよい。 As shown in FIG. 2B, the lower electrode 12 is formed on the substrate 10 so as to cover the sacrificial layer 38 by using, for example, a sputtering method, a vacuum vapor deposition method, or a CVD method. The lower electrode 12 is patterned into a desired shape by using, for example, a photolithography method and an etching method. As a result, a through hole 35a is formed in the lower electrode 12. The lower electrode 12 may be formed by a lift-off method.

図２（ｃ）に示すように、基板１０上に下部電極１２を覆うように圧電膜１４および上部電極１６を例えばスパッタリング法、真空蒸着法またはＣＶＤ法を用い形成する。 As shown in FIG. 2C, the piezoelectric film 14 and the upper electrode 16 are formed on the substrate 10 so as to cover the lower electrode 12 by using, for example, a sputtering method, a vacuum deposition method, or a CVD method.

図２（ｄ）に示すように、上部電極１６および圧電膜１４を例えばフォトリソグラフィ法およびエッチング法を用い所望の形状にパターニングする。上部電極１６は、リフトオフ法により形成してもよい。下部電極１２上に配線２６を例えば真空蒸着法およびリフトオフ法を用い形成する。配線２６は、スパッタリング法、真空蒸着法またはＣＶＤ法、並びにフォトリソグラフィ法およびエッチング法を用い形成してもよい。 As shown in FIG. 2D, the upper electrode 16 and the piezoelectric film 14 are patterned into a desired shape by using, for example, a photolithography method and an etching method. The upper electrode 16 may be formed by a lift-off method. The wiring 26 is formed on the lower electrode 12 by using, for example, a vacuum deposition method and a lift-off method. The wiring 26 may be formed by using a sputtering method, a vacuum vapor deposition method or a CVD method, and a photolithography method and an etching method.

貫通孔３５ａを介し、犠牲層３８をエッチング液により除去する。下部電極１２、圧電膜１４および上部電極１６の内部応力を圧縮応力としておくことで、下部電極１２が基板１０の反対側に基板１０から離れるように膨れる。下部電極１２と基板１０との間にドーム状の膨らみを有する空隙３０が形成される。犠牲層３８がＭｇＯの場合、犠牲層３８のエッチング液として例えば硝酸系溶液を用いる。以上により、実施例１の圧電薄膜共振器が作製される。 The sacrificial layer 38 is removed by the etching solution through the through hole 35a. By setting the internal stresses of the lower electrode 12, the piezoelectric film 14, and the upper electrode 16 as compressive stresses, the lower electrode 12 swells on the opposite side of the substrate 10 so as to be separated from the substrate 10. A gap 30 having a dome-shaped bulge is formed between the lower electrode 12 and the substrate 10. When the sacrificial layer 38 is MgO, for example, a nitric acid-based solution is used as the etching solution for the sacrificial layer 38. As described above, the piezoelectric thin film resonator of Example 1 is manufactured.

［比較例１］
図３は、比較例１に係る圧電薄膜共振器の平面図である。図３に示すように、貫通孔３５ｂの平面形状は円形であり、幅Ｒ１とＲ２とは略同じである。貫通孔３５ｂの平面視の面積が小さくなると、貫通孔３５ｂを介し犠牲層３８にエッチング液が効率よく導入できない。また、フォトリソグラフィおよびエッチングが難しくなる。このため、貫通孔３５ｂの面積は一定以上であることが好ましい。 [Comparative Example 1]
FIG. 3 is a plan view of the piezoelectric thin film resonator according to Comparative Example 1. As shown in FIG. 3, the planar shape of the through hole 35b is circular, and the widths R1 and R2 are substantially the same. When the area of the through hole 35b in a plan view becomes small, the etching solution cannot be efficiently introduced into the sacrificial layer 38 through the through hole 35b. It also makes photolithography and etching difficult. Therefore, the area of the through hole 35b is preferably equal to or larger than a certain area.

しかしながら、比較例１のように貫通孔３５ｂを円形とすると、幅Ｒ２が大きくなる。このため、圧電薄膜共振器の長軸方向の長さＬ０＝Ｌ１＋２×Ｒ２＋αが大きくなってしまう。 However, if the through hole 35b is circular as in Comparative Example 1, the width R2 becomes large. Therefore, the length L0 = L1 + 2 × R2 + α in the long axis direction of the piezoelectric thin film resonator becomes large.

［実施例１の効果］
実施例１によれば、貫通孔３５ａ（第１貫通孔）は、Ｘ方向（共振領域５０に沿う方向）の幅Ｒ１がＹ方向（沿う方向に交差する方向）の幅Ｒ２より大きい。これにより、貫通孔３５ａの面積が比較例１の貫通孔３５ｂの面積とほぼ同じであっても幅Ｒ２を小さくできる。よって、圧電薄膜共振器のＸ方向の長さＬ０＝Ｌ１＋２×Ｒ２＋αを比較例１より小さくできる。例えば実施例１および比較例１の幅Ｒ２をそれぞれ４μｍおよび８μｍとすると、Ｌ０を８μｍ小さくできる。よって、圧電薄膜共振器を小型化できる。また、比較例１と貫通孔３５ａの面積がほぼ同じであるため、犠牲層３８のエッチング液を効率よく導入できる。 [Effect of Example 1]
According to the first embodiment, in the through hole 35a (first through hole), the width R1 in the X direction (direction along the resonance region 50) is larger than the width R2 in the Y direction (direction intersecting the along direction). As a result, the width R2 can be reduced even if the area of the through hole 35a is substantially the same as the area of the through hole 35b of Comparative Example 1. Therefore, the length L0 = L1 + 2 × R2 + α of the piezoelectric thin film resonator in the X direction can be made smaller than that of Comparative Example 1. For example, if the widths R2 of Example 1 and Comparative Example 1 are 4 μm and 8 μm, respectively, L0 can be reduced by 8 μm. Therefore, the piezoelectric thin film resonator can be miniaturized. Further, since the area of the through hole 35a is almost the same as that of Comparative Example 1, the etching solution of the sacrificial layer 38 can be efficiently introduced.

貫通孔３５ａの平面形状として外周は曲線の形状（円をつぶしたような形状）を例に説明したが、貫通孔３５ａは長方形等の多角形でもよい。貫通孔３５ａは共振領域５０の外にあれば、貫通孔３５ａの位置はいずれでもよい。また、貫通孔３５ａの個数は１個でもよく３個以上でもよい。共振領域５０の平面形状が楕円形状のように細長い場合、エッチング液を効率的に犠牲層３８に導入するためには、貫通孔３５ａは長軸の延長線上に２個あることが好ましい。 As the planar shape of the through hole 35a, a curved shape (a shape like a crushed circle) is described as an example of the outer circumference, but the through hole 35a may be a polygon such as a rectangle. As long as the through hole 35a is outside the resonance region 50, the position of the through hole 35a may be arbitrary. Further, the number of through holes 35a may be one or three or more. When the planar shape of the resonance region 50 is elongated such as an elliptical shape, it is preferable that there are two through holes 35a on the extension line of the long axis in order to efficiently introduce the etching solution into the sacrificial layer 38.

図４（ａ）および図４（ｂ）は、実施例２に係る圧電薄膜共振器の平面図である。図４（ａ）および図４（ｂ）のように、２つの貫通孔３５ａおよび３５ｂの形状が異なる。貫通孔３５ａの幅Ｒ１は貫通孔３５ｂの幅Ｒ１より大きく、貫通孔３５ａの幅Ｒ２は貫通孔３５ｂの幅Ｒ２より小さい。例えば、図４（ａ）では、貫通孔３５ａの幅Ｒ１およびＲ２はそれぞれ１６μｍおよび４μｍである。図４（ｂ）では、貫通孔３５ａの幅Ｒ１およびＲ２はそれぞれ３２μｍおよび２μｍである。図４（ａ）および図４（ｂ）では、貫通孔３５ａの幅Ｒ１およびＲ２はいずれも８μｍである。その他の構成は実施例１と同じであり説明を省略する。 4 (a) and 4 (b) are plan views of the piezoelectric thin film resonator according to the second embodiment. As shown in FIGS. 4A and 4B, the shapes of the two through holes 35a and 35b are different. The width R1 of the through hole 35a is larger than the width R1 of the through hole 35b, and the width R2 of the through hole 35a is smaller than the width R2 of the through hole 35b. For example, in FIG. 4A, the widths R1 and R2 of the through hole 35a are 16 μm and 4 μm, respectively. In FIG. 4B, the widths R1 and R2 of the through hole 35a are 32 μm and 2 μm, respectively. In FIGS. 4A and 4B, the widths R1 and R2 of the through hole 35a are both 8 μm. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

図５は、実施例３に係るフィルタの平面図である。図６（ａ）および図６（ｂ）は、図５の領域ＡおよびＢの拡大図である。図５に示すように、基板１０上に圧電薄膜共振器１８、配線２６およびパッド２２が設けられている。圧電薄膜共振器１８は実施例１、２および比較例１に係る圧電薄膜共振器である。配線２６は圧電薄膜共振器１８間を電気的に接続する。パッド２２は、外部と接続するための端子であり、例えばバンプまたはボンディングワイヤ等が接合する。配線２６およびパッド２２は、例えば金膜、アルミニウム膜または銅膜等の金属層である。 FIG. 5 is a plan view of the filter according to the third embodiment. 6 (a) and 6 (b) are enlarged views of regions A and B of FIG. As shown in FIG. 5, a piezoelectric thin film resonator 18, a wiring 26, and a pad 22 are provided on the substrate 10. The piezoelectric thin film resonator 18 is the piezoelectric thin film resonator according to Examples 1 and 2 and Comparative Example 1. The wiring 26 electrically connects the piezoelectric thin film resonators 18. The pad 22 is a terminal for connecting to the outside, and for example, a bump, a bonding wire, or the like is bonded. The wiring 26 and the pad 22 are metal layers such as, for example, a gold film, an aluminum film, or a copper film.

圧電薄膜共振器１８は、直列共振器Ｓ１からＳ４および並列共振器Ｐ１からＰ４を含む。パッド２２は、入力端子Ｉｎ、出力端子Ｏｕｔおよびグランド端子Ｇｎｄを含む。入力端子Ｉｎと出力端子Ｏｕｔとの間に直列共振器Ｓ１からＳ４が直列に、並列共振器Ｐ１からＰ４が並列に接続されている。直列共振器Ｓ４は直列に分割されている。 The piezoelectric thin film resonator 18 includes series resonators S1 to S4 and parallel resonators P1 to P4. The pad 22 includes an input terminal In, an output terminal Out, and a ground terminal Gnd. The series resonators S1 to S4 are connected in series, and the parallel resonators P1 to P4 are connected in parallel between the input terminal In and the output terminal Out. The series resonator S4 is divided in series.

図６（ａ）に示すように、隣接する直列共振器Ｓ３と並列共振器Ｐ３との間で貫通孔３５ａが近接する。貫通孔３５ａが円形の場合、直列共振器Ｓ３と並列共振器Ｐ３の貫通孔３５ａが一体となってしまう。この場合、犠牲層３８の除去が安定化しない。貫通孔３５ａを近接させないためには直列共振器Ｓ３と並列共振器Ｐ３とを離すことになり、チップサイズが大きくなる。そこで、貫通孔３５ａの平面形状を円形でなく実施例１または２のように細長い形状とする。これにより、チップサイズを大きくすることなく、直列共振器Ｓ３と並列共振器Ｐ３の貫通孔３５ａが一体となることを抑制でき、チップ面積を小さくできる。 As shown in FIG. 6A, the through hole 35a is close to the adjacent series resonator S3 and the parallel resonator P3. When the through hole 35a is circular, the through hole 35a of the series resonator S3 and the parallel resonator P3 are integrated. In this case, the removal of the sacrificial layer 38 is not stabilized. In order to keep the through holes 35a away from each other, the series resonator S3 and the parallel resonator P3 are separated from each other, and the chip size becomes large. Therefore, the planar shape of the through hole 35a is not circular but elongated as in Example 1 or 2. As a result, it is possible to prevent the series resonator S3 and the through hole 35a of the parallel resonator P3 from being integrated without increasing the chip size, and the chip area can be reduced.

図６（ｂ）に示すように、基板１０（すなわちチップ）の端部にはスクライブライン１１が設けられている。スクライブライン１１はチップを個片化するときの切断領域である。直列共振器Ｓ２と並列共振器Ｐ３の貫通孔３５ａが基板１０の端部に近接している。スクライブライン１１から一定距離Ｌ３は、パターンの配置を許容しない領域である。パターンが基板１０の端部に形成されると、パターン欠け等が生じる可能性があるため、このような配置を許可しない領域を設ける。比較例１のように円形の貫通孔３５ｂの場合、スクライブライン１１から距離Ｌ３を確保しようとすると、直列共振器Ｓ２と並列共振器Ｐ３をスクライブライン１１から離すことになり、チップ面積が大きくなる。貫通孔３５ａを実施例１または２のように細長い形状とする。これにより、チップ面積を小さくできる。 As shown in FIG. 6B, a scribe line 11 is provided at the end of the substrate 10 (that is, a chip). The scribe line 11 is a cutting region when the chips are fragmented. The through hole 35a of the series resonator S2 and the parallel resonator P3 is close to the end of the substrate 10. The constant distance L3 from the scribe line 11 is an area where the arrangement of the pattern is not allowed. If the pattern is formed at the end of the substrate 10, the pattern may be chipped or the like. Therefore, a region that does not allow such arrangement is provided. In the case of the circular through hole 35b as in Comparative Example 1, when trying to secure the distance L3 from the scribe line 11, the series resonator S2 and the parallel resonator P3 are separated from the scribe line 11, and the chip area becomes large. .. The through hole 35a has an elongated shape as in Example 1 or 2. As a result, the chip area can be reduced.

細長い貫通孔３５ａの反対側の貫通孔は細長い貫通孔３５ａでもよいし、円形の貫通孔３５ｂでもよい。 The through hole on the opposite side of the elongated through hole 35a may be an elongated through hole 35a or a circular through hole 35b.

実施例２のように、貫通孔３５ｂ（第２貫通孔）の幅Ｒ１は貫通孔３５ａ（第１貫通孔）の幅Ｒ１より小さく、貫通孔３５ｂの幅Ｒ２は貫通孔３５ａの幅Ｒ２より小さい。このように、貫通孔の形状を異ならせることで、貫通孔の形状を柔軟にすることができ、チップサイズを小さくできる。 As in the second embodiment, the width R1 of the through hole 35b (second through hole) is smaller than the width R1 of the through hole 35a (first through hole), and the width R2 of the through hole 35b is smaller than the width R2 of the through hole 35a. .. By making the shape of the through hole different in this way, the shape of the through hole can be made flexible and the chip size can be reduced.

貫通孔３５ａおよび３５ｂは共振領域５０の中心を挟んで設けられている。これにより、犠牲層３８を効率よく除去できる。しかし、貫通孔の分圧電薄膜共振器が長くなる。よって、貫通孔の少なくとも一方を細長い貫通孔３５ａとすることが好ましい。なお、共振領域５０の中心は幾何学的な中心でなくてもよい。 The through holes 35a and 35b are provided so as to sandwich the center of the resonance region 50. As a result, the sacrificial layer 38 can be efficiently removed. However, the piezoelectric thin film resonator becomes longer due to the through hole. Therefore, it is preferable that at least one of the through holes is an elongated through hole 35a. The center of the resonance region 50 does not have to be the geometric center.

特に、共振領域５０は長手方向と短手方向を有し、貫通孔３５ａおよび３５ｂが長手方向に設けられている。これにより、犠牲層３８を効率よく除去できる。しかし、圧電薄膜共振器の長さＬ０が大きくなる。よって、貫通孔の少なくとも一方を貫通孔３５ａとすることが好ましい。共振領域５０は楕円形状以外に長方形等の長手方向を有する形状であればよい。 In particular, the resonance region 50 has a longitudinal direction and a lateral direction, and through holes 35a and 35b are provided in the longitudinal direction. As a result, the sacrificial layer 38 can be efficiently removed. However, the length L0 of the piezoelectric thin film resonator becomes large. Therefore, it is preferable that at least one of the through holes is a through hole 35a. The resonance region 50 may have a shape having a longitudinal direction such as a rectangle in addition to the elliptical shape.

図６（ａ）のように、直列共振器Ｓ３の貫通孔３５ａは隣接する他の圧電薄膜共振器である並列共振器Ｐ３との間に設けられている。このように、圧電薄膜共振器の間に位置する貫通孔３５ａを細長くすることで、チップ面積を小さくできる。 As shown in FIG. 6A, the through hole 35a of the series resonator S3 is provided between the parallel resonator P3, which is another adjacent piezoelectric thin film resonator. In this way, the chip area can be reduced by elongated the through holes 35a located between the piezoelectric thin film resonators.

図６（ｂ）のように、並列共振器Ｐ３の貫通孔３５ａは共振領域５０に最も近い基板１０の端部と共振領域５０との間に設けられている。基板１０の端部と共振領域５０との間には、他の圧電薄膜共振器は設けられていない。このように、基板１０の端部に近い貫通孔３５ａを細長くすることで、チップ面積を小さくできる。 As shown in FIG. 6B, the through hole 35a of the parallel resonator P3 is provided between the end portion of the substrate 10 closest to the resonance region 50 and the resonance region 50. No other piezoelectric thin film resonator is provided between the end of the substrate 10 and the resonance region 50. In this way, the chip area can be reduced by making the through hole 35a near the end of the substrate 10 elongated.

実施例３では、ラダー型フィルタを例に説明した。ラダー型フィルタの直列共振器および並列共振器の個数は適宜設定できる。実施例１から２およびその変形例の圧電薄膜共振器はラダー型フィルタ以外に適用してもよい。 In Example 3, a ladder type filter has been described as an example. The number of series resonators and parallel resonators of the ladder type filter can be set as appropriate. The piezoelectric thin film resonators of Examples 1 and 2 and their modifications may be applied to other than the ladder type filter.

実施例４は、空隙の構成を変えた例である。図７は、実施例４に係る圧電薄膜共振器の断面図である。図７に示すように、基板１０の上面に窪みが形成されている。下部電極１２は、基板１０上に平坦に形成されている。これにより、空隙３０が、基板１０の窪みに形成されている。空隙３０は共振領域５０を含むように形成されている。その他の構成は、実施例１および２と同じであり説明を省略する。実施例４のように空隙３０の形状は任意である。 Example 4 is an example in which the configuration of the void is changed. FIG. 7 is a cross-sectional view of the piezoelectric thin film resonator according to the fourth embodiment. As shown in FIG. 7, a recess is formed on the upper surface of the substrate 10. The lower electrode 12 is formed flat on the substrate 10. As a result, the gap 30 is formed in the recess of the substrate 10. The gap 30 is formed so as to include the resonance region 50. Other configurations are the same as those of the first and second embodiments, and the description thereof will be omitted. The shape of the void 30 is arbitrary as in the fourth embodiment.

実施例５はマルチプレクサの例である。図８は、実施例５に係るデュプレクサの回路図である。図５に示すように、共通端子Ａｎｔと送信端子Ｔｘとの間に送信フィルタ４０が接続されている。共通端子Ａｎｔと受信端子Ｒｘとの間に受信フィルタ４２が接続されている。送信フィルタ４０は、送信端子Ｔｘから入力された信号のうち送信帯域の信号を送信信号として共通端子Ａｎｔに通過させ、他の周波数の信号を抑圧する。受信フィルタ４２は、共通端子Ａｎｔから入力された信号のうち受信帯域の信号を受信信号として受信端子Ｒｘに通過させ、他の周波数の信号を抑圧する。送信フィルタ４０および受信フィルタ４２の少なくとも一方を実施例３のフィルタまたは実施例１、２および３の圧電薄膜共振器を含むフィルタとすることができる。 Example 5 is an example of a multiplexer. FIG. 8 is a circuit diagram of the duplexer according to the fifth embodiment. As shown in FIG. 5, a transmission filter 40 is connected between the common terminal Ant and the transmission terminal Tx. A reception filter 42 is connected between the common terminal Ant and the reception terminal Rx. The transmission filter 40 passes a signal in the transmission band among the signals input from the transmission terminal Tx to the common terminal Ant as a transmission signal, and suppresses signals of other frequencies. The reception filter 42 passes a signal in the reception band among the signals input from the common terminal Ant to the reception terminal Rx as a reception signal, and suppresses signals of other frequencies. At least one of the transmission filter 40 and the reception filter 42 can be a filter of Example 3 or a filter including the piezoelectric thin film resonators of Examples 1, 2 and 3.

マルチプレクサの例としてデュプレクサを説明したが、トリプレクサまたはクワッドプレクサでもよい。 Although the duplexer has been described as an example of the multiplexer, it may be a triplexer or a quadplexer.

以上、本発明の実施例について詳述したが、本発明はかかる特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。 Although the examples of the present invention have been described in detail above, the present invention is not limited to such specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.

１０基板
１２下部電極
１４圧電膜
１６上部電極
１８圧電薄膜共振器
２２パッド
２６配線
３０空隙
４０送信フィルタ
４２受信フィルタ
５０共振領域
10 Substrate 12 Lower electrode 14 Piezoelectric film 16 Upper electrode 18 Piezoelectric thin film resonator 22 Pad 26 Wiring 30 Void 40 Transmission filter 42 Reception filter 50 Resonance region

Claims

With the board
With the piezoelectric film provided on the substrate,
The upper electrode provided on the piezoelectric film and
To form at least a portion of the sandwich resonance region of the piezoelectric film and the upper electrode, between the substrate and the piezoelectric film, provided through a gap between the substrate, the leads and the air gap A lower electrode having a first through hole and a second through hole outside the resonance region,
Equipped with
The first width of the first through hole in the first direction along the outer circumference at the portion closest to the first through hole in the outer circumference of the resonance region is the said in the first orthogonal direction orthogonal to the first direction. Larger than the second width of the first through hole,
The third width of the second through hole in the second direction along the outer circumference at the portion of the outer circumference closest to the second through hole is smaller than the first width and is orthogonal to the second direction. A piezoelectric thin film resonator in which the fourth width of the second through hole in the direction is larger than the second width.

The piezoelectric thin film resonator according to claim 1, wherein the third width and the fourth width are equal.

The piezoelectric thin film resonator according to claim 2, wherein the first through hole and the second through hole are provided with the center of the resonance region interposed therebetween.

The piezoelectric thin film resonator according to claim 3, wherein the resonance region has a longitudinal direction and a lateral direction, and the first through hole and the second through hole are provided in the longitudinal direction.

The first through hole is provided between the edge of the substrate closest to the resonance region and the resonance region.
No other piezoelectric thin film resonator is provided between the edge of the substrate and the resonance region .
Said second through hole, the second through-hole with respect to the resonance region and the opposite side of the end portion of the substrate, between, claims 1 to 4 in which the other piezoelectric thin-film resonators are provided The piezoelectric thin film resonator according to any one item.

The first through hole et provided between the first other piezoelectric thin-film resonators adjacent is,
The first distance between the first through hole and the through hole closest to the first through hole among the through holes of the first and other piezoelectric thin film resonators is the second through hole and the second through hole. The piezoelectric according to any one of claims 1 to 4, which is shorter than the second distance between the through hole of the second other piezoelectric thin film resonator closest to the through hole and the through hole closest to the second through hole. Thin film resonator.

The piezoelectric thin film resonator according to any one of claims 2 to 4, wherein the areas of the first through hole and the second through hole are substantially the same.

A filter including the piezoelectric thin film resonator according to any one of claims 1 to 7.

A multiplexer containing the filter according to claim 8.