JP6931120B2 - フルデジタルのモノリシックなフレーム平均化レシーバに関する非結像spadアーキテクチャの集約 - Google Patents
フルデジタルのモノリシックなフレーム平均化レシーバに関する非結像spadアーキテクチャの集約 Download PDFInfo
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Description
本出願は、その内容が、本明細書に参照によって援用される、2017年8月7日出願された米国特許出願第15/670,082号に対する優先権を主張する。
I.概要
II.例示的なシステム
III.例示的な方法
Claims (20)
- システムであって、
複数のマクロピクセルであって、前記複数のマクロピクセルの各マクロピクセルが単一光子アバランシェダイオード(SPAD)のアレイを備え、各SPADが、前記システムの外部環境から光を検出することに応じてトリガされるときに、それぞれの光信号を提供するように構成されている、複数のマクロピクセルと、
複数のパイプライン加算器であって、前記複数のパイプライン加算器の各パイプライン加算器が前記複数のマクロピクセルのそれぞれの部分に通信可能に結合されている、複数のパイプライン加算器と、
メモリおよび少なくとも1つのプロセッサを備えた制御装置であって、前記少なくとも1つのプロセッサが、動作を行うように前記メモリに格納された命令を実行し、前記動作が、
聴取期間の間に、前記複数のパイプライン加算器の各パイプライン加算器において、前記複数のマクロピクセルの前記それぞれの部分からそれぞれの光信号を受信することと、
前記複数のマクロピクセルの前記それぞれの部分からの前記それぞれの光信号に基づいて、前記複数のパイプライン加算器の各パイプライン加算器に、出力を提供させることであって、前記出力が一連のフレームを備え、前記一連のフレームの各フレームが、所与の聴取期間の間にトリガされた、前記複数のマクロピクセルの前記それぞれの部分のSPADの平均数を含む、提供させることと、を含む、制御装置と、を備える、システム。 - 前記複数のマクロピクセル、前記複数のパイプライン加算器、および前記制御装置が、モノリシックな単一チップレシーバを提供するように、基板上に配置されている、請求項1に記載のシステム。
- 前記複数のマクロピクセルが、2N個のマクロピクセルを含み、前記複数のパイプライン加算器がNビットのパイプライン加算器を含み、Nが少なくとも10である、請求項1に記載のシステム。
- 前記複数のパイプライン加算器に通信可能に結合されたフレーム集約ブロックをさらに備え、前記動作が、前記フレーム集約ブロックに、前記一連のフレームを集約させ、前記フレーム集約ブロックが、加算器回路およびデジタルバッファ回路を備え、集約されたフレームの最大数が少なくとも2Fであり、Fが少なくとも6である、請求項3に記載のシステム。
- 前記メモリが、少なくとも5キロバイト*(N+F)を含む静的ランダムアクセスメモリブロックを備え、Fが少なくとも6である、請求項4に記載のシステム。
- 前記フレーム集約ブロックに通信可能に結合されたパルス処理ブロックをさらに備え、前記動作が、前記一連のフレームに基づいて、前記パルス処理ブロックに、パルス到着時刻またはパルス強度のうちの少なくとも1つを判定させること、をさらに含む、請求項4に記載のシステム。
- 前記パルス処理ブロックが、少なくとも200,000個の抵抗トランジスタ論理(RTL)ゲートを備える、請求項6に記載のシステム。
- 出力ブロックをさらに備え、前記出力ブロックが前記パルス処理ブロックに通信可能に結合されており、前記出力ブロックが高速シリアルインターフェースを備え、前記動作が、前記処理された一連のフレームに基づいて、前記出力ブロックに、シリアル出力を提供させること、をさらに含む、請求項6に記載のシステム。
- 前記高速シリアルインターフェースが、車両制御装置または無線通信インターフェースのうちの少なくとも1つに通信可能に結合された、周辺構成要素相互接続エクスプレス(PCIe)バスを備える、請求項8に記載のシステム。
- クロック信号を提供するように構成されたクロックをさらに備え、前記複数のマクロピクセル、前記複数のパイプライン加算器、前記フレーム集約ブロック、前記パルス処理ブロック、および前記出力ブロックのうちの少なくともいくつかの動作が、前記クロック信号に基づく、請求項8に記載のシステム。
- 各SPADが、1550nmまたは780nmのうちの少なくとも1つの波長を備えた光を検出するように構成されている、請求項1に記載のシステム。
- 各マクロピクセルの光子検出効率が、所与のマクロピクセルにおけるSPADフィルファクタを乗じた所与のSPADの光子検出確率(PDP)を含み、各マクロピクセルの前記光子検出効率が少なくとも8%である、請求項1に記載のシステム。
- 前記聴取期間が、300ピコ秒以上、500ピコ秒以下の範囲内にある、請求項1に記載のシステム。
- 各マクロピクセルに結合された、マイクロレンズアレイをさらに備える、請求項1に記載のシステム。
- 各マクロピクセルが、1024個または2048個のうちの少なくとも1つの個数のSPADを備える、請求項1に記載のシステム。
- 前記複数のマクロピクセルが、16個、32個、または64個のうちの少なくとも1つの個数のマクロピクセルを備える、請求項1に記載のシステム。
- 聴取期間の間に、複数のパイプライン加算器の各パイプライン加算器において、複数のマクロピクセルのそれぞれの部分からそれぞれの光信号を受信することであって、前記複数のマクロピクセルの各マクロピクセルが単一光子アバランシェダイオード(SPAD)のアレイを備え、各SPADが、外部環境から光を検出することに応じてトリガされるときに、それぞれの光信号を提供するように構成されており、前記複数のパイプライン加算器の各パイプライン加算器が、前記複数のマクロピクセルのそれぞれの部分に通信可能に結合されている、受信することと、
前記複数のマクロピクセルの前記それぞれの部分からの前記それぞれの光信号に基づいて、前記複数のパイプライン加算器の各パイプライン加算器に、出力を提供させることであって、前記出力が一連のフレームを備え、前記一連のフレームの各フレームが、所与の聴取期間の間にトリガされた、前記複数のマクロピクセルの前記それぞれの部分のSPADの平均数を含む、提供させることと、を含む、方法。 - フレーム集約ブロックに、前記一連のフレームを集約させること、をさらに含み、前記フレーム集約ブロックが、加算器回路およびデジタルバッファ回路を備え、集約されたフレームの最大数が少なくとも2Fであり、Fが少なくとも6である、請求項17に記載の方法。
- 前記一連のフレームに基づいて、パルス処理ブロックに、パルス到着時刻またはパルス強度のうちの少なくとも1つを判定させること、をさらに含む、請求項18に記載の方法。
- 前記処理された一連のフレームに基づいて、出力ブロックに、シリアル出力を提供させること、をさらに含む、請求項19に記載の方法。
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US15/670,082 | 2017-08-07 | ||
US15/670,082 US10677899B2 (en) | 2017-08-07 | 2017-08-07 | Aggregating non-imaging SPAD architecture for full digital monolithic, frame averaging receivers |
PCT/US2018/044979 WO2019032370A1 (en) | 2017-08-07 | 2018-08-02 | NON-IMAGING SPAD ARCHITECTURE AGGREGATION FOR COMPLETELY DIGITAL MONOLITHIC FRAME RECEIVERS |
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US11105925B2 (en) | 2017-03-01 | 2021-08-31 | Ouster, Inc. | Accurate photo detector measurements for LIDAR |
US10677899B2 (en) * | 2017-08-07 | 2020-06-09 | Waymo Llc | Aggregating non-imaging SPAD architecture for full digital monolithic, frame averaging receivers |
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