JP6930317B2 - Terminal pin joining method and joining jig - Google Patents

Terminal pin joining method and joining jig Download PDF

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JP6930317B2
JP6930317B2 JP2017175314A JP2017175314A JP6930317B2 JP 6930317 B2 JP6930317 B2 JP 6930317B2 JP 2017175314 A JP2017175314 A JP 2017175314A JP 2017175314 A JP2017175314 A JP 2017175314A JP 6930317 B2 JP6930317 B2 JP 6930317B2
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substrate
terminal pin
joining
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holding
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JP2019054025A (en
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下田 将義
将義 下田
外薗 洋昭
洋昭 外薗
光利 澤野
光利 澤野
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Fuji Electric Co Ltd
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Description

本発明は、電気機器、電子機器、通信機器等の配線接続及び部品の接続等に用いる実装技術分野において利用される端子ピンの接合方法及び接合用冶具に関する。 The present invention relates to a terminal pin joining method and a joining jig used in the field of mounting technology used for wiring connection of electrical equipment, electronic equipment, communication equipment, etc. and connection of parts.

実装技術分野では、構造体の孔内に半田が充填されてリード線等の挿入実装部品を固着する半田付け構造が提案されている(例えば、特許文献1)。 In the field of mounting technology, a soldering structure has been proposed in which solder is filled in a hole of a structure to fix an insertion mounting component such as a lead wire (for example, Patent Document 1).

また、複数の端子ピンを治具にエア吸着させ、基板上でエア加圧により押し付けた状態で端子ピンを接合する技術も提案されている(例えば、特許文献2)。 Further, a technique has also been proposed in which a plurality of terminal pins are attracted to a jig with air and the terminal pins are joined in a state of being pressed by air pressurization on a substrate (for example, Patent Document 2).

特開2007‐181880号公報Japanese Unexamined Patent Publication No. 2007-181880 特開2000−349220号公報Japanese Unexamined Patent Publication No. 2000-349220

特許文献1の技術における半田付け構造は、リード線を基板上にフロー半田付けして予め実装された後に表面実装部品を搭載して混載実装する際、リフロー半田付け温度をフロー半田付けに用いた半田材の融点以上に設定すると、リード線のフロー半田付け部が再溶融する。よって、リード線のフロー半田付け部が再溶融する結果、リード線のリード線が傾く、又は、リード線が基板上から浮く、若しくは、脱離する等、半田付け不良が生じることが懸念される。また、リード線が傾いて垂直度を保てない現象が生じる要因として、基板の反りにともなう、スルーホールの傾斜も挙げられる。 In the soldering structure in the technique of Patent Document 1, the reflow soldering temperature is used for flow soldering when the lead wires are flow-soldered on the substrate and mounted in advance, and then the surface mount components are mounted and mixed-mounted. If it is set above the melting point of the solder material, the flow soldered portion of the lead wire will be remelted. Therefore, as a result of the remelting of the flow soldered portion of the lead wire, there is a concern that the lead wire of the lead wire may be tilted, or the lead wire may float or come off from the substrate, resulting in soldering failure. .. Further, as a factor that causes a phenomenon that the lead wire is tilted and the verticality cannot be maintained, there is also the tilt of the through hole due to the warp of the substrate.

さらに、特許文献2の技術では、エア加圧により押し付けた状態で端子ピン等の挿入実装部品を接合する際に基板の反り防止対策がないので、加熱接合後に端子ピンが傾くおそれがあった。さらに、エア加圧なので基板に対する端子ピンの押し付け力が弱く、基板に対して端子ピンが不安定である問題があった。 Further, in the technique of Patent Document 2, since there is no measure to prevent warpage of the substrate when joining the through-hole mounting parts such as terminal pins in a state of being pressed by air pressurization, there is a possibility that the terminal pins may be tilted after heat joining. Further, since the air is pressurized, the pressing force of the terminal pin against the substrate is weak, and there is a problem that the terminal pin is unstable with respect to the substrate.

したがって、本発明の目的は、部品の実装工程中に半田が再溶融した際に生じる端子ピンの傾きを補正できる端子ピンの接合方法及び接合用冶具を提供することにある。 Therefore, an object of the present invention is to provide a terminal pin joining method and a joining jig that can correct the inclination of the terminal pins that occurs when the solder is remelted during the component mounting process.

上記目的を達成するため、本発明の端子ピンの接合方法は、基板上に半導体チップが搭載された半導体装置の前記半導体チップ上及び前記基板上の少なくとも一方に、端子ピンを立設して接合する接合方法において、
前記半導体チップ上及び前記基板上の少なくとも一方に、前記端子ピンの一端を、接合材を介して当接させて、前記端子ピンを立設する工程と、
前記端子ピンの他端を治具により保持して、前記端子ピンの姿勢を保持する姿勢保持工程と、
前記基板を前記治具により保持して、前記基板の反りを抑制する基板の形状維持工程と、
前記端子ピン及び前記基板を前記治具で保持した状態で、加熱・冷却して、前記接合材を溶融・固化させ、前記端子ピンを固着する工程と、
を含むことを特徴とする。
In order to achieve the above object, in the method of joining terminal pins of the present invention, terminal pins are erected and joined on at least one of the semiconductor chip and the substrate of a semiconductor device in which a semiconductor chip is mounted on a substrate. In the joining method
A step of erection of the terminal pin by bringing one end of the terminal pin into contact with at least one of the semiconductor chip and the substrate via a bonding material.
A posture holding step of holding the other end of the terminal pin with a jig to hold the posture of the terminal pin,
The process of maintaining the shape of the substrate by holding the substrate with the jig and suppressing the warp of the substrate, and the process of maintaining the shape of the substrate.
A step of heating and cooling the terminal pin and the substrate with the jig to melt and solidify the bonding material and fix the terminal pin.
It is characterized by including.

本発明の端子ピンの接合方法によれば、端子ピンの姿勢を保持する姿勢保持工程により端子ピンの基板に対する垂直度を維持し、形状維持工程により基板の反りを抑制するので、部品の実装工程中に半田が再溶融した際に生じる端子ピンの傾きを補正できと共に、基板の反りを抑制できる。 According to the terminal pin joining method of the present invention, the posture holding step of holding the posture of the terminal pin maintains the verticality of the terminal pin with respect to the substrate, and the shape maintaining step suppresses the warp of the substrate. The inclination of the terminal pin generated when the solder is remelted inside can be corrected, and the warp of the substrate can be suppressed.

本発明の端子ピンの接合方法の一つの態様においては、
前記治具は、前記基板が載置される支持板と、
前記支持板における前記基板の周りに一端が固着され且つ立設されるフレームと、
前記フレームの他端部に設けられ且つ前記基板から突出する端子ピンの先端を保持する凹部を有する押さえ板と、
前記基板の周縁部を前記支持板との間で挟持する把持板と、
を備え、
前記姿勢保持工程において、前記基板を前記支持板上に載置し、前記端子ピンの他端を前記凹部に嵌合させて、前記押さえ板で前記端子ピンの他端を保持することが好ましい。この態様によれば、端子ピンの先端を保持する凹部を有する押さえ板で当該先端を確保するので、端子ピンの垂直度が安定する。
In one aspect of the terminal pin joining method of the present invention,
The jig includes a support plate on which the substrate is placed and a support plate on which the substrate is placed.
A frame in which one end is fixed and erected around the substrate in the support plate, and
A holding plate provided at the other end of the frame and having a recess for holding the tip of a terminal pin protruding from the substrate.
A grip plate that sandwiches the peripheral edge of the substrate between the support plate and
With
In the posture holding step, it is preferable that the substrate is placed on the support plate, the other end of the terminal pin is fitted into the recess, and the other end of the terminal pin is held by the holding plate. According to this aspect, since the tip is secured by the holding plate having the recess for holding the tip of the terminal pin, the verticality of the terminal pin is stabilized.

本発明の端子ピンの接合方法の一つの態様においては、
前記形状維持工程において、前記基板の周囲に配置された把持板により、前記支持板との間で前記基板の周縁部を挟持して前記基板の反りを抑制する、ことが好ましい。この態様によれば、把持板によりリフロー時の基板の周縁部の支持板への密着度が向上する。
In one aspect of the terminal pin joining method of the present invention,
In the shape maintaining step, it is preferable that the grip plate arranged around the substrate sandwiches the peripheral edge portion of the substrate with the support plate to suppress the warp of the substrate. According to this aspect, the grip plate improves the degree of adhesion of the peripheral edge portion of the substrate to the support plate during reflow.

本発明の端子ピンの接合用冶具は、
基板上に半導体チップが搭載された半導体装置の前記半導体チップ上及び前記基板上の少なくとも一方に、端子ピンを立設して接合するための端子ピンの接合用冶具において、
前記基板が載置される支持板と、
前記支持板における前記基板の周りに一端が固着され且つ立設されるフレームと、
前記フレームの他端部に設けられ且つ前記基板から突出する端子ピンの先端を保持する凹部を有する押さえ板と、
前記基板の周縁部を前記支持板との間で挟持する把持板と、
を備えることを特徴とする。
The jig for joining the terminal pin of the present invention
In a jig for joining terminal pins for erected and joining terminal pins on at least one of the semiconductor chip and the substrate of a semiconductor device in which a semiconductor chip is mounted on a substrate.
A support plate on which the substrate is placed and
A frame in which one end is fixed and erected around the substrate in the support plate, and
A holding plate provided at the other end of the frame and having a recess for holding the tip of a terminal pin protruding from the substrate.
A grip plate that sandwiches the peripheral edge of the substrate between the support plate and
It is characterized by having.

本発明の端子ピンの接合用冶具によれば、実装工程での基板の反りにともなう端子ピンの傾きを抑制するとともに、表面実装部品の半田付け部が再溶融する場合にも、端子ピンを保持し、端子ピンの姿勢制御できるので、端子ピンが混載実装された構造体の接合信頼性を確保することが可能となる。 According to the jig for joining terminal pins of the present invention, the inclination of the terminal pins due to the warp of the substrate in the mounting process is suppressed, and the terminal pins are held even when the soldered portion of the surface mount component is remelted. However, since the attitude of the terminal pins can be controlled, it is possible to ensure the joining reliability of the structure in which the terminal pins are mixedly mounted.

本発明の端子ピンの接合用冶具の一つの態様においては、
前記押さえ板の前記凹部はテーパー状の内側面を有することが好ましい。この態様によれば、凹部にテーパー状の内側面があるので、基板の反りにともなう端子ピンの傾きを抑制し、且つ、半導体チップ下半田接合部が再溶融したときの半導体チップ傾きにともなう端子ピンの傾きを補正し、垂直度を保つことができる。
In one aspect of the terminal pin joining jig of the present invention,
The recess of the holding plate preferably has a tapered inner surface. According to this aspect, since the concave portion has a tapered inner surface, the inclination of the terminal pin due to the warp of the substrate is suppressed, and the terminal due to the inclination of the semiconductor chip when the solder joint under the semiconductor chip is remelted. The inclination of the pin can be corrected and the verticality can be maintained.

本発明の端子ピンの接合方法によれば、実装工程中に生じる基板の反りを抑制しつつ、凹部付き治具にて端子ピンの先端を固定することで、実装工程中に半田が再溶融した際に生じる端子ピンの傾きを補正することができる。 According to the terminal pin joining method of the present invention, the solder was remelted during the mounting process by fixing the tip of the terminal pin with a jig with a recess while suppressing the warpage of the substrate that occurs during the mounting process. It is possible to correct the inclination of the terminal pin that occurs at that time.

本発明の実施形態の端子ピンの接合方法により作製される端子ピンが半田付けされた構造体の模式的な断面図である。It is a schematic cross-sectional view of the structure in which the terminal pin produced by the method of joining the terminal pin of the embodiment of this invention is soldered. 実施形態の端子ピンの接合用冶具の模式的な斜視図である。It is a schematic perspective view of the jig for joining a terminal pin of an embodiment. 実施形態の端子ピンの接合用冶具により、基板上に半導体チップが予め搭載されている半導体チップ上に端子ピンが立設保持された様子を示す模式的な斜視図である。FIG. 5 is a schematic perspective view showing a state in which a terminal pin is erected and held on a semiconductor chip in which a semiconductor chip is preliminarily mounted on a substrate by a jig for joining the terminal pin of the embodiment. 図3のXX線に沿った端子ピンの接合用冶具及び基板等の模式的な断面図である。FIG. 3 is a schematic cross-sectional view of a jig for joining terminal pins, a substrate, and the like along the XX line of FIG. 本発明の実施形態の端子ピンの接合用冶具における押さえ板の作用面を示す平面図である。It is a top view which shows the working surface of the holding plate in the jig for joining a terminal pin of embodiment of this invention. 本発明の実施形態の端子ピンの接合用冶具における押さえ板を外した状態を示す上面図である。It is a top view which shows the state which the holding plate is removed in the jig for joining a terminal pin of embodiment of this invention. 本発明の実施形態の端子ピンの接合用冶具における押さえ板の一部の模式的な拡大部分断面図である。It is a schematic enlarged partial cross-sectional view of a part of a holding plate in the jig for joining a terminal pin of embodiment of this invention. 本発明の実施形態の端子ピンの接合用冶具における押さえ板の一部の模式的な拡大部分断面図である。It is a schematic enlarged partial cross-sectional view of a part of a holding plate in the jig for joining a terminal pin of embodiment of this invention. 本発明の実施形態の端子ピンの接合方法により作製される端子ピンが半田付けされた他の構造体の模式的な断面図である。It is a schematic cross-sectional view of another structure in which the terminal pin produced by the method of joining the terminal pin of the embodiment of this invention is soldered. 本発明の実施形態の端子ピンの接合方法のプロセスフロー図である。It is a process flow diagram of the connection method of the terminal pin of the embodiment of this invention. 本発明の実施形態の端子ピンの接合方法の要部の工程における接合用冶具及び基板等の模式的な断面図である。It is a schematic cross-sectional view of the joining jig, the substrate and the like in the process of the main part of the joining method of the terminal pin of the embodiment of this invention. 本発明の実施例の一部の工程(S3)及び(S8)の半導体チップ接合の温度プロファイル及び端子ピン接合の温度プロファイルを示すグラフである。It is a graph which shows the temperature profile of the semiconductor chip junction and the temperature profile of the terminal pin junction of a part of steps (S3) and (S8) of the Example of this invention. 本発明の実施例による基板の反り量の測定結果と予備試験とによる基板の反り量の測定結果を示すグラフである。It is a graph which shows the measurement result of the warpage amount of a substrate by the Example of this invention, and the measurement result of the warpage amount of a substrate by a preliminary test.

以下、本発明の端子ピンの接合用冶具と端子ピンの接合方法の実施形態について、図面を参照しつつ具体的に説明する。なお、図面において同一の構成要素については、同一の符号を付け、重複する構成要素の説明は省略する。 Hereinafter, embodiments of the terminal pin joining jig and the terminal pin joining method of the present invention will be specifically described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and the description of the overlapping components will be omitted.

(端子ピンが半田付けされた構造体)
まず、実施形態の端子ピンの接合方法により作製される端子ピンが半田付けされた構造体について説明する。
(Structure with soldered terminal pins)
First, a structure in which the terminal pins manufactured by the method of joining the terminal pins of the embodiment are soldered will be described.

図1に、実施形態の端子ピンの接合方法により作製される端子ピンが半田付けされた構造体1の模式的な断面図を示す。当該端子ピンが半田付けされた構造体がパワー半導体モジュールに用いられる部品である場合を説明するが、本発明はこれに限定されず、端子ピン以外の挿入実装部品に適用できる。 FIG. 1 shows a schematic cross-sectional view of the structure 1 to which the terminal pins manufactured by the method of joining the terminal pins of the embodiment are soldered. The case where the structure to which the terminal pin is soldered is a component used for a power semiconductor module will be described, but the present invention is not limited to this, and can be applied to an insertion mounting component other than the terminal pin.

図1において、当該端子ピンが半田付けされた構造体1は、基板2と、該基板上の半導体チップ3と、該半導体チップ上の端子ピン4とを備えている。基板2(回路板2b)と半導体チップ3は、例えば半田5等の接合材により電気的に接続されている。半導体チップ3と端子ピン4も半田5等の接合材により電気的に接続されている。 In FIG. 1, the structure 1 to which the terminal pins are soldered includes a substrate 2, a semiconductor chip 3 on the substrate, and a terminal pin 4 on the semiconductor chip. The substrate 2 (circuit board 2b) and the semiconductor chip 3 are electrically connected by a bonding material such as solder 5. The semiconductor chip 3 and the terminal pin 4 are also electrically connected by a bonding material such as solder 5.

基板2は、絶縁板2aと、絶縁板2aのおもて面すなわち主面に設けられた回路板2bと、絶縁板2aの裏面に設けられた金属板2cとが積層された積層基板である。絶縁板2aは例えば窒化珪素、窒化アルミニウム、酸化アルミニウム等の絶縁性セラミックスからなる。回路板2b及び金属板2cは、例えば銅等の金属からなる。そして回路板2bは、絶縁板2a上に選択的に形成されていて、これにより所定の電気回路(図示せず)を構成している。基板2の積層基板として、例えばDCB(Direct Copper Bonding)基板等を用いることができる。DCB基板は、絶縁板2aに銅等からなる回路板2b、金属板2cが直接接合されている基板である。絶縁板2aが絶縁性のため、回路板2bと金属板2cとは電気的に絶縁されている。 The substrate 2 is a laminated substrate in which an insulating plate 2a, a circuit plate 2b provided on the front surface, that is, the main surface of the insulating plate 2a, and a metal plate 2c provided on the back surface of the insulating plate 2a are laminated. .. The insulating plate 2a is made of insulating ceramics such as silicon nitride, aluminum nitride, and aluminum oxide. The circuit plate 2b and the metal plate 2c are made of a metal such as copper. The circuit plate 2b is selectively formed on the insulating plate 2a, thereby forming a predetermined electric circuit (not shown). As the laminated substrate of the substrate 2, for example, a DCB (Direct Copper Bonding) substrate or the like can be used. The DCB substrate is a substrate in which a circuit plate 2b made of copper or the like and a metal plate 2c are directly bonded to the insulating plate 2a. Since the insulating plate 2a is insulating, the circuit plate 2b and the metal plate 2c are electrically insulated from each other.

半導体チップ3は、特に限定されないが、例えばIGBT(Insulated Gate Bipolar Transistor)やパワーMOSFET(Metal Oxide Semiconductor Field Effect Transistor)やFWD(Free Wheeling Diode)であってもよいし、これらを一つの半導体チップの中で縦方向に形成されたRB−IGBT(Reverse Blocking-Insulated Gate Bipolar Transistor )やRC−IGBT(Reverse Conducting-Insulated Gate Bipolar Transistor)であってもよい。SiCからなる半導体チップ(例えばSiC−MOSFET)は、シリコンからなる半導体チップに比べて高耐圧で、且つ高周波でのスイッチングが可能である。 The semiconductor chip 3 is not particularly limited, and may be, for example, an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or an FWD (Free Wheeling Diode). It may be an RB-IGBT (Reverse Blocking-Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) formed in the vertical direction. A semiconductor chip made of SiC (for example, SiC-MOSFET) has a higher withstand voltage than a semiconductor chip made of silicon and can switch at a high frequency.

半導体チップ3には、図示しないが、おもて面と裏面を備える半導体基板に縦型のスイッチング素子が設けられてもよい。半導体チップ3は、そのおもて面に主電極(図示せず)を備え、その裏面にも電極(図示せず)を備えていてもよい。例えば半導体チップ3がIGBTである場合には、おもて面には、主電極のエミッタ電極及びゲート電極が形成され、裏面にはコレクタ電極が形成されていてもよい。 Although not shown, the semiconductor chip 3 may be provided with a vertical switching element on a semiconductor substrate having a front surface and a back surface. The semiconductor chip 3 may have a main electrode (not shown) on its front surface and an electrode (not shown) on its back surface. For example, when the semiconductor chip 3 is an IGBT, the emitter electrode and the gate electrode of the main electrode may be formed on the front surface, and the collector electrode may be formed on the back surface.

端子ピン4は、一端及び他端を備える棒状の導電部材であり、一端が例えば半田5等の接合材を介して半導体チップ3に電気的且つ機械的に接続されている。端子ピン4の他端は、半導体チップ3に対向して配置され得る配線基板(図示せず)に電気的且つ機械的に接続されることができる。なお、図示しない配線基板と端子ピン4とは、例えば、配線基板の所定の位置に形成されている孔に端子ピン4を圧入することにより電気的且つ機械的に接続される。圧入の他、半田やロウ付け、又はカシメによることもできる。 The terminal pin 4 is a rod-shaped conductive member having one end and the other end, and one end is electrically and mechanically connected to the semiconductor chip 3 via a bonding material such as solder 5. The other end of the terminal pin 4 can be electrically and mechanically connected to a wiring board (not shown) that can be arranged to face the semiconductor chip 3. The wiring board and the terminal pin 4 (not shown) are electrically and mechanically connected, for example, by press-fitting the terminal pin 4 into a hole formed at a predetermined position on the wiring board. In addition to press fitting, soldering, brazing, or caulking can also be used.

端子ピン4は、例えば互いに平行な平坦な両端面を備える円柱や角柱等のピン形状を有し、銅等の電気抵抗が低く、熱伝導率が高い金属材料から形成される。端子ピン4は、1つの半導体チップ3のおもて面上に、複数個の端子ピンを配置することが好ましい。こうすることによって、半導体チップ3から配線基板(図示せず)への熱伝導性を向上させることができる。 The terminal pin 4 has a pin shape such as a cylinder or a prism having flat both end surfaces parallel to each other, and is formed of a metal material such as copper having low electrical resistance and high thermal conductivity. It is preferable that a plurality of terminal pins 4 are arranged on the front surface of one semiconductor chip 3. By doing so, the thermal conductivity from the semiconductor chip 3 to the wiring board (not shown) can be improved.

半田5は、Sn−Ag系、Sn−Cu系、Sn−Sb系、Sn−Sb−Ag系等の半田材料を用いることができる。パワー半導体モジュール1において、各々の接合に半田5として同じ半田材料を用いてもよいし、例えば、半導体チップ3及び回路板2bを接合する半田5と半導体チップ3及び端子ピン4を接合する半田5とに異なる半田材料を用いてもよい。 As the solder 5, a solder material such as Sn-Ag type, Sn-Cu type, Sn-Sb type, Sn-Sb-Ag type and the like can be used. In the power semiconductor module 1, the same solder material may be used as the solder 5 for each joining. For example, the solder 5 for joining the semiconductor chip 3 and the circuit board 2b and the solder 5 for joining the semiconductor chip 3 and the terminal pin 4 are joined. A different solder material may be used.

(端子ピンの接合用冶具)
次に、実施形態の端子ピンの接合方法に用いられる端子ピンの接合用冶具について説明する。
(Jig for joining terminal pins)
Next, a jig for joining the terminal pins used in the method for joining the terminal pins of the embodiment will be described.

図2に、実施形態の端子ピンの接合方法に用いられる端子ピンの接合用冶具10の模式的な斜視図を示す。図3は、端子ピンの接合用冶具10により、基板2上に半導体チップ3が予め搭載されている半導体チップ3上に端子ピン4が立設するように、保持された様子を示す模式的な斜視図である。図4は、図3のXX線に沿った端子ピンの接合用冶具10及び基板2等の模式的な断面図である。 FIG. 2 shows a schematic perspective view of the terminal pin joining jig 10 used in the terminal pin joining method of the embodiment. FIG. 3 is a schematic view showing a state in which the terminal pin 4 is held by the terminal pin joining jig 10 so that the terminal pin 4 is erected on the semiconductor chip 3 on which the semiconductor chip 3 is previously mounted on the substrate 2. It is a perspective view. FIG. 4 is a schematic cross-sectional view of a jig 10 for joining terminal pins and a substrate 2 along the XX line of FIG.

かかる接合用冶具10は、基板2が載置される四角形の支持板SPと、支持板SPにおける基板2の周りに一端が固着され且つ立設されるフレームFRと、フレームFRの他端部に設けられた押さえ板PP、基板2の周縁部を支持板SPとの間で挟持する把持板PH(基板反り抑制治具とも呼ぶ)と、から構成される。 The joining jig 10 is provided on a rectangular support plate SP on which the substrate 2 is placed, a frame FR whose one end is fixed and erected around the substrate 2 in the support plate SP, and the other end of the frame FR. It is composed of a holding plate PP provided, and a grip plate PH (also referred to as a substrate warpage suppressing jig) that sandwiches the peripheral edge portion of the substrate 2 with the support plate SP.

四角のフレームFRには四つの脚部FL(各一端)がそれぞれ含まれ、四角形の支持板SPの四隅にそれぞれ固着されている。 The quadrangular frame FR includes four leg FLs (each end) and is fixed to the four corners of the quadrangular support plate SP.

フレームFRの枠本体(他端の段差部)には四角形の押さえ板PPが嵌合されている。押さえ板PPのおもて面の四隅は、それぞれ保持加圧用ネジPPbにより、支持板SPに向かうように所定圧力で加圧されつつ保持されている。 A quadrangular holding plate PP is fitted to the frame body (the stepped portion at the other end) of the frame FR. The four corners of the front surface of the pressing plate PP are held by the holding and pressurizing screws PPb while being pressurized at a predetermined pressure toward the support plate SP.

押さえ板PPの裏面(作用面)の略中央には、図5に示すように、複数の凹部RCが形成されている。この実施形態では、3×3のマトリクス上に配置された9つの凹部RCが形成されている。凹部RCは基板2から突出する端子ピン4の先端をそれぞれ保持する。 As shown in FIG. 5, a plurality of recesses RC are formed substantially in the center of the back surface (working surface) of the pressing plate PP. In this embodiment, nine recesses RC arranged on a 3 × 3 matrix are formed. The recess RC holds the tip of the terminal pin 4 protruding from the substrate 2, respectively.

基板2は、図6に示すように、支持板SPのおもて面の略中央に位置合わせして載置され、その周縁部(四隅)が支持板SPとの間で把持板PHにより挟持されている。基板2のおもて面の四隅は、それぞれ把持板PHと保持加圧用ネジPHbにより、支持板SPに向かうように所定圧力で加圧されつつ保持されている。基板2のおもて面の略中央には、図6に示すように、3×3のマトリクス上に配置された9組の半導体チップ3と端子ピン4が載置されている。 As shown in FIG. 6, the substrate 2 is placed so as to be positioned substantially at the center of the front surface of the support plate SP, and its peripheral edges (four corners) are sandwiched between the support plate SP and the support plate SP by the grip plate PH. Has been done. The four corners of the front surface of the substrate 2 are held while being pressed at a predetermined pressure toward the support plate SP by the grip plate PH and the holding pressurizing screw PHb, respectively. As shown in FIG. 6, nine sets of semiconductor chips 3 and terminal pins 4 arranged on a 3 × 3 matrix are placed substantially in the center of the front surface of the substrate 2.

図4に示すように、基板2上に半導体チップ3が予め搭載されている半導体チップ3上に立設する端子ピン4は、端子ピンの接合用冶具10により、支持板SPと押さえ板PPの間において所定圧力で加圧されつつ保持される。この状態でリフロー処理が行われる。 As shown in FIG. 4, the terminal pin 4 standing on the semiconductor chip 3 on which the semiconductor chip 3 is mounted in advance on the substrate 2 is made of a support plate SP and a holding plate PP by a jig 10 for joining the terminal pins. It is held while being pressurized at a predetermined pressure between them. The reflow process is performed in this state.

図7に示すように、端子ピン4の先端を保持する押さえ板PPの凹部RCは、テーパー状の内側面12(内周傾斜面)を有する。この実施形態の凹部RCは円錐台形状の凹部であり、図7に示すように、中央の底面11を包囲して内周傾斜面12が形成されて構成される。テーパー状の内側面12において、底面11と内周傾斜面12の成すテーパー角度θは90度以上150度以下が好ましく、90度以上120度以下がより好ましい。円錐台形状の凹部RCにより、端子ピン4の嵌合の際に基板2に対する端子ピン4の位置合わせが確実となる。なお、凹部RCの断面形状は、図8に示すような断面矩形状、すなわち角度θ=90°となる形状であってもよい。このような形状としては、円柱形状をなす凹部が挙げられる。端子ピン4の直径及び端子ピン傾きの許容値から、テーパー角度並びに、端子ピン4の側面及び内側面12の間のクリアランス量を決定すればよい。 As shown in FIG. 7, the recess RC of the holding plate PP that holds the tip of the terminal pin 4 has a tapered inner side surface 12 (inner peripheral inclined surface). The recess RC of this embodiment is a truncated cone-shaped recess, and as shown in FIG. 7, an inner peripheral inclined surface 12 is formed so as to surround the central bottom surface 11. In the tapered inner surface 12, the taper angle θ formed by the bottom surface 11 and the inner peripheral inclined surface 12 is preferably 90 degrees or more and 150 degrees or less, and more preferably 90 degrees or more and 120 degrees or less. The truncated cone-shaped recess RC ensures that the terminal pins 4 are aligned with the substrate 2 when the terminal pins 4 are fitted. The cross-sectional shape of the recess RC may be a rectangular cross-sectional shape as shown in FIG. 8, that is, a shape having an angle θ = 90 °. Examples of such a shape include a recess having a cylindrical shape. The taper angle and the clearance amount between the side surface and the inner side surface 12 of the terminal pin 4 may be determined from the allowable values of the diameter of the terminal pin 4 and the inclination of the terminal pin.

接合用冶具10における、支持板SP、フレームFR、押さえ板PP及び把持板PHは例えば、ファインセラミックスから構成される。 The support plate SP, the frame FR, the holding plate PP, and the grip plate PH in the joining jig 10 are made of, for example, fine ceramics.

なお、上記の実施形態例では、端子ピン4が基板2上に予め搭載された半導体チップ3上に半田5を介して立設した構造体の場合を説明したが、本発明はこれには限定されず、図9に示すように、端子ピン4が基板2上に半田5のみを介して直接立設したものを含む場合にも適用できる。 In the above embodiment, the case where the terminal pin 4 is erected on the semiconductor chip 3 mounted in advance on the substrate 2 via the solder 5 has been described, but the present invention is limited to this. However, as shown in FIG. 9, it can be applied to the case where the terminal pin 4 is directly erected on the substrate 2 only through the solder 5.

(端子ピンの接合方法)
図10は端子ピンの接合方法のプロセスフロー図である。
(How to join terminal pins)
FIG. 10 is a process flow diagram of a method of joining terminal pins.

端子ピンの接合方法は、基板上の所定位置に半田を塗布し(S1)、当該半田上に半導体チップを搭載し(S2)、基板に半導体チップを加熱接合し(S3)、基板上の半導体チップのおもて面等に半田を塗布し(S4)、当該半田上に端子ピンを立設・搭載し(S5)、治具により端子ピンの姿勢を保持し(S6)、基板を治具により保持して基板の反りを抑制し(S7)、基板等に端子ピンを加熱接合(S8)する工程を、を含む。 The terminal pin bonding method is as follows: a solder is applied to a predetermined position on a substrate (S1), a semiconductor chip is mounted on the solder (S2), a semiconductor chip is heat-bonded to the substrate (S3), and a semiconductor on the substrate is bonded. Solder is applied to the front surface of the chip (S4), terminal pins are erected and mounted on the solder (S5), the posture of the terminal pins is held by a jig (S6), and the substrate is used as a jig. (S7) includes a step of heat-bonding the terminal pins to the substrate or the like (S8).

端子ピンの接合方法の要部の工程(S4)〜(S7)について図11を参照しつつ説明する。ここでは、上記工程(S1)〜(S3)により、半導体チップ3が基板2上に半田(図示せず)を介して予め搭載されているものとする。また、基板2上に予め搭載された半導体チップ3上に端子ピン4を半田5を介して立設させ、且つ端子ピン4を基板2上に半田5のみを介して直接立設させる構造体(図9)の場合の端子ピンの接合方法を説明する。 The main steps (S4) to (S7) of the terminal pin joining method will be described with reference to FIG. Here, it is assumed that the semiconductor chip 3 is pre-mounted on the substrate 2 via solder (not shown) by the above steps (S1) to (S3). Further, a structure in which the terminal pins 4 are erected on the semiconductor chip 3 mounted in advance on the substrate 2 via the solder 5, and the terminal pins 4 are erected directly on the substrate 2 via the solder 5 only. The method of joining the terminal pins in the case of FIG. 9) will be described.

工程(S4)において、図11(a)に示すように、フレームFRの脚部に囲まれる支持板SPの中央に基板2を載置した後、半導体チップ3上及び基板2の所定位置上に半田5を塗布する。 In the step (S4), as shown in FIG. 11A, after the substrate 2 is placed in the center of the support plate SP surrounded by the legs of the frame FR, the substrate 2 is placed on the semiconductor chip 3 and on the predetermined positions of the substrate 2. Apply solder 5.

工程(S5)において、図11(b)に示すように、半導体チップ3上及び基板2上の半田5上の少なくとも一方に、それぞれ端子ピン4の一端を、当接させて、端子ピン4を立設する。 In the step (S5), as shown in FIG. 11B, one end of the terminal pin 4 is brought into contact with at least one of the semiconductor chip 3 and the solder 5 on the substrate 2, respectively, and the terminal pin 4 is brought into contact with the terminal pin 4. Stand up.

工程(S6)において、図11(c)に示すように、フレームFRの他端部に設けられた押さえ板PPの凹部RCに端子ピン4の他端を挿入し、保持加圧用ネジPPbにより、押さえ板PPで端子ピン4の他端を押圧して、端子ピン4の姿勢を保持する。 In the step (S6), as shown in FIG. 11C, the other end of the terminal pin 4 is inserted into the recess RC of the holding plate PP provided at the other end of the frame FR, and the holding and pressurizing screw PPb is used. The other end of the terminal pin 4 is pressed by the pressing plate PP to hold the posture of the terminal pin 4.

工程(S7)において、図11(d)に示すように、基板反り抑制治具PH(把持板)を保持加圧用ネジPHbにより締め付けて、支持板SPとの間で基板2の周縁部を挟持して保持し、基板2の反りを抑制する。 In the step (S7), as shown in FIG. 11D, the substrate warpage suppressing jig PH (grip plate) is tightened by the holding and pressurizing screw PHb, and the peripheral edge portion of the substrate 2 is sandwiched between the support plate SP and the support plate SP. And hold it, and suppress the warp of the substrate 2.

その後、端子ピン4及び基板2を上記治具で保持した状態で、加熱・冷却して、半田5を溶融・固化させ、端子ピン4を基板2に固着つつ電気的且つ機械的に接続する。 Then, while the terminal pin 4 and the substrate 2 are held by the above jig, the solder 5 is heated and cooled to melt and solidify the solder 5, and the terminal pin 4 is electrically and mechanically connected to the substrate 2 while being fixed to the substrate 2.

(予備試験)
予備試験として、端子ピンの接合方法にて発現する基板の反りを測定し、基板の反りを定義した。
(Preliminary test)
As a preliminary test, the warpage of the substrate developed by the terminal pin joining method was measured, and the warp of the substrate was defined.

予備試験における表面実装部品の上面に端子ピンが半田付けされた構造体(図6参照)は、銅製端子ピン(1mm直径で長さ15mm)9本と、DCB基板(一辺20mmの正方形で厚さ1mm)1枚と、半導体チップ(3mmの正方形で厚さ0.5mm)9個とから構成された。 The structure (see Fig. 6) in which the terminal pins are soldered to the upper surface of the surface mount component in the preliminary test consists of nine copper terminal pins (1 mm diameter and 15 mm in length) and a DCB substrate (a square with a side of 20 mm and a thickness). It was composed of one 1 mm) and nine semiconductor chips (3 mm square and 0.5 mm thick).

図10に示す端子ピンの接合方法のプロセスフローから、治具により端子ピンの姿勢を保持する工程(S6)及び基板を治具により保持して基板の反りを抑制する工程(S7)を省略して、半導体チップ上に半田を塗布して端子ピンを搭載した後、加熱接合した構造体を作成した。 From the process flow of the terminal pin joining method shown in FIG. 10, the step of holding the posture of the terminal pin with a jig (S6) and the step of holding the substrate with a jig to suppress the warp of the substrate (S7) are omitted. Then, solder was applied onto the semiconductor chip, terminal pins were mounted, and then a heat-bonded structure was created.

図12(a)及び図12(b)は、図10に示す端子ピンの接合方法のプロセスフローにおける基板に半導体チップを加熱接合する工程(S3)及び基板等に端子ピンを加熱接合する工程(S8)の半導体チップ接合の温度プロファイル及び端子ピン接合の温度プロファイルをそれぞれ示す。 12 (a) and 12 (b) show a step (S3) of heat-bonding the semiconductor chip to the substrate in the process flow of the terminal pin bonding method shown in FIG. 10 and a step of heat-bonding the terminal pin to the substrate or the like (S3). The temperature profile of the semiconductor chip junction and the temperature profile of the terminal pin junction in S8) are shown.

予備試験で得られた構造体の基板の反り量はレーザ変位計(型式:LK−G3000、キーエンス製)を用い、基板裏面の断面形状データを取得した。基板裏面の断面形状にて、最大値と最小値の差を基板の反りと定義する。この結果を図13の「治具なし」のグラフに示す。図13に示されるように、基板の一辺に平行なX方向の基板の反り量の平均値は約79μmであり、X方向に直交するY方向の基板の反り量の平均値は約94μmであった。X方向、Y方向いずれも反り量の目標値(≦70μm)を満足しない。その結果、端子ピンに傾きが生じ、基板の端子ピン側に対向する配線基板の対応するピン穴に端子ピンが挿入できない状態となった。なお、反り量の目標値(≦70μm)は半田厚さバラツキ(100μm±30μm)を考慮し、基板の反り量の目標値を設定したものである。 A laser displacement meter (model: LK-G3000, manufactured by KEYENCE) was used to obtain the cross-sectional shape data of the back surface of the substrate for the amount of warpage of the substrate of the structure obtained in the preliminary test. The difference between the maximum value and the minimum value in the cross-sectional shape of the back surface of the substrate is defined as the warp of the substrate. This result is shown in the graph of "without jig" in FIG. As shown in FIG. 13, the average value of the amount of warpage of the substrate in the X direction parallel to one side of the substrate is about 79 μm, and the average value of the amount of warpage of the substrate in the Y direction orthogonal to the X direction is about 94 μm. rice field. Neither the X direction nor the Y direction satisfies the target value of the amount of warpage (≦ 70 μm). As a result, the terminal pins are tilted, and the terminal pins cannot be inserted into the corresponding pin holes of the wiring board facing the terminal pin side of the board. The target value of the warp amount (≦ 70 μm) is set in consideration of the variation in solder thickness (100 μm ± 30 μm).

(実施例)
図10に示す端子ピンの接合方法を用いた以外、上記予備試験と同一の条件にて構造体を作成した。
(Example)
The structure was prepared under the same conditions as the above preliminary test except that the terminal pin joining method shown in FIG. 10 was used.

図4に示すように、端子ピン姿勢保持用治具10を用いて、端子ピンの姿勢を保持しながら、端子ピンをDCB基板に向けて押さえた。 As shown in FIG. 4, the terminal pin posture holding jig 10 was used to hold the terminal pin posture toward the DCB substrate while holding the terminal pin posture.

上記予備試験の反り量を抑制するため、図2に示す端子ピン姿勢保持用治具10を用いた。押さえ板PP及び保持加圧用ネジPPbによる基板を保持するときの面圧は、0.3MPa〜50MPaの範囲とした。押さえ板PP及び保持加圧用ネジPPbにより、加熱工程、冷却工程で生じる端子ピンの傾きを抑制できた。 In order to suppress the amount of warpage in the preliminary test, the terminal pin posture holding jig 10 shown in FIG. 2 was used. The surface pressure when holding the substrate by the holding plate PP and the holding and pressurizing screw PPb was in the range of 0.3 MPa to 50 MPa. The holding plate PP and the holding and pressurizing screw PPb could suppress the inclination of the terminal pin caused in the heating process and the cooling process.

押さえ板PP及び保持加圧用ネジPPbによる面圧の範囲は、基板の形状、サイズにより異なる。基板の面圧の下限値を0.3MPaとしているのは、0.3MPaに満たない面圧では基板の反りを抑制できないためである。一方、50MPaを超える面圧で加圧したとき、表面実装部品にクラックが発生する、若しくは、半導体チップを破壊する等の不具合が発生した。よって、端子ピンを加圧するときの面圧の上限値を50MPaとした。 The range of surface pressure due to the holding plate PP and the holding and pressurizing screw PPb differs depending on the shape and size of the substrate. The lower limit of the surface pressure of the substrate is set to 0.3 MPa because the warpage of the substrate cannot be suppressed with a surface pressure of less than 0.3 MPa. On the other hand, when the pressure was applied at a surface pressure exceeding 50 MPa, problems such as cracks in the surface mount components or breakage of the semiconductor chip occurred. Therefore, the upper limit of the surface pressure when the terminal pin is pressurized is set to 50 MPa.

本実施例では、端子ピンに嵌る押さえ板PPの凹部は、端子ピンの傾きに応じたテーパー形状を有することで、半田接合部が再溶融して、端子ピンの先端位置にズレが生じても、端子ピンを一定の傾き内で固定することができることを確認した。 In this embodiment, the recess of the holding plate PP that fits into the terminal pin has a tapered shape according to the inclination of the terminal pin, so that even if the solder joint is remelted and the tip position of the terminal pin is displaced. , It was confirmed that the terminal pin can be fixed within a certain inclination.

一方、端子ピンの先端をテーパー形状凹部付き治具に固定し、押さえ板PPに2kgの荷重(端子ピン1本当たり2/9kgの荷重)をかけ、各端子ピンの端面に3MPaの面圧を付与して実装したときの基板の反り量の測定結果(予備試験と実施例)を、図13の「治具あり」のグラフに示す。各端子ピンの端面に3MPaの面圧をかける工程に関しては、感圧紙による面圧とネジ締め量の関係に基づき、ネジ締め量を決定した。X方向の基板の反り量の平均値は約14μm、Y方向の基板の反り量の平均値は約17μm(治具を使用しないときの1/5以下)となり、X方向、Y方向いずれも反り量の目標値(≦70μm)を満足し、基板の端子ピン側に対向する配線基板の対応するピン穴に端子ピンが挿入できる状態を確保できた。 On the other hand, the tip of the terminal pin is fixed to a jig with a tapered concave portion, a load of 2 kg (a load of 2/9 kg per terminal pin) is applied to the holding plate PP, and a surface pressure of 3 MPa is applied to the end face of each terminal pin. The measurement results (preliminary test and examples) of the amount of warpage of the substrate when the substrate is applied and mounted are shown in the graph of “with jig” in FIG. Regarding the step of applying a surface pressure of 3 MPa to the end face of each terminal pin, the screw tightening amount was determined based on the relationship between the surface pressure of the pressure sensitive paper and the screw tightening amount. The average value of the amount of warpage of the substrate in the X direction is about 14 μm, and the average value of the amount of warpage of the substrate in the Y direction is about 17 μm (less than 1/5 when no jig is used). The target value of the amount (≦ 70 μm) was satisfied, and a state in which the terminal pin could be inserted into the corresponding pin hole of the wiring board facing the terminal pin side of the board could be secured.

本実施例の接合用治具を用いることで、実装工程での基板の反りにともなう端子ピンの傾きを抑制して垂直度を保つとともに、半導体チップ下の半田接合部が再溶融したときに生じる端子ピンの傾きを補正することで、DCB基板上の半導体チップの上面に端子ピンが半田付けされた構造体を安定して形成できる。また、同様の手法にて治具形状及び加圧条件出しをすることで、端子ピンと表面実装部品が混載実装された構造体にも適用できる。 By using the joining jig of this embodiment, the inclination of the terminal pin due to the warp of the substrate in the mounting process is suppressed to maintain the verticality, and it occurs when the solder joint under the semiconductor chip is remelted. By correcting the inclination of the terminal pins, a structure in which the terminal pins are soldered can be stably formed on the upper surface of the semiconductor chip on the DCB substrate. Further, by setting the jig shape and pressurizing conditions by the same method, it can be applied to a structure in which terminal pins and surface mount components are mixedly mounted.

以上、本発明は、上記の実施形態、実施例に限定されるものではなく、その要旨を変更しない範囲内で適宜変形して実施することができるものである。 As described above, the present invention is not limited to the above-described embodiments and examples, and can be appropriately modified and implemented without changing the gist thereof.

1‥構造体、2‥基板、3‥半導体チップ、4‥端子ピン、5‥半田、10‥接合用冶具、SP‥支持板、FR‥フレーム、PP‥押さえ板、PH‥把持板、RC‥凹部。 1 Structure, 2 Substrate, 3 Semiconductor chip, 4 Terminal pin, 5 Solder, 10 Jig for joining, SP Support plate, FR Frame, PP Press plate, PH Grip plate, RC Recess.

Claims (5)

基板上に半導体チップが搭載された半導体装置の前記半導体チップ上及び前記基板上の少なくとも一方に、端子ピンを立設して接合する接合方法であって、
前記半導体チップ上及び前記基板上の少なくとも一方に、前記端子ピンの一端を、接合材を介して当接させて、前記端子ピンを立設する工程と、
前記端子ピンの他端を治具により保持して、前記端子ピンの姿勢を保持する姿勢保持工程と、
前記基板を前記治具により保持して、前記基板の反りを抑制する基板の形状維持工程と、
前記端子ピン及び前記基板を前記治具で保持した状態で、加熱・冷却して、前記接合材を溶融・固化させ、前記端子ピンを固着する工程と、
を含むことを特徴とする端子ピンの接合方法。
It is a joining method in which terminal pins are erected and joined to at least one of the semiconductor chip and the substrate of a semiconductor device in which a semiconductor chip is mounted on a substrate.
A step of erection of the terminal pin by bringing one end of the terminal pin into contact with at least one of the semiconductor chip and the substrate via a bonding material.
A posture holding step of holding the other end of the terminal pin with a jig to hold the posture of the terminal pin,
The process of maintaining the shape of the substrate by holding the substrate with the jig and suppressing the warp of the substrate, and the process of maintaining the shape of the substrate.
A step of heating and cooling the terminal pin and the substrate with the jig to melt and solidify the bonding material and fix the terminal pin.
A method of joining terminal pins, which comprises.
前記治具は、前記基板が載置される支持板と、
前記支持板における前記基板の周りに一端が固着され且つ立設されるフレームと、
前記フレームの他端部に設けられ且つ前記基板から突出する端子ピンの先端を保持する凹部を有する押さえ板と、
前記基板の周縁部を前記支持板との間で挟持する把持板と、
を備え、
前記姿勢保持工程において、前記基板を前記支持板上に載置し、前記端子ピンの他端を前記凹部に嵌合させて、前記押さえ板で前記端子ピンの他端を保持し、
前記形状維持工程において、前記基板の周囲に配置された把持板により、前記支持板との間で前記基板の周縁部を挟持して前記基板の反りを抑制する、請求項1に記載の端子ピンの接合方法。
The jig includes a support plate on which the substrate is placed and a support plate on which the substrate is placed.
A frame in which one end is fixed and erected around the substrate in the support plate, and
A holding plate provided at the other end of the frame and having a recess for holding the tip of a terminal pin protruding from the substrate.
A grip plate that sandwiches the peripheral edge of the substrate between the support plate and
With
In the posture holding step, the substrate is placed on the support plate, the other end of the terminal pin is fitted into the recess, and the other end of the terminal pin is held by the holding plate.
The terminal pin according to claim 1, wherein in the shape maintaining step, a grip plate arranged around the substrate sandwiches a peripheral edge portion of the substrate between the grip plate and the support plate to suppress warpage of the substrate. Joining method.
前記押さえ板の前記凹部は、テーパー状の内側面を有する、請求項2に記載の端子ピンの接合方法。 The method for joining terminal pins according to claim 2, wherein the recess of the holding plate has a tapered inner surface surface. 基板上に半導体チップが搭載された半導体装置の前記半導体チップ上及び前記基板上の少なくとも一方に、端子ピンを立設して接合するための端子ピンの接合用冶具であって、
前記基板が載置される支持板と、
前記支持板における前記基板の周りに一端が固着され且つ立設されるフレームと、
前記フレームの他端部に設けられ且つ前記基板から突出する端子ピンの先端を保持する凹部を有する押さえ板と、
前記基板の周縁部を前記支持板との間で挟持する把持板と、
を備えることを特徴とする端子ピンの接合用冶具。
A jig for joining terminal pins for erection and joining of terminal pins on at least one of the semiconductor chip and the substrate of a semiconductor device in which a semiconductor chip is mounted on a substrate.
A support plate on which the substrate is placed and
A frame in which one end is fixed and erected around the substrate in the support plate, and
A holding plate provided at the other end of the frame and having a recess for holding the tip of a terminal pin protruding from the substrate.
A grip plate that sandwiches the peripheral edge of the substrate between the support plate and
A jig for joining terminal pins, which is characterized by being provided with.
前記押さえ板の前記凹部はテーパー状の内側面を有する、請求項4に記載の端子ピンの接合用冶具。 The jig for joining terminal pins according to claim 4, wherein the recess of the holding plate has a tapered inner surface surface.
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