JP6921271B1 - Electronic control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an electronic control device having a function of monitoring a power supply voltage of an IC not only at the time of starting the IC but also during operation. An electronic control device is composed of a power supply circuit unit, a reset unit, a voltage holding unit having a switch, and an IC, and when the IC is started to supply power from the power supply circuit unit, the reset unit is used. In response to the reset release signal RST by, the switch is opened, and the reset release voltage Vrst held by the voltage holding capacitor of the voltage holding part is compared and judged with the minimum operating voltage of the IC, and the normal operation of the IC is also performed. Even at times, the voltage holding signal HOLD is output to the switch intermittently or temporarily, and the difference in holding voltage due to the voltage holding capacitor when the switch is open and when the switch is closed is compared to detect abnormalities in the power supply voltage of the IC. judge. [Selection diagram] Fig. 1

Description

The present application relates to an electronic control device having a function of monitoring a power supply voltage.

The electronic control device detects that the applied power supply voltage is equal to or higher than the preset voltage, and releases the reset to start the internal system after the preset delay time elapses. Power-on reset (POR:) A Power-On Reset) function is generally provided, and a method of monitoring voltage at the time of reset release or a method of changing the reset release time according to a situation is widely known.

For example, in the secondary battery voltage monitoring circuit of Patent Document 1, in a memory backup circuit using a lithium ion secondary battery that performs constant voltage charging, the charging circuit is cut off when a reset signal is generated immediately after the power is turned on, and the reset time is set. It is possible to operate the voltage detection circuit that detects the voltage of the lithium ion secondary battery only inside and hold the voltage detection result when the reset is released so that the accurate battery voltage of the lithium ion secondary battery can be detected. Have been described.

Further, for example, in the semiconductor device of Patent Document 2, the trailing edge of the power-on reset signal is delayed by the delay time set by the setting unit to generate an internal reset signal, and the internal circuit is reset by the internal reset signal. It is stated that.

Japanese Unexamined Patent Publication No. 11-168841 Japanese Unexamined Patent Publication No. 2014-68124

However, the secondary battery voltage monitoring circuit of Patent Document 1 can monitor the power supply voltage at startup, but cannot monitor the power supply voltage during IC operation.
Further, in the semiconductor device of Patent Document 2, when the power supply rises slowly and the power supply voltage at the time of reset release is less than the rated voltage of the IC, the reset delay time at the next start-up is lengthened. Although the reset can be released with an appropriate power supply voltage, there is a problem that the power supply voltage during IC operation cannot be monitored.

This application has been made to solve the above-mentioned problems, and avoids the double installation of the power supply voltage monitoring circuit of the IC, and powers the IC not only at the time of starting the IC but also during the operation of the IC. It is an object of the present invention to provide an electronic control device capable of monitoring a voltage.

The electronic control device disclosed in the present application includes an IC that controls the entire device, a power supply circuit unit that is connected to the power supply terminal of the IC and supplies a stabilizing voltage, and is connected to the power supply circuit unit and is stable. It is composed of a reset unit that detects the voltage and outputs the reset release signal to the IC, a switch, a rectifier circuit, and a voltage holding capacitor, and holds and releases the stabilized voltage by the voltage holding signal and the reset release signal. The voltage holding unit is provided, and when the IC is started, the stabilized voltage becomes equal to or higher than the reset release voltage threshold value, and after a predetermined delay time elapses, the opening / closing is performed by the reset release signal output from the reset unit. When the device is opened and the voltage held in the voltage holding capacitor is less than the minimum operating voltage of the IC, it is determined that the stabilized voltage is abnormal, and during normal operation of the IC. When the switch is opened by the voltage holding signal and the first voltage held in the voltage holding capacitor is less than the minimum operating voltage of the IC, the stabilized voltage is abnormal. When the first voltage is equal to or higher than the minimum operating voltage of the IC, the switch is closed by the voltage holding signal, and the second voltage is held in the voltage holding capacitor. If the difference from the first voltage is equal to or greater than the set value, it is determined that the stabilized voltage is abnormal.

According to the electronic control device disclosed in the present application, when an IC having a reset unit and a voltage holding unit and power supply is started from the power supply circuit unit is started, the switch is turned on in response to a reset release signal by the reset unit. By making the circuit open and comparing the voltage held by the voltage holding capacitor of the voltage holding part with the minimum operating voltage of the IC, and also during the normal operation of the IC, the voltage holding signal is intermittently or temporarily sent to the switch. By comparing the difference between the voltages held by the voltage holding capacitors when the switch is open and when the switch is closed, it is possible to determine an abnormality in the power supply voltage of the IC.

It is a block diagram which shows the schematic structure of the electronic control device which concerns on Embodiment 1. FIG. It is a figure which shows the 1st structural example of the circuit structure of the voltage holding part in Embodiment 1. FIG. It is a figure which shows the 2nd structural example of the circuit structure of the voltage holding part in Embodiment 1. FIG. It is a time chart which shows the relationship between the stabilization voltage at the time of start-up, a reset release voltage, and a reset release signal in the first embodiment. It is a flowchart which shows the procedure of power supply voltage abnormality detection at the time of a normal operation in Embodiment 1. FIG. It is a figure which shows the relationship between the opening / closing signal and the operation of a switch in Embodiment 1. FIG.

Embodiment 1.
FIG. 1 is a block diagram showing a schematic configuration of an electronic control device according to a first embodiment. FIG. 2 is a diagram showing a first configuration example of the circuit configuration of the voltage holding unit. FIG. 3 is a diagram showing a second configuration example of the circuit configuration of the voltage holding unit. FIG. 4 is a time chart showing the relationship between the stabilized voltage, the reset release voltage, and the reset release signal at the time of startup. FIG. 5 is a flowchart showing a procedure for detecting a power supply voltage abnormality during normal operation. Further, FIG. 6 is a table showing the relationship between the open / close signal and the operation of the switch.

First, the overall configuration of the electronic control device according to the first embodiment will be described with reference to FIG.
The electronic control device 100 of the first embodiment includes an IC 40 that controls the entire device, a first power supply circuit unit 11 that is connected to the AVcc terminal of the IC 40 and supplies a reference voltage Vref, an EVcc terminal that is a power input terminal of the IC 40, and an EVcc terminal. The second power supply circuit unit 12 connected to the reset unit 20 to supply the stabilized voltage Vcc, the reset unit 20 that detects the input voltage and outputs the reset release signal RST to the Reset terminal of the IC 40, the voltage holding signal HOLD and the reset release. It is composed of a voltage holding unit 30 that holds and releases the input voltage by the signal RST, and a voltage dividing circuit 37 that is connected to the voltage holding unit 30 and outputs a voltage proportional to the input voltage to the A / D terminal of the IC 40. ing. Further, the input terminals of the first power supply circuit unit 11 and the second power supply circuit unit 12 are connected to the battery 1 which is an external power supply via the power supply relay 2, and the power supply voltage Vbb is supplied to the electronic control device 100. There is.

Next, a specific configuration of each part that is a component of the electronic control device 100 will be described.
The first power supply circuit unit 11 transforms a constant voltage, for example, the power supply voltage Vbb of the DC12V system of the battery 1 which is an external power supply, to a regulated voltage Vcc of 5V, and supplies power to the AVcc terminal as a reference voltage Vref of the IC40.
Further, the second power supply circuit unit 12 transforms the power supply voltage Vbb of the DC12V system of the battery 1 to a stabilized voltage Vcc of 5V and supplies power to the EVcc terminal which is the power supply terminal of the IC 40, similarly to the first power supply circuit unit 11. At the same time, it is output to the reset unit 20. Here, it is desirable that the first power supply circuit unit 11 and the second power supply circuit unit 12 are linear regulators in order to make their outputs more stable voltages.

The reset unit 20 detects that the input voltage Vi of the input terminal becomes equal to or higher than the reset release voltage threshold Vth preset for the time to (see FIG. 4A), and the preset delay time td After that, the reset release signal RST is output at time tr as the output voltage Vo of the output terminal (see FIG. 4B). Further, the reset unit 20 is configured so that at least one of the reset release voltage threshold value Vth and the delay time td is set according to the write value of the non-volatile memory 21 provided inside.

The input terminal of the reset unit 20 is connected to the output terminal of the second power supply circuit unit 12. Further, the output terminal of the reset unit 20 is connected to the Reset terminal of the IC 40, and is also connected to the voltage holding signal input terminal C of the voltage holding unit 30 via the first rectifying element 35a. Here, when the internal circuit of the output terminal of the reset unit 20 is an open collector such as an npn type transistor, for example, the pull-up resistor 22 having the output terminal of the second power supply circuit unit 12 as the pull-up destination. May be provided.

The non-volatile memory 21 referred to here is, for example, an EEPROM (Electrically Erasable Probe Read Only Memory) that can be electrically erased or rewritten.
Further, in the above description, the first power supply circuit unit 11, the second power supply circuit unit 12, and the reset unit 20 are respectively configured independently, but a part or all of them are integrated. It doesn't matter if there is.

The voltage holding unit 30 holds or releases the input voltage by an open / close signal from the outside, and has a so-called sample hold circuit configuration. By providing the rectifier circuit 38 composed of the diode 39 from the rear stage to the front stage, different voltage holding operations are performed depending on the fluctuation state of the input voltage. That is, when the input voltage of the voltage input terminal A of the voltage holding unit 30 is constant or rising, it operates as a sample hold circuit, and when the input voltage drops, it operates as a bottom hold circuit. The voltage output terminal B of the voltage holding unit 30 is connected to the A / D terminal of the IC 40 via the voltage dividing circuit 37. Further, the voltage holding signal input terminal C of the voltage holding unit 30 is connected to the output terminal of the reset unit 20 via the first rectifying element 35a, and outputs the voltage holding signal HOLD via the second rectifying element 35b. It is also connected to the HOLD terminal of the IC40.

The voltage dividing circuit 37 is configured to output a voltage proportional to the voltage input from the voltage output terminal B of the voltage holding unit 30 to the A / D terminal of the IC 40 by, for example, resistance voltage dividing.

The IC 40 controls the entire electronic control device 100, and examples thereof include a microcomputer and an FPGA. The microcomputer or FPGA is reset by inputting the reset release signal RST after the regulated voltage Vcc is in the operable voltage range and after a certain delay time td has elapsed, and the operation is started. do.

The IC 40 has an AVcc terminal, which is a reference voltage input terminal connected to the output terminal of the first power supply circuit unit 11, an EVcc terminal, which is a power supply input terminal connected to the output terminal of the second power supply circuit unit 12, and a reset. The Reset terminal connected to the output terminal of the unit 20 and the first rectifying element 35a connected to the voltage holding unit 30, the RDU terminal that outputs to the non-volatile memory 21 of the reset unit 20, and the output terminal of the voltage dividing circuit 37. The A / D terminal for A / D conversion of the input voltage and the HOLD terminal for outputting the voltage holding signal HOLD to the voltage holding unit 30 via the second rectifying element 35b are provided.

Next, with reference to FIG. 2, the details of the circuit configuration of the voltage holding unit 30 and the connection relationship thereof will be described. The voltage holding unit 30 includes a switch 36, a voltage holding capacitor 32, and a rectifier circuit 38. The voltage holding unit 30 has a voltage input terminal A, a voltage output terminal B, and a voltage holding signal input terminal C. The voltage input terminal A is an output terminal of the second power supply circuit unit 12, and the voltage output terminal B is a voltage output terminal B. , The voltage holding signal input terminal C is connected to the voltage dividing circuit 37, respectively, to the first rectifying element 35a and the second rectifying element 35b, respectively.

The switch 36 is composed of, for example, a pnp type transistor 31 and a base resistor 34. The emitter terminal of the transistor 31 is connected to the voltage input terminal A of the voltage holding unit 30, and the collector terminal is a voltage holding capacitor. In addition to being connected to 32, it is also connected to the voltage output terminal B of the voltage holding unit 30. The base terminal of the transistor 31 is connected to the voltage holding signal input terminal C of the voltage holding unit 30 via the base resistor 34. The rectifier circuit 38 is composed of a diode 39 as shown in FIG.

Next, with reference to FIG. 4, the operation of the electronic control device 100 when the power supply relay 2 is closed and the power supply is started from the battery 1 will be described. 4 (a) and 4 (b) are time charts showing the relationship between the stabilized voltage Vcc when the power supply of the electronic control device 100 is started, the reset release voltage Vrst, and the reset release signal RST.

When the reset unit 20 detects that the input value of the stabilization voltage Vcc is equal to or higher than the reset release voltage threshold Vth with respect to the value written in the non-volatile memory 21, after the delay time td has elapsed. , The output voltage Vo of the output terminal is switched from Low to High, and the reset release signal RST is output to the IC 40 and the voltage holding unit 30. Here, the reset release voltage threshold value Vth and the delay time td can be arbitrarily set as needed.

The voltage holding unit 30 opens the switch 36 by the reset release signal RST to hold the stabilized voltage Vcc at the time of reset release as the reset release voltage Vrst by the voltage holding capacitor 32, and divides the voltage by the voltage dividing circuit 37. On the other hand, in the IC 40, after the reset is released by the reset release signal RST, the voltage divided by the voltage dividing circuit 37 is input to the A / D terminal, and the A / D conversion value is calculated.

The reference voltage at this time is Vref, and by dividing the voltage by the voltage dividing circuit 37, it is possible to perform A / D conversion without saturating the A / D conversion value even if Vrst> Vref. ing.

After that, it is determined whether or not the A / D conversion value is equal to or higher than the minimum operating voltage of the IC40, and if it is equal to or higher than the minimum operating voltage, it is determined that the stabilized voltage Vcc of the IC40 is normal, and the minimum operation is performed. If the voltage is less than the voltage, the reset release optimization signal RDU is output to the non-volatile memory 21, for example, the reset release time td (= delay time) is increased by 10%, or the value of the reset release voltage threshold Vth is set to 0. By rewriting to increase .1V, the next startup can be started with an appropriate power supply voltage and delay time.

Subsequently, with reference to the flowchart of FIG. 5, a procedure for detecting a voltage abnormality of the stabilized voltage Vcc during normal operation, which is in a stable state after the IC 40 is normally started, will be described.
The operation of the IC40 is started (step S400).
The IC 40 outputs an open signal by the voltage holding signal HOLD in order to open the switch 36 (step S401).
As a result, the switch 36 is opened (step S402).
The IC 40 A / D converts the voltage held in the voltage holding capacitor 32 and calculates the A / D conversion value (1) (step S403).
The IC 40 compares the “A / D conversion value (1)” with the “minimum operating voltage of the IC 40” (step S404).
If the relationship of "A / D conversion value (1) <minimum operating voltage of IC40" is satisfied, it is determined to be YES, and if it is not satisfied, it is determined to be NO.
Here, if it is determined to be NO in step S404, the IC 40 outputs a closing signal by the reset release signal RST in order to close the switch 36 (step S405).
As a result, the switch 36 is closed (step S406).
The IC 40 A / D converts the voltage held in the voltage holding capacitor 32 and calculates the A / D conversion value (2) (step S407).
The IC40 compares "| A / D conversion value (2) -A / D conversion value (1) |" with the "set value" (step S408).
If the relationship of "| A / D conversion value (2) -A / D conversion value (1) |">"setvalue" is satisfied, it is determined to be YES, and if it is not satisfied, NO is selected. Judge that there is.
That is, if the difference between the A / D conversion value (2) and the A / D conversion value (1) is larger than the set value, it is determined to be YES, and if it is smaller than the set value, it is determined to be NO.
If YES in step S404 or YES in step S408, it is determined that the regulated voltage Vcc is abnormal (step S410).
If it is determined to be NO in step S408, it is determined that the regulated voltage Vcc is normal (step S409), and the normal operation of the IC 40 is continued. Further, the process returns to step S401, and this series of procedures is repeated.
Here, the set value in step S408 is, for example, a preset allowable ripple voltage value in the power supply voltage of the IC 40.

FIG. 6 is a table showing the relationship between the voltage holding signal HOLD and the reset release signal RST, which are switching signals, and the operation of the switch 36.

In this way, the IC 40 repeatedly executes the calculation of the A / D conversion value using the voltage held in the voltage holding capacitor 32 when the switch 36 is opened and when the switch is closed, and stabilizes the voltage. We are measuring Vcc. As a result, when the switch 36 is opened, the voltage when the switch 36 is closed is measured with reference to the bottom-held voltage, the two values are compared, and the difference is greater than or equal to the set value. In some cases, it can be detected that the stabilized voltage Vcc is fluctuating.

Further, when the A / D conversion value of the voltage held by the voltage holding capacitor 32 calculated by the IC 40 is less than the minimum operating voltage, it is possible to detect an abnormality as if the stabilized voltage Vcc has decreased. It is possible.

When A / D conversion of the voltage of the voltage holding capacitor 32 is performed at a fixed cycle, detection omission of voltage abnormality may occur when synchronized with the fluctuation cycle of the power supply voltage, so A / D conversion is performed. It is desirable to perform it at an indefinite cycle.

In the first circuit configuration example of the voltage holding unit 30 shown in FIG. 2, the case where only the diode 39 is used as the rectifier circuit 38 is shown, but the rectifier circuit is as shown in the second circuit configuration example shown in FIG. By making 38 an ideal diode circuit composed of a diode 39 and an operational amplifier 33, the potential difference between the front stage and the rear stage of the switch 36 can be made almost 0 when the switch 36 is opened, so that the accuracy is higher. Good voltage detection is possible.

As described above, according to the electronic control device according to the first embodiment, it is possible to avoid the double installation of the power supply voltage monitoring circuit, and to make the IC compact and inexpensive, not only at the time of starting the IC but also during operation. It has the effect of being able to monitor the power supply voltage of.

In the above embodiment, the case where the battery is used as the external power source has been described, but the case where the AC power source is converted to direct current and used may be used.

Also, although the present application describes exemplary embodiments, the various features, embodiments, and functions described in the embodiments are not limited to the application of a particular embodiment, but alone. , Or in various combinations are applicable to embodiments.
Therefore, innumerable variations not illustrated are envisioned within the scope of the techniques disclosed herein. For example, it is assumed that at least one component is modified, added or omitted.

Further, in the figure, the same reference numerals indicate the same or corresponding parts.

1 Battery, 2 Power supply relay, 11 1st power supply circuit, 12 2nd power supply circuit, 20 Reset, 21 Non-volatile memory, 22 Pull-up resistor, 30 Voltage holder, 40 IC, 100 Electronic controller, 31 Transistor , 32 voltage holding capacitor, 33 optotype, 34 base resistance, 35a first rectifier element, 35b second rectifier element, 36 switch, 37 voltage divider circuit, 38 rectifier circuit, 39 diode, Vbb power supply voltage, Vcc stabilized voltage, Vref reference voltage, HOLD voltage holding signal, RST reset release signal, RDU reset release optimization signal

Claims (6)

An IC that controls the entire device,
A power supply circuit unit that is connected to the power supply terminal of the IC and supplies a regulated voltage.
A reset unit that is connected to the power supply circuit unit, detects the stabilized voltage, and outputs a reset release signal to the IC.
It is composed of a switch, a rectifier circuit, and a voltage holding capacitor, and includes a voltage holding unit that holds and releases the stabilized voltage by a voltage holding signal and a reset release signal.
When the IC is started, the stabilization voltage becomes equal to or higher than the reset release voltage threshold value, and after a predetermined delay time elapses, the switch is opened by the reset release signal output from the reset unit, and the voltage holding capacitor is used. If the held voltage is less than the minimum operating voltage of the IC, it is determined that the stabilized voltage is abnormal, and the voltage is determined to be abnormal.
When the switch is opened by the voltage holding signal during the normal operation of the IC and the first voltage held in the voltage holding capacitor is less than the minimum operating voltage of the IC. It is determined that the stabilized voltage is abnormal,
When the first voltage is equal to or higher than the minimum operating voltage of the IC, the switch is closed by the voltage holding signal, and the second voltage held in the voltage holding capacitor and the first voltage are used. An electronic control device characterized in that if the difference from the voltage is equal to or greater than a set value, it is determined that the stabilized voltage is abnormal. The electronic control device according to claim 1, wherein the first voltage or the second voltage is obtained at an indefinite period. A voltage dividing circuit connected to the voltage holding unit and dividing the voltage held in the voltage holding capacitor is provided, and the output voltage of the voltage dividing circuit is set to the first voltage and the second voltage. The electronic control device according to claim 1 or 2. The electronic control device according to any one of claims 1 to 3, wherein the first voltage and the second voltage are A / D converted in the IC. The electronic control device according to any one of claims 1 to 4, wherein the rectifier circuit is an ideal diode circuit composed of a diode and an operational amplifier, which rectifies from the rear stage to the front stage. .. Claims 1 to 1, wherein when the voltage held in the voltage holding capacitor is less than a set value during normal operation of the IC, it is determined that the stabilized voltage is abnormal. 5. The electronic control device according to any one of 5.

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