JP6917917B2 - Display device - Google Patents

Description

Embodiments of the present invention relate to display devices.

In recent years, various techniques for improving the display quality of display devices have been studied. In one example, a technique is disclosed in which two walls are formed outside the display area, different potentials are applied to the electrodes formed on the two walls, and impurity ions are trapped between the two walls. .. In another example, a technique is disclosed in which different potentials are applied to the three electrodes formed in the frame region to capture impurity ions in the frame region.

Japanese Unexamined Patent Publication No. 2017-90794 Japanese Unexamined Patent Publication No. 2017-11396

An object of the present embodiment is to provide a display device capable of suppressing a decrease in reliability.

According to this embodiment
Display and
A non-display unit located around the display unit and
The first metal wiring located in the non-display part and
An insulating layer located on the first metal wiring and
A first transparent conductive film located on the insulating layer, having the same potential as the first metal wiring, and superimposing on the first metal wiring.
A second transparent conductive film having a potential different from that of the first transparent conductive film, which is located between the first transparent conductive film and the display unit, is provided.
The first transparent conductive film has a first edge facing the second transparent conductive film, and has a first edge.
The second transparent conductive film has a second edge facing the first transparent conductive film and has a second edge.
The first metal wiring provides a display device having a third edge located between the first edge and the second edge in a plan view.

FIG. 1 is a plan view showing the appearance of the display device DSP of the present embodiment. FIG. 2 is a plan view showing a configuration example of the touch sensor TS. FIG. 3 is a plan view showing the sensor electrode Rx and the pixel PX shown in FIG. FIG. 4 is a diagram showing a basic configuration and an equivalent circuit of the pixel PX. FIG. 5 is a plan view showing an example of the pixel layout. FIG. 6 is a cross-sectional view of the display panel PNL along the line EF shown in FIG. FIG. 7A is an enlarged plan view of the region AR1 along the straight line portion E13 of the non-display portion NDA shown in FIG. FIG. 7B is an enlarged plan view of the protrusion SLE1 shown in FIG. 7A and its periphery. FIG. 8 is an enlarged plan view of the region AR2 along the round portion R11 of the non-display portion NDA shown in FIG. FIG. 9 is a diagram showing a cross-sectional view of the display panel PNL along the line GH shown in FIG. FIG. 10 is a diagram showing the relationship between the protrusion ratio (%) of the metal wiring SL1 and the electric field strength. FIG. 11 is an enlarged plan view of the region AR3 along the straight line portion E11 of the non-display portion NDA shown in FIG. FIG. 12 is a plan view showing another configuration example of the display device DSP.

Hereinafter, the present embodiment will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention are naturally included in the scope of the present invention. Further, in order to clarify the description, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is merely an example, and the present invention is provided. It does not limit the interpretation. Further, in the present specification and each figure, components exhibiting the same or similar functions as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and duplicate detailed description may be omitted as appropriate. ..

In the present embodiment, a liquid crystal display device will be described as an example of the display device DSP. The main configuration disclosed in the present embodiment is a self-luminous display device having an organic electroluminescence display element or the like, an electronic paper type display device having an electrophoretic element or the like, and a MEMS (Micro Electro Mechanical Systems). It can also be applied to an applied display device or a display device to which electrochromism is applied.

FIG. 1 is a plan view showing the appearance of the display device DSP of the present embodiment. In one example, the first direction X, the second direction Y, and the third direction Z are orthogonal to each other, but may intersect at an angle other than 90 degrees. The first direction X and the second direction Y correspond to the directions parallel to the main surface of the substrate constituting the display device DSP, and the third direction Z corresponds to the thickness direction of the display device DSP. In the present specification, the direction toward the tip of the arrow indicating the third direction Z is referred to as upward (or simply upward), and the direction opposite from the tip of the arrow is referred to as downward (or simply downward). Further, it is assumed that there is an observation position for observing the display device DSP on the tip side of the arrow indicating the third direction Z, and the observation position is directed toward the XY plane defined by the first direction X and the second direction Y. Seeing is called plan view.

Here, a plan view of the display device DSP in the XY plane is shown. The display device DSP includes a display panel PNL, a flexible printed circuit board 1, and an IC chip 2.

The display panel PNL is a liquid crystal display panel and includes a first substrate SUB1, a second substrate SUB2, a liquid crystal layer LC described later, a seal SE, and a light-shielding layer LS. The display panel PNL includes a display unit DA for displaying an image and a frame-shaped non-display unit NDA that surrounds the display unit DA. The second substrate SUB2 faces the first substrate SUB1. The first substrate SUB1 has a mounting portion MA extending in the second direction Y from the second substrate SUB2.
The seal SE is located in the non-display portion NDA, adheres the first substrate SUB1 and the second substrate SUB2, and seals the liquid crystal layer LC. The light-shielding layer LS is located on the non-display portion NDA. The seal SE is provided at a position where it overlaps with the light-shielding layer LS in a plan view. In FIG. 1, the region where the seal SE is arranged and the region where the light-shielding layer LS is arranged are indicated by different diagonal lines, and the region where the seal SE and the light-shielding layer LS overlap is indicated by cross-hatching. The light-shielding layer LS is provided on the second substrate SUB2.

The display unit DA is located inside surrounded by the light-shielding layer LS. The display unit DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The display unit DA includes a pair of edge portions E1 and E2 extending along the first direction X, a pair of edge portions E3 and E4 extending along the second direction Y, and four round portions R1 to R4. And have. The display panel PNL has a pair of straight portions E11 and E12 extending along the first direction X, a pair of straight portions E13 and E14 extending along the second direction Y, and two round portions R11 and R12. And have. The round portions R11 and R12 are located outside the round portions R1 and R2, respectively. The radius of curvature of the round portion R11 may be the same as or different from the radius of curvature of the round portion R1.

The flexible printed circuit board 1 and the IC chip 2 are mounted on the mounting unit MA. The IC chip 2 may be mounted on a flexible printed circuit board 1. The IC chip 2 has a built-in display driver DD that outputs a signal necessary for displaying an image in a display mode for displaying an image. In the illustrated example, the IC chip 2 has a built-in touch controller TC that controls a touch sensing mode that detects the approach or contact of an object with the display device DSP.

The display panel PNL of the present embodiment is a transmissive type having a transmissive display function for displaying an image by selectively transmitting light from the back side of the first substrate SUB1, and light from the front side of the second substrate SUB2. It may be either a reflection type having a reflection display function for displaying an image by selectively reflecting the light, or a semitransparent type having a transmission display function and a reflection display function.
Further, although the detailed configuration of the display panel PNL will be omitted here, the display panel PNL has a display mode using a lateral electric field along the main surface of the substrate and a vertical electric field along the normal of the main surface of the substrate. It corresponds to the display mode to be used, the display mode to use the gradient electric field inclined diagonally with respect to the main surface of the substrate, and the display mode to use the above-mentioned lateral electric field, longitudinal electric field, and gradient electric field in an appropriate combination. Any configuration may be provided. The substrate main surface here is a surface parallel to the XY plane defined by the first direction X and the second direction Y.

FIG. 2 is a plan view showing a configuration example of the touch sensor TS. Here, the self-capacity type touch sensor TS will be described, but the touch sensor TS may be a mutual capacity type. The touch sensor TS includes a plurality of sensor electrodes Rx (Rx1, Rx2 ...) And a plurality of sensor wirings L (L1, L2 ...). The plurality of sensor electrodes Rx are located on the display unit DA and are arranged in a matrix in the first direction X and the second direction Y. One sensor electrode Rx constitutes a sensor block which is the smallest unit capable of touch sensing. The plurality of sensor wirings L extend along the second direction Y and are lined up in the first direction X in the display unit DA. Each of the sensor wirings L is provided at a position where it overlaps with, for example, a signal line S described later. Further, each of the sensor wirings L is pulled out to the non-display unit NDA and electrically connected to the IC chip 2.

Here, attention is paid to the relationship between the sensor wirings L1 to L3 arranged in the first direction X and the sensor electrodes Rx1 to Rx3 arranged in the second direction Y. The sensor wiring L1 overlaps with the sensor electrodes Rx1 to Rx3 and is electrically connected to the sensor electrode Rx1.
The sensor wiring L2 overlaps with the sensor electrodes Rx2 and Rx3 and is electrically connected to the sensor electrode Rx2. The dummy wiring D20 is separated from the sensor wiring L2. The dummy wiring D20 overlaps with the sensor electrode Rx1 and is electrically connected to the sensor electrode Rx1. The sensor wiring L2 and the dummy wiring D20 are located on the same signal line.
The sensor wiring L3 overlaps with the sensor electrode Rx3 and is electrically connected to the sensor electrode Rx3. The dummy wiring D31 overlaps with the sensor electrode Rx1 and is electrically connected to the sensor electrode Rx1. The dummy wiring D32 is separated from the dummy wiring D31 and the sensor wiring L3. The dummy wiring D32 overlaps with the sensor electrode Rx2 and is electrically connected to the sensor electrode Rx2. The sensor wiring L3 and the dummy wirings D31 and D32 are located on the same signal line.

In the touch sensing mode, the touch controller TC applies a touch drive voltage to the sensor wiring L. As a result, a touch drive voltage is applied to the sensor electrode Rx, and sensing is performed on the sensor electrode Rx. The sensor signal corresponding to the sensing result at the sensor electrode Rx is output to the touch controller TC via the sensor wiring L. The touch controller TC or an external host detects whether or not the object is approaching or touching the display device DSP and the position coordinates of the object based on the sensor signal.
In the display mode, the sensor electrode Rx functions as a common electrode CE to which a common voltage (Vcom) is applied. The common voltage is applied from the voltage supply unit included in the display driver DD, for example, via the sensor wiring L.

Wiring WL1 to WL3 are arranged in the non-display unit NDA. In the illustrated example, the wirings WL1 to WL3 are arranged along the straight line portion E13, the round portion R11, the straight line portion E11, the round portion R12, and the straight line portion E14. Of the wirings WL1 to WL3, the wiring WL2 is closest to the display unit DA. The wiring WL1 is located between the wiring WL2 and the wiring WL3.
In one example, the wiring WL1 corresponds to a linear first transparent conductive film (hereinafter, may be referred to as a first wiring) formed of a transparent conductive material, and the wiring WL2 is a linear first transparent conductive material formed of a transparent conductive material. Corresponding to the second transparent conductive film (hereinafter, may be referred to as a second wiring), the wiring WL3 may be a linear third transparent conductive film (hereinafter, may be referred to as a third wiring) formed of a transparent conductive material. ) Corresponds to. The potential of the wiring WL1 is different from the potentials of the wiring WL2 and the wiring WL3, and is, for example, a fixed potential. The potential of the wiring WL2 is the same as the potential of the wiring WL3. For example, a common voltage is applied to the wiring WL2. The potential of the wiring WL1 may be relatively low or high with respect to the potential of the wiring WL2. The wiring WL1 functions as an ion trap wiring that captures positive impurity ions when its potential is lower than the potential of the wiring WL2. Alternatively, the wiring WL1 functions as an ion trap wiring that captures negative electrode impurity ions when its potential is higher than the potential of the wiring WL2.

FIG. 3 is a plan view showing the sensor electrode Rx and the pixel PX shown in FIG. In FIG. 3, the direction that intersects the second direction Y at an acute angle counterclockwise is defined as the direction D1, and the direction that intersects the second direction Y at an acute angle clockwise is defined as the direction D2. The angle θ1 formed by the second direction Y and the direction D1 is substantially the same as the angle θ2 formed by the second direction Y and the direction D2.

One sensor electrode Rx is arranged over a plurality of pixels PX. In the illustrated example, the pixel PX located in the odd-numbered rows along the second direction Y extends along the direction D1. Further, the pixel PX located in the even-numbered rows along the second direction Y extends along the direction D2. The pixel PX here indicates a minimum unit that can be individually controlled according to a pixel signal, and may be referred to as a sub-pixel. Further, the minimum unit for realizing color display may be referred to as a main pixel MP. The main pixel MP is configured to include a plurality of sub-pixels PX that display colors different from each other. In one example, the main pixel MP includes red pixels that display red, green pixels that display green, and blue pixels that display blue as sub-pixels PX. Further, the main pixel MP may include a white pixel that displays white.
In one example, 60 to 70 main pixel MPs are arranged along the first direction X, and 60 to 70 main pixel MPs are arranged along the second direction in one sensor electrode Rx.

FIG. 4 is a diagram showing a basic configuration and an equivalent circuit of the pixel PX. The plurality of scanning lines G are connected to the scanning line driving circuit GD. The plurality of signal lines S are connected to the signal line drive circuit SD. The scanning line G and the signal line S do not necessarily have to extend linearly, and a part of them may be bent. For example, it is assumed that the signal line S extends in the second direction Y even if a part of the signal line S is bent.

The common electrode CE is provided for each sensor block B. The common electrode CE is connected to a voltage supply unit CD of a common voltage (Vcom) and is arranged over a plurality of pixels PX. Further, the common electrode CE is also connected to the touch controller TC as described above, and also functions as a sensor electrode Rx.
Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, and the like. The switching element SW is composed of, for example, a thin film transistor (TFT), and is electrically connected to the scanning line G and the signal line S. The scanning line G is electrically connected to the gate electrode GE of the switching element SW in each of the pixels PX arranged in the first direction X. The signal line S is electrically connected to the source electrode SE of the switching element SW in each of the pixels PX arranged in the second direction Y. The pixel electrode PE is electrically connected to the drain electrode DE of the switching element SW. Each of the pixel electrode PEs faces the common electrode CE, and the liquid crystal layer LC is driven by the electric field generated between the pixel electrode PE and the common electrode CE. The holding capacitance CS is formed between, for example, an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE.

FIG. 5 is a plan view showing an example of the pixel layout. The scanning lines G1 to G3 extend linearly along the first direction X, and are arranged at intervals in the second direction Y. The signal lines S1 to S7 extend substantially along the second direction Y, and are arranged at intervals in the first direction X.

Between the scanning lines G1 and G2, the red pixel PR1, the green pixel PG1, the blue pixel PB1, the red pixel PR1, the green pixel PG1, and the white pixel PW1 are arranged in this order along the first direction X.
Between the scanning lines G1 and G2, the signal lines S1 to S3 are arranged at the same interval W1, the signal lines S4 to S7 are arranged at the same interval W1, and the interval W2 of the signal lines S3 and S4 is larger than the interval W1. The blue pixel PB1 is located between the signal lines S3 and S4. The intervals W1 and W2 are both lengths along the first direction X.
Pixel electrodes PE11 having the same shape are arranged in the red pixel PR1 and the green pixel PG1, respectively, a pixel electrode PE12 larger than the pixel electrode PE11 is arranged in the blue pixel PB1, and a pixel electrode PE12 smaller than the pixel electrode PE11 is arranged in the white pixel PW1. The pixel electrode PE13 is arranged. With respect to the length Lx along the first direction X, the pixel electrodes PE11 and PE13 have the same length Lx1, and the pixel electrode PE12 has a length Lx2 longer than the length Lx1. With respect to the length Ly along the second direction Y, the pixel electrode PE11 has a length Ly1 and the pixel electrode PE12 has a length Ly2 longer than the length Ly1 and the pixel electrode PE13 has a length shorter than the length Ly1. It has Ly3. The pixel electrodes PE11 and PE13 are located between the scanning lines G1 and G2. The pixel electrode PE12 is located between the scanning lines G1 and G2 and intersects the scanning lines G2.
The pixel electrodes PE11 to PE13 have band electrodes Pa1 to Pa3 extending along the direction D1, respectively. In the illustrated example, the band electrodes Pa1 and Pa3 are two, and the band electrodes Pa2 are three. The band electrodes Pa1 to Pa3 are located between the scanning lines G1 and G2. With respect to the length Ld along the direction D1, the band electrode Pa1 has a length Ld1, the band electrode Pa2 has a length Ld2 longer than the length Ld1, and the band electrode Pa3 has a length Ld3 shorter than the length Ld1. Have.

Between the scanning lines G2 and G3, the red pixel PR2, the green pixel PG2, the white pixel PW2, the red pixel PR2, the green pixel PG2, and the blue pixel PB2 are arranged in this order along the first direction X. The red pixels PR1 and PR2, the green pixels PG1 and PG2, the blue pixels PB1 and the white pixels PW2, and the white pixels PW1 and the blue pixels PB2 are arranged in the second direction Y, respectively.
Between the scanning lines G2 and G3, the signal lines S1 to S6 are arranged at equal intervals W1, and the interval W2 of the signal lines S6 and S7 is larger than the interval W1. The blue pixel PB2 is located between the signal lines S6 and S7.
Although not described in detail, pixel electrodes PE21 having the same shape are arranged in the red pixel PR2 and the green pixel PG2, pixel electrodes PE22 larger than the pixel electrode PE21 are arranged in the blue pixel PB2, and pixel electrodes PE22 larger than the pixel electrode PE21 are arranged in the white pixel PW2. A pixel electrode PE 23 smaller than the pixel electrode PE 21 is arranged. The pixel electrodes PE21 to PE23 each have band electrodes Pb1 to Pb3 extending along the direction D2. The pixel electrodes PE21 to PE23 have the same shape as the pixel electrodes PE11 to PE13, respectively. The width of the band electrode Pb3 along the first direction X is larger than the width of the band electrode Pb1 along the first direction X. Further, the width of the band electrode Pb2 along the first direction X is smaller than the width of the band electrode Pb1 along the first direction X.

FIG. 6 is a cross-sectional view of the display panel PNL along the line EF shown in FIG. The illustrated example corresponds to an example in which the FFS (Fringe Field Switching) mode, which is one of the display modes using the lateral electric field, is applied.

The first substrate SUB1 includes an insulating substrate 10, insulating layers 11 to 16, signal lines S4 and S5, metal wirings ML4 and ML5, a common electrode CE, a pixel electrode PE11, an alignment film AL1, and the like.
The insulating substrate 10 is a substrate having light transmittance such as a glass substrate or a flexible resin substrate. The insulating layer 11 is located on the insulating substrate 10. The insulating layer 12 is located above the insulating layer 11. The insulating layer 13 is located on the insulating layer 12. Although not shown, the semiconductor layer of the switching element SW is located between the insulating layer 11 and the insulating layer 12. Further, the scanning line G is located between the insulating layer 12 and the insulating layer 13.
The signal lines S4 and S5 are located on the insulating layer 13 and are covered by the insulating layer 14.
The signal lines S4 and S5 are located in the same layer as other signal lines S (not shown). The signal lines S4 and S5 are metal materials such as aluminum (Al), titanium (Ti), silver (Ag), molybdenum (Mo), tungsten (W), copper (Cu), and chromium (Cr), and these metals. It is formed of an alloy or the like in which materials are combined, and may have a single-layer structure or a multi-layer structure. In one example, the signal lines S4 and S5 are laminated bodies in which a layer containing titanium (Ti), a layer containing aluminum (Al), and a layer containing titanium (Ti) are laminated in this order.

The metal wirings ML4 and ML5 are located on the insulating layer 14 and are covered by the insulating layer 15. The metal wiring ML4 is located directly above the signal line S4, and the metal wiring ML5 is located directly above the signal line S5. The metal wirings ML4 and ML5 are formed of the above-mentioned metal material, an alloy in which the above-mentioned metal materials are combined, or the like, and may have a single-layer structure or a multi-layer structure. In one example, the metal wirings ML4 and ML5 include a layer containing titanium (Ti), a layer containing aluminum (Al), and a laminate in which layers containing titanium (Ti) are laminated in this order, or molybdenum (Mo). It is a laminate in which a layer, a layer containing aluminum (Al), and a layer containing molybdenum (Mo) are laminated in this order.

The common electrode CE is located on the insulating layer 15 and is covered with the insulating layer 16. The common electrode CE is a transparent electrode formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The common electrode CE is electrically connected to the metal wiring ML4 or the like. As described above, the common electrode CE also functions as the sensor electrode Rx, and the metal wiring ML4 also functions as the sensor wiring L and the dummy wiring D that are electrically connected to the sensor electrode Rx.

The pixel electrode PE 11 is located on the insulating layer 16 and is covered with the alignment film AL1. The pixel electrode PE11 is a transparent electrode formed of a transparent conductive material such as ITO or IZO.

The insulating layers 11 to 13 and the insulating layer 16 are inorganic insulating layers formed of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer structure. It may have a multi-layer structure. The insulating layers 14 and 15 are organic insulating layers formed of, for example, an organic insulating material such as an acrylic resin. The insulating layer 15 may be an inorganic insulating layer.

The second substrate SUB2 includes an insulating substrate 20, a light-shielding layer BM, a color filter CF, an overcoat layer OC, an alignment film AL2, and the like.
Like the insulating substrate 10, the insulating substrate 20 is a substrate having light transmittance such as a glass substrate or a resin substrate. The light-shielding layer BM and the color filter CF are located on the side of the insulating substrate 20 facing the first substrate SUB1. The color filter CF is arranged at a position facing the pixel electrode PE11, and a part of the color filter CF overlaps the light shielding layer BM. The overcoat layer OC covers the color filter CF. The overcoat layer OC is formed of a transparent resin. The alignment film AL2 covers the overcoat layer OC. The alignment film AL1 and the alignment film AL2 are formed of, for example, a material exhibiting horizontal orientation. The first substrate SUB1 and the second substrate SUB2 described above are arranged so that the alignment film AL1 and the alignment film AL2 face each other.

The liquid crystal layer LC is located between the first substrate SUB1 and the second substrate SUB2, and is held between the alignment film AL1 and the alignment film AL2. The liquid crystal layer LC includes a liquid crystal molecule LM. The liquid crystal layer LC is composed of a positive type (positive dielectric anisotropy) liquid crystal material or a negative type (negative dielectric anisotropy) liquid crystal material.

The optical element OD1 including the polarizing plate PL1 is adhered to the insulating substrate 10. The optical element OD2 including the polarizing plate PL2 is adhered to the insulating substrate 20. The optical element OD1 and the optical element OD2 may be provided with a retardation plate, a scattering layer, an antireflection layer, and the like, if necessary.

In such a display panel PNL, in an off state in which an electric field is not formed between the pixel electrode PE11 and the common electrode CE, the liquid crystal molecule LM is initially arranged in a predetermined direction between the alignment film AL1 and the alignment film AL2. Oriented. In such an off state, the light emitted from the illumination device IL toward the display panel PNL is absorbed by the optical element OD1 and the optical element OD2, resulting in a dark display. On the other hand, in the on state where an electric field is formed between the pixel electrode PE11 and the common electrode CE, the liquid crystal molecules LM are oriented in a direction different from the initial orientation direction due to the electric field, and the orientation direction is controlled by the electric field. .. In such an on state, a part of the light from the illuminating device IL passes through the optical element OD1 and the optical element OD2 and becomes a bright display.

FIG. 7A is an enlarged plan view of the region AR1 along the straight line portion E13 of the non-display portion NDA shown in FIG. The non-display portion NDA along the straight portion E14 also has the same structure as the region AR1 shown in FIG. 7A. Here, the edge portion E3 of the display unit DA corresponds to the edge portion close to the wiring WL2 of the common electrode CE located on the outermost periphery of the display unit DA. The straight portion E13 corresponds to the edge portion of the insulating substrate 10 shown in FIG.

The scanning line drive circuit GD shown in FIG. 4 is located between the edge portion E3 and the straight line portion E13, and includes a plurality of circuit units GU1 and GU2 arranged along the second direction Y. Each circuit unit is composed of, for example, a semiconductor layer, a conductive layer which is the same layer as the scanning line G, and a plurality of transistors formed by using the conductive layer which is the same layer as the signal line S. The circuit unit GU1 is composed of, for example, a shift register SR1, gate switches GS1 to GS4, and the like. The other circuit unit GU2 is also configured in the same manner as the circuit unit GU1.

The shift register SR1 is located between the straight line portion E13 and the gate switches GS1 to GS4. The gate switches GS1 to GS4 are located between the shift register SR1 and the wiring WL2. Further, the gate switches GS1 to GS4 are arranged in this order along the second direction Y. The wiring WL3 is superimposed on the shift register SR1. Further, the wiring WL3 is superimposed on a part of the gate switches GS1 to GS4. Such wiring WL3 functions as a shield layer that shields the electric field from the scanning line drive circuit GD such as the shift register SR1. The wiring WL2 is superimposed on the other part of the gate switches GS1 to GS4.

The shift register SR1 is electrically connected to each of the gate switches GS1 and GS2 via the wiring 100, and is electrically connected to each of the gate switches GS3 and GS4 via the wiring 200. The wiring 100 is located between the gate switch GS1 and the gate switch GS2 between the wiring WL1 and the wiring WL3. The wiring 200 is located between the gate switch GS3 and the gate switch GS4 between the wiring WL1 and the wiring WL3.

The gate switches GS1 to GS4 are electrically connected to the scanning lines G1 to G4, respectively. The scanning line G1 is drawn from the gate switch GS1 to the side not facing the gate switch GS2, and the scanning line G2 is drawn from the gate switch GS2 to the side facing the gate switch GS3. The scanning line G3 is drawn out from the gate switch GS3 to the side facing the gate switch GS2 and is adjacent to the scanning line G2. The scanning line G4 is drawn from the gate switch GS4 to a side that does not face the gate switch GS3.
The gate switch GS4 and the gate switch GS5 included in the circuit unit GU2 are arranged along the second direction Y. The scanning line G4 is drawn from the gate switch GS4 to the side facing the gate switch GS5. The scanning line G4 is adjacent to the scanning line G5 drawn from the gate switch GS5. That is, focusing on the wiring WL1 and WL3, the gate switches GS1 and GS2 are located between the scanning lines G1 and G2, and neither gate switch exists between the scanning lines G2 and G3. Gate switches GS3 and GS4 are located between G3 and G4, and neither gate switch exists between scanning lines G4 and G5. The scanning lines G1 to G5 extend along the first direction X and are arranged at equal intervals in the second direction Y on the display unit DA.

Between the edge portion E3 and the straight portion E13, the wirings WL1 to WL3 extend along the second direction Y. The metal wiring SL1 is located between the wirings WL2 and WL3 and extends along the second direction Y. The wiring WL1 is superimposed on the metal wiring SL1. The metal wiring SL2 is located between the metal wiring SL1 and the edge E3, and extends along the second direction Y. The wiring WL2 is superimposed on the metal wiring SL2. The wiring WL2 includes a first layer WL21 and a second layer WL22. The first layer WL21 is superimposed on the metal wiring SL2, and the second layer WL22 is superimposed on the first layer WL21. As will be described in detail later, an insulating layer is interposed between the metal wiring SL1 and the wiring WL1 and between the metal wiring SL2 and the wiring WL2, respectively. The scanning lines G1 to G5 intersect the wirings WL1 and WL2 and intersect the metal wirings SL1 and SL2.

The wiring WL1 and the metal wiring SL1 have the same potential, and the first voltage V1 is applied. The wiring WL2 and the metal wiring SL2 have the same potential, and a second voltage V2 different from the first voltage V1 is applied. That is, the potential of the wiring WL2 is different from the potential of the wiring WL1. The potential of the wiring WL3 is different from the potential of the wiring WL1. In one example, a second voltage V2 is applied to the wiring WL3, and the potential of the wiring WL3 is the same as that of the wiring WL2. For example, the first voltage V1 is −7V, which is equivalent to the low level of the control signal supplied to the scanning line G, and the second voltage V2 is 0V, which is equivalent to the common voltage supplied to the common electrode CE.

Here, attention is paid to the wiring WL1 and the metal wiring SL1. The metal wiring SL1 has a protruding portion SLB1 that protrudes from the wiring WL1 toward the wiring WL2. In other words, the wiring WL1 has an edge EG11 facing the wiring WL2, the wiring WL2 has an edge EG12 facing the wiring WL1, and the metal wiring SL1 has an edge EG13 located between the edge EG11 and the edge EG12. is doing. The edge EG13 does not overlap with either the edge EG11 or EG12. The portion of the metal wiring SL1 from the edge EG11 to the edge EG13 corresponds to the protruding portion SLB1. In the illustrated example, the extending directions of the edges EG11 to EG13 are all parallel to the second direction Y, and are parallel to the extending directions of the wirings WL1 and WL2 or the extending directions of the metal wiring SL1. Further, in the illustrated example, the first layer WL21 is closer to the wiring WL1 than the second layer WL22, and the edge EG12 of the wiring WL2 is provided by the first layer WL21, but the present invention is not limited to this. For example, when the wiring WL2 does not include the first layer or when the second layer WL22 is closer to the wiring WL1 than the first layer WL21, the edge EG12 of the wiring WL2 is included in the second layer WL22.

As will be described in detail later, in plan view, the shortest distance from the edge EG11 to the edge EG12 is defined as the first distance DT1, and the shortest distance from the edge EG11 to the edge EG13 is defined as the second distance DT2. Here, the first distance DT1 and the second distance DT2 are defined as distances along a direction orthogonal to the extending direction of each edge. In the illustrated example, the first distance DT1 and the second distance DT2 are both distances along the first direction X.

Further, the metal wiring SL1 has a protruding portion SLE1 between the scanning lines G2 and G3 that protrudes from the wiring WL1 toward the wiring WL3. In other words, the wiring WL1 has an edge EG21 facing the wiring WL3, the wiring WL3 has an edge EG22 facing the wiring WL1, and the metal wiring SL1 has an edge EG23 located between the edge EG21 and the edge EG22. Have. The edge EG23 does not overlap with either the edge EG21 or EG22. The portion of the metal wiring SL1 from the edge EG21 to the edge EG23 corresponds to the protruding portion SLE1. Similarly, the metal wiring SL1 has a protruding portion SLE2 between the scanning lines G4 and G5 that protrudes from the wiring WL1 toward the wiring WL3.

The metal wiring SL1 does not have a protruding portion between the gate switches GS1 and GS2, and has an edge EG24 facing the wiring WL3. The wiring WL1 is superimposed on the edge EG24. That is, the edge EG24 is located between the edges EG11 and EG21. In the metal wiring SL1, the edge EG23 is closer to the wiring WL3 than the edge EG24. Similarly, the metal wiring SL1 does not have a protrusion between the gate switches GS3 and GS4.

The protrusion SLE1 has a width WS1 smaller than the distance GP1 between the scanning lines G2 and G3 without superimposing on any of the scanning lines G2 and G3. The interval GP1 and the width WS1 here correspond to the lengths along the second direction Y. Similarly, the protrusion SLE2 has a width WS2 smaller than the interval GP2 of the scanning lines G4 and G5 without superimposing on any of the scanning lines G4 and G5. In one example, the interval GP1 is equivalent to the interval GP2, but may be different from the interval GP2. Further, the width WS1 is equivalent to the width WS2, but may be different from the width WS2.

The protruding portion SLB1 overlaps with each of the scanning lines G1 to G5. Further, the protruding portion SLB1 also protrudes toward the wiring WL3 between each of the scanning lines G1 to G5.

Next, focus on the wiring WL2 and the metal wiring SL2. As described above, the wiring WL2 includes the first layer WL21 and the second layer WL2, but the first layer WL21 having the edge EG12 closest to the wiring WL1 is focused on. The metal wiring SL2 has a protruding portion SLB2 that protrudes from the first layer WL21 toward the wiring WL1. In other words, the metal wiring SL2 has an edge EG14 located between the edge EG12 and the edge EG13. The edge EG13 does not overlap with either the edge EG12 or EG13. The portion of the metal wiring SL2 from the edge EG12 to the edge EG14 corresponds to the protruding portion SLB2. In the illustrated example, the extending direction of the edge EG14 is parallel to the second direction Y and parallel to the extending direction of the metal wiring SL2.

In the example shown in FIG. 7A, the wirings WL1 to WL3 correspond to the first wiring to the third wiring, respectively, the metal wirings SL1 and SL2 correspond to the first metal wiring and the second metal wiring, respectively, and the protruding portion SLB1 corresponds to the first wiring. The protrusion SLE1 or SLE2 corresponds to the second protrusion, the protrusion SLB2 corresponds to the third protrusion, and the scanning lines G2 and G3 (or the scanning lines G4 and G5) correspond to the first protrusion, respectively. Corresponds to the scanning line and the second scanning line.

FIG. 7B is an enlarged plan view of the protrusion SLE1 shown in FIG. 7A and its periphery. In the illustrated example, each of the scanning lines G2 and G3 is formed by using the conductive layers CL1 and CL2. The conductive layer CL1 is located in the same layer as the scanning line G in the display unit DA, and is located between the insulating layers 12 and 13 shown in FIG. The conductive layer CL2 is located in the same layer as the signal line S in the display unit DA, and is located between the insulating layers 13 and 14 shown in FIG. The conductive layers CL1 and CL2 are electrically connected to each other through the contact hole CH. The contact hole CH does not overlap with the metal wiring SL1 but overlaps with the wiring WL1 and is located between the edge EG21 and the edge EG24.

The conductive layer CL1 is located on the side intersecting the edge EG11 of the wiring WL1 (the side close to the wiring WL2). The conductive layer CL2 is located on the side intersecting the edge EG21 of the wiring WL1 (the side close to the wiring WL3). The metal wiring SL1 is located in a layer different from the conductive layer CL1 and is located in the same layer as the conductive layer CL2. Therefore, in the scanning lines G2 and G3, on the side close to the wiring WL2, the first layer CL1 is superimposed on the metal wiring SL1 including the protruding portion SLB1 via the insulating layer. On the other hand, on the side close to the wiring WL3, the second layer CL2 does not overlap with the metal wiring SL1 and does not overlap with the protruding portion SLE1.

FIG. 8 is an enlarged plan view of the region AR2 along the round portion R11 of the non-display portion NDA shown in FIG. The non-display portion NDA along the round portion R2 also has the same structure as the region AR2 shown in FIG. Here, the round portion R1 of the display unit DA corresponds to the edge portion of the display unit DA that is located on the outermost circumference and is close to the wiring WL2 of the common electrode CE. The round portion R11 corresponds to the edge portion of the insulating substrate 10 shown in FIG.

The circuit unit GU3 includes a shift register SR3, gate switches GS6 to GS9, and the like. The circuit unit GU4 includes a shift register SR4, a gate switch GS10, and the like. The configuration of each of these circuit units GU3 and GU4 is the same as that of the circuit unit GU1 shown in FIG. 7A. The gate switches GS6 to GS10 are electrically connected to the scanning lines G6 to G10, respectively. The scanning lines G6 to G9 extend along the first direction X and are arranged at equal intervals in the second direction Y on the display unit DA.
The wirings WL1 to WL3 and the metal wirings SL1 and SL2 extend along the round portion R1 between the round portions R1 and R11. The wiring WL1 is located between the wirings WL2 and WL3 and is superimposed on the metal wiring SL1. The wiring WL2 is located between the wiring WL1 and the round portion R1 and is superimposed on the metal wiring SL2. The wiring WL3 is located between the wiring WL1 and the round portion R11.

The metal wiring SL1 has a protruding portion SLB1 that protrudes from the wiring WL1 toward the wiring WL2. Further, the metal wiring SL1 has a protruding portion SLE3 that protrudes from the wiring WL1 toward the wiring WL3 between the scanning lines G7 and G8. Similarly, the metal wiring SL1 has a protruding portion SLE4 between the scanning lines G9 and G10 that protrudes from the wiring WL1 toward the wiring WL3.
The protrusion SLE3 has a width WS3 smaller than the interval GP3 of the scanning lines G7 and G8 without superimposing on any of the scanning lines G7 and G8. Similarly, the protrusion SLE4 has a width WS4 smaller than the interval GP4 of the scanning lines G9 and G10 without superimposing on any of the scanning lines G9 and G10. The interval GP4 is larger than the interval GP3, and the width WS4 is larger than the width WS3. Further, the interval GP4 is larger than the interval GP2 shown in FIG. 7A, and the width WS4 is larger than the width WS2.

In the example shown in FIG. 8, the wirings WL1 to WL3 correspond to the first wiring to the third wiring, respectively, the metal wirings SL1 and SL2 correspond to the first metal wiring and the second metal wiring, respectively, and the protruding portion SLB1 corresponds to the first metal wiring. It corresponds to one protruding portion, the protruding portion SLE3 or SLE4 corresponds to the fourth protruding portion, and the scanning lines G7 and G8 (or scanning lines G9 and G10) correspond to the third scanning line and the fourth scanning line, respectively.

FIG. 9 is a diagram showing a cross-sectional view of the display panel PNL along the line GH shown in FIG. Insulating layers 14 to 16 are included as the insulating layer located between the metal wiring SL1 and the wiring WL1. The metal wirings SL1 and SL2 are located on the insulating layer 13 and are covered by the insulating layer 14. The metal wirings SL1 and SL2 are located in the same layer as the signal line S4 and the like shown in FIG. 6, and are formed of a metal material which is the same material as the signal line S4. Further, a part of the electrodes or a part of the wiring constituting the scanning line drive circuit GD described above is located on the insulating layer 13. In the metal wiring SL1, the protruding portion SLE4 is located on the scanning line drive circuit GD side, and the protruding portion SLB1 is located on the metal wiring SL2 side. The insulating layer 15 is laminated on the insulating layer 14.

The first layer WL21 of the wiring WL2 is located on the insulating layer 15 and is covered with the insulating layer 16. The first layer WL21 is located in the same layer as the common electrode CE shown in FIG. 6, and is formed of a transparent conductive material which is the same material as the common electrode CE. The insulating layer 16 is laminated on the insulating layer 15.

The wiring WL1, the wiring WL3, and the second layer WL22 of the wiring WL2 are located on the insulating layer 16 and are covered with the alignment film AL1. The wiring WL1, the wiring WL3, and the second layer WL22 are located in the same layer as the pixel electrode PE11 and the like shown in FIG. 6, and are formed of a transparent conductive material which is the same material as the pixel electrode PE11.

The liquid crystal layer LC is superimposed on the wirings WL1 to WL3. In the illustrated example, the side of the wiring WL3 that is close to the wiring WL1 and the liquid crystal layer LC are superimposed, and the side that is separated from the wiring WL1 and the seal SE are superimposed.

When the shortest distance from the edge EG11 to the edge EG12 is the first distance DT1 and the shortest distance from the edge EG11 to the edge EG13 is the second distance DT2, the protrusion ratio (%) of the protruding portion SLB1 is defined as DT2 / DT1. do.

In the example shown in FIG. 9, the insulating layer 14 corresponds to the first organic layer, the insulating layer 15 corresponds to the second organic layer, and the insulating layer 16 corresponds to the inorganic layer. Further, the edge EG11 corresponds to the first edge, the edge EG12 corresponds to the second edge, and the edge EG13 corresponds to the third edge.

According to this embodiment, the first voltage V1 is applied to the wiring WL1 and the metal wiring SL1. A second voltage V2 is applied to the wirings WL2 and WL3 and the metal wiring SL2. In this case, an electric field is generated between the wiring WL1 and the wiring WL3, and between the wiring WL1 and the wiring WL2, respectively. Such an electric field is effective in capturing the impurity ions contained in the liquid crystal layer LC, and can suppress the local aggregation of the impurity ions on the display panel.

Further, since the metal wiring SL1 located in a layer different from the wiring WL1 has a protruding portion SLB1 protruding toward the wiring WL2 from the wiring WL1, the wiring WL2 is added to the electric field between the wiring WL2 and the wiring WL1. Since an electric field is generated between the wire and the metal wiring SL1, the electric field concentration near the edge EG11 of the wiring WL1 is relaxed.
Similarly, since the metal wiring SL1 has a protruding portion SLE that protrudes from the wiring WL1 toward the wiring WL3, in addition to the electric field between the wiring WL3 and the wiring WL1, between the wiring WL3 and the metal wiring SL1. Since an electric field is generated, the electric field concentration near the edge EG21 of the wiring WL1 is relaxed.
In this way, since the electric field strength in the wiring WL1 is relaxed, the corrosion (reduction) of the wiring WL1 can be suppressed, and the generation of bubbles due to the corrosion of the wiring WL1 can be suppressed. Therefore, it is possible to suppress a decrease in reliability of the display device DSP.

Further, the above configuration is applied not only in the straight portion but also in the round portion of the display panel PNL even if a sufficient distance cannot be secured between the wiring WL1 and the wiring WL2 and between the wiring WL1 and the wiring WL3. By doing so, corrosion of the wiring WL1 can be suppressed, and a narrow frame can be realized.

Each of the scanning lines G intersects the wiring WL1 and the metal wiring SL1, and the control signal supplied to the scanning line G is at a low level equivalent to the potential of the wiring WL1 in most of the one-frame period. be. Therefore, the scanning line G intersecting the wiring WL1 and the metal wiring SL1 contributes to the relaxation of the electric field strength in the wiring WL1.

FIG. 10 is a diagram showing the relationship between the protrusion ratio (%) of the metal wiring SL1 and the electric field strength. This is a simulation result when the edge EG12 and the edge EG14 shown in FIG. 7A are superimposed in a plan view. The horizontal axis in the figure is the protrusion rate (%) of the metal wiring SL1, which is a value calculated by the second distance (DT2) / first distance (DT1). The vertical axis of the figure is the electric field strength (1.0E6V / m). The electric field strength A generated at the edge EG11 is plotted with a solid line, and the electric field strength B generated at the edge EG12 is plotted with a dotted line. The case where the protrusion ratio is positive corresponds to the case where the edge EG 13 is located outside the edge EG 11 (the side close to the wiring WL 2). The case where the protrusion ratio is zero corresponds to the case where the edge EG 13 is located directly below the edge EG 11. As a reference value Ref, the electric field strength when the edge EG13 is located inside the edge EG11 (the side separated from the wiring WL2) or the metal wiring SL1 does not exist is also shown.

Focusing on the electric field strength A of the edge EG11 shown by the solid line in FIG. 10, it can be confirmed that the electric field strength tends to decrease as the protrusion rate increases. This is because as the protrusion rate increases, the metal wiring SL1 approaches the wiring WL2, and the electric field generated between the wiring WL2 and the metal wiring SL1 increases. Based on such a tendency, it is desirable that the protrusion rate is 5% or more from the viewpoint of suppressing corrosion of the wiring WL1. Further, it is more desirable that the protrusion rate at which the electric field strength is halved from the reference value is 15% or more.

On the other hand, paying attention to the electric field strength B of the edge EG12 shown by the dotted line in FIG. 10, it can be confirmed that the electric field strength tends to increase as the protrusion ratio increases. This is because as the protrusion rate increases, the metal wiring SL1 having a potential different from that of the wiring WL2 approaches the wiring WL2. Based on such a tendency, from the viewpoint of suppressing corrosion of the wiring WL2, the protrusion rate is preferably 50% or less, and more preferably 30% or less.

As described above, in order to realize the narrowing of the frame of the display device DSP and suppress the corrosion of the wirings WL1 and WL2 due to the electric field concentration, the protrusion rate is preferably 5% or more and 50% or less. It is more desirable that it is% or more and 30% or less. In one example, the width of the protrusion SLB1 (second distance DT2) is 5 μm to 10 μm.

Next, another configuration example of this embodiment will be described.
FIG. 11 is an enlarged plan view of the region AR3 along the straight line portion E11 of the non-display portion NDA shown in FIG. In the region AR3 along the straight line portion E11, the metal wiring SL3 is provided instead of the scanning line drive circuit GD. The metal wiring SL3 has the same potential as the wiring WL3, and for example, a second voltage V2 is applied. The wiring WL3 is superimposed on the metal wiring SL3. The metal wiring SL3 has a protruding portion SLB3 that protrudes from the wiring WL3 toward the wiring WL1. In other words, the wiring WL3 has an edge EG22 facing the wiring WL1, and the metal wiring SL3 has an edge EG31 located between the edge EG21 and the edge EG22. The edge EG31 does not overlap with any of the edges EG21 to EG23. The portion of the metal wiring SL3 from the edge EG22 to the edge EG31 corresponds to the protruding portion SLB3. The metal wiring SL3 is located in the same layer as the metal wiring SL1 and the like, and is formed of the same material as the metal wiring SL1.

Further, the edge EG23 of the metal wiring SL1 is located on the wiring WL3 side of the edge EG21 of the wiring WL1 in almost the entire area of the region AR3. That is, the metal wiring SL1 does not have a partially protruding portion as shown in FIGS. 7A and 8 on the side facing the wiring WL3, but the protruding portion over almost the entire area on the side facing the wiring WL3. Has SLE.

In the example shown in FIG. 11, the metal wiring SL3 corresponds to the third metal wiring, and the protruding portion SLB3 corresponds to the fifth protruding portion.

Even in such a configuration example, when an electric field is generated between the wiring WL1 and the wiring WL3, an electric field is also formed between the wiring WL1 and the metal wiring SL3, and the electric field concentration on the wiring WL3 is relaxed. .. Therefore, corrosion of the wiring WL3 can be suppressed. In the illustrated example, the wiring SL4 having a potential different from that of the wiring WL3 is arranged directly under the wiring WL3. The wiring SL4 does not protrude from the wiring WL3 toward the wiring WL1, and is surrounded by the wiring WL3 and the metal wiring SL3. Therefore, electric field leakage from the wiring SL4 is suppressed.

FIG. 12 is a plan view showing another configuration example of the display device DSP. The wiring WL4 intersects the metal wiring SL1 and the wiring WL1. The potential of the wiring WL4 is different from that of the wiring WL1. In such a layout, the metal wiring SL1 has not only the protruding portion SLB1 protruding toward the wiring WL2 but also the protruding portion SLE protruding toward the wiring WL3. The wiring WL4 overlaps with the protruding portion SLB1 and the protruding portion SLE.
In the example shown in FIG. 12, the wiring SL4 corresponds to the fourth metal wiring, and the protruding portion SLE corresponds to the sixth protruding portion.

In such a configuration example, when an electric field is generated between the wiring WL1 and the wiring WL4, an electric field is also formed between the metal wiring SL3 and the wiring WL4, and the electric field concentration on the wiring WL1 is relaxed. .. Therefore, corrosion of the wiring WL1 can be suppressed.

As described above, according to the present embodiment, it is possible to provide a display device capable of suppressing a decrease in reliability.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.
For example, in the present embodiment, the pixel widths of the red pixel, the green pixel, and the white pixel are the same, but the pixel widths of these pixels may be different. Further, in the present embodiment, the pixel electrodes of the red pixel, the green pixel, and the white pixel have the same shape, but the shapes of these pixel electrodes may be different.

DSP ... Display device DA ... Display unit NDA ... Non-display unit WL ... Wiring SL ... Metal wiring G ... Scanning line S ... Signal line

Claims (13)

Display and
A non-display unit located around the display unit and
The first metal wiring located in the non-display part and
An insulating layer located on the first metal wiring and
A first transparent conductive film located on the insulating layer, having the same potential as the first metal wiring, and superimposing on the first metal wiring.
A second transparent conductive film having a potential different from that of the first transparent conductive film, which is located between the first transparent conductive film and the display unit, is provided.
The first transparent conductive film has a first edge facing the second transparent conductive film, and has a first edge.
The second transparent conductive film has a second edge facing the first transparent conductive film and has a second edge.
The first metal wiring is a display device having a third edge located between the first edge and the second edge in a plan view. The display device according to claim 1, wherein the first metal wiring has a first protruding portion that protrudes toward the second transparent conductive film from the first transparent conductive film in a plan view. Further, a third transparent conductive film located in the non-display portion and having the same potential as the second transparent conductive film,
A first scanning line and a second scanning line intersecting with the first metal wiring are provided.
The first transparent conductive film is located between the second transparent conductive film and the third transparent conductive film, and is located between the second transparent conductive film and the third transparent conductive film.
The first metal wiring has a second protruding portion between the first scanning line and the second scanning line, which protrudes from the first transparent conductive film toward the third transparent conductive film in a plan view. The display device according to claim 2, which has. The display device according to claim 3, wherein the width of the second protruding portion is smaller than the distance between the first scanning line and the second scanning line. The display device according to claim 4, wherein the first protruding portion is superimposed on the first scanning line and the second scanning line. Further, a second metal wiring having the same potential as the second transparent conductive film is provided.
The second transparent conductive film overlaps with the second metal wiring,
The display device according to claim 2, wherein the second metal wiring has a third protruding portion that protrudes toward the first transparent conductive film from the second transparent conductive film in a plan view. In addition, with an insulating substrate,
A third scanning line and a fourth scanning line, which are located on the insulating substrate and intersect with the first metal wiring, are provided.
In a plan view, the first metal wiring has a fourth protruding portion between the third scanning line and the fourth scanning line, which protrudes from the first transparent conductive film toward the third transparent conductive film. Have and
The insulating substrate has a round portion and a straight portion, and has a round portion and a straight portion.
The second protruding portion is located at the non-display portion along the straight portion.
The fourth protrusion is located at the non-display portion along the round portion.
The display device according to claim 3, wherein the width of the fourth protrusion is larger than the width of the second protrusion. The insulating layer includes a first organic layer, a second organic layer laminated on the first organic layer, and an inorganic layer laminated on the second organic layer.
The first metal wiring is covered with the first organic layer, and the first metal wiring is covered with the first organic layer.
The first transparent conductive film and the third transparent conductive film are located on the inorganic layer.
The display device according to claim 2, wherein the second transparent conductive film is located between the second organic layer and the inorganic layer, or on the inorganic layer. Further, a first substrate, a second substrate, and a liquid crystal layer held between the first substrate and the second substrate are provided.
The first substrate includes the first transparent conductive film, the second transparent conductive film, and the third transparent conductive film.
The display device according to claim 8, wherein the liquid crystal layer is superimposed on the first transparent conductive film, the second transparent conductive film, and the third transparent conductive film. Further, a seal for adhering the first substrate and the second substrate is provided.
The display device according to claim 9, wherein the seal is superimposed on the third transparent conductive film. When the distance from the first edge to the second edge is defined as the first distance and the distance from the first edge to the third edge is defined as the second distance,
The display device according to claim 1, wherein the second distance is 5% or more and 50% or less of the first distance. Further, a third metal wiring having the same potential as the third transparent conductive film is provided.
The third transparent conductive film overlaps with the third metal wiring,
The display device according to claim 3, wherein the third metal wiring has a fifth protruding portion that protrudes toward the first transparent conductive film from the third transparent conductive film in a plan view. Further, a fourth metal wiring that intersects with the first metal wiring and has a potential different from that of the first transparent conductive film is provided.
The first metal wiring has a sixth protruding portion that protrudes toward the third transparent conductive film from the first transparent conductive film in a plan view.
The display device according to claim 3, wherein the fourth metal wiring overlaps with the first protruding portion and the sixth protruding portion.

Images