JP6901583B2 - Semiconductor device - Google Patents

Description

The invention disclosed herein relates to a semiconductor device (eg, a composite isolator) that handles pulse signals.

Conventionally, for example, in the field of AC / DC converters and DC / DC converters used as power supplies for in-vehicle equipment and industrial equipment, the insulation between the primary circuit system and the secondary circuit system is magnetically coupled using an isolator. There is a technology to keep it.

As an example of the prior art related to the above, Patent Document 1 can be mentioned.

Japanese Unexamined Patent Publication No. 2008-187821

However, in an environment where a lot of switching noise is generated around the isolator, it is difficult to accurately transmit the pulse signal, and especially in an AC / DC converter with a high input voltage, there is a problem that the noise level generated in the isolator is large. It was.

The above-mentioned problems apply not only to isolators but also to semiconductor devices in general that handle pulse signals.

An object of the invention disclosed in the present specification is to provide a semiconductor device capable of reducing noise of a pulse signal in view of the above-mentioned problems found by the inventor of the present application.

The semiconductor device disclosed in the present specification includes a first chip that is a transmitting side of a pulse signal, a second chip that is a receiving side of the pulse signal, and the first chip and the above using an integrated transformer. It has a third chip that transmits the pulse signal from the first chip to the second chip while being electrically insulated from the second chip, and the second chip and the third chip are each in the preceding stage. A first electrode for receiving an input of the pulse signal from the chip via a bonding wire is provided, and at least one lower region of the first electrode of each chip is electrically connected to the first electrode. It is configured to be insulated and provided with a second electrode connected to the reference potential end (first configuration).

In the semiconductor device having the first configuration, the second electrode may have a configuration (second configuration) formed by using a metal layer or a polysilicon layer.

Further, in the semiconductor device having the first or second configuration, the second electrode may have an area equal to or larger than that of the first electrode in a plan view (third configuration).

Further, in the semiconductor device having any of the first to third configurations, at least one layer short-circuited between the first electrode and the second electrode by one of the first electrode and the second electrode. It is preferable to use a configuration in which an intermediate electrode is provided (fourth configuration).

Further, in the semiconductor device having the fourth configuration, between the first electrode and the second electrode, as the intermediate electrode, at least one layer of the first intermediate electrode short-circuited to the first electrode and the said. It is preferable to have a configuration in which at least one layer of the second intermediate electrode short-circuited to the second electrode is alternately laminated (fifth configuration).

Further, in the semiconductor device having any of the first to fifth configurations, the first chip may have a configuration (sixth configuration) having a function of adjusting the pulse width of the pulse signal.

Further, the semiconductor device having any of the first to sixth configurations functions as a control main body of an isolated switching power supply by transmitting signals between the primary circuit system and the secondary circuit system while electrically insulating them. It is preferable to use a configuration (seventh configuration).

Further, the insulated switching power supply disclosed in the present specification has a configuration (eighth configuration) including a semiconductor device having a seventh configuration and a switching output stage controlled by the semiconductor device. ing.

In the isolated switching power supply having the eighth configuration, the switching output stage electrically insulates the primary circuit system and the secondary circuit system by using a transformer, and the DC input supplied to the primary circuit system. It is preferable to have a configuration (nineth configuration) that functions as a component of the DC / DC converter that generates a DC output voltage from the voltage and supplies it to the load of the secondary circuit system.

Further, the isolated switching power supply having the ninth configuration may have a configuration (tenth configuration) further including a rectifying unit that generates the DC input voltage from the AC input voltage.

Further, the electronic device disclosed in the present specification includes an isolated switching power supply having any of the eighth to tenth configurations, and a load that operates by receiving power supply from the insulated switching power supply. It is said to be a configuration (11th configuration).

Further, the chips disclosed in the present specification include a first electrode for receiving an input of a pulse signal via a bonding wire, and are provided in a region below the first electrode to be electrically connected to the first electrode. The second electrode, which is insulated from the ground and connected to the reference potential end, is integrated (12th configuration).

Further, the chip disclosed in the present specification has a pad for receiving an input of a pulse signal via a wire, and the wire functions as an inductor forming a filter and is connected to the pad or the pad. The wiring layer is configured to function as the first electrode of the capacitor forming the filter (thirteenth configuration).

In the chip having the thirteenth configuration, the inductance value of the inductor may be adjusted by the length, diameter, number of wires, or material of the wire (fourth configuration).

Further, in the chip having the 14th configuration, the length of the wire may be adjusted by the position of the pad (15th configuration).

Further, in the chip having any of the thirteenth to fifteenth configurations, the capacitance value of the capacitor is adjusted by the facing area between the first electrode and the second electrode or the distance between the electrodes (the sixteenth configuration). It is good to set it to.

Further, in the chip having the 16th configuration, the distance between the first electrode and the second electrode is any of the first electrode and the second electrode among the plurality of wiring layers formed in a laminated manner. It is preferable to use a configuration (17th configuration) that is adjusted depending on whether or not a wiring layer is used.

Further, in the chip having the 17th configuration, the distance between the electrodes of the 1st electrode and the 2nd electrode may be adjusted by the thickness of the interlayer insulating layer (18th configuration).

Further, in the chip having the 16th configuration, the first electrode and the second electrode are formed in the same wiring layer, and have comb teeth that mesh with each other at a distance between the electrodes (a configuration in which the first electrode and the second electrode are formed in the same wiring layer. It is preferable to use the 19th configuration).

Further, the chip having any of the 13th to 19th configurations may have a configuration (20th configuration) in which the pad is exposed and a protective layer for covering the surface of the chip is further provided.

According to the invention disclosed in the present specification, it is possible to provide a semiconductor device capable of reducing noise of a pulse signal.

Block diagram showing the overall configuration of an electronic device equipped with an isolated switching power supply Schematic diagram showing the first embodiment of the power supply IC Equivalent circuit diagram of the signal transmission path in the first embodiment Schematic diagram showing the second embodiment of the power supply IC Equivalent circuit diagram of the signal transmission path in the second embodiment Schematic diagram showing a first structural example of a capacitor Schematic diagram showing a second structural example of a capacitor Schematic diagram showing a third structural example of a capacitor Schematic diagram for explaining the method of adjusting the inductance value Schematic diagram for concretely explaining the method of adjusting the inductance value Schematic diagram showing a fourth structural example of a capacitor Schematic diagram showing a fifth structural example of a capacitor Schematic diagram showing a fifth structural example of a capacitor

<Insulated switching power supply>
FIG. 1 is a block diagram showing an overall configuration of an electronic device provided with an isolated switching power supply. The electronic device X of this configuration example has an isolated switching power supply 1 and a load 2 that operates by receiving power supply from the insulated switching power supply 1.

The isolated switching power supply 1 electrically insulates between the primary circuit system 1p (GND1 system) and the secondary circuit system 1s (GND2 system), and is supplied to the primary circuit system 1p from the commercial AC power supply PW. An AC / DC converter that converts an input voltage Vac (for example, AC85-265V) into a desired DC output voltage Vo (for example, DC10-30V) and supplies it to the load 2 of the secondary circuit system 1s. The DC / DC conversion unit 20 is included.

The rectifying unit 10 is a circuit block that generates a DC input voltage Vi (for example, DC120 to 375V) from an AC input voltage Vac and supplies it to the DC / DC converter 20, a filter 11, a diode bridge 12, a capacitor 13, and a capacitor 13. 14 and is included. The filter 11 removes noise and surge from the AC input voltage Vac. The diode bridge 12 full-wave rectifies the AC input voltage Vac to generate the DC input voltage Vi. The capacitor 13 removes harmonic noise of the AC input voltage Vac. The capacitor 14 smoothes the DC input voltage Vi. A protective element such as a fuse may be provided in front of the rectifying unit 10.

The DC / DC converter 20 is a circuit block that generates a desired DC output voltage Vo from the DC input voltage Vi and supplies it to the load 2, and is a power supply IC 100 and various discrete components (transformer TR) externally attached to the power supply IC 100. , N-channel type MOS field effect transistor N1, sense resistor Rs, diode D1, capacitor C1, and resistors R1 and R2).

The power supply IC 100 is an isolated switching power supply that uses an isolator chip 130 (details will be described later) to electrically insulate between the primary circuit system 1p and the secondary circuit system 1s and transmit signals between them. It is a semiconductor device that functions as a control main body of 1 (particularly DC / DC converter 20). For example, the power supply IC 100 receives the feedback input of the voltage dividing voltage Vdiv (= voltage dividing voltage of the DC output voltage Vo) generated in the secondary circuit system 1s, and turns on / on the transistor N1 provided in the primary circuit system 1p. Perform off control.

The transformer TR is a primary winding Lp (number of turns Np) and a secondary winding Ls (number of turns Ns) that are magnetically coupled to each other with opposite polarities while electrically insulating between the primary circuit system 1p and the secondary circuit system 1s. including. The first end of the primary winding Lp is connected to the application end of the DC input voltage Vi. The second end of the primary winding Lp is connected to the drain of the transistor N1. The first end of the secondary winding Ls is connected to the anode of the diode D1. The second end of the secondary winding Ls is connected to the ground end GND2 of the secondary circuit system 1s. The number of turns Np and Ns may be arbitrarily adjusted so that a desired DC output voltage Vo can be obtained. For example, the larger the number of turns Np or the smaller the number of turns Ns, the lower the DC output voltage Vo, and conversely, the smaller the number of turns Np or the larger the number of turns Ns, the higher the DC output voltage Vo.

The transistor N1 functions as an output switch element that is turned on / off according to the gate signal G1 input from the power supply IC 100. Specifically, the transistor N1 is turned on when the gate signal G1 is at a high level and turned off when the gate signal G1 is at a low level. As described above, the drain of the transistor N1 is connected to the second end of the primary winding Lp. The source of the transistor N1 is connected to the first end of the sense resistor Rs. The second end of the sense resistor Rs is connected to the ground end GND1 of the primary circuit system 1p. The sense resistor Rs functions as a current / voltage conversion element for detecting the primary current Ip flowing through the transistor N1 as a sense voltage Vs (= Ip × Rs).

The anode of the diode D1 is connected to the first end of the secondary winding Ls, as described above. Both the cathode of the diode D1 and the first end of the capacitor C1 are connected to the output end of the DC output voltage Vo. The second end of the capacitor C1 is connected to the grounded end GND2. The diode D1 and the capacitor C1 connected in this way function as a rectifying and smoothing unit that rectifies and smoothes the induced voltage generated in the secondary winding Ls to generate a DC output voltage Vo.

The resistors R1 and R2 are connected in series between the output end of the DC output voltage Vo and the ground end GND2, and output the divided voltage Vdiv (= Vo × R2 / (R1 + R2)) from the connection node between them. Functions as a voltage divider.

In the DC / DC converter 20 having the above configuration, the transformer TR, the transistor N1, the diode D1, and the capacitor C1 function as a switching output stage that generates a DC output voltage Vo from the DC input voltage Vi by the flyback method. To do.

Next, the step-down operation of the switching output stage will be briefly described. When the transistor N1 is turned on, the primary current Ip toward the ground end GND1 flows from the application end of the DC input voltage Vi via the primary winding Lp, the transistor N1, and the sense resistor Rs, so that the primary winding Electrical energy is stored in the wire Lp.

After that, when the transistor N1 is turned off, an induced voltage is generated in the secondary winding Ls magnetically coupled to the primary winding Lp, and the secondary winding Ls is directed from the secondary winding Ls to the ground end GND2 via the diode D1. Current Is flows. At this time, a DC output voltage Vo obtained by rectifying and smoothing the induced voltage of the secondary winding Ls is supplied to the load 2.

After that, the same switching operation as described above is repeated by turning on / off the transistor N1.

As described above, according to the isolated switching power supply 1 of this configuration example, the DC output voltage Vo is generated from the AC input voltage Vac while electrically insulating the primary circuit system 1p and the secondary circuit system 1s. Can be supplied to the load 2.

<Power supply IC (first embodiment)>
FIG. 2 is a schematic view showing a first embodiment of the power supply IC 100. The power supply IC 100 of the present embodiment is a multi-chip type semiconductor device (so-called composite isolator) in which a primary side control chip 110, a secondary side control chip 120, and an isolator chip 130 are sealed in a single package. Is.

The primary side control chip 110 has an RS flip-flop 111 and pads T11 and T12 as receiving units for receiving pulse signals S10 and S20 from the secondary side control chip 120 via the isolator chip 130. Further, the primary side control chip 110 has pulse signal generation units 112 and 113 and pads T13 and T14 as transmission units for transmitting pulse signals S30 and S40 to the secondary side control chip 120 via the isolator chip 130. The reference potential end of the primary control chip 110 is connected to the ground terminal GND1.

The secondary side control chip 120 has pulse signal generation units 121 and 122 and pads T21 and T22 as transmission units for transmitting pulse signals S10 and S20 to the primary side control chip 110 via the isolator chip 130. Further, the secondary side control chip 120 has an RS flip-flop 123 and pads T23 and T24 as receiving units for receiving pulse signals S30 and S40 from the primary side control chip 110 via the isolator chip 130. The reference potential end of the secondary control chip 120 is connected to the ground terminal GND2.

As the pulse signal generation units 112 and 113 and the pulse signal generation units 121 and 122, for example, a one-shot pulse generation circuit can be preferably used.

The isolator chip 130 is an integrated transformer 131 to 131 as a means for transmitting pulse signals S10 to S40 between both chips while electrically insulating the primary side control chip 110 and the secondary side control chip 120. It has 134, pads T31a to T34a, and pads T31b to T34b. The integrated transformers 131 to 134 include an input winding (solid line) and an output winding (broken line) magnetically coupled to each other with the same polarity.

When focusing on the pulse signals S10 and S20, the secondary control chip 120 corresponds to the first chip that is the transmission side of the pulse signals S10 and S20, and the primary control chip 110 is the pulse signals S10 and S20. It corresponds to the second chip on the receiving side. Further, the isolator chip 130 electrically insulates between the primary side control chip 110 and the secondary side control chip 120 by using the integrated transformers 131 and 132, and from the secondary side control chip 120 to the primary side control chip 120. It corresponds to the third chip that transmits the pulse signals S10 and S20 to 110.

On the other hand, when focusing on the pulse signals S30 and S40, the primary side control chip 110 corresponds to the first chip that is the transmission side of the pulse signals S30 and S40, and the secondary side control chip 120 is the pulse signals S30 and S40. It corresponds to the second chip on the receiving side. Further, the isolator chip 130 electrically insulates between the primary side control chip 110 and the secondary side control chip 120 by using the integrated transformers 133 and 134, and from the primary side control chip 110 to the secondary side control chip 130. Corresponds to the third chip that transmits the pulse signals S30 and S40 to 120.

Next, focusing on the transmission paths of the pulse signals S10 and S20, the connection relationship between the elements will be described in order from the upstream side of each. The output ends of the pulse signal generation units 121 and 122 are connected to the pads T21 and T22, respectively. The pads T21 and T22 are connected to the pads T31b and T32b via bonding wires W21 and W22, respectively. The pads T31b and T32b are connected to the input windings (solid lines) of the integrated transformers 131 and 132, respectively. The output windings (broken lines) of the integrated transformers 131 and 132 are connected to the pads T31a and T32a. The pads T31a and T32a are connected to the pads T11 and T12 via bonding wires W11 and W12, respectively. The pads T11 and T12 are connected to the set end (S) and the reset end (R) of the RS flip-flop 111, respectively.

Subsequently, the transmission operation of the pulse signals S10 and S20 will be described. The pulse signal generation unit 121 pulse-drives the input winding (solid line) of the integrated transformer 131 when the output end (Q) of the RS flip-flop 111 is set to the first logic level (for example, high level). As a result, an induced pulse is generated in the output winding (broken line) of the integrated transformer 131, and this is transmitted as a pulse signal S10 (= corresponding to the set signal) to the set end (S) of the RS flip-flop 111.

On the other hand, the pulse signal generation unit 122 pulse-drives the input winding (solid line) of the integrated transformer 132 when the output end (Q) of the RS flip-flop 111 is reset to the second logic level (for example, low level). .. As a result, an induced pulse is generated in the output winding (broken line) of the integrated transformer 132, and this is transmitted as a pulse signal S20 (= corresponding to the reset signal) to the reset end (R) of the RS flip-flop 111.

The RS flip-flop 111 sets the output end (Q) to the first logic level (for example, high level) according to the pulse signal S10 input to the set end (S), and is input to the reset end (R). The output end (Q) is reset to the second logic level (for example, low level) according to the pulse signal S20.

The secondary side control chip 120 has, for example, an output feedback control unit (not shown) that controls the duty of the pulse width modulation signal PWM so that the voltage dividing voltage Vdiv matches the reference voltage Vref, and the pulse signal. The generation units 121 and 122 may be configured to pulse drive each input winding (solid line) of the integrated transformers 131 and 132 at, for example, the rising timing and the falling timing of the pulse width modulation signal PWM. Further, the primary side control chip 110 may be configured to switch the logic level of the gate signal G1 according to the logic level of the output end (Q) of the RS flip-flop 111, for example.

Next, focusing on the transmission paths of the pulse signals S30 and S40, the connection relationship between the elements will be described in order from the upstream side of each. The output ends of the pulse signal generators 112 and 113 are connected to the pads T13 and T14, respectively. The pads T13 and T14 are connected to the pads T33a and T34a via bonding wires W13 and W14, respectively. The pads T33a and T34a are connected to the input windings (solid lines) of the integrated transformers 133 and 134, respectively. The output windings (dashed lines) of the integrated transformers 133 and 134 are connected to the pads T33b and T34b. The pads T33b and T34b are connected to the pads T23 and T24 via bonding wires W23 and W24, respectively. The pads T23 and T24 are connected to the set end (S) and the reset end (R) of the RS flip-flop 123, respectively.

Subsequently, the transmission operation of the pulse signals S30 and S40 will be described. The pulse signal generation unit 112 pulse-drives the input winding (solid line) of the integrated transformer 133 when the output end (Q) of the RS flip-flop 123 is set to the first logic level (for example, high level). As a result, an induced pulse is generated in the output winding (broken line) of the integrated transformer 133, and this is transmitted as a pulse signal S30 (= corresponding to the set signal) to the set end (S) of the RS flip-flop 123.

On the other hand, the pulse signal generation unit 113 pulse-drives the input winding (solid line) of the integrated transformer 134 when the output end (Q) of the RS flip-flop 123 is reset to the second logic level (for example, low level). .. As a result, an induced pulse is generated in the output winding (broken line) of the integrated transformer 134, and this is transmitted as a pulse signal S40 (= corresponding to the reset signal) to the reset end (R) of the RS flip-flop 123.

The RS flip-flop 123 sets the output end (Q) to the first logic level (for example, high level) according to the pulse signal S30 input to the set end (S), and is input to the reset end (R). The output end (Q) is reset to the second logic level (for example, low level) according to the pulse signal S40.

The primary side control chip 110 has, for example, an abnormality notification unit (not shown) that generates an abnormality notification signal ERR to the secondary side control chip 120, and the pulse signal generation units 112 and 113 have, for example, an abnormality. The input windings (solid lines) of the integrated transformers 133 and 134 may be pulse-driven at the rising and falling timings of the notification signal ERR. Further, the secondary side control chip 120 may be configured to switch whether or not to shut down the DC output voltage Vo generation operation according to the logic level of the output end (Q) of the RS flip-flop 123, for example. ..

By the way, in the package of the power supply IC 100, not only the isolator chip 130 but also the primary side control chip 110 and the secondary side control chip 120 that generate switching noise are sealed. As described above, in an environment where a large amount of switching noise is generated around the isolator chip 130, it is difficult to accurately transmit the pulse signals S10 to S40. In particular, in the isolated switching power supply 1 to which a high AC input voltage Vac is input, the noise level generated in the isolator chip 130 is large, and it is very important to reduce this.

Therefore, in the power supply IC 100 of the present embodiment, an LC low-pass filter is introduced on the upstream side (= input winding side) of each of the integrated transformers 131 to 134. In particular, as the inductor L for forming the LC low-pass filter, the inductance component of the bonding wire (W21, W22, W13, W14) is positively used. Further, the capacitor C for forming the LC low-pass filter is formed by utilizing the signal input pads (T31b, T32b, T33a, T34a) of the isolation chip 130 and the conductor layer and the dielectric layer in the region below the signal input pads (T31b, T32b, T33a, T34a). (See the hatch area in the figure, details will be described later).

In this way, by introducing the LC low-pass filter 220 on the upstream side of each of the integrated transformers 131 to 134, the noise of each of the pulse signals S10 to S40 transmitted via the isolator chip 130 can be effectively reduced. Is possible.

The pulse signal generation units 121 and 122, and the pulse signal generation units 112 and 113, respectively, have a function of arbitrarily adjusting the pulse widths of the pulse signals S10 to S40. By providing this function, the pulse width of the pulse signals S10 to S40 can be optimized even if the cutoff frequency fc (= 1 / (2π · √ (LC)) of the LC low-pass filter varies slightly. , The noise of the pulse signals S10 to S40 can be appropriately reduced.

FIG. 3 is an equivalent circuit diagram of the signal transmission path according to the first embodiment. As shown in this figure, the integrated transformer 210 includes an input winding 211 and an output winding 212 that are magnetically coupled to each other with the same polarity. Further, an LC low-pass filter 220 is introduced on the upstream side (= input winding 211 side) of the integrated transformer 210. The LC low-pass filter 220 includes an inductor 221 and a capacitor 222.

The first end of the inductor 221 is connected to the signal input end IN. The second end of the inductor 221 and the first end of the capacitor 222 are connected to the first end of the input winding 211 as the output end of the LC low-pass filter 220. The second end of the capacitor 222 and the second end of the input winding 211 are both connected to the first grounded end. The first end of the output winding 212 is connected to the signal output end OUT. The second end of the output winding 212 is connected to the second grounded end.

When the integrated transformer 210 is understood as the integrated transformer 131 or 132 mentioned above, the signal input end IN corresponds to the pad T21 or T22, and the inductor 221 is the inductance component (= inductor) of the bonding wire W21 or W22. It corresponds to L), the capacitor 222 corresponds to the capacitor C formed in the lower region of the pad T31b or T32b, the signal output end OUT corresponds to the pad T31a or T32a, and the first grounding end corresponds to the grounding end GND2. , The second grounding end corresponds to the grounding end GND1.

Further, when the integrated transformer 210 is understood as the integrated transformer 133 or 134 described above, the signal input terminal IN corresponds to the pad T13 or T14, and the inductor 221 is the inductance component (= inductor) of the bonding wire W13 or W14. It corresponds to L), the capacitor 222 corresponds to the capacitor C formed in the lower region of the pad T33a or T34a, the signal output end OUT corresponds to the pad T33b or T34b, and the first grounding end corresponds to the grounding end GND1. , The second grounding end corresponds to the grounding end GND2.

<Power supply IC (second embodiment)>
FIG. 4 is a schematic view showing a second embodiment of the power supply IC 100. The power supply IC 100 of this embodiment is based on the first embodiment (FIG. 2) described above, and an LC low-pass filter is introduced on the downstream side (= output winding side) of each of the integrated transformers 131 to 134. It is characterized by points. Even in the power supply IC 100 of the present embodiment, the inductance component of the bonding wire (W11, W12, W23, W24) is positively used as the inductor L for forming the LC low-pass filter. Further, the capacitor C for forming the LC low-pass filter includes the signal input pads (T11, T12, T23, T24) of the primary side control chip 110 and the secondary side control chip 120, respectively, and the conductor layer and the dielectric in the region below the signal input pads (T11, T12, T23, T24). It is formed using the body layer (see the hatched area in the figure, details will be described later).

By introducing the LC low-pass filter 220 on the downstream side of each of the integrated transformers 131 to 134 in this way, the pulse signal transmitted via the isolator chip 130 as in the first embodiment (FIG. 2) described above. It is possible to effectively reduce the noise of each of S10 to S40.

The pulse signal generation units 121 and 122 and the pulse signal generation units 112 and 113 have a function of arbitrarily adjusting the pulse widths of the pulse signals S10 to S40, as in the first embodiment (FIG. 2) described above. It is desirable to have. However, when adjusting the pulse width, unlike the first embodiment (FIG. 2) described above, it is necessary to consider not only the cutoff frequency fc of the LC low-pass filter but also the coupling degree of each of the integrated transformers 131 to 134. It should be noted that there is a point.

FIG. 5 is an equivalent circuit diagram of the signal transmission path according to the second embodiment. As shown in this figure, the LC low-pass filter 230 is introduced on the downstream side (= output winding 212 side) of the integrated transformer 210. The LC low-pass filter 230 includes an inductor 231 and a capacitor 232.

The first end of the input winding 211 is connected to the signal input end IN. The second end of the input winding 211 is connected to the first grounded end. The first end of the output winding 212 is connected to the first end of the inductor 231. The second end of the output winding 212 is connected to the second grounded end. The second end of the inductor 231 and the first end of the capacitor 232 are connected to the signal output end OUT as the output end of the LC low-pass filter 230. The second end of the capacitor 232 is connected to the second grounded end.

When the integrated transformer 210 is understood as the integrated transformer 131 or 132 mentioned above, the signal input end IN corresponds to the pad T31b or T32b, and the inductor 231 is the inductance component (= inductor) of the bonding wire W11 or W12. Corresponding to L), the capacitor 232 corresponds to the capacitor C formed in the lower region of the pad T11 or T12, the signal output end OUT corresponds to the pad T11 or T12, and the first grounding end corresponds to the grounding end GND2. , The second grounding end corresponds to the grounding end GND1.

Further, when the integrated transformer 210 is understood as the integrated transformer 133 or 134 described above, the signal input terminal IN corresponds to the pad T33a or T34a, and the inductor 231 is the inductance component (= inductor) of the bonding wire W23 or W24. It corresponds to L), the capacitor 232 corresponds to the capacitor C formed in the lower region of the pad T23 or T24, the signal output end OUT corresponds to the pad T23 or T24, and the first grounding end corresponds to the grounding end GND1. , The second grounding end corresponds to the grounding end GND2.

In the above, the first embodiment (FIG. 3) in which the LC low-pass filter 220 is introduced on the upstream side of the integrated transformer 210 and the second embodiment (FIG. 3) in which the LC low-pass filter 230 is introduced on the downstream side of the integrated transformer 210 (FIG. 3). Although FIG. 5) has been described individually, the first embodiment and the second embodiment may be combined and adopted. That is, it is also possible to introduce LC low-pass filters 220 and 230 on both the upstream side and the downstream side of the integrated transformer 210, respectively.

<Capacitor forming method>
Next, a method for forming the capacitor C constituting the LC low-pass filter will be described in detail.

FIG. 6 is a schematic view showing a first structural example of the capacitor C, and here, a vertical cross-sectional view (upper row) and a partial top view (lower row) of the chip on which the capacitor C is formed are drawn. In the vertical cross-sectional view (upper row), a cross section when the chip is vertically cut along the A1-A2 line in the partial top view (lower row) is depicted. The chip corresponds to the isolator chip 130 of the first embodiment (FIG. 2), or the primary side control chip 110 or the secondary side control chip 120 of the second embodiment (FIG. 4).

In the chip of this figure, the bonding wire 301, which is the transmission path of the pulse signal, is connected to the pad 302.

According to the first embodiment described above, the bonding wire W21 or W22 in FIG. 2 or the bonding wire W13 or W14 in FIG. 2 corresponds to the bonding wire 301 in the present figure, and the pads T31b or T32b or the pads T33a in FIG. Alternatively, T34a corresponds to the pad 302 in this figure.

On the other hand, according to the second embodiment described above, the bonding wire W11 or W12 in FIG. 4 or the bonding wire W23 or W24 corresponds to the bonding wire 301 in the present figure, and the pad T11 or T12 or the pad T23 in FIG. Alternatively, T24 corresponds to the pad 302 in this figure.

Further, the chip in this figure has a two-layer wiring structure in which a first metal layer (1st MTL), an interlayer insulation layer (ILD), and a second metal layer (2nd MTL) are laminated in this order from the lower layer side (board side). It is said that. Examples of the material of each metal layer (1st MTL, 2nd MTL) include Al and Cu. Further, as the material of the interlayer insulating layer (ILD), SiO _{2 and the} like can be mentioned.

Metal wirings 303 and 306 are laid on the second metal layer (2nd MTL). A rectangular (for example, 100 μm × 100 μm) pad connection region is formed in the metal wiring 303 in a plan view, and an electrical connection with the pad 302 is established in the region. That is, the pad connection region of the metal wiring 303 functions as a first electrode for receiving the input of the pulse signal from the chip in the previous stage via the bonding wire 301 and the pad 302. Therefore, in the following description, the pad connection region of the metal wiring 303 may be referred to as the first electrode 303.

On the other hand, the metal wiring 306 also has a pad connection region similar to the above, and an electrical connection with the pad 307 is established in this region. The pad 307 is connected to a predetermined reference potential end (= grounding end or a low potential end equivalent thereto). Further, the metal wiring 306 is connected to the metal wiring 304 laid in the first metal layer (1st MTL) via a via 305 penetrating the interlayer insulation layer (ILD).

The metal wiring 304 extends to a region below the first electrode 303 (= a region that overlaps with the first electrode 303 in the vertical direction of the chip), and is equal to or more than the first electrode 303 in a plan view thereof. A rectangular area having the area of is formed. However, electrical insulation is maintained between the rectangular region and the first electrode 303 by separating an interlayer insulating layer (ILD). That is, the rectangular region is electrically insulated from the first electrode 303 and functions as a second electrode connected to the reference potential end. Therefore, in the following description, the rectangular region of the metal wiring 304 may be referred to as a second electrode 304.

By adopting this structural example, the capacitor C can be formed by the first electrode 303 and the second electrode 304, which are conductors, and the dielectric (interstitial insulating layer (ILD)) sandwiched between the two electrodes. it can. Further, in the present structural example, since the lower region of the pad 302 can be effectively used, the area of the chip is not unnecessarily increased when the capacitor C is formed.

FIG. 7 is a schematic view showing a second structural example of the capacitor C. In this structural example, a polysilicon layer (poly-Si) is laminated and formed on the lower layer side (board side) of the first metal layer (1st MTL) based on the first structural example (FIG. 6) described above. It has a three-layer wiring structure.

That is, in the chip of this figure, the polysilicon layer (poly-Si), the first interlayer insulating layer (1st ILD), the first metal layer (1st MTL), and the second interlayer insulating layer (2nd ILD) are arranged in this order from the lower layer side (board side). ) And the second metal layer (2nd MTL) are laminated.

Similar to the first structural example (FIG. 6), metal wirings 303 and 306 are laid in the second metal layer (2nd MTL). Further, the point that the rectangular pad connection region formed in the metal wiring 303 functions as the first electrode described above is no different from the above.

On the other hand, the metal wiring layer 306 is connected to the metal wiring 315 laid in the first metal layer (1st MTL) via a via 316 penetrating the second interlayer insulating layer (2nd ILD). Further, the metal wiring 315 is connected to the polysilicon wiring 313 laid in the polysilicon layer (poly-Si) via a via 314 penetrating the first interlayer insulating layer (1st ILD).

The polysilicon wiring 313 extends to a region below the first electrode 303, and in a plan view thereof, a rectangular region having an area equal to or larger than that of the first electrode 303 is formed. The rectangular region functions as the second electrode described above. Therefore, in the following description, the rectangular region of the polysilicon wiring 313 may be referred to as a second electrode 313.

By the way, since the mutual distance between the first electrode 303 and the second electrode 313 in FIG. 7 is longer than the mutual distance between the first electrode 303 and the second electrode 304 in FIG. 6, it is formed between the two electrodes. The capacitance value of the capacitor C is reduced.

Therefore, an intermediate electrode 312 formed by using the first metal layer (1st MTL) is newly provided between the first electrode 303 and the second electrode 313. The intermediate electrode 312 is short-circuited with the first electrode 303 via a via 311 penetrating the second interlayer insulating layer (2nd ILD). On the other hand, between the intermediate electrode 312 and the second electrode 313, electrical insulation is maintained by separating the first interlayer insulating layer (1st ILD).

By adopting this structural example, the capacitor C is formed by the intermediate electrodes 312 and the second electrodes 313, which are conductors, and the dielectric (first interlayer insulating layer (1st ILD)) sandwiched between the two electrodes. Can be done. Therefore, it is possible to maintain the capacitance value of the capacitor C even if the mutual distance between the first electrode 303 and the second electrode 313 increases due to the multi-layer wiring of the chip.

The intermediate electrode 312 may be formed in a rectangular shape having an area equal to or larger than that of the first electrode 303 and the second electrode 313 in a plan view.

Further, in this figure, a structure in which the intermediate electrode 312 and the first electrode 303 are short-circuited to insulate between the intermediate electrode 312 and the second electrode 313 is given as an example, but conversely, the intermediate electrode 312 and The structure may be such that the first electrode 303 is insulated and the intermediate electrode 312 and the second electrode 313 are short-circuited. In that case, the capacitor C is formed by the first electrode 303 and the intermediate electrode 312, which are conductors, and the dielectric (second interlayer insulating layer (2nd ILD)) sandwiched between the two electrodes.

FIG. 8 is a schematic view showing a third structural example of the capacitor C. In this structural example, the second electrode 401 (polysilicon layer), the first intermediate electrode 402 (first metal layer), the second intermediate electrode 403 (second metal layer), in this order from the lower layer side (board side) of the chip. The first electrode 404 (third metal layer) is laminated and formed.

The first intermediate electrode 402 is short-circuited with the first electrode 404. On the other hand, the second intermediate electrode 403 is short-circuited with the second electrode 401.

That is, between the first electrode 404 and the second electrode 401, at least one layer of the first intermediate electrode 402 short-circuited to the first electrode 401 and at least one short-circuited to the second electrode 401 as the above-mentioned intermediate electrodes. The second intermediate electrode 403 of one layer is alternately laminated.

By adopting such a structure, the capacitor Cx formed between the second electrode 401 and the first intermediate electrode 402, and the capacitor Cy formed between the first intermediate electrode 402 and the second intermediate electrode 403. And, since the capacitor Cz formed between the second intermediate electrode 403 and the first electrode 404 can be connected in parallel to form the capacitor C, the capacitance value (C = Cx + Cy + Cz) can be increased. It will be possible.

<Inductance value adjustment method>
Next, a method of adjusting the inductance value of the inductor L forming the LC low-pass filter will be described with reference to FIG. As shown in this figure, the first chip 510 on the transmitting side of the pulse signal is provided with a pad 511 for outputting the pulse signal. On the other hand, the second chip 520, which is the receiving side of the pulse signal, is provided with a pad 521 for receiving the input of the pulse signal. The pad 511 and the pad 521 are connected by a bonding wire 530.

Here, in order to adjust the inductance value of the inductor L forming the LC low-pass filter, it is conceivable to adjust the length l, the diameter φ, the number n, the material, and the like of the bonding wire 530. For example, when adjusting the length l of the bonding wire 530, the distance d between the two chips may be changed, or the position of the pad 511 or the pad 521 may be changed.

FIG. 10 is a schematic diagram for specifically explaining the method of adjusting the inductance value. In this figure, an example in which the positions of the pads T32a and T32b are changed is given based on FIG. 4 described above.

More specifically, in the plan view of the power supply IC 100, when the vertical and horizontal directions of the paper surface are defined as the vertical and horizontal directions of the power supply IC 100 (and thus the isolator chip 130), the pad T32a is on the left side of the integrated transformer 132. = It is provided on the lower side of the integrated transformer 132, not on the side close to the primary control chip 110). Further, the pad T32b is provided not on the right side of the integrated transformer 132 (= the close edge side of the secondary control chip 120) but on the upper side of the integrated transformer 132.

With such an arrangement, the bonding wires W12 and W22 connected to the pads T32a and T32b, respectively, can be made longer than the other bonding wires, and the respective inductance values can be increased.

That is, the length l of the bonding wire (and the inductance value of the inductor L forming the LC low-pass filter) can be arbitrarily adjusted depending on the position of the pad.

In this figure, for the sake of simplicity, only the arrangement of the pads T32a and T32b is described differently from the others, but for the other pads as well, the required length of the bonding wire connected to each (extended). Needless to say, the respective arrangements may be adjusted according to the inductance value of the inductor L forming the LC low-pass filter).

<Capacity value adjustment method>
The inductance value of the inductor L forming the LC low-pass filter changes not only with the length l of the bonding wire but also with the diameter φ, the number n, the material, and the like. Therefore, in order to optimize the cutoff frequency of the LC low-pass filter, it is necessary to adjust the capacitance value of the capacitor C according to the inductance value of the inductor L. In the following, a method for adjusting the capacitance value of the capacitor C will be described in detail with specific examples.

FIG. 11 is a schematic view showing a fourth structural example of the capacitor C, and here, a vertical cross-sectional view of a chip on which the capacitor C is formed is depicted. The chip corresponds to the isolator chip 130 of the first embodiment (FIG. 2).

The chip of this structural example has a five-layer wiring structure in which the polysilicon layer 600 and the metal layers 610 to 640 are laminated and formed in order from the lower layer side (board side). Further, an interlayer insulating layer 650 is formed between the polysilicon layer 600 and the metal layer 610. Similarly, interlayer insulating layers 660 to 680 are formed between the metal layers 610 to 640, respectively.

That is, in the chip of this figure, the polysilicon layer 600, the interlayer insulating layer 650, the metal layer 610, the interlayer insulating layer 660, the metal layer 620, the interlayer insulating layer 670, the metal layer 630, and the interlayer are arranged in this order from the lower layer side (board side). The insulating layer 680 and the metal layer 640 are laminated and formed.

Examples of the material of the metal layers 610 to 640 include Al and Cu. Further, examples of the material of the interlayer insulating layers 650 to 680 include SiO ₂ .

Polysilicon wiring 601 is laid on the polysilicon layer 600. The polysilicon wiring 601 is extended to the lower region of the pad (= metal wiring 641 described later) that receives the input of the pulse signal via the bonding wire.

Metal wirings 611 and 612 are laid on the metal layer 610. The metal wiring 611 has an overlapping region with the polysilicon wiring 601 (= a region facing the polysilicon wiring 601 with the interlayer insulation layer 650 interposed therebetween). However, electrical insulation is maintained between the polysilicon wiring 601 and the metal wiring 611 with an interlayer insulating layer 650 in between. The metal wiring 612 is connected to the polysilicon wiring 601 via a via 651 penetrating the interlayer insulating layer 650.

Metal wirings 621 to 623 are laid on the metal layer 620. The metal wiring 621 is connected to the metal wiring 611 via a via 661 penetrating the interlayer insulating layer 660. Further, the metal wiring 621 has an overlapping region with the polysilicon wiring 601 (= a region facing the polysilicon wiring 601 with the interlayer insulating layers 650 and 660 interposed therebetween without passing through the metal layer 611). However, electrical insulation is maintained between the polysilicon wiring 601 and the metal wiring 621 with the interlayer insulating layers 650 and 660 separated from each other. The metal wirings 622 and 623 are connected to the metal wirings 612 via vias 662 and 663 that penetrate the interlayer insulating layer 660, respectively.

Metal wiring 631 and 632 are laid on the metal layer 630. The metal wiring 631 is connected to the metal wirings 621 and 622 via vias 671 and 672 that penetrate the interlayer insulating layer 670. The metal wiring 632 is connected to the metal wiring 623 via a via 673 penetrating the interlayer insulating layer 670. The input winding of the integrated transformer is formed by the conductive path (metal wiring 631 → via 672 → metal wiring 622 → via 662 → metal wiring 612) laid in the central portion of the drawing.

Metal wirings 641 and 642 are laid on the metal layer 640. The metal wiring 641 is connected to the metal wiring 631 via a via 681 penetrating the interlayer insulating layer 680. The metal wiring 641 is formed in a rectangular shape in a plan view thereof, and functions as a pad for receiving a pulse signal input via the bonding wire. That is, the metal wiring 641 corresponds to the pad T31b or T32b or the pad T33a or T34a of the first embodiment (FIG. 2).

On the other hand, the metal wiring 642 is connected to the metal wiring 632 via a via 682 penetrating the interlayer insulating layer 680. The metal wiring 642 is formed in a rectangular shape in a plan view thereof, and functions as a GND pad connected to a predetermined reference potential end (= grounding end or a low potential end equivalent thereto).

Further, an insulating layer 691 is formed on the upper layer of the interlayer insulating layer 680 so as to fill the periphery of the metal wirings 641 and 642. Further, a protective layer 692 is formed on the outermost surface of the chip to protect the surface of the chip while exposing at least a part of the metal wirings 641 and 642 that function as pads. Examples of the material of the protective layer 692 include polyimide and the like. By providing such a protective layer 792, it is possible to relieve stress during packaging and prevent scratches during probe inspection. However, the insulating layer 791 and the protective layer 692 may be omitted.

By adopting this structural example, a capacitor C in which the metal wirings 611 and 621 are used as the first electrode, the polysilicon wiring 601 is used as the second electrode, and the interlayer insulating layers 650 and 660 sandwiched between the two electrodes are used as dielectrics. Can be formed.

That is, in the chip of this structural example, the bonding wire connected to the pad (= metal wiring 641) functions as the inductor L forming the LC low-pass filter, and the metal wiring 641 (further connected to this) functions as the pad. The metal wirings 611 and 621) function as the first electrode of the capacitor C forming the LC low-pass filter.

Further, in the case of the chip of this structure example, the lower region of the pad (= metal wiring 641) that receives the input of the pulse signal via the bonding wire can be effectively used, so that the area of the chip is increased when the capacitor C is formed. It does not increase unnecessarily.

Since the capacitance value of the capacitor C is represented by C = S / d, it can be arbitrarily adjusted according to the facing area S between the first electrode and the second electrode or the distance d between the electrodes. .. For example, the facing area S can be adjusted by adjusting the area and number of the metal wirings 611 and 621 facing the polysilicon wiring 601.

Further, the distance d between the electrodes can be adjusted depending on which wiring layer is used as the first electrode and the second electrode of the capacitor C among the plurality of wiring layers formed in a laminated manner. More specifically, in the chip of this structural example, both the metal wiring 611 and 621 are used as the first electrode of the capacitor C. For example, the metal wiring 611 is omitted and only the metal wiring 621 is used as the capacitor C. When the first electrode is used, the distance d between the electrodes can be extended to reduce the capacitance value of the capacitor C. Further, the distance d between the electrodes can be arbitrarily adjusted by changing the chip manufacturing process to optimize the thickness of the interlayer insulating layer itself.

In view of the above, it can be said that the larger the number of wiring stages (number of layers) of the chip and the thinner the interlayer insulating layer, the easier it is to adjust the characteristics (capacity value and equivalent series resistance value) of the capacitor C.

FIG. 12 is a schematic view showing a fifth structural example of the capacitor C, and here, a vertical sectional view (upper row), a partial plan view (middle row), and a partially enlarged view (lower row) of the chip on which the capacitor C is formed are shown. ) Is depicted. In the vertical cross-sectional view (upper row), a cross section when the chip is vertically cut along the A3-A4 line in the partial plan view (middle row) is depicted. Further, in the partial plan view (middle stage), metal wirings 711 and 712 are drawn by seeing through from the chip surface. Further, in the partially enlarged view (lower row), the inside of the round frame of the partial plan view (middle row) is partially enlarged and depicted.

The chip of this structural example has a three-layer wiring structure in which the polysilicon layer 700 and the metal layers 710 and 720 are laminated in this order from the lower layer side (board side). Further, an interlayer insulating layer 730 is formed between the polysilicon layer 700 and the metal layer 710. Similarly, an interlayer insulating layer 740 is formed between the metal layer 710 and the metal layer 720.

That is, in the chip of this figure, the polysilicon layer 700, the interlayer insulating layer 730, the metal layer 710, the interlayer insulating layer 740, and the metal layer 720 are laminated and formed in this order from the lower layer side (board side). The description of the insulating layer and the protective layer that cover the chip surface is omitted.

Polysilicon wiring 701 is laid on the polysilicon layer 700. The polysilicon wiring 701 is extended to the lower region of the pad (= metal wiring 721 described later) that receives the input of the pulse signal via the bonding wire.

Metal wirings 711 to 713 are laid on the metal layer 710. The metal wires 711 and 713 are connected to the polysilicon wiring 701 via vias 731 and 732 that penetrate the interlayer insulating layer 730, respectively. On the other hand, electrical insulation is maintained between the polysilicon wiring 701 and the metal wiring 721 with an interlayer insulating layer 730. The metal wirings 711 and 712 are characterized in their respective planar shapes, and this point will be described in detail later.

Metal wirings 721 and 722 are laid on the metal layer 720. The metal wiring 721 is connected to the metal wiring 712 via a via 741 penetrating the interlayer insulating layer 740. The metal wiring 721 is formed in a rectangular shape in a plan view thereof, and functions as a pad for receiving a pulse signal input via the bonding wire.

On the other hand, the metal wiring 722 is connected to the metal wiring 713 via a via 742 penetrating the interlayer insulating layer 740. The metal wiring 722 is formed in a rectangular shape in a plan view thereof, and functions as a GND pad connected to a predetermined reference potential end (= grounding end or a low potential end equivalent thereto).

By adopting this structural example, the metal wiring 712 is used as the first electrode, the polysilicon wiring 701 and the metal wiring 711 are used as the second electrode, and the interlayer insulating layers 730 and 740 sandwiched between the two electrodes are used as dielectrics. Capacitor C can be formed.

In particular, in the chip of this structural example, the metal wiring 712 (= corresponding to the first electrode of the capacitor C) and the metal wiring 711 (= corresponding to the second electrode of the capacitor C) are formed on the same metal layer 710. It is provided with comb teeth 711a and 711b that mesh with each other at a predetermined distance between electrodes (so-called MIM [Metal-Insulator-Metal] structure). According to such a structure, the facing area S between the metal wiring 712 (= first electrode) and the metal wiring 711 (= second electrode) can be expanded, so that the capacitance value of the capacitor C can be increased. It will be possible.

FIG. 13 is a schematic view showing a fifth structural example of the capacitor C, and here, a vertical cross-sectional view (upper row) and a top view (lower row) of the chip on which the capacitor C is formed are drawn. In the vertical cross-sectional view (upper row), a cross section when the chip is vertically cut along the A5-A6 line in the upper surface view (lower row) is depicted.

The chip of this structural example includes a pad 801 for receiving a pulse signal input via a bonding wire 800, and a pad 802 connected to a predetermined reference potential end (= grounding end or a low potential end equivalent thereto). An insulating layer 803 formed so as to fill the periphery of the pads 801 and 802, and a protective layer 804 that covers the surface of the chip while exposing at least a part (= the area surrounded by a large broken line) of the pads 801 and 802. Has.

These pads 801 and 802 are formed adjacent to each other on the surface of the chip and include comb teeth 801a and 801b that mesh with each other at a predetermined distance between the electrodes. According to such a structure, the facing area S between the pad 801 (= corresponding to the first electrode of the capacitor C) and the pad 802 (= corresponding to the second electrode of the capacitor C) can be expanded, so that the capacitor C can be expanded. It is possible to increase the capacity value of.

<Other variants>
In addition to the above-described embodiment, the various technical features disclosed in the present specification can be modified in various ways without departing from the spirit of the technical creation. For example, the introduction target of the LC low-pass filter is not limited to various chips (primary side control chip 110, secondary side control chip 120, and isolator chip 130) that handle pulse signals inside the power supply IC 100, and bonding. It can be extended and understood for all chips in which a pulse signal is input via a wire.

As described above, it should be considered that the above-described embodiment is exemplary in all respects and is not restrictive, and the technical scope of the present invention is not the description of the above-mentioned embodiment but the scope of claims. It should be understood that it is as indicated by and includes all modifications that fall within the meaning and scope of the claims.

The semiconductor device disclosed in the present specification can be used, for example, in an in-vehicle device or an industrial device.

1 Insulated switching power supply 1p primary circuit system (GND1 system)
1s secondary circuit system (GND2 system)
2 Load 10 Rectifier 11 Filter 12 Diode bridge 13, 14 Capacitor 20 DC / DC converter 100 Power supply IC
110 Primary side control chip 111 RS flip-flop 112, 113 Pulse signal generator 120 Secondary side control chip 121, 122 Pulse signal generator 123 RS flip-flop 130 Isolator chip 131-134 Integrated transformer 210 Integrated transformer 211 Input winding 212 Output winding 220, 230 LC low-pass filter 221 231 Inductor 222, 232 Capacitor 301 Bonding wire 302, 307 Pad 303 Metal wiring (first electrode)
304 Metal wiring (second electrode)
312 Intermediate electrode 313 polysilicon wiring (second electrode)
306, 315 Metal wiring 305, 311, 314, 316 Via 401 2nd electrode 402 1st intermediate electrode 403 2nd intermediate electrode 404 1st electrode 510 1st chip 511 pad 520 2nd chip 521 pad 530 Bonding wire 600 Polysilicon layer 601 Polysilicon wiring 610, 620, 630, 640 Metal layer 611, 612, 621-623, 631, 632 Metal wiring 641, 642 Metal wiring (pad)
650, 660, 670, 680 Interlayer insulation layer 651, 661-663, 671-673, 681, 682 Via 691 Insulation layer 692 Protective layer 700 polysilicon layer 701 polysilicon wiring 710, 720 Metal layer 711, 712, 713 Metal wiring 711a, 712a Comb teeth 721, 722 Metal wiring (pad)
730, 740 Interlayer insulation layer 731, 732, 741, 742 Via 800 Bonding wire 801, 802 Pad 801a, 802a Comb tooth 803 Insulation layer 804 Protective layer C1 Capacitor D1 Diode Lp Primary winding Ls Secondary winding N1 N channel type MOS Field Effect Transistor PW Commercial AC Power Supply R1, R2 Resistance Rs Sense Resistance T11-T14 Pad T21-T24 Pad T31a-T34a Pad T31b-T34b Pad TR Transformer W11-W14, W21-W24 Bonding Wire X Electronic Equipment

Claims (19)

A first chip configured to be the transmitting side of the pulse signal,
A second chip configured to be the receiving side of the pulse signal,
A third chip configured to transmit the pulse signal from the first chip to the second chip while electrically insulating between the first chip and the second chip using an integrated transformer. ,
Have,
The second chip and the third chip each include a first electrode configured to receive an input of the pulse signal from a chip in the previous stage via a bonding wire.
One of the first electrode of each chip, at least one of the lower region, and a second electrode provided that are configured so that is connected to the reference potential terminal while being insulated first electrode and electrically ,
The second electrode has a larger area than the first electrode in a plan view, and is connected to a pad connected to the reference potential end via a via provided at a position not overlapping with the first electrode. A semiconductor device that is connected. A first chip configured to be the transmitting side of the pulse signal,
A second chip configured to be the receiving side of the pulse signal,
A third chip configured to transmit the pulse signal from the first chip to the second chip while electrically insulating between the first chip and the second chip using an integrated transformer. ,
Have,
The second chip and the third chip each include a first electrode configured to receive an input of the pulse signal from a chip in the previous stage via a bonding wire.
One of the first electrode of each chip, at least one of the lower region, and a second electrode provided that are configured so that is connected to the reference potential terminal while being insulated first electrode and electrically ,
A semiconductor device in which at least one intermediate electrode short-circuited to the second electrode is provided between the first electrode and the second electrode. Wherein between the first electrode and the second electrode corresponds to at least a layer of the first intermediate electrode is short-circuited to the first electrode, at least one layer of the second intermediate electrode is shorted to the second electrode The semiconductor device according to claim 2 , wherein the intermediate electrodes are alternately laminated. The semiconductor device according to any one of claims 1 to 3, wherein the second electrode is formed by using a metal layer or a polysilicon layer. The semiconductor device according to any one of claims 1 to 4 , wherein the first chip has a function of adjusting a pulse width of the pulse signal. The semiconductor device according to any one of claims 1 to 5 , which functions as a control main body of an isolated switching power supply by transmitting signals between each other while electrically insulating the primary circuit system and the secondary circuit system. .. The semiconductor device according to claim 6 and
The switching output stage controlled by the semiconductor device and
Has an isolated switching power supply. The switching output stage electrically insulates the primary circuit system and the secondary circuit system using a transformer, and generates a DC output voltage from the DC input voltage supplied to the primary circuit system to generate the secondary circuit system. The isolated switching power supply according to claim 7, which functions as a component of a DC / DC converter configured to supply the load of the above. The isolated switching power supply according to claim 8 , further comprising a rectifying unit configured to generate the DC input voltage from an AC input voltage. The isolated switching power supply according to any one of claims 7 to 9,
A load configured to operate by receiving power from the isolated switching power supply,
Have an electronic device. A first electrode configured to receive a pulse signal input via a bonding wire,
A second electrode configured to so that is connected to the reference potential terminal with insulated electrically with the first electrode disposed in the lower region of the first electrode,
Ri formed by integrated,
The second electrode has a larger area than the first electrode in a plan view, and is connected to a pad connected to the reference potential end via a via provided at a position not overlapping with the first electrode. The chip that is connected. A first electrode configured to receive a pulse signal input via a bonding wire,
A second electrode configured to so that is connected to the reference potential terminal with insulated electrically with the first electrode disposed in the lower region of the first electrode,
Ri formed by integrated,
A chip in which at least one layer of intermediate electrodes short-circuited to the second electrode is provided between the first electrode and the second electrode. The chip according to claim 11 or 12, wherein the bonding wire functions as an inductor forming a filter, and the first electrode and the second electrode each function as both end electrodes of a capacitor forming the filter. Inductance value of the inductor, the length of the bonding wire, diameter, number, or may be adjusted by the material, chip according to claim 13. The length of the bonding wire, the first electrode and the electrical connection can be adjusted by the configuration position of the input pad to be established, according to claim 14 chips. The capacitance value of the capacitor, the first electrode and are adjusted by the distance between the opposing area or electrode and the second electrode, the chip according to any one of claims 13 to 15. The distance between the first electrode and the second electrode is adjusted depending on which wiring layer is used as the first electrode and the second electrode among the plurality of wiring layers formed in a laminated manner . Item 16. The chip according to item 16. The inter-electrode distance between the first electrode and the second electrode is adjusted by the thickness of the interlayer insulating layer, chip according to claim 17. The chip according to claim 15 , further comprising a protective layer that covers the surface of the chip while exposing the input pad.

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