JP6898621B2 - Multi-stage amplifier circuit - Google Patents

Description

The present invention relates to a technique relating to a multi-stage amplifier circuit used for amplifying an electric signal, and more particularly to a technique capable of widening a wide band, reducing power consumption, area saving, and noise reduction.

As shown in FIG. 19, the conventional multi-stage amplifier circuit is configured by connecting a plurality of amplifier circuits A1 and A2 having the same gain and band in series. In FIG. 19, IN is a signal input terminal, OUT is a signal output terminal, PL is a positive power supply line, and NL is a negative power supply line. When the same gain and band are realized by the one-stage amplifier circuit and the multi-stage amplifier circuit, the multi-stage amplifier circuit has a feature that the power consumption is lower (see Non-Patent Document 1).

When, for example, TIA (Transimpedance Amplifier) is realized by a conventional multi-stage amplifier circuit, since a plurality of amplifier circuits having similar frequency characteristics are connected in series, there is a problem that the attenuation gradient becomes large and the -3 dB band becomes narrow. there were.

20 (A) is a diagram showing the frequency characteristics of the amplifier circuit A1, FIG. 20 (B) is a diagram showing the frequency characteristics of the amplifier circuit A2, and FIG. 20 (C) is a multi-stage amplifier in which the amplifier circuits A1 and A2 are connected in series. It is a figure which shows the frequency characteristic of a circuit. Assuming that the gains of the amplifier circuits A1 and A2 are G and the cutoff frequency is f _{-3 dB} , the gain G'of the multi-stage amplifier circuit is larger than the gain G of the amplifier circuits A1 and A2. On the other hand, the cutoff frequency _{f'-3 dB} of the multi-stage amplifier circuit is lower than _{the cutoff frequency f -3} dB of the amplifier circuits A1 and A2.

C.-H.Wu, C.-H.Lee, W.-S.Chen, and S.-I.Liu, "CMOS wideband amplifiers using multiple inductive-series peaking technique", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 2, 2005

The present invention has been made to solve the above problems, and an object of the present invention is to provide a multi-stage amplifier circuit having a wider band than the conventional one.

The multi-stage amplifier circuit of the present invention includes a plurality of amplifier circuits connected in cascade and a passive circuit connected to two amplifier circuits other than the first stage, and the passive circuit is a two amplifier circuits other than the first stage. A first inserted between the positive power supply terminal and the positive power supply line of the first amplifier circuit and at least one of the negative power supply terminal and the negative power supply line of the first amplifier circuit. The resistor and between the positive power supply terminal and the positive power supply line of the second amplifier circuit different from the first amplifier circuit among the two amplifier circuits other than the first stage, and the negative side of the second amplifier circuit. A second resistor inserted in at least one of the power supply terminal and the negative power supply line, one end is connected to the terminal on the first amplifier circuit side of the first resistor, and the other end is the second resistor. It is composed of the capacitance connected to the terminal on the second amplifier circuit side of the resistor, and the two amplifier circuits other than the first stage are inverting amplifier circuits, and the characteristic of the passive circuit is that this passive circuit is inserted. It is characterized in that the gains of the two amplifier circuits are set so as to rise at a frequency higher than the cutoff frequency of the first-stage amplifier circuit.

Further, one configuration example (third, seventh, and ninth embodiments) of the multi-stage amplifier circuit of the present invention is characterized in that the capacitance between the gate and the source of the MOS transistor is used as the capacitance of the passive circuit. It is a thing.
Further, in one configuration example (first and second embodiments) of the multi-stage amplifier circuit of the present invention, the amplifier circuit other than the first stage is a source grounded amplifier circuit.
Further, in one configuration example of the multi-stage amplifier circuit of the present invention (fourth, eighth to tenth embodiments), the amplifier circuit other than the first stage is an inverter amplifier circuit.
Further, in one configuration example (10th embodiment) of the multi-stage amplifier circuit of the present invention, the first-stage amplifier circuit is a transimpedance amplifier circuit having a feedback resistor inserted between an input terminal and an output terminal. ..

According to the present invention, between the positive power supply terminal and the positive power supply line of one or more amplifier circuits other than the first stage, and between the negative power supply terminal and the negative power supply line of one or more amplifier circuits other than the first stage. Insert a passive circuit in at least one of them so that the characteristics of the passive circuit increase at a frequency higher than the cutoff frequency of the first stage amplifier circuit so that the gain of one or more amplifier circuits into which this passive circuit is inserted rises. By setting, the gain can be improved at high frequencies, so that a multi-stage amplifier circuit having a wider band than the conventional one can be realized.

Further, in the present invention, by configuring the passive circuit with a parallel circuit of a resistor and a capacitance, it is possible to reduce the power consumption of the multi-stage amplifier circuit as compared with the case where the passive circuit is realized by an active element. Further, in the present invention, it is possible to realize the area saving of the multi-stage amplifier circuit as compared with the case where the passive circuit is realized by the inductor.

Further, in the present invention, by configuring the passive circuit with the first and second resistors and the capacitance, the area of the multi-stage amplifier circuit can be reduced as compared with the case where the passive circuit is composed of the parallel circuit of the resistor and the capacitance. can do.

Further, in the present invention, by using the capacitance between the gate and the source of the MOS transistor as the capacitance of the passive circuit, the area of the multi-stage amplifier circuit can be further reduced.

FIG. 1 is a block diagram showing a configuration of a multi-stage amplifier circuit of the present invention. FIG. 2 is a diagram for explaining the frequency characteristics of the multi-stage amplifier circuit of the present invention. FIG. 3 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a first embodiment of the present invention. FIG. 4 is a diagram for explaining the frequency characteristics of the multi-stage amplifier circuit according to the first embodiment of the present invention. FIG. 5 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a second embodiment of the present invention. FIG. 6 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a third embodiment of the present invention. FIG. 7 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a fourth embodiment of the present invention. FIG. 8 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a fifth embodiment of the present invention. FIG. 9 is a diagram illustrating the frequency characteristics of the multi-stage amplifier circuit according to the fifth embodiment of the present invention. FIG. 10 is a circuit diagram showing the configuration of a conventional multi-stage amplifier circuit. FIG. 11 is a circuit diagram showing a configuration of a multi-stage amplifier circuit in which a fourth embodiment and a fifth embodiment of the present invention are combined. FIG. 12 is a diagram showing the frequency characteristics of each amplifier circuit of FIG. 11 and the frequency characteristics of the multi-stage amplifier circuit. FIG. 13 is a diagram showing the frequency characteristics of the multi-stage amplifier circuits of FIGS. 10 and 11. FIG. 14 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a sixth embodiment of the present invention. FIG. 15 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a seventh embodiment of the present invention. FIG. 16 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to an eighth embodiment of the present invention. FIG. 17 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a ninth embodiment of the present invention. FIG. 18 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a tenth embodiment of the present invention. FIG. 19 is a block diagram showing a configuration of a conventional multi-stage amplifier circuit. FIG. 20 is a diagram illustrating the frequency characteristics of a conventional multi-stage amplifier circuit.

[Outline of Invention]
In the present invention, a passive circuit is inserted between an amplifier circuit other than the first stage and a power supply line in the multi-stage amplifier circuit. In the conventional technique, an element whose impedance does not fluctuate depending on a frequency such as a resistor is inserted between the amplifier circuit and the power supply line. On the other hand, in the present invention, as shown in FIG. 1, passive circuits 1 and 2 whose impedance fluctuates depending on the frequency are inserted between the amplifier circuit A2 in the subsequent stage and the power supply lines PL and NL. PT in FIG. 1 is a positive power supply terminal of the amplifier circuit A2, and NT is a negative power supply terminal of the amplifier circuit A2. According to the present invention, when a signal is input, the gain can be changed according to the fluctuation of the potential difference between the amplifier circuit A2 and the power supply lines PL and NL, and the gain can be improved at a high frequency.

2 (A) is a diagram showing the frequency characteristics of the amplifier circuit A1 of FIG. 1, FIG. 2 (B) is a diagram showing the frequency characteristics of the amplifier circuit A2 of FIG. 1, and FIG. 2 (C) is a diagram showing the amplifier circuits A1 and A2. It is a figure which shows the frequency characteristic of the multi-stage amplifier circuit connected in tandem. By inserting the passive circuits 1 and 2, the frequency characteristic of the amplifier circuit A2 becomes a characteristic that the gain increases at a high frequency as shown in FIG. 2 (B). Assuming that the gain of the amplifier circuit A1 is G _A1 and the cutoff frequency is f _{-3 dB , the gain G'of the multi-stage amplifier circuit is larger than the gain G A1} of the amplifier circuit A1, and _{the cutoff frequency f'-3 dB} of the multi-stage amplifier circuit is amplified. It becomes higher than the cutoff frequency f _{-3dB of the circuit A1.}

[First Example]
Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 3 is a circuit diagram showing the configuration of the multi-stage amplifier circuit according to the first embodiment of the present invention, and the same configurations as those in FIG. 1 are designated by the same reference numerals. The multi-stage amplifier circuit of this embodiment is composed of the amplifier circuits A1 and A2a connected in series and the passive circuit 2a inserted between the negative power supply terminal and the negative power supply line NL of the subsequent amplifier circuit A2a. To.

In the amplifier circuit A2a, the gate (input terminal of the amplifier circuit A2a) is connected to the output terminal of the amplifier circuit A1, and the drain (output terminal of the amplifier circuit A2a and the positive power supply terminal) is connected to the signal output terminal OUT of the multi-stage amplifier circuit. The nMOS transistor Q1 is formed, and the load resistor R1 has one end connected to the positive power supply line PL and the other end connected to the drain of the nMOS transistor Q1. The amplifier circuit A2a is a source grounded amplifier circuit including an nMOS transistor Q1 and a load resistance R1.

The passive circuit 2a has a resistor R2 having one end connected to the source of the nMOS transistor Q1 (the negative power supply terminal of the amplifier circuit A2a) and the other end connected to the negative power supply line NL, and one end to the source of the nMOS transistor Q1. It is composed of a capacitance C1 which is connected and the other end is connected to the negative power supply line NL. As described above, the passive circuit 2a of this embodiment is a parallel circuit including the resistor R2 and the capacitance C1.

The impedance of the passive circuit 2a approaches Rs (Rs is the resistance value of the resistor R2) as the input frequency approaches 0, and approaches 0 as the input frequency approaches infinity. The gain of the amplifier circuit A2a when the input frequency is 0 is Rd / Rs (Rd is the resistance value of the load resistance R1). Here, assuming that the transconductance of the amplifier circuit A2a is gm, it is assumed that Rs >> 1 / gm. From this, the gain of the amplifier circuit A2a at a low frequency is lower than that of a general source-grounded amplifier circuit having a load resistance value of Rd.

However, since the impedance of the passive circuit 2a becomes 0, the gain of the amplifier circuit A2a at a high frequency returns to the same level as that of a general source grounded amplifier circuit of Rd. As a result, it is possible to realize an amplifier circuit A2a in which the gain increases at a high frequency as in FIG. 2B.

4 (A) is a diagram showing the frequency characteristics of the amplifier circuit A1 of FIG. 3, FIG. 4 (B) is a diagram showing the frequency characteristics of the amplifier circuit A2a of FIG. 3, and FIG. 4 (C) is a diagram showing the amplifier circuits A1 and A2a. It is a figure which shows the frequency characteristic of the multi-stage amplifier circuit connected in tandem. In this embodiment, if the cutoff frequency of the first-stage amplifier circuit A1 is f ₁ and the frequency at the zero point where the gain of the second-stage amplifier circuit A2a rises is f ₂ , the following equation may be established.
f ₁ <f ₂ ... (1)

By setting the frequency characteristics in this way, a multi-stage amplifier circuit in which the gain G'is larger than _{the gain G A1} of the amplifier circuit A1 and the cutoff frequency _{f'-3 dB is higher than the cutoff frequency f 1 of the amplifier circuit A1 is realized.} can do. In the general design method of this embodiment, the resistance value Rd of the load resistor R1 and the resistance value Rs of the resistor R2 are set so that the gain at the high frequency of the amplifier circuit A2a becomes a desired value, and the equation (1) is set. ) Satisfy the capacity value of the capacity C1.

In this embodiment, by configuring the passive circuit 2a with the resistor R2 and the capacitance C1, the power consumption of the multi-stage amplifier circuit can be reduced as compared with the case where the passive circuit is realized by the active element. Further, in this embodiment, the area of the circuit can be reduced as compared with the case where the passive circuit is realized by the inductor.

[Second Example]
Next, a second embodiment of the present invention will be described. FIG. 5 is a circuit diagram showing the configuration of the multi-stage amplifier circuit according to the second embodiment of the present invention, and the same configurations as those in FIGS. 1 and 3 are designated by the same reference numerals. The multi-stage amplifier circuit of this embodiment is composed of the amplifier circuits A1 and A2b connected in series and the passive circuit 1b inserted between the positive power supply terminal and the positive power supply line PL of the subsequent amplifier circuit A2b. To.

In the amplifier circuit A2b, the gate (input terminal of the amplifier circuit A2b) is connected to the output terminal of the amplifier circuit A1, and the drain (output terminal of the amplifier circuit A2b and the negative power supply terminal) is connected to the signal output terminal OUT of the multi-stage amplifier circuit. It is composed of a pMOS transistor Q2 and a load resistor R3 having one end connected to the drain of the pMOS transistor Q2 and the other end connected to the negative power supply line NL. The amplifier circuit A2b is a source grounded amplifier circuit including a pMOS transistor Q2 and a load resistor R3.

The passive circuit 1b has a resistor R4 having one end connected to the positive power supply line PL and the other end connected to the source of the pMOS transistor Q2 (the positive power supply terminal of the amplifier circuit A2b), and one end to the positive power supply line PL. The other end is composed of a capacitance C2 connected to the source of the pMOS transistor Q2. The passive circuit 1b is a parallel circuit including the resistor R4 and the capacitance C2.

The impedance of the passive circuit 1b approaches Rs (Rs is the resistance value of the resistor R4) as the input frequency approaches 0, and approaches 0 as the input frequency approaches infinity. The gain of the amplifier circuit A2b when the input frequency is 0 is Rd / Rs (Rd is the resistance value of the load resistance R3). As in the first embodiment, assuming that the transconductance of the amplifier circuit A2b is gm, it is assumed that Rs >> 1 / gm. From this, the gain of the amplifier circuit A2b at a low frequency is lower than that of a general source-grounded amplifier circuit having a load resistance value of Rd.

However, since the impedance of the passive circuit 1b becomes 0, the gain of the amplifier circuit A2b at a high frequency returns to the same level as that of a general source grounded amplifier circuit of Rd. As a result, it is possible to realize an amplifier circuit A2b in which the gain increases at a high frequency as in FIG. 4B.

In this embodiment, as in the first embodiment, assuming that the cutoff frequency of the first-stage amplifier circuit A1 is f ₁ and the frequency at the zero point where the gain of the second-stage amplifier circuit A2b increases is f ₂ , the equation (1) It should be designed so that is satisfied. _{As a result, the gain G'is larger than the gain G A1} of the amplifier circuit A1 and the cutoff frequency _{f'-3 dB} is the amplifier circuit A1 as in the multi-stage amplifier circuit of the first embodiment shown in FIG. 4 (C). It is possible to realize a multi-stage amplifier circuit having a cutoff frequency _{higher than f 1.} In the general design method of this embodiment, the resistance value Rd of the load resistor R3 and the resistance value Rs of the resistor R4 are set so that the gain at the high frequency of the amplifier circuit A2b becomes a desired value, and the equation (1) ) Satisfy the capacity value of the capacity C2.

In this embodiment, by configuring the passive circuit 1b with the resistor R4 and the capacitance C2, the power consumption of the multi-stage amplifier circuit can be reduced as compared with the case where the passive circuit is realized by the active element. Further, in this embodiment, the area of the multi-stage amplifier circuit can be reduced as compared with the case where the passive circuit is realized by the inductor.

In the first and second embodiments, the amplifier circuits A2a and A2b in the subsequent stage may be an amplifier circuit having a configuration other than the source grounded amplifier circuit.

[Third Example]
Next, a third embodiment of the present invention will be described. FIG. 6 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a third embodiment of the present invention, and the same configurations as those in FIGS. 1, 3, and 5 are designated by the same reference numerals. The multi-stage amplifier circuit of this embodiment is composed of the amplifier circuits A1 and A2b connected in series and the passive circuit 1c inserted between the positive power supply terminal PT and the positive power supply line PL of the subsequent amplifier circuit A2b. Will be done.

In the passive circuit 1c, instead of the capacitance C2 of the second embodiment, the gate is connected to the positive power supply line PL, and the source, drain, and body are connected to the positive power supply terminal PT of the amplifier circuit A2b. Q3 is used. Since the MOS transistor of the fine process has a very thin oxide film between the gate and the source, by adopting the configuration shown in FIG. 6, the positive power supply line PL and the positive power supply terminal PT of the amplifier circuit A2b can be obtained. The behavior is the same as when the capacitance C2 is inserted between. Instead of the nMOS transistor Q3, a pMOS transistor in which the gate is connected to the positive power supply line PL and the source, drain and body are connected to the positive power supply terminal PT of the amplifier circuit A2b may be used.

In this embodiment, the passive circuit 1c is applied to the second embodiment, but instead of the capacitance C1 of the first embodiment, the gate is connected to the negative power supply line NL, and the source and the source are connected. An nMOS transistor or pMOS transistor in which the drain and the body are connected to the negative power supply terminal of the amplifier circuit A2a may be used.

Further, in this embodiment, the direction of the nMOS transistor or pMOS transistor is reversed, the source, drain and body of the nMOS transistor or pMOS transistor are connected to the positive power supply line PL or the negative power supply line NL, and the gate is an amplifier circuit. It may be connected to the positive power supply terminal of A2b or the negative power supply terminal of the amplifier circuit A2a.
Further, as described above, the amplifier circuits A2a and A2b in the subsequent stage may be an amplifier circuit having a configuration other than the source grounded amplifier circuit.

Since the oxide film between the gate and the source of the MOS transistor of the fine process is thinner than the insulating film used in the MIM (Metal Insulator Metal) capacitance, in this embodiment, the same effect as in the first and second embodiments is obtained. In addition, the capacity value per area can be increased. Further, when the capacitances C1 and C2 are arranged as in the first and second embodiments, other elements cannot be arranged directly above the capacitances C1 and C2 in order to avoid unnecessary capacitive coupling. When a MOS transistor is used as a capacitance as in the example, another element can be arranged directly above the MOS transistor. As a result, in this embodiment, the area of the multi-stage amplifier circuit can be further reduced.

[Fourth Example]
Next, a fourth embodiment of the present invention will be described. FIG. 7 is a circuit diagram showing the configuration of the multi-stage amplifier circuit according to the fourth embodiment of the present invention, and the same configurations as those in FIGS. 1, 3, 5, and 6 are designated by the same reference numerals. .. The multi-stage amplifier circuit of this embodiment includes an amplifier circuit A1 and A2d connected in series, a passive circuit 1d inserted between the positive power supply terminal and the positive power supply line PL of the subsequent amplifier circuit A2d, and an amplifier circuit. It is composed of a passive circuit 2d inserted between the negative power supply terminal of A2d and the negative power supply line NL.

In the amplifier circuit A2d, the gate (input terminal of the amplifier circuit A2d) is connected to the output terminal of the amplifier circuit A1, and the drain (output terminal of the amplifier circuit A2d) is connected to the signal output terminal OUT of the multi-stage amplifier circuit. The gate (the input terminal of the amplifier circuit A2d) is connected to the output terminal of the amplifier circuit A1, and the drain (the output terminal of the amplifier circuit A2d) is connected to the signal output terminal OUT of the multi-stage amplifier circuit. Will be done. The amplifier circuit A2d is an inverter amplifier circuit including a pMOS transistor Q4 and an nMOS transistor Q5.

In the passive circuit 1d, one end is connected to the positive power supply line PL, the other end is connected to the source of the pMOS transistor Q4 (the positive power supply terminal of the amplifier circuit A2d), and one end is connected to the positive power supply line PL. It is composed of a capacitance C3 which is connected and the other end is connected to the source of the pMOS transistor Q4. As described above, the passive circuit 1d of this embodiment is a parallel circuit including the resistor R5 and the capacitance C3.

The passive circuit 2d has a resistor R6 having one end connected to the source of the nMOS transistor Q5 (the negative power supply terminal of the amplifier circuit A2d) and the other end connected to the negative power supply line NL, and one end to the source of the nMOS transistor Q5. It is composed of a capacitance C4 which is connected and the other end is connected to the negative power supply line NL. The passive circuit 2d is a parallel circuit including the resistor R6 and the capacitance C4.

In the inverter amplifier circuit, either the pMOS transistor Q4 or the nMOS transistor Q5 is turned off depending on the magnitude of the input signal, which can be regarded as a load resistance. That is, when the pMOS transistor Q4 is in the off state, the pMOS transistor Q4 becomes the load resistance of the nMOS transistor Q5, and when the nMOS transistor Q5 is in the off state, the nMOS transistor Q5 becomes the load resistance of the pMOS transistor Q4. Further, when the pMOS transistor Q4 is in the off state, the pMOS transistor Q4 and the resistor R5 are connected in series, so that the load resistance of the nMOS transistor Q5 becomes large. Further, when the nMOS transistor Q5 is in the off state, the nMOS transistor Q5 and the resistor R6 are connected in series, so that the load resistance of the pMOS transistor Q4 becomes large.

Also in this embodiment, assuming that the cutoff frequency of the first stage amplifier circuit A1 is f ₁ and the frequency of the zero point where the gain of the second stage amplifier circuit A2d rises is f ₂ , the capacitances C3 and C4 satisfy the equation (1). The capacity value of may be set.

In this embodiment, the passive circuit 1d is composed of the resistor R5 and the capacitance C3, and the passive circuit 2d is composed of the resistor R6 and the capacitance C4. Power consumption can be reduced. Further, in this embodiment, the area of the circuit can be reduced as compared with the case where the passive circuit is realized by the inductor. Further, in this embodiment, the gain of the multi-stage amplifier circuit can be improved as compared with the case where the passive circuit is provided in the power supply line on one side as in the first and second embodiments.

When an inverter amplification circuit is used as the amplifier circuit A2d, either the positive power supply terminal and the positive power supply line PL of the amplifier circuit A2d or the negative power supply terminal and the negative power supply line NL are used. The passive circuit may be inserted only in.

[Fifth Example]
Next, a fifth embodiment of the present invention will be described. FIG. 8 is a circuit diagram showing the configuration of the multi-stage amplifier circuit according to the fifth embodiment of the present invention, and the same configurations as those in FIGS. 1, 3, 5 and 7 are designated by the same reference numerals. .. The multi-stage amplifier circuit of this embodiment includes an amplifier circuit A1 to A3 connected in series, a passive circuit 2e inserted between the negative power supply terminal NT and the negative power supply line NL of the amplifier circuit A2, and an amplifier circuit A3. It is composed of a passive circuit 4e inserted between the negative power supply terminal NT and the negative power supply line NL.

One end of the passive circuit 2e is connected to the negative power supply terminal NT of the amplifier circuit A2, the other end is connected to the resistor R7 connected to the negative power supply line NL, and one end is connected to the negative power supply terminal NT of the amplifier circuit A2. The other end is composed of a capacitance C5 connected to the negative power supply line NL.

One end of the passive circuit 4e is connected to the negative power supply terminal NT of the amplifier circuit A3, the other end is connected to the resistor R8 connected to the negative power supply line NL, and one end is connected to the negative power supply terminal NT of the amplifier circuit A3. The other end is composed of a capacitance C6 connected to the negative power supply line NL.

9 (A) is a diagram showing the frequency characteristics of the amplifier circuit A1 of FIG. 8, FIG. 9 (B) is a diagram showing the frequency characteristics of the amplifier circuit A2 of FIG. 8, and FIG. 9 (C) is the amplifier circuit A3 of FIG. 9 (D) is a diagram showing the frequency characteristics of the amplifier circuits A1 to A3, and is a diagram showing the frequency characteristics of the multi-stage amplifier circuit in which the amplifier circuits A1 to A3 are connected in series. Assuming a source-grounded amplifier circuit as the amplifier circuits A1 to A3, the zero point at which the gain of the second-stage amplifier circuit A2 rises from the equivalent transconductance and equivalent output resistance of the amplifier circuit A2 and the parallel circuit (passive circuit 2e). The frequency f _{2 of} is as follows.
f ₂ = 1 / (2πRC) ・ ・ ・ (2)

R in the equation (2) is the resistance value of the resistor R7 of the passive circuit 2e, and C is the capacitance value of the capacitance C5 of the passive circuit 2e. If the resistance value of the resistor R8 of the passive circuit 4e R, a capacitance value of the capacitor C6 of the passive circuit 4e is C, wherein also the frequency f ₃ of the zero point gain of the amplifier circuit A3 of the third stage is increased (2 ) Can be expressed. Assuming that the cutoff frequency of the first-stage amplifier circuit A1 is f ₁ , it may be designed so that any of the following equations (3) to (5) is satisfied.
f ₁ <f ₂ <f ₃ ... (3)
f ₁ <f ₃ <f ₂ ... (4)
f ₁ <f ₂ = f ₃ ... (5)

By setting the frequency characteristics in this way, a multi-stage amplifier circuit in which the gain G'is larger than _{the gain G A1} of the amplifier circuit A1 and the cutoff frequency _{f'-3 dB is higher than the cutoff frequency f 1 of the amplifier circuit A1 is realized.} can do. In the general design method of this embodiment, the resistance values of the resistors R7 and R8 are set so that the gain at high frequencies of the amplifier circuits A2 and A3 becomes a desired value, and the equations (3) to (5) are set. The capacity values of the capacities C5 and C6 may be set so as to satisfy any of the above.

In this embodiment, the passive circuit 2e to a plurality of amplifier circuits A2, A3, and 4e provided, blocking of the respective amplifier circuits A2, the frequency of the zero point gain A2 rises f _2, f ₃ a first-stage amplifier circuit A1 By making the frequency _{higher than f 1} , the -3 dB band of the multi-stage amplifier circuit can be further extended as compared with the first to fourth embodiments.

In this embodiment, the passive circuit 2e is composed of the resistor R7 and the capacitance C5, and the passive circuit 4e is composed of the resistor R8 and the capacitance C6. The power consumption of the circuit can be reduced. Further, in this embodiment, the area of the multi-stage amplifier circuit can be reduced as compared with the case where the passive circuit is realized by the inductor. Further, in this embodiment, since the band can be extended by the amplifier circuits A2 and A3 in the subsequent stage, the feedback resistance provided in the amplifier circuit A1 in the first stage can be further increased, and TIA with a better SN ratio can be realized. be able to.

In this embodiment, as the configurations of the amplifier circuit A2 and the passive circuit 2e, and the amplifier circuit A3 and the passive circuit 4e, respectively, the configurations corresponding to the amplifier circuits A2a and the passive circuit 2a of the first embodiment are used. However, the present invention is not limited to this, and a configuration corresponding to the second embodiment may be used, a configuration corresponding to the third embodiment may be used, or a configuration corresponding to the fourth embodiment may be used. You may use it. Further, as described in the fourth embodiment, when the inverter amplifier circuit is used as the amplifier circuits A2 and A3, the power supply terminal between the positive side power supply terminal and the positive side power supply line PL of the amplifier circuits A2 and A3 and the negative power supply terminal are used. The passive circuit may be inserted only in either one of the power supply line NL and the negative power supply line NL. Further, in this embodiment, the amplifier circuit into which the passive circuit is inserted is set to two stages, but it goes without saying that the number of stages may be three or more.

Here, the circuit in which the fourth embodiment and the fifth embodiment are combined is compared with the conventional circuit disclosed in Non-Patent Document 1, and the band extension effect of the present invention is verified. FIG. 10 shows the configuration of the conventional multi-stage amplifier circuit disclosed in Non-Patent Document 1, and FIG. 11 shows the configuration of the multi-stage amplifier circuit in which the fourth embodiment and the fifth embodiment are combined.

The first-stage amplifier circuit A1f is composed of a pMOS transistor Q6, an nMOS transistor Q7, and a feedback resistor R9. The second-stage amplifier circuit A2f is composed of a pMOS transistor Q8, an nMOS transistor Q9, and a feedback resistor R10. The third-stage amplifier circuit A3f is composed of a pMOS transistor Q10, an nMOS transistor Q11, and a feedback resistor R11.

The passive circuit 1f inserted between the second stage amplifier circuit A2f and the positive power supply line PL is composed of a parallel circuit of the resistor R12 and the capacitance C7. The passive circuit 2f inserted between the amplifier circuit A2f and the negative power supply line NL is composed of a parallel circuit of the resistor R13 and the capacitance C8. The passive circuit 3f inserted between the third stage amplifier circuit A3f and the positive power supply line PL is composed of a parallel circuit of the resistor R14 and the capacitance C9. The passive circuit 4f inserted between the amplifier circuit A3f and the negative power supply line NL is composed of a parallel circuit of the resistor R15 and the capacitance C10.

Here, the resistance values of the feedback resistors R9 to R11 are set to 300Ω, the sizes of the pMOS transistors Q6, Q8, and Q10 are set to 60 nm × 54 μm, and the sizes of the nMOS transistors Q7, Q9, and Q11 are set to 60 nm × 36 μm. Further, the resistance values of the resistors R12 to R15 were set to 20Ω, the capacitance values of the capacitances C7 and C8 were set to 6pF, and the capacitance values of the capacitors C9 and C10 were set to 3pF.

FIG. 12 is a diagram showing the frequency characteristics of the amplifier circuits A1f to A3f of FIG. 11 and the frequency characteristics of the multi-stage amplifier circuit in which the amplifier circuits A1f to A3f are connected in sequence. In FIG. 12, 120 shows the frequency characteristics of the first-stage amplifier circuit A1f, 121 shows the frequency characteristics of the second-stage amplifier circuit A2f, 122 shows the frequency characteristics of the third-stage amplifier circuit A3f, and 123 shows the frequency characteristics of the multi-stage amplifier circuit. ing. A gain peak appears near DC for the first-stage amplifier circuit A1f in FIG. 11, and a gain peak appears near 4 GHz for the second-stage amplifier circuit A2f, and a gain near 12 GHz appears for the third-stage amplifier circuit A3f. Peak is appearing.

FIG. 13 is a diagram showing the frequency characteristics of the multi-stage amplifier circuits of FIGS. 10 and 11. 130 of FIG. 13 shows the frequency characteristics of the multi-stage amplifier circuit of FIG. 10, and 131 shows the frequency characteristics of the multi-stage amplifier circuit of FIG. According to the configuration of FIG. 11, it can be seen that the 9 GHz band is extended as compared with the conventional multi-stage amplifier circuit of FIG.

[Sixth Example]
Next, a sixth embodiment of the present invention will be described. FIG. 14 is a circuit diagram showing the configuration of the multi-stage amplifier circuit according to the sixth embodiment of the present invention, and the same configurations as those in FIGS. 1, 3, 5 and 8 are designated by the same reference numerals. .. The multi-stage amplifier circuit of this embodiment includes an amplifier circuit A1, A2g, A3g connected in series, and a passive circuit 5g inserted between the positive power supply terminal PT and the positive power supply line PL of the amplifier circuits A2g, A3g. Consists of.

The two amplifier circuits A2g and A3g of this embodiment are inverting amplifier circuits. The passive circuit 5g has a resistor R16 having one end connected to the positive power supply line PL and the other end connected to the positive power supply terminal PT of the amplifier circuit A2g, and one end connected to the positive power supply line PL and the other end. A resistor R17 connected to the positive power supply terminal PT of the amplifier circuit A3g, and a capacitance C11 having one end connected to the terminal on the amplifier circuit A2g side of the resistor R16 and the other end connected to the terminal on the amplifier circuit A3g side of the resistor R17. It is composed of and.

Assuming that the capacitance value of the capacitance C11 is C / 2, the gain improving effect of the multi-stage amplifier circuit of this embodiment is that the capacitance values of the capacitances C5 and C6 of the fifth embodiment are both C, and the amplifiers A2 and A3 Is equivalent to the case where is an inverting amplifier circuit.
In this embodiment, the gain of the amplifier circuit A3g of the cutoff frequency f _1, the frequency of the zero point gain of the amplifier circuit A2g the second stage is increased f _2, 3-stage of the first-stage amplifier A1 rises Assuming that the frequency of the zero point is f ₃ , it may be designed so that any of the equations (3) to (5) is satisfied.

In this embodiment, the capacitance of the capacitance C11 may be halved as compared with the case where two capacitances are inserted in parallel to the resistors R16 and R17, respectively, so that the same gain improvement can be obtained in a circuit area narrower than that of the fifth embodiment. be able to. Therefore, the area of the circuit can be reduced.

In this embodiment, the cases where the inverting amplifier circuits A2g and A3g are, for example, a source grounded amplifier circuit using a pMOS transistor are shown, but the amplifier circuits A2g and A3g are, for example, a source grounded amplifier circuit using an nMOS transistor. If this is the case, a circuit similar to the passive circuit 5g may be inserted between the negative power supply terminals NT of the amplifier circuits A2g and A3g and the negative power supply line NL. In this case, the capacitance of the passive circuit is the terminal on the amplifier circuit A2g side of the resistor inserted between the negative power supply terminal NT of the amplifier circuit A2g and the negative power supply line NL, and the negative power supply terminal NT of the amplifier circuit A3g. It is connected to the terminal on the amplifier circuit A3g side of the resistor inserted between the power line NL and the negative power supply line NL.

[7th Example]
Next, a seventh embodiment of the present invention will be described. FIG. 15 is a circuit diagram showing the configuration of the multi-stage amplifier circuit according to the seventh embodiment of the present invention, and the same configurations as those in FIGS. 1, 3, 5, 8 and 14 are designated by the same reference numerals. It is done. The multi-stage amplifier circuit of this embodiment includes an amplifier circuit A1, A2g, A3g connected in series, and a passive circuit 5h inserted between the positive power supply terminal PT and the positive power supply line PL of the amplifier circuits A2g, A3g. Consists of.

In the passive circuit 5h, instead of the capacitance C11 of the sixth embodiment, the gate is connected to the terminal on the amplifier circuit A2g side of the resistor R16, and the source, drain and body are connected to the terminal on the amplifier circuit A3g side of the resistor R17. The nMOS transistor Q12 was used. As described in the third embodiment, since the MOS transistor of the fine process has a very thin oxide film between the gate and the source, the resistors R16 and R17 can be combined by adopting the configuration as shown in FIG. The behavior is the same as when the capacitance C11 is inserted between them. Further, instead of the nMOS transistor Q12, a pMOS transistor in which the gate is connected to the terminal on the amplifier circuit A2g side of the resistor R16 and the source, drain and body are connected to the terminal on the amplifier circuit A3g side of the resistor R17 can be used. Good.

In this embodiment, the cases where the inverting amplifier circuits A2g and A3g are, for example, a source grounded amplifier circuit using a pMOS transistor are shown, but when the amplifier circuits A2g and A3g are, for example, a source grounded amplifier circuit using an nMOS transistor. An nMOS transistor or a pMOS transistor may be used as the capacitance of the passive circuit inserted between the negative power supply terminal NT of the amplifier circuits A2g and A3g and the negative power supply line NL.

Further, the direction of the nMOS transistor or pMOS transistor used as a capacitance is reversed, the source, drain and body of the nMOS transistor or pMOS transistor are connected to the terminal on the A2g side of the amplifier circuit A2g of the resistor R16, and the gate is the amplifier circuit of the resistor R17. It may be connected to the terminal on the A3g side.

In this embodiment, in addition to the same effect as in the sixth embodiment, it is possible to increase the capacity value per area. Further, when the capacitance C11 is arranged as in the sixth embodiment, another element cannot be arranged immediately above the capacitance C11, but when the MOS transistor is used as the capacitance as in this embodiment, the MOS is used. Other elements can be placed directly above the transistor. As a result, in this embodiment, the area of the multi-stage amplifier circuit can be reduced.

[8th Example]
Next, an eighth embodiment of the present invention will be described. FIG. 16 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to an eighth embodiment of the present invention, and has the same configuration as that of FIGS. 1, 3, 5, 8, 14, and 15. It is coded. The multi-stage amplifier circuit of this embodiment includes an amplifier circuit A1, A2i, A3i connected in series, and a passive circuit 5i inserted between the positive power supply terminal PT and the positive power supply line PL of the amplifier circuits A2i, A3i. It is composed of a passive circuit 6i inserted between the negative power supply terminal NT of the amplifier circuits A2i and A3i and the negative power supply line NL.

The two amplifier circuits A2i and A3i of this embodiment are inverter amplifier circuits. In the passive circuit 5i, one end is connected to the positive power supply line PL and the other end is connected to the resistor R18 connected to the positive power supply terminal PT of the amplifier circuit A2i, and one end is connected to the positive power supply line PL and the other end is connected. A resistor R19 connected to the positive power supply terminal PT of the amplifier circuit A3i, and a capacitance C12 having one end connected to the terminal on the amplifier circuit A2i side of the resistor R18 and the other end connected to the terminal on the amplifier circuit A3i side of the resistor R19. It is composed of and.

One end of the passive circuit 6i is connected to the negative power supply terminal NT of the amplifier circuit A2i, the other end is connected to the resistor R20 connected to the negative power supply line NL, and one end is connected to the negative power supply terminal NT of the amplifier circuit A3i. The other end is the resistor R21 connected to the negative power supply line NL, and one end is connected to the terminal on the amplifier circuit A2i side of the resistor R20, and the other end is connected to the terminal on the amplifier circuit A3i side of the resistor R21. It is composed of and.

Assuming that the capacitance values of the capacitances C12 and C13 are C / 2, the gain improving effect of the multi-stage amplifier circuit of this embodiment is that the capacitance values of the capacitances C7 to C10 in FIG. 11 are all C, and the amplifiers A2f and A3f in FIG. Is equivalent to the case where is an inverting amplifier circuit.
In this embodiment, the gain of the amplifier circuit A3i of the frequency of the zero point gain is increased in the cut-off frequency f _1, 2-stage amplifier circuit A2i f _2, 3-stage of the first-stage amplifier A1 rises Assuming that the frequency of the zero point is f ₃ , it may be designed so that any of the equations (3) to (5) is satisfied.

In this embodiment, the resistance between the off-side transistor and the power supply line becomes the load resistance of the on-side transistor as in the fourth embodiment. Therefore, as in the sixth and seventh embodiments, one side is used. The gain of the multi-stage amplifier circuit can be improved as compared with the case where the passive circuit is provided in the power supply line.

Further, in this embodiment, since the capacitances of the capacitances C12 and C13 may be halved as compared with the case where the capacitances C7 to C10 are inserted in parallel with the resistors R12 to R15 of FIG. 11, the amplifiers A2f and A3f are configured in FIG. It is possible to obtain the same gain improvement with a narrower circuit area than when the inverting amplifier circuit is used. Therefore, the area of the multi-stage amplifier circuit can be reduced.

[9th Example]
Next, a ninth embodiment of the present invention will be described. FIG. 17 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a ninth embodiment of the present invention, and has the same configuration as that of FIGS. 1, 3, 5, 8 and 14 to 16. It is coded. The multi-stage amplifier circuit of this embodiment includes an amplifier circuit A1, A2i, A3i connected in series, and a passive circuit 5j inserted between the positive power supply terminal PT and the positive power supply line PL of the amplifier circuits A2i, A3i. It is composed of a passive circuit 6j inserted between the negative power supply terminal NT of the amplifier circuits A2i and A3i and the negative power supply line NL.

In the passive circuit 5j, instead of the capacitance C12 of the eighth embodiment, the source, drain, and body are connected to the terminal on the amplifier circuit A2i side of the resistor R18, and the gate is connected to the terminal on the amplifier circuit A3i side of the resistor R19. This is the one using the nMOS transistor Q13. In the passive circuit 6j, instead of the capacitance C13 of the eighth embodiment, the source, drain, and body are connected to the terminal on the amplifier circuit A2i side of the resistor R20, and the gate is connected to the terminal on the amplifier circuit A3i side of the resistor R21. The nMOS transistor Q14 is used.

Instead of the nMOS transistor Q13, a pMOS transistor in which the source, drain, and body are connected to the terminal on the amplifier circuit A2i side of the resistor R18 and the gate is connected to the terminal on the amplifier circuit A3i side of the resistor R19 may be used. Good. Similarly, instead of the nMOS transistor Q14, a pMOS transistor in which the source, drain, and body are connected to the terminal on the amplifier circuit A2i side of the resistor R20 and the gate is connected to the terminal on the amplifier circuit A3i side of the resistor R21 is used. May be good.

Further, the direction of the nMOS transistor or pMOS transistor used as a capacitance is reversed, the gate of the nMOS transistor or pMOS transistor is connected to the terminal on the amplifier circuit A2i side of the resistors R18 and R20, and the source, drain and body are connected to the resistor R19, It may be connected to the terminal of the amplifier circuit A3i side of R21.

In this embodiment, in addition to the same effect as in the eighth embodiment, it is possible to increase the capacity value per area. Further, when the capacitances C12 and C13 are arranged as in the eighth embodiment, other elements cannot be arranged immediately above the capacitances C12 and C13, but when the MOS transistor is used as the capacitance as in this embodiment. Other elements can be arranged directly above the MOS transistor. As a result, in this embodiment, the area of the multi-stage amplifier circuit can be reduced.

[10th Example]
Next, a tenth embodiment of the present invention will be described. FIG. 18 is a circuit diagram showing a configuration of a multi-stage amplifier circuit according to a tenth embodiment of the present invention, and has the same configuration as that of FIGS. 1, 3, 5, 8 and 14 to 17. It is coded. The multi-stage amplifier circuit of this embodiment includes amplifier circuits A1k, A2i, and A3i connected in series, and passive circuits 5j and 6j.

The first-stage amplifier circuit A1k of this embodiment is a transimpedance amplifier circuit having a feedback resistor R22 inserted between an input terminal and an output terminal.
In this embodiment, since the band can be compensated by the amplifier circuits A2i and A3i in the subsequent stage, the value of the feedback resistor R22 can be increased in the amplifier circuit A1k in the first stage. Thereby, in this embodiment, the input conversion noise of the transimpedance amplifier circuit can be reduced, and the transimpedance amplifier circuit with low noise, wide band, and low power consumption is realized by the longitudinal connection of the amplifier circuits A1k, A2i, and A3i. be able to.

In this embodiment, the case where the amplifier circuit A1k is applied to the ninth embodiment has been described, but it may be applied to any of the first to eighth embodiments.
Further, when an inverter amplifier circuit is used as the amplifier circuits A2i and A3i as in the eighth to tenth embodiments, between the positive power supply terminal PT and the positive power supply line PL of the amplifier circuits A2i and A3i, and The passive circuit may be inserted only in either one of the negative power supply terminal NT and the negative power supply line NL.

The present invention can be applied to an amplifier circuit.

1,1b to 1d, 1f, 2,2a, 2d to 2f, 3f, 4e, 4f, 5g to 5j, 6i, 6j ... Passive circuits, A1, A1f, A1k, A2, A2a, A2b, A2d, A2f, A2g , A2i, A3, A3f, A3g, A3i ... Amplifier circuit, Q1 to Q14 ... Transistor, R1 to R22 ... Resistor, C1 to C13 ... Capacitance, PL ... Positive power supply line, NL ... Negative power supply line, PT ... Positive side Power terminal, NT ... Negative power terminal.

Claims (5)

Multiple amplifier circuits connected in series and
It is equipped with a passive circuit connected to the two amplifier circuits other than the first stage.
The passive circuit
Of the two amplifier circuits other than the first stage, between the positive power supply terminal and the positive power supply line of the first amplifier circuit, and between the negative power supply terminal and the negative power supply line of the first amplifier circuit. With the first resistor inserted in at least one
Of the two amplifier circuits other than the first stage, between the positive power supply terminal and the positive power supply line of the second amplifier circuit different from the first amplifier circuit, and the negative power supply terminal of the second amplifier circuit. A second resistor inserted in at least one of the negative power lines,
One end is connected to the terminal on the first amplifier circuit side of the first resistor, and the other end is connected to the terminal on the second amplifier circuit side of the second resistor.
The two amplifier circuits other than the first stage are inverting amplifier circuits.
The characteristic of the passive circuit is that the gain of the two amplifier circuits into which the passive circuit is inserted is set to increase at a frequency higher than the cutoff frequency of the first-stage amplifier circuit. circuit. In the multi-stage amplifier circuit according to claim 1,
A multi-stage amplifier circuit characterized in that the capacitance between the gate and the source of a MOS transistor is used as the capacitance of the passive circuit. In the multi-stage amplifier circuit according to claim 1 or 2.
The amplifier circuit other than the first stage is a multi-stage amplifier circuit characterized in that it is a source grounded amplifier circuit. In the multi-stage amplifier circuit according to claim 1 or 2.
The amplifier circuit other than the first stage is a multi-stage amplifier circuit characterized in that it is an inverter amplifier circuit. In the multi-stage amplifier circuit according to any one of claims 1 to 4.
The first-stage amplifier circuit is a multi-stage amplifier circuit characterized in that it is a transimpedance amplifier circuit having a feedback resistor inserted between an input terminal and an output terminal.

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