JP6875823B2 - Data transmitter / receiver - Google Patents

Description

The present invention relates to a data transmission / reception device that performs serial communication by a pace synchronization method.

A conventional data transmission / reception device is disclosed in Patent Document 1. This data transmission / reception device has a transmission unit and a reception unit, and serial communication is performed between the transmission unit and the reception unit by a pace synchronization method. The transmission unit has a clock generation unit that oscillates at a predetermined cycle to generate a clock. The transmitting unit transmits a data string having a predetermined number of bits of data to the receiving unit.

A start bit is added to the beginning of the data string transmitted from the transmitting unit, and the receiving unit detects a pulse corresponding to the bit width of the received start bit and generates a clock having a period of this bit width. As a result, the clocks of the transmitting unit and the receiving unit can be reliably synchronized, and the data string can be normally transmitted from the transmitting unit to the receiving unit.

Japanese Unexamined Patent Publication No. 11-177543

However, according to the data transmission / reception device disclosed in Patent Document 1, the data transmission / reception device has a complicated configuration because it requires a clock generation means for detecting the pulse width of the start bit and generating a clock from the pulse width. There was a problem of becoming.

In view of the above problems, it is an object of the present invention to provide a data transmission / reception device capable of reliably transmitting a data string by synchronizing the clocks of a transmission unit and a reception unit with a simple configuration.

In order to achieve the above object, the data transmission / reception device of the present invention performs serial communication between the transmission unit and the reception unit by a pace synchronization method, and arranges a predetermined number of data between the start bit and the stop bit. In a data transmission / reception device for transmitting / receiving a data string, the transmission unit has a first clock output unit that outputs a first clock that oscillates in a predetermined cycle, and the reception unit outputs a second clock that oscillates in a predetermined cycle. It has two clock output units, and when the receiving unit detects a reception error, the transmitting unit or the receiving unit corrects the amount of difference in the period between the first clock and the second clock, and the first It is characterized in that the clock and the second clock are synchronized to retransmit the data string from the transmitting unit to the receiving unit.

Further, the present invention is characterized in that, in the data transmission / reception device having the above configuration, the receiving unit detects the deviation amount, and the transmitting unit corrects the deviation amount.

Further, the present invention is characterized in that, in the data transmission / reception device having the above configuration, the receiving unit detects the deviation amount and corrects the deviation amount.

Further, the present invention is characterized in that, in the data transmission / reception device having the above configuration, the transmission unit detects the deviation amount and corrects the deviation amount.

Further, the present invention is characterized in that, in the data transmission / reception device having the above configuration, the deviation amount is detected based on the cycle of the start bit.

Further, the present invention is characterized in that, in the data transmission / reception device having the above configuration, the data string is continuous with the stop bits and has a blank period composed of a plurality of bits having the same level as the stop bits.

Further, the present invention is characterized in that, in the data transmission / reception device having the above configuration, the blank period is composed of a bit number of 1/2 or more of the bit number of the data string.

Further, the present invention is characterized in that, in the data transmission / reception device having the above configuration, the deviation amount is detected based on a correction amount measurement signal composed of a pulse signal having a predetermined pulse width transmitted from the reception unit to the transmission unit. It is supposed to be.

According to the data transmission / reception device of the present invention, when the receiving unit detects a reception error, the transmitting unit or the receiving unit corrects the amount of deviation between the cycles of the first clock and the second clock, and the first clock and the second clock. The data string is retransmitted from the transmitting unit to the receiving unit in synchronization with. As a result, the data string can be reliably received by the receiving unit by synchronizing the first clock of the transmitting unit and the second clock of the receiving unit with a simple configuration.

A side sectional view showing a refrigerator provided with the data transmission / reception device according to the first embodiment of the present invention. The front view which shows the operation panel of the refrigerator provided with the data transmission / reception device of 1st Embodiment of this invention. The block diagram which shows the structure of the refrigerator provided with the data transmission / reception device of 1st Embodiment of this invention. The figure explaining the data string sent and received by the data transmission / reception device which concerns on 1st Embodiment of this invention. The figure explaining the period of the 1st and 2nd clocks output from the 1st and 2nd clock output part which concerns on 1st Embodiment of this invention. The figure explaining the cycle of the data string sent and received by the data transmission / reception device which concerns on 1st Embodiment of this invention. The figure which shows the operation of the data transmission / reception device which concerns on 1st Embodiment of this invention. The figure which shows the operation of the data transmission / reception device which concerns on 2nd Embodiment of this invention. The figure which shows the operation of the data transmission / reception device which concerns on 3rd Embodiment of this invention. The figure which shows the operation of the data transmission / reception device which concerns on 5th Embodiment of this invention.

<First Embodiment>
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a side sectional view showing a refrigerator 1 provided with the data transmission / reception device of the first embodiment. The refrigerator 1 is provided with a refrigerating chamber 3, a freezing chamber 4, and a vegetable compartment 5 in this order from above the heat insulating box 2.

The refrigerating room 3 stores the stored items in a refrigerator, and the freezing room 4 stores the stored items in a frozen state. The vegetable compartment 5 is maintained at a higher temperature than the refrigerating chamber 3, and stores such as vegetables are refrigerated. An electrical box 37 is arranged at the lower part of the back surface of the heat insulating box body 2.

The refrigerating chamber 3 is opened and closed by a rotary door 3a whose end is pivotally supported. An operation panel 40 (see FIG. 2) is arranged on the front surface of the door 3a. The freezing chamber 4 and the vegetable compartment 5 are opened and closed by drawer-type doors 4a and 5a integrally formed with a storage case (not shown), respectively.

Cold air passages 7 and 8 communicating with each other via a damper 35 are provided on the back surfaces of the freezing chamber 4 and the refrigerating chamber 3. A cooler 31 and a blower 32 are arranged in the cold air passage 7, and a discharge port 7a facing the freezing chamber 4 opens. A discharge port 8a facing the refrigerating chamber 3 opens in the cold air passage 8.

A machine room 6 is provided behind the vegetable room 5, and a compressor 30 for operating the refrigeration cycle is installed in the machine room 6. A condenser (not shown), a capillary tube (not shown), and a cooler 31 are connected in order to the compressor 30 via a refrigerant pipe (not shown) through which a refrigerant flows, and the compressor 30 returns to the compressor 30. As a result, the refrigeration cycle is operated, and the cooler 31 exchanges heat with the air flowing through the cold air passage 7 to generate cold air.

When the blower 32 is driven, air flows through the cold air passage 7. At this time, when the damper 35 is opened, cold air flows through the cold air passage 8. The cold air flowing through the cold air passages 7 and 8 is discharged to the freezing chamber 4 and the refrigerating chamber 3 via the discharge ports 7a and 8a, respectively.

The freezing chamber 4 is provided with a return port (not shown) for returning cold air to the cold air passage 7. A communication passage (not shown) communicating with the vegetable compartment 5 is led out to the refrigerating chamber 3, and a return port (not shown) for returning cold air to the cold air passage 7 is provided in the vegetable compartment 5.

FIG. 2 shows a front view of the operation panel 40 provided on the front surface of the door 3a. The operation panel 40 includes an operation unit 41 having a plurality of operation keys, and a display unit 42 having a display panel 43 and a plurality of indicators 44.

The operation unit 41 inputs user setting conditions such as temperature setting of the refrigerating chamber 3 and the freezing chamber 4 of the refrigerator 1. The display panel 43 is formed of a liquid crystal panel or the like and displays a set temperature or the like. The indicator 44 displays an operating mode or the like during operation by emitting light from an LED arranged on the back surface of the operation panel 40. As a result, the display unit 42 notifies the operating state of the refrigerator 1 by a display. Further, the display unit 42 displays the input state at the time of setting by the operation unit 41.

FIG. 3 is a block diagram showing a data transmission / reception device 60 of the refrigerator 1. The data transmission / reception device 60 transmits the operation command signal input by the operation unit 41 to the control board 20 housed in the electrical box 37. The data transmission / reception device 60 has a transmission unit 61 and a reception unit 62, and performs serial communication by a UART (Universal Asynchronous Receiver Transmitter) by a synchronous communication method. Both the transmitting unit 61 and the receiving unit 62 can transmit and receive, and bidirectional communication by half-duplex communication is possible. When the transmitting unit 61 is in the receiving state, the receiving unit 62 is in the transmitting state.

The transmission unit 61 includes a control board 10 arranged behind the operation panel 40. The receiving unit 62 includes a control board 20 arranged in the electrical box 37 (see FIG. 1). The control board 10 is provided with the microcomputer 11, and the control board 20 is provided with the microcomputer 21.

The microprocessor 11 has a CPU 12 that controls each unit, and a storage unit 13, a clock output unit (first clock output unit) 15, and an I / F 14 are connected to the CPU 12. The microcomputer 11 controls the drive of the operation unit 41.

The microprocessor 21 has a CPU 22 that controls each unit, and a storage unit 23, a clock output unit (second clock output unit) 25, and an I / F 24 are connected to the CPU 22. The microcomputer 21 controls the drive of the compressor 30, the blower 32, and the damper 35 based on the set state stored in the storage unit 23.

The clock output units 15 and 25 are internal clocks of the microcomputers 11 and 21, and are composed of, for example, an oscillation circuit using a resistor and a capacitor. The clock output unit 25 outputs a first clock that oscillates in a predetermined period T1, and the clock output unit 25 outputs a second clock that oscillates in a predetermined period T2.

Further, the clock output units 15 and 25 can change the cycles T1 and T2 of the first clock and the second clock by the control from the microcomputers 11 and 21. For example, when the clock output units 15 and 25 include a frequency dividing circuit that divides the output clock of the oscillation circuit, the first clock can be arbitrarily set by setting the frequency dividing ratio according to the signals from the microcomputers 11 and 21. , The cycles T1 and T2 of the second clock can be changed.

The storage units 13 and 23 are composed of a ROM and a RAM, and store control programs and various data executed by the CPUs 12 and 22, respectively. Further, the storage units 13 and 23 temporarily store the operations performed by the CPUs 12 and 22. The I / Fs 14 and 24 perform serial communication with each other via the communication line 18.

FIG. 4 is a diagram illustrating a data string transmitted / received between the transmitting unit 61 and the receiving unit 62. FIG. 4A shows the bit structure of the data string. 4 (b) and 4 (c) show the first clock and the second clock, respectively.

A plurality of data strings are included in the communication data transmitted / received between the transmission unit 61 and the reception unit 62, and each data string is sequentially transmitted. The data string has data D0 to D7 composed of a plurality of bits. Further, the start bit S1 is added before the data D0 to D7, and the parity bit P and the stop bit S2 are added in order after the data D0 to D7. Further, a blank period B composed of a plurality of consecutive bits is added to the stop bit S2 at the end of the data string.

The start bit S1 is a low level "0" signal and consists of 1 bit. The receiving unit 62 detects the start bit S1 and recognizes the beginning of the data D0 to D7.

The stop bit S2 is a high level "1" signal and consists of 1 bit. The receiving unit 62 detects the stop bit S2 and recognizes the end of the data D0 to D7. The stop bit S2 may be 1.5 bits or 2 bits.

The data D0 to D7 are each composed of a combination of low level "0" or high level "1" signals, and consist of 8 bits (1 byte) in total.

The parity bit P is added to check whether or not the data D0 to D7 have been sent normally, and is composed of one bit. The parity bit P can be selected from even parity or odd parity.

The blank period B is intended to improve the accuracy of detecting the amount of clock deviation, which will be described later, and is composed of, for example, 11 bits. Further, in the blank period B, all signals having the same level as the stop bit S2, that is, a high level "1" signal are selected. As a result, the receiving unit 62 can detect that the blank period B is when a predetermined number of high level "1" signals are continuously received. Then, it can be recognized that the start bit S1 of the next data string is received when the low level "0" signal is detected after the blank period B.

The transmission unit 61 transmits a data string bit by bit based on the period T1 of the first clock output by the clock output unit 15.

On the other hand, the receiving unit 62 receives the data string transmitted from the transmitting unit 61 bit by bit based on the period T2 of the second clock output by the clock output unit 25. It is necessary that the period T1 and the period T2 coincide with each other, and if the amount of deviation between the two occurs by a predetermined amount or more, the transmission unit 61 and the reception unit 62 are out of synchronization and the data string cannot be transmitted normally.

FIG. 5 is a diagram for explaining the cycles of the first and second clocks. The first and second clocks output by the clock output units 15 and 25 are set to output reference clocks having the same period T'.

However, since the clock output units 15 and 25 are internal clocks of the microcomputers 11 and 21, the cycles T1 and T2 of the first and second clocks depend on the element variation of each oscillation circuit, the usage environment of the refrigerator 1, and the number of years of use. May deviate from the reference clock period T', respectively. When a deviation amount occurs between the period T1 and the period T2, the deviation amount is corrected by the following method.

FIG. 6 is a diagram illustrating a transmission / reception state of the data string. The transmission unit 61 sequentially transmits a plurality of data strings. The CPU 22 of the receiving unit 62 measures the period Ts of the start bits S1 of a plurality of data strings by the count number N2 of the second clock. The data string is transmitted from the transmission unit 61 based on the first clock, and the period Ts of the start bits S1 is a predetermined count number N1 of the first clock. As a result, the amount of deviation δ of the second clock with respect to the first clock is represented by T2 / T1 = N1 / N2.

The CPU 22 corrects the deviation amount δ with respect to the period T2 of the second clock output by the clock output unit 25. That is, the deviation amount δ of the second clock is corrected to set the period to T2 / δ. As a result, the first clock and the second clock can be synchronized.

If the blank period B is long, the transmission speed of the data D0 to D7 from the transmission unit 61 to the reception unit 62 decreases. However, since the period Ts of the start bit S1 becomes long, it is possible to reduce the measurement error of the period Ts and improve the detection accuracy of the deviation amount δ.

Further, it is more desirable to form the blank period B with a number of bits longer than the total number of bits of the start bit S1, the data D0 to D7, the parity bit P, and the stop bit S2, because the start bit S1 can be reliably detected. That is, the blank period B may be formed to have a number of bits that is ½ or more of the number of bits in the data string.

If the number of consecutive bits of the high level "1" can be reduced to a predetermined number or less by encoding the data, the blank period B may be formed to have a number of bits longer than the predetermined number. Further, although the detection accuracy of the start bit S1 is lowered, the blank period B may be omitted from the data string.

Further, although the deviation amount δ is detected from the period Ts of the start bit, the deviation amount δ may be derived from the time of the blank period B. Further, although the ratio of the period T1 of the first clock to the period T2 of the second clock is defined as the deviation amount δ, the difference Tx between the period T1 and the period T2 (see FIG. 5) may be used as the deviation amount.

FIG. 7 is a diagram showing the operation of the data transmission / reception device 60. For example, when an operation for lowering the temperature is input from the operation unit 41, an operation command signal is transmitted from the control board 10 to the control board 20 to control the compressor 30 and the like.

In step # 11, the CPU 12 of the transmission unit 61 transmits an operation command signal (communication data) including a plurality of data strings from the I / F 14 to the reception unit 62 via the communication line 18. The operation command signal transmitted from the I / F 14 is received by the I / F 24 and transferred to the CPU 22.

In step # 12, the CPU 22 determines whether or not the operation command signal can be normally received. If the operation command signal can be normally received, the normal reception signal notifying that the operation command signal has been normally received is transmitted to the transmission unit 61 in step # 14.

On the other hand, when the cycle T1 of the first clock and the cycle T2 of the second clock of the receiving unit 62 are not synchronized, the receiving unit 62 cannot normally receive the operation command signal. Therefore, in step # 12, the CPU 22 determines that a reception error is obtained by a parity check or the like.

When the CPU 22 determines that the reception error is obtained, the CPU 22 measures the cycle Ts of the start bit S1 of the data string to be received next in step # 21 to detect the deviation amount δ between the cycle T1 and the cycle T2. The deviation amount δ is stored in the storage unit 23.

Next, in step # 23, the receiving unit 62 corrects the deviation amount δ with respect to the period T2 of the second clock output by the clock output unit 25 to set the period to T2 / δ. Then, in step # 25, the receiving unit 62 transmits a retransmission request signal requesting the retransmission of the operation command signal to the transmitting unit 61 based on the second clock corrected for the deviation amount δ.

Since the transmission unit 61 is corrected so that the second clock matches the first clock, the retransmission request signal can be normally received. As a result, in step # 26, the transmission unit 61 retransmits the operation command signal from the I / F 14 to the reception unit 62 via the communication line 18.

The operation command signal transmitted from the I / F 14 is received by the I / F 24 and transferred to the CPU 22. Since the second clock corrected by the deviation amount δ matches the first clock, the CPU 22 can normally receive the operation command signal. Then, the CPU 22 controls and operates the compressor 30 according to the received operation command signal.

According to the present embodiment, when the receiving unit 62 detects a reception error, the receiving unit 62 detects the amount δ of the period deviation between the first clock and the second clock. Then, the receiving unit 62 corrects the deviation amount δ, synchronizes the first clock and the second clock, and retransmits the data string from the transmitting unit 61 to the receiving unit 62.

As a result, in order to correct the deviation amount δ of the period between the first clock and the second clock and retransmit the data string, the data is synchronized by the first clock and the second clock by the receiving unit 62 with a simple configuration. The column can be reliably received. Therefore, even if a reception error occurs, the data string can be continuously transmitted and received.

Further, the deviation amount δ is detected based on the period Ts of the start bit S1. As a result, since the number of bits of the period Ts is large, the period Ts can be detected accurately, and the deviation amount δ can be accurately detected. Therefore, the first clock and the second clock can be reliably synchronized.

Further, the data string has a blank period B composed of a plurality of high-level bits continuous with the stop bit S2. As a result, the start bit S1 can be detected accurately, and the period Ts and the deviation amount δ can be detected more accurately.

Further, since the blank period B is composed of a number of bits that is ½ or more of the number of bits of the data string, the start bit S1 can be detected more accurately.

<Second Embodiment>
FIG. 8 is a diagram showing the operation of the data transmission / reception device 60 according to the second embodiment. The same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. The present embodiment is different from the first embodiment in that the deviation amount δ is corrected on the transmission unit 61 side.

When the CPU 22 of the receiving unit 62 determines in step # 12 that a reception error is determined, the receiving unit 62 detects the deviation amount δ between the period T1 and the period T2 in step # 21 as in the first embodiment.

Next, in step # 22, the receiving unit 62 transmits the data of the deviation amount δ to the transmitting unit 61. At this time, the receiving unit 62 lowers the baud rate to a predetermined value and transmits. Further, the transmitting unit 61 lowers the baud rate to a predetermined value and stands by when a timeout occurs in which the signal for notifying normal reception from the receiving unit 62 is not received for a predetermined period. As a result, the transmission unit 61 can receive the data of the deviation amount δ.

In step # 23, the CPU 12 of the transmission unit 61 corrects the deviation amount δ of the first clock output by the clock output unit 15 based on the received deviation amount δ, and sets the period to T1 and δ. Then, in step # 26, the transmission unit 61 retransmits the operation command signal based on the first clock corrected by the deviation amount δ.

The operation command signal transmitted from the I / F 14 is received by the I / F 24 and transferred to the CPU 22. Since the first clock corrected by the deviation amount δ matches the second clock, the CPU 22 can normally receive the operation command signal.

According to this embodiment, the same effect as that of the first embodiment can be obtained. Further, the receiving unit 62 detects the deviation amount δ, and the transmitting unit 61 corrects the deviation amount δ. Therefore, the processing of the microcomputers 11 and 21 can be distributed to reduce the burden. Further, even when the performance of the microcomputer 21 of the receiving unit 62 is low, the data string can be transmitted / received by correcting the deviation amount δ by the microcomputer 11 of the transmitting unit 61.

In the present embodiment, the receiving unit 62 may correct the deviation amount δ with respect to the second clock and transmit the second clock without lowering the baud rate in step # 22 (T2 / δ). At this time, in step # 26 and thereafter, the transmission unit 61 corrects the deviation amount δ with respect to the first clock and performs transmission. Thereby, the processing of the microcomputers 11 and 21 can be distributed.

Further, in step # 22, the number of bits of the data in the data string may be reduced (for example, 4 bits) to transmit the data having a deviation amount δ. As a result, since the data length is shortened, the occurrence of a reception error can be avoided, and the transmission unit 61 can receive the data with the deviation amount δ.

<Third Embodiment>
FIG. 9 is a diagram showing the operation of the data transmission / reception device 60 according to the third embodiment. The same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. The present embodiment is different from the first embodiment in that the misalignment amount δ is detected and corrected on the transmission unit 61 side.

If the CPU 22 of the receiving unit 62 determines in step # 12 that a reception error has occurred, the receiving unit 62 transmits a correction amount measurement signal to the transmitting unit 61 in step # 13. As the correction amount measurement signal, a data string capable of detecting the amount δ of the period deviation between the first clock and the second clock as described above in the first embodiment is used.

Since the first clock and the second clock are not synchronized in the transmission unit 61, a reception error of the correction amount measurement signal transmitted from the reception unit 62 occurs. Therefore, in step # 21, the CPU 12 of the transmission unit 61 measures the period Ts of the start bits S1 of the sequentially received data strings, detects the deviation amount δ, and stores it in the storage unit 13.

In step # 23, the CPU 12 of the transmission unit 61 corrects the deviation amount δ of the first clock output by the clock output unit 15 based on the received deviation amount δ, and sets the period to T1 and δ. Then, in step # 26, the transmission unit 61 retransmits the operation command signal based on the first clock corrected by the deviation amount δ.

According to this embodiment, the same effect as that of the first embodiment can be obtained. Further, even when the performance of the microcomputer 21 of the receiving unit 62 is low, the data string can be transmitted / received by correcting the deviation amount δ by the microcomputer 11 of the transmitting unit 61.

<Fourth Embodiment>
Next, a fourth embodiment will be described. In this embodiment, the configuration of the deviation amount measurement signal is different from that in the third embodiment. Other parts are the same as those in the third embodiment.

When the CPU 22 of the receiving unit 62 determines in step # 12 of FIG. 9 that a reception error is determined, the receiving unit 62 transmits a correction amount measurement signal consisting of a pulse signal having a predetermined pulse width to the transmitting unit 61 in step # 13. The pulse width of the correction amount measurement signal is generated by a second clock having a predetermined count number N20.

In step # 21, the CPU 12 of the transmission unit 61 detects the deviation amount δ from the pulse width of the received correction amount measurement signal. That is, the pulse width of the correction amount measurement signal is detected by the count number N10 of the first clock. T1 · N10 = T2 · N20 is established from the cycle T1 of the first clock and the cycle T2 of the second clock. As a result, the amount of deviation δ is represented by T2 / T1 = N10 / N20.

In step # 23, the CPU 12 of the transmission unit 61 corrects the deviation amount δ of the first clock output by the clock output unit 15 based on the received deviation amount δ, and sets the period to T1 and δ. Then, in step # 26, the transmission unit 61 retransmits the operation command signal based on the first clock corrected by the deviation amount δ.

According to this embodiment, the same effect as that of the third embodiment can be obtained. In the present embodiment, it is desirable to set the correction amount measurement signal to 13 bits or more and transmit it by communication other than UART, and it is more preferable to set the correction amount measurement signal to 16 bits. Thereby, the detection accuracy of the pulse width of the correction amount measurement signal can be improved.

<Fifth Embodiment>
FIG. 10 is a diagram showing the operation of the data transmission / reception device 60 according to the fifth embodiment. The same parts as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. In the first embodiment, the first embodiment corrects the first clock based on a plurality of expected deviation amounts δh stored in advance in the storage unit 13 of the transmission unit 62 until the reception unit 62 normally receives the operation command signal. Different from.

If the CPU 22 of the receiving unit 62 determines in step # 12 of FIG. 10 that a reception error is determined, the receiving unit 62 transmits a retransmission request signal requesting the transmitting unit 61 to retransmit the operation command signal in step # 21. At this time, the receiving unit 62 lowers the baud rate to a predetermined value and transmits. Further, the transmitting unit 61 lowers the baud rate to a predetermined value and stands by when a timeout occurs in which the signal for notifying normal reception from the receiving unit 62 is not received for a predetermined period. As a result, the transmitting unit 61 can receive the retransmission request signal from the receiving unit 62.

Further, when a timeout occurs, the transmitting unit 61 may move to step # 22 without waiting for the reception of the retransmission request signal from the receiving unit 62.

In step # 22, the CPU 12 of the transmission unit 61, which is determined to require retransmission, corrects the first clock output by the clock output unit 15 based on the estimated deviation amount δh stored in advance, and sets the period to T1 · δh. Then, returning to step # 11, the transmission unit 61 retransmits the operation command signal based on the corrected first clock.

The receiving unit 62 and the transmitting unit 61 repeat steps # 11 to # 22 to correct the first clock until the CPU 22 determines in step # 12 that the operation command signal has been normally received.

If it is determined in step # 12 that the CPU 22 of the receiving unit 62 has normally received the signal, the receiving unit 62 transmits a signal informing the transmitting unit 61 that the operation command signal has been normally received in step # 14. The transmission unit 61 that has received the normal reception signal from the reception unit 62 stores the set expected deviation amount δh, and thereafter corrects the first clock with this expected deviation amount δh.

Here, the expected deviation amount δh is determined based on the maximum deviation amount of the first clock and the second clock, and the maximum deviation amount is derived from the frequency range predetermined by the specifications of the first clock and the second clock. .. For example, the frequency range of the first clock is greater than -4% and less than + 4% with respect to the frequency of 1.2 kHz, and the frequency range of the second clock is -6% with respect to the frequency of 1.2 kHz. When it is larger and less than + 6%, the maximum deviation amount is derived as 10.6% = (1.2 × 1.04) / (1.2 × 0.94).

Further, even if the corrected first clock does not match the second clock, if the deviation amount δ is within the error range (within the allowable deviation amount range), the receiving unit 62 normally receives the operation command. Can be done.

For example, in the data string of FIG. 4A, there is a length of 11 clocks from the start bit S1 to the stop bit S2 in the first clock of FIG. 4B. At this time, the rise of the second clock of FIG. 4 (c) is synchronized with the start (fall) of the start bit S1 of the data string of FIG. 4 (a), and the first clock of the second clock of FIG. 4 (c) is synchronized. Bit recognition is started at the center (50%) of the start bit S1 due to the falling edge of. Further, bit recognition is performed at the center (50%) of the stop bit S2 due to the falling edge of the 11th clock of the second clock.

That is, the length from the start of synchronization of the second clock in FIG. 4C to the bit recognition of the stop bit S2 is 10.5 clocks. Then, in order to recognize the stop bit S2 normally, it is necessary to be less than ± 50% of the clock period with respect to the center of the stop bit S2.

Therefore, the permissible amount of deviation per clock cycle is ± 50% ÷ 10.5 = ± 4.7%. In other words, if the amount of deviation δ is greater than -4.7% and less than + 4.7%, the amount of deviation δ is within the margin of error.

That is, if the expected deviation amount δh corrected by the transmission unit 61 in step # 22 is within the range of the maximum deviation amount, and the corrected deviation amount δ of the first clock and the second clock is within the error range, reception is performed. The unit 62 can normally receive the operation command signal.

Therefore, by correcting the first clock within the range of the maximum deviation amount while stepping the expected deviation amount δh every time below the allowable deviation amount (for example, 4%), the corrected first clock and the second clock can be adjusted. The amount of deviation δ can be reliably corrected within the error range.

Specifically, the expected deviation amount δh corrected by the transmission unit 61 in step # 22 is set to any of 0%, + 4%, -4%, + 8%, -8%, + 12%, and -12%. By doing so, the receiving unit 62 can normally receive the operation command signal. The order of setting the expected deviation amount δh is arbitrary, but it may be gradually increased in order from 0% as in the above arrangement. Further, the expected deviation amount δh at the time of the previous normal reception may be used as the initial value.

According to the present embodiment, the correction of the first clock is repeated within the range of the maximum deviation amount while incrementing the expected deviation amount δh for each value equal to or less than the allowable deviation amount that can be tolerated as an error. As a result, the data string can be reliably transmitted / received by correcting the difference amount δ of the period between the first clock and the second clock as in the second to fourth embodiments. Further, the deviation amount δ between the first clock and the second clock can be corrected without preparing a signal or processing for detecting the deviation amount δ.

Further, in another embodiment, the CPUs 12 and 22 may be connected to the AC clock included in the AC power supply of the refrigerator 1 to generate a common first and second clocks from the AC clock. In this case, since the first and second clocks do not have a cycle shift, the transmission unit 61 and the reception unit 62 can be reliably synchronized. Further, a timer may be provided on the control board to generate the first and second clocks.

Further, the transmitting unit 61 and the receiving unit 62 may be provided on the same control board. At this time, the deviation amounts of the first clock and the second clock cycles T1 and T2 with respect to the reference clock cycle T'may be measured and stored in advance, and the first clock and the second clock may be corrected at the time of communication, respectively.

Further, although the data transmission / reception device 60 is provided in the refrigerator 1, it may be provided in other electric devices such as a microwave oven and a washing machine.

According to the present invention, it can be used for electric devices such as refrigerators, microwave ovens, and washing machines equipped with a plurality of microcomputers.

1 Refrigerator 2 Insulation box 3 Refrigerator room 3a, 4a, 5a Door 4 Freezer room 5 Vegetable room 6 Machine room 7, 8 Cold air passage 10, 20 Control board 11, 21 Microcomputer 12, 22 CPU
13, 23 Storage unit 14, 24 Communication unit 15, 25 Clock output unit (1st and 2nd clock output units)
18 Communication line 30 Compressor 31 Cooler 32 Blower 35 Damper 37 Electrical box 40 Operation panel 41 Operation unit 42 Display unit 43 Display panel 44 Indicator 60 Data transmitter / receiver 61 Transmitter unit 62 Receiver B Blank period D0 to D7 Data P parity bit S1 Start bit S2 Stop bit T1, T2 Cycle Ts Start bit cycle Tx Difference δ Deviation amount δh Expected deviation amount

Claims (6)

In a data transmission / reception device that performs serial communication between a transmission unit and a reception unit by a pace synchronization method and transmits / receives a data string in which a predetermined number of bits of data are arranged between a start bit and a stop bit.
The transmitting unit has a first clock output unit that outputs a first clock that oscillates in a predetermined cycle, and the receiving unit has a second clock output unit that outputs a second clock that oscillates in a predetermined cycle. When the unit detects a reception error,
The receiving unit detects and corrects the amount of difference in the period between the first clock and the second clock, synchronizes the first clock and the second clock, and receives the data from the receiving unit to the transmitting unit. A data transmission / reception device characterized in that a data string re-transmission request signal for which an error has been detected is transmitted, and the data string is retransmitted from the transmission unit to the reception unit. In a data transmission / reception device that performs serial communication between a transmission unit and a reception unit by a pace synchronization method and transmits / receives a data string in which a predetermined number of bits of data are arranged between a start bit and a stop bit.
The transmitting unit has a first clock output unit that outputs a first clock that oscillates in a predetermined cycle, and the receiving unit has a second clock output unit that outputs a second clock that oscillates in a predetermined cycle. When the unit detects a reception error,
The receiving unit detects the amount of difference in the period between the first clock and the second clock, transmits the re-transmission request signal of the data string in which the reception error is detected from the receiving unit to the transmitting unit, and retransmits the data string. The transmission request signal includes the deviation amount, and the transmission unit corrects the deviation amount of the period between the first clock and the second clock based on the deviation amount, and the data string from the transmission unit to the reception unit. A data transmission / reception device characterized by retransmitting a clock. The baud rate or the number of data bits of the retransmission request signal transmitted from the receiving unit to the transmitting unit is smaller than the baud rate or the number of data bits of the data string when the receiving unit detects the reception error. The data transmission / reception device according to claim 2. In a data transmission / reception device that performs serial communication between a transmission unit and a reception unit by a pace synchronization method and transmits / receives a data string in which a predetermined number of bits of data are arranged between a start bit and a stop bit.
The transmitting unit has a first clock output unit that outputs a first clock that oscillates in a predetermined cycle, and the receiving unit has a second clock output unit that outputs a second clock that oscillates in a predetermined cycle. When the unit detects a reception error,
A re-transmission request signal of the data string in which the reception error is detected is transmitted from the receiving unit to the transmitting unit.
The retransmission request signal includes a correction amount measurement signal for detecting a period deviation between the first clock and the second clock.
The transmission unit detects and corrects the amount of difference in the period between the first clock and the second clock based on the correction amount measurement signal, synchronizes the first clock and the second clock, and then synchronizes the first clock with the second clock. A data transmission / reception device characterized in that the data string is retransmitted from the transmission unit to the reception unit. Data transmission and reception apparatus according to any one of claims 1 to 4, characterized in that to detect the displacement amount based on the period of the start bit. The data transmission / reception device according to claim 5, wherein the data string is continuous with the stop bits and has a blank period composed of a plurality of bits having the same level as the stop bits.

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