JP6874007B2 - Comparator, AD converter, solid-state image sensor, electronic device, and control method of comparator - Google Patents

Description

The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic device, and a control method of the comparator, and in particular, it has made it possible to reduce power consumption while improving the determination speed of the comparator. The present invention relates to a comparator, an AD converter, a solid-state imaging device, an electronic device, and a control method of the comparator.

In the signal readout method of a solid-state image sensor, for example, when AD conversion is performed within a limited area such as in a pixel, the most area-efficient method is an integral type consisting of a comparator and a digital circuit in the subsequent stage. Slope type) AD conversion method.

Non-Patent Document 1 has been proposed as a technique for realizing AD conversion within a limited area by using an integral type AD conversion method. For example, in the method of Non-Patent Document 1, the digital circuit in the subsequent stage is used as one DRAM circuit, and the slope signal is input to the comparator a plurality of times. For example, in the case of 8-bit AD conversion, the same slope signal is repeatedly input to the comparator eight times. Then, the operation of storing the code of 0 or 1 at the time when the output of the comparator is inverted and the operation of outputting the code to the outside of the pixel are repeated eight times, and when the comparison of the entire surface is completed, the code is read out to the outside.

D. Yang, B. Fowler, and A. El Gamal, "A Nyquist rate pixel levelADC for CMOS image sensors," in Proc. IEEE 1998 Custom Integrated Circuits Conf., Santa Clara, CA, May 1998, pp. 237-240 ..

When arranging the AD converter in the pixel, the accommodation area of the circuit is limited, unlike the case where there is a relatively large degree of freedom in the area such as column parallelism in which the AD converter is arranged for each pixel row. , It is difficult to make a comparator that fully meets the requirements. For example, the judgment speed of comparison may be slowed down, or the power consumption may increase when trying to improve the performance.

The present disclosure has been made in view of such a situation, and makes it possible to reduce the power consumption while improving the determination speed of the comparator.

The first aspect of the comparator of the present disclosure includes a differential input circuit that operates at a first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal, and the first power supply. It operates at a second power supply voltage that is equal to or lower than the voltage, and the comparison result signal that represents the comparison result of the voltage of the input signal and the reference signal is inverted based on the output signal from the differential input circuit. a positive feedback circuit to speed up the transition speed at the time of the said output signal of the differential input circuit, and a voltage conversion circuit for converting the second signal corresponding to the power supply voltage, said differential input circuit Is a first transistor and a second transistor constituting the current mirror, a third transistor in which the reference signal is input to the gate, a fourth transistor in which the input signal is input to the gate, and a first transistor as a constant current source. The first, second, and sixth transistors include a fifth transistor and a sixth transistor that outputs the output signal, and the third to fifth transistors are composed of MIMO transistors. The sources of the first, second and sixth transistors are connected to the first power supply voltage of 2V or less, the source of the fifth transistor is connected to a voltage lower than 0V, and the third transistor is connected to the third transistor. The fourth transistor is connected between the drain of the first transistor and the drain of the fifth transistor, and the fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor. Is configured by connecting the gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit.

In the first aspect of the present disclosure, the differential input circuit is operated at the first power supply voltage, the signal is output when the voltage of the input signal is higher than the voltage of the reference signal, and the positive feedback circuit is described above. A comparison that represents a comparison of the voltages of the input signal and the reference signal based on the output signal from the differential input circuit, operated at a second power supply voltage equal to or lower than the first power supply voltage. The transition speed when the result signal is inverted is increased, and in the voltage conversion circuit, the output signal of the differential input circuit is converted into a signal corresponding to the second power supply voltage, and the differential input circuit is used. Is a first transistor and a second transistor constituting the current mirror, a third transistor in which the reference signal is input to the gate, a fourth transistor in which the input signal is input to the gate, and a first transistor as a constant current source. A 5 transistor and a 6th transistor for outputting the output signal are provided, the 1st, 2nd and 6th transistors are composed of a MIMO transistor, and the 3rd to 5th transistors are composed of an NMOS transistor. , The source of the first, second and sixth transistors is connected to the first power supply voltage of 2V or less, the source of the fifth transistor is connected to a voltage lower than 0V, and the third transistor is connected. , The fourth transistor is connected between the drain of the first transistor and the drain of the fifth transistor, and the fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor. The transistor is configured by connecting the gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit.

The AD converter of the second aspect of the present disclosure is a differential input circuit that operates at a first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal, and the first. A comparison result signal that operates at a second power supply voltage equal to or lower than the power supply voltage and represents a comparison result of the voltages of the input signal and the reference signal based on the output signal from the differential input circuit is obtained. has a positive feedback circuit to speed up the transition speed at the time of reversing, the output signal of the differential input circuit, and a voltage conversion circuit for converting the signal corresponding to the second power supply voltage, the differential The input circuit includes a first transistor and a second transistor constituting the current mirror, a third transistor in which the reference signal is input to the gate, a fourth transistor in which the input signal is input to the gate, and as a constant current source. The fifth transistor and the sixth transistor for outputting the output signal are included, the first, second and sixth transistors are composed of a MIMO transistor, and the third to fifth transistors are composed of an NMOS transistor. The source of the first, second and sixth transistors is connected to the first power supply voltage of 2V or less, the source of the fifth transistor is connected to a voltage lower than 0V, and the third transistor is connected. Is connected between the drain of the first transistor and the drain of the fifth transistor, and the fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor. The 6-transistor is a data storage unit that stores a comparator configured by connecting a gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit, and a time code when the comparison result signal is inverted. And.

In the second aspect of the present disclosure, the differential input circuit is operated at the first power supply voltage, the signal is output when the voltage of the input signal is higher than the voltage of the reference signal, and the positive feedback circuit is described as described above. A comparison that represents a comparison of the voltages of the input signal and the reference signal based on the output signal from the differential input circuit, operated at a second power supply voltage equal to or lower than the first power supply voltage. The transition speed when the result signal is inverted is increased, and in the voltage conversion circuit, the output signal of the differential input circuit is converted into a signal corresponding to the second power supply voltage, and the differential input circuit is used. Is a first transistor and a second transistor constituting the current mirror, a third transistor in which the reference signal is input to the gate, a fourth transistor in which the input signal is input to the gate, and a first transistor as a constant current source. A 5 transistor and a 6th transistor for outputting the output signal are provided, the 1st, 2nd and 6th transistors are composed of a MIMO transistor, and the 3rd to 5th transistors are composed of an NMOS transistor. , The source of the first, second and sixth transistors is connected to the first power supply voltage of 2V or less, the source of the fifth transistor is connected to a voltage lower than 0V, and the third transistor is connected. , The fourth transistor is connected between the drain of the first transistor and the drain of the fifth transistor, and the fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor. The transistor is configured by connecting the gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit, and the data storage unit stores the time code when the comparison result signal is inverted.

The solid-state imaging device of the third aspect of the present disclosure operates at the first power supply voltage, and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal, and the first A comparison result signal that operates at a second power supply voltage that is equal to or lower than the power supply voltage and represents a comparison result of the voltages of the input signal and the reference signal based on the output signal from the differential input circuit. has a positive feedback circuit to speed up the transition speed at the time of reversing, the output signal of the differential input circuit, and a voltage conversion circuit for converting the signal corresponding to the second power supply voltage, the differential The input circuit includes a first transistor and a second transistor constituting the current mirror, a third transistor in which the reference signal is input to the gate, a fourth transistor in which the input signal is input to the gate, and as a constant current source. The fifth transistor and the sixth transistor for outputting the output signal are included, the first, second and sixth transistors are composed of a MIMO transistor, and the third to fifth transistors are composed of an NMOS transistor. The source of the first, second and sixth transistors is connected to the first power supply voltage of 2V or less, the source of the fifth transistor is connected to a voltage lower than 0V, and the third transistor is connected. Is connected between the drain of the first transistor and the drain of the fifth transistor, and the fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor. The 6-transistor has a comparator configured by connecting a gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit, and a data storage unit that stores a time code when the comparison result signal is inverted. It includes an AD converter including the above, and a pixel circuit that outputs a charge signal generated by receiving light incident on a pixel and performing photoelectric conversion to the differential input circuit as the input signal.

The electronic device of the fourth aspect of the present disclosure is a differential input circuit that operates at a first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal, and the first power supply. It operates at a second power supply voltage that is the same as or lower than the voltage, and the comparison result signal that represents the comparison result of the voltage of the input signal and the reference signal is inverted based on the output signal from the differential input circuit. It has a positive feedback circuit that speeds up the transition speed at the time of operation, and a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage, and the differential input. The circuit comprises a first transistor and a second transistor constituting the current mirror, a third transistor in which the reference signal is input to the gate, a fourth transistor in which the input signal is input to the gate, and a constant current source. The first, second, and sixth transistors include a fifth transistor and a sixth transistor that outputs the output signal, and the third to fifth transistors are composed of an NMOS transistor. The sources of the first, second and sixth transistors are connected to the first power supply voltage of 2V or less, the source of the fifth transistor is connected to a voltage lower than 0V, and the third transistor is connected. , The fourth transistor is connected between the drain of the first transistor and the drain of the fifth transistor, and the fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor. The transistor includes a comparator configured by connecting a gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit, and a data storage unit that stores a time code when the comparison result signal is inverted. An AD converter including an AD converter, and a solid-state imaging device including a pixel circuit that outputs a charge signal generated by receiving light incident on a pixel and performing photoelectric conversion to the differential input circuit as the input signal. Be prepared.

In the third and fourth aspects of the present disclosure, in the differential input circuit, the differential input circuit is operated at the first power supply voltage, and the signal is output when the voltage of the input signal is higher than the voltage of the reference signal, and the positive feedback circuit. In the second power supply voltage which is equal to or lower than the first power supply voltage, and based on the output signal from the differential input circuit, a comparison result of the voltages of the input signal and the reference signal. The transition speed when the comparison result signal representing the above is inverted is increased, and in the voltage conversion circuit, the output signal of the differential input circuit is converted into a signal corresponding to the second power supply voltage, and the differential The input circuit includes a first transistor and a second transistor constituting the current mirror, a third transistor in which the reference signal is input to the gate, a fourth transistor in which the input signal is input to the gate, and a constant current source. The fifth transistor and the sixth transistor for outputting the output signal are provided, the first, second, and sixth transistors are composed of MIMO transistors, and the third to fifth transistors are NMOS transistors. The source of the first, second and sixth transistors is connected to the first power supply voltage of 2V or less, the source of the fifth transistor is connected to a voltage lower than 0V, and the first Three transistors are connected between the drain of the first transistor and the drain of the fifth transistor, and the fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor. The sixth transistor is configured by connecting the gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit, and the data storage unit stores the time code when the comparison result signal is inverted. To. In the pixel circuit, a charge signal generated by receiving light incident on the pixel and performing photoelectric conversion is output to the differential input circuit as the input signal.

The control method of the comparator of the fifth aspect of the present disclosure operates with a differential input circuit operating at a first power supply voltage and a second power supply voltage equal to or lower than the first power supply voltage. The differential input circuit includes a positive feedback circuit and a voltage conversion circuit, and the differential input circuit has a first transistor and a second transistor constituting a current mirror, a third transistor in which a reference signal is input to a gate, and an input signal. The first, second, and sixth transistors include a fourth transistor input to the gate, a fifth transistor as a constant current source, and a sixth transistor that outputs an output signal of the differential input circuit. The third to fifth transistors are composed of an NMOS transistor, and the sources of the first, second and sixth transistors are connected to the first power supply voltage of 2 V or less, and the first power supply voltage is connected. The source of the five transistors is connected to a voltage lower than 0V, the third transistor is connected between the drain of the first transistor and the drain of the fifth transistor, and the fourth transistor is the second. A comparator connected between the drain of the transistor and the drain of the fifth transistor, the sixth transistor is configured by connecting the gate to the drain of the second transistor and the drain to the voltage conversion circuit. the differential input circuit, a signal voltage of the input signal and outputs a signal when higher than the voltage of the reference signal, the voltage conversion circuit, the output signal, corresponding to said second power supply voltage converted to, the positive feedback circuit is, on the basis of the said output signal of said differential input circuit which has been converted by the voltage conversion circuit, the comparison result signal representative of the comparison result of the voltage of the input signal and the reference signal is reversed Increase the transition speed when doing.

In the fifth aspect of the present disclosure, a differential input circuit operating at a first power supply voltage and a positive feedback circuit operating at a second power supply voltage equal to or lower than the first power supply voltage. The differential input circuit includes a first transistor and a second transistor constituting a current mirror, a third transistor in which a reference signal is input to the gate, and an input signal input to the gate. The first, second, and sixth transistors include a fourth transistor, a fifth transistor as a constant current source, and a sixth transistor that outputs an output signal of the differential input circuit, and the first, second, and sixth transistors are composed of MIMO transistors. , The 3rd to 5th transistors are composed of NMOS transistors, the sources of the 1st, 2nd and 6th transistors are connected to the 1st power supply voltage of 2V or less, and the source of the 5th transistor is , The third transistor is connected between the drain of the first transistor and the drain of the fifth transistor, and the fourth transistor is connected to the drain of the second transistor and the drain of the second transistor. The differential input of the comparator which is connected to the drain of the fifth transistor, the sixth transistor is configured by connecting the gate to the drain of the second transistor and the drain to the voltage conversion circuit. in the circuit, the signal is output when the voltage of the input signal is higher than the voltage of the reference signal, in the voltage conversion circuit, the output signal is converted into a signal corresponding to said second power supply voltage, wherein in the positive feedback circuit, the transition speed at which the voltage based on the output signal of the differential input circuit which has been converted by the conversion circuit, the comparison result signal is inverted result of the comparison of the voltage of the input signal and the reference signal Is speeded up.

The control method of the comparator, the AD converter, the solid-state image sensor, the electronic device, and the comparator may be an independent device or a module incorporated in another device.

According to the first to fifth aspects of the present disclosure, it is possible to reduce the power consumption while improving the determination speed of the comparator.

The effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a figure which shows the schematic structure of the solid-state image sensor which concerns on this disclosure. It is a block diagram which shows the detailed composition example of a pixel. It is a circuit diagram which shows the 1st structure of the comparison circuit. It is a figure which shows the transition of each signal during operation of a comparison circuit. It is a figure explaining the detailed structure of a pixel circuit. It is a timing chart explaining the 1st configuration of a comparison circuit and the operation of a pixel. It is a circuit diagram which shows the 2nd structure of the comparison circuit. It is a circuit diagram which shows the 3rd structure of a comparison circuit. It is a circuit diagram which shows the 4th structure of the comparison circuit. It is a circuit diagram which shows the 5th structure of the comparison circuit. It is a circuit diagram which shows the 6th structure of the comparison circuit. It is a timing chart explaining the 6th configuration of a comparison circuit and the operation of a pixel. It is a circuit diagram which shows the structural example of the comparison circuit in the case of pixel sharing. It is a conceptual diagram which constitutes a solid-state image sensor by laminating two semiconductor substrates. It is a figure which shows the circuit configuration example in the case of configuring a solid-state image sensor with two semiconductor substrates. It is a conceptual diagram which constitutes a solid-state image sensor by stacking three semiconductor substrates. It is a figure which shows the circuit configuration example in the case of constructing a solid-state image sensor with three semiconductor substrates. It is a block diagram which shows the structural example of the image pickup apparatus as an electronic device which concerns on this disclosure.

Hereinafter, embodiments for carrying out the present disclosure (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. Schematic configuration example of a solid-state image sensor 2. Detailed configuration example of pixels 3. First configuration example of the comparison circuit 4. Second configuration example of the comparison circuit 5. Third configuration example of the comparison circuit 6. Fourth configuration example of the comparison circuit 7. Fifth configuration example of the comparison circuit 8. Sixth configuration example of the comparison circuit 9. Pixel sharing configuration example 10. Multiple board configuration 1
11. Multiple board configuration 2
12. Application example to electronic devices

<1. Schematic configuration example of a solid-state image sensor>
FIG. 1 shows a schematic configuration of a solid-state image sensor according to the present disclosure.

The solid-state image sensor 1 of FIG. 1 has a pixel array unit 22 in which pixels 21 are arranged in a two-dimensional array on a semiconductor substrate 11 using, for example, silicon (Si) as a semiconductor. The pixel array unit 22 is also provided with a time code transfer unit 23 that transfers the time code generated by the time code generation unit 26 to each pixel 21. Around the pixel array unit 22 on the semiconductor substrate 11, a pixel drive circuit 24, a DAC (D / A Converter) 25, a time code generator 26, a vertical drive circuit 27, an output unit 28, and a timing generation circuit 29 Is formed.

Each of the pixels 21 arranged in a two-dimensional array is provided with a pixel circuit 41 and an ADC 42, as will be described later with reference to FIG. 2, and the pixel 21 is a light receiving element (for example, a photo) in the pixel. A charge signal corresponding to the amount of light received by the diode) is generated, converted into a digital pixel signal SIG, and output.

The pixel drive circuit 24 drives the pixel circuit 41 (FIG. 2) in the pixel 21. The DAC 25 generates a reference signal (reference voltage signal) REF, which is a slope signal whose level (voltage) monotonically decreases with the passage of time, and supplies the reference signal (reference voltage signal) REF to each pixel 21. The time code generation unit 26 generates a time code used when each pixel 21 converts an analog pixel signal SIG into a digital signal (AD conversion), and supplies the time code to the corresponding time code transfer unit 23. A plurality of time code generation units 26 are provided for the pixel array unit 22, and as many time code transfer units 23 as the number corresponding to the time code generation unit 26 are provided in the pixel array unit 22. .. That is, the time code generation unit 26 and the time code transfer unit 23 that transfers the time code generated there have a one-to-one correspondence.

The vertical drive circuit 27 controls the output unit 28 to output the digital pixel signal SIG generated in the pixel 21 to the output unit 28 in a predetermined order based on the timing signal supplied from the timing generation circuit 29. The digital pixel signal SIG output from the pixel 21 is output from the output unit 28 to the outside of the solid-state image sensor 1. The output unit 28 performs predetermined digital signal processing such as black level correction processing for correcting the black level and CDS (Correlated Double Sampling) processing as necessary, and then outputs the digital signal to the outside.

The timing generation circuit 29 is configured by a timing generator or the like that generates various timing signals, and supplies the generated various timing signals to the pixel drive circuit 24, the DAC 25, the vertical drive circuit 27, and the like.

The solid-state image sensor 1 is configured as described above. In FIG. 1, as described above, all the circuits constituting the solid-state image sensor 1 have been described as being formed on one semiconductor substrate 11, but as will be described later, the solid-state image sensor 1 is configured. The circuit to be used may be divided into a plurality of semiconductor substrates 11 and arranged.

<2. Detailed configuration example of pixels>
FIG. 2 is a block diagram showing a detailed configuration of the pixel 21.

The pixel 21 is composed of a pixel circuit 41 and an ADC (AD converter) 42.

The pixel circuit 41 outputs a charge signal corresponding to the amount of received light to the ADC 42 as an analog pixel signal SIG. The ADC 42 converts the analog pixel signal SIG supplied from the pixel circuit 41 into a digital signal.

The ADC 42 includes a comparison circuit 51 and a data storage unit 52.

The comparison circuit 51 compares the reference signal REF supplied from the DAC 25 with the pixel signal SIG, and outputs an output signal VCO as a comparison result signal representing the comparison result. The comparison circuit 51 inverts the output signal VCO when the reference signal REF and the pixel signal SIG are the same (voltage).

The comparison circuit 51 is composed of a differential input circuit 61, a voltage conversion circuit 62, and a positive feedback circuit (PFB) 63, the details of which will be described later with reference to FIG.

In addition to the output signal VCO being input from the comparison circuit 51 to the data storage unit 52, the vertical drive circuit 27 indicates that the operation is a pixel signal writing operation and the WR signal indicating that the pixel signal reading operation is being performed. The signal and the WORD signal that controls the read timing of the pixel 21 during the read operation of the pixel signal are supplied from the vertical drive circuit 27. Further, the time code generated by the time code generation unit 26 is also supplied via the time code transfer unit 23.

The data storage unit 52 includes a latch control circuit 71 that controls a time code writing operation and a reading operation based on the WR signal and the RD signal, and a latch storage unit 72 that stores the time code.

In the time code writing operation, the latch control circuit 71 is updated every unit time supplied from the time code transfer unit 23 while the Hi (High) output signal VCO is input from the comparison circuit 51. The time code is stored in the latch storage unit 72. Then, when the reference signal REF and the pixel signal SIG become the same (voltage) and the output signal VCO supplied from the comparison circuit 51 is inverted to Lo (Low), the time code supplied is written (updated). It is stopped, and the time code finally stored in the latch storage unit 72 is held in the latch storage unit 72. The time code stored in the latch storage unit 72 represents the time when the pixel signal SIG and the reference signal REF become equal, and data indicating that the pixel signal SIG was the reference voltage at that time, that is, digitization. Represents the light intensity value.

After the sweep of the reference signal REF is completed and the time code is stored in the latch storage units 72 of all the pixels 21 in the pixel array unit 22, the operation of the pixel 21 is changed from the writing operation to the reading operation.

In the time code reading operation, the latch control circuit 71 is based on the WORD signal that controls the reading timing, and when the pixel 21 reaches its own reading timing, the time code stored in the latch storage unit 72 ( The digital pixel signal SIG) is output to the time code transfer unit 23. The time code transfer unit 23 sequentially transfers the supplied time code in the column direction (vertical direction) and supplies it to the output unit 28.

The following is an inverted time code when the output signal VCO read from the latch storage unit 72 is inverted in the time code reading operation in order to distinguish it from the time code written in the latch storage unit 72 in the time code writing operation. The digitized pixel data indicating that the pixel signal SIG was the reference voltage at that time is also referred to as AD conversion pixel data.

<3. First configuration example of the comparison circuit>
FIG. 3 is a circuit diagram showing a detailed configuration of the differential input circuit 61, the voltage conversion circuit 62, and the positive feedback circuit 63 that constitute the comparison circuit 51.

The differential input circuit 61 compares the pixel signal SIG output from the pixel circuit 41 in the pixel 21 with the reference signal REF output from the DAC 25, and determines when the pixel signal SIG is higher than the reference signal REF. Output a signal (current).

The differential input circuit 61 includes transistors 81 and 82 as a differential pair, transistors 83 and 84 constituting a current mirror, transistors 85 as a constant current source for supplying a current IB corresponding to the input bias current Vb, and a difference. It is composed of a transistor 86 that outputs an output signal HVO of the dynamic input circuit 61.

Transistors 81, 82, and 85 are composed of NMOS (Negative Channel MOS) transistors, and transistors 83, 84, and 86 are composed of MOSFETs (Positive Channel MOS) transistors.

Of the transistors 81 and 82 that form a differential pair, the reference signal REF output from the DAC 25 is input to the gate of the transistor 81, and the pixel output from the pixel circuit 41 in the pixel 21 is input to the gate of the transistor 82. The signal SIG is input. The sources of the transistors 81 and 82 are connected to the drain of the transistor 85, and the source of the transistor 85 is connected to GND (ground).

The drain of the transistor 81 is connected to the gates of the transistors 83 and 84 and the drain of the transistor 83 constituting the current mirror circuit, and the drain of the transistor 82 is connected to the drain of the transistor 84 and the gate of the transistor 86. The sources of transistors 83, 84, and 86 are connected to the first supply voltage VDDH.

The voltage conversion circuit 62 is composed of, for example, an NMOS type transistor 91. The drain of the transistor 91 is connected to the drain of the transistor 86 of the differential input circuit 61, the source of the transistor 91 is connected to a predetermined connection point in the positive feedback circuit 63, and the gate of the transistor 86 is connected to the bias voltage VBIAS. It is connected.

The transistors 81 to 86 constituting the differential input circuit 61 are circuits that operate at a high voltage up to the first power supply voltage VDDH, and the positive feedback circuit 63 has a second power supply voltage VDDL that is lower than the first power supply voltage VDDH. It is a working circuit. Here, the first power supply voltage VDDH is set to, for example, 2.9 [V], and the second power supply voltage VDDL is set to, for example, 1.1 [V]. The voltage conversion circuit 62 converts the output signal HVO input from the differential input circuit 61 into a low-voltage signal (conversion signal) LVI in which the positive feedback circuit 63 can operate, and supplies the output signal HVO to the positive feedback circuit 63.

The bias voltage VBIAS may be any voltage that converts the transistors 101 to 105 of the positive feedback circuit 63 that operates at a constant voltage into a voltage that does not destroy the transistors 101 to 105. For example, the bias voltage VBIAS can be the same voltage (VBIAS = VDDL) as the second power supply voltage VDDL of the positive feedback circuit 63.

The positive feedback circuit 63 is inverted when the pixel signal SIG is higher than the reference signal REF based on the conversion signal LVI in which the output signal HVO from the differential input circuit 61 is converted into a signal corresponding to the second power supply voltage VDDL. Outputs the comparison result signal. Further, the positive feedback circuit 63 speeds up the transition speed when the output signal VCO output as the comparison result signal is inverted.

The positive feedback circuit 63 is composed of five transistors 101 to 105. Here, the transistors 101, 102, and 104 are composed of MOSFET transistors, and the transistors 103 and 105 are composed of MIMO transistors.

The source of the transistor 91, which is the output end of the voltage conversion circuit 62, is connected to the drain of the transistors 102 and 103 and the gate of the transistors 104 and 105. The source of the transistors 101 and 104 is connected to the second power supply voltage VDDL, the drain of the transistor 101 is connected to the source of the transistor 102, and the gate of the transistor 102 is the output end of the positive feedback circuit 63. It is connected to the drain of. The sources of transistors 103 and 105 are connected to GND. The initialization signal INI2 is supplied to the gate of the transistor 101, and the initialization signal INI1 is supplied to the gate of the transistor 103.

The transistors 104 and 105 form an inverter circuit, and the connection point between the drains thereof is an output end at which the comparison circuit 51 outputs an output signal VCO.

The operation of the comparison circuit 51 configured as described above will be described. FIG. 4 shows the transition of each signal during the operation of the comparison circuit 51. In FIG. 4, “G86” represents the gate potential of the transistor 86.

First, the reference signal REF is set to a voltage higher than the pixel signal SIG of all the pixels 21, and the initialization signals INI1 and INI2 are set to Hi, so that the comparison circuit 51 is initialized.

More specifically, a reference signal REF is applied to the gate of the transistor 81, and a pixel signal SIG is applied to the gate of the transistor 82. When the voltage of the reference signal REF is higher than the voltage of the pixel signal SIG, most of the current output by the transistor 85, which is a current source, flows to the transistor 83 connected to the diode via the transistor 81. The channel resistance of the transistor 84 having a gate common to the transistor 83 becomes sufficiently low to keep the gate of the transistor 86 at substantially the first power supply voltage VDDH level, and the transistor 86 is cut off. Therefore, even if the transistor 91 of the voltage conversion circuit 62 is conducting, the positive feedback circuit 63 as the charging circuit does not charge the conversion signal LVI. On the other hand, since the Hi signal is supplied as the initialization signals INI1 and INI2, the transistor 103 conducts and the positive feedback circuit 63 discharges the conversion signal LVI. Further, since the transistor 101 is cut off, the positive feedback circuit 63 does not charge the conversion signal LVI via the transistor 102. As a result, the conversion signal LVI is discharged to the GND level, the positive feedback circuit 63 outputs the Hi output signal VCO by the transistors 104 and 105 constituting the inverter, and the comparison circuit 51 is initialized.

After initialization, the initialization signals INI1 and INI2 are set to Lo, and the sweep of the reference signal REF is started.

During the period when the reference signal REF is higher than the pixel signal SIG, the transistor 86 is turned off and cut off, and the output signal VCO becomes a Hi signal, so that the transistor 102 is also turned off and cut off. The transistor 103 is also cut off because the initialization signal INI1 is Lo. The conversion signal LVI keeps GND in a high impedance state, and the Hi output signal VCO is output.

When the reference signal REF becomes lower than the pixel signal SIG, the output current of the transistor 85 of the current source does not flow through the transistor 81, the gate potentials of the transistors 83 and 84 increase, and the channel resistance of the transistor 84 increases. The current flowing through the transistor 82 causes a voltage drop to lower the gate potential of the transistor 86, and the transistor 91 becomes conductive. The output signal HVO output from the transistor 86 is converted into a conversion signal LVI by the transistor 91 of the voltage conversion circuit 62 and supplied to the positive feedback circuit 63. The positive feedback circuit 63 as a charging circuit charges the conversion signal LVI and brings the potential closer from the GND voltage to the second power supply voltage VDDL.

When the voltage of the conversion signal LVI exceeds the threshold voltage of the inverter composed of the transistors 104 and 105, the output signal VCO becomes Lo and the transistor 102 becomes conductive. The transistor 101 is also conducting because the Lo initialization signal INI2 is applied, and the positive feedback circuit 63 rapidly charges the conversion signal LVI via the transistors 101 and 102 to set the potential to the second power supply voltage. Lift up to VDDL at once.

Since the bias voltage VBIAS is applied to the gate of the transistor 91 of the voltage conversion circuit 62, the transistor 91 is cut off when the voltage of the conversion signal LVI reaches a voltage value lower than the bias voltage VBIAS by the transistor threshold value. Even if the transistor 86 remains conductive, the conversion signal LVI is not charged any more, and the voltage conversion circuit 62 also functions as a voltage clamp circuit.

Charging the conversion signal LVI by the continuity of the transistor 102 is a positive feedback operation that accelerates the movement of the conversion signal LVI, starting from the fact that the conversion signal LVI has risen to the inverter threshold value. The transistor 85, which is the current source of the differential input circuit 61, is set to a very small current per circuit because the number of circuits operating in parallel and simultaneously in the solid-state imaging device 1 is enormous. Further, the reference signal REF is swept very slowly because the voltage changing in the unit time when the time code is switched becomes the LSB step of AD conversion. Therefore, the change in the gate potential of the transistor 86 is also slow, and the change in the output current of the transistor 86 driven by the change is also slow. However, by applying positive feedback to the conversion signal LVI charged by the output current from the subsequent stage, the output signal VCO can transition sufficiently rapidly. Desirably, the transition time of the output signal VCO is a fraction of the unit time of the time code, and is typically 1 ns or less. The comparison circuit 51 of the present disclosure can achieve this output transition time only by setting a small current of, for example, 0.1 uA, to the transistor 85 of the current source.

<Detailed configuration example of pixel circuit>
The detailed configuration of the pixel circuit 41 will be described with reference to FIG.

FIG. 5 is a circuit diagram showing details of the pixel circuit 41 added to the comparison circuit 51 shown in FIG.

The pixel circuit 41 is composed of a photodiode (PD) 121 as a photoelectric conversion element, an emission transistor 122, a transfer transistor 123, a reset transistor 124, and an FD (floating diffusion layer) 125.

The emission transistor 122 is used when adjusting the exposure period. Specifically, when the emission transistor 122 is turned on when the exposure period is desired to be started at an arbitrary timing, the electric charge accumulated in the photodiode 121 up to that point is discharged, so that the emission transistor 122 is turned off. After that, the exposure period will start.

The transfer transistor 123 transfers the electric charge generated by the photodiode 121 to the FD125. The reset transistor 124 resets the electric charge held in the FD 125. The FD125 is connected to the gate of the transistor 82 of the differential input circuit 61. As a result, the transistor 82 of the differential input circuit 61 also functions as an amplification transistor of the pixel circuit 41.

The source of the reset transistor 124 is connected to the gate of the transistor 82 of the differential input circuit 61 and the FD125, and the drain of the reset transistor 124 is connected to the drain of the transistor 82. Therefore, there is no fixed reset voltage to reset the charge on the FD125. This is because the reset voltage for resetting the FD125 can be arbitrarily set by using the reference signal REF by controlling the circuit state of the differential input circuit 61.

<Pixel timing chart>
The operation of the pixel 21 shown in FIG. 5 will be described with reference to the timing chart of FIG.

First, at time t1, the reference signal REF is _{set to the reset voltage V rst} that resets the charge of the FD 125 from _{the standby voltage V stb} so far, and the charge of the FD 125 is reset by turning on the reset transistor 124. Will be done.

Next, at time t2, the initialization signal INI2 supplied to the gate of the transistor 101 of the positive feedback circuit 63 is set to Hi, and immediately after that, the initialization signal IN1I supplied to the gate of the transistor 103 is set to Hi. , The positive feedback circuit 63 is set to the initial state.

Further, at time t2, the reference signal REF is _{raised to a predetermined voltage V u} , and the comparison between the reference signal REF and the pixel signal SIG (sweep of the reference signal REF) is started. At this point, the output signal VCO is Hi because the reference signal REF is larger than the pixel signal SIG.

At time t3 when it is determined that the reference signal REF and the pixel signal SIG are the same, the output signal VCO is inverted (transitioned to Low). When the output signal VCO is inverted, the positive feedback circuit 63 speeds up the inversion of the output signal VCO as described above. Further, the data storage unit 52 latch-stores the time data (N-bit DATA [1] to DATA [N]) at the time when the output signal VCO is inverted.

At time t4, which is the start time of the signal write period and the signal read period, the voltage of the reference signal REF supplied to the gate of the transistor 81 of the comparison circuit 51 is at a level at which the transistor 81 is turned off (standby voltage V _stb). ) Is reduced. As a result, the current consumption of the comparison circuit 51 during the signal reading period is suppressed.

At time t5, the WORD signal that controls the read timing becomes Hi, and the time data (N-bit DATA [1] to DATA [N]) stored in the latch is output from the latch control circuit 71 of the data storage unit 52. To. The time data acquired here is P-phase data at the reset level during CDS (Correlated Double Sampling) processing.

At time t6, the reference signal REF is _{raised to a predetermined voltage V u} , and the initialization signal INI2 supplied to the gate of the transistor 101 is set to Hi. Immediately after that, the initialization signal INI1 supplied to the gate of the transistor 103 is also set to Hi, and the positive feedback circuit 63 is set to the initial state again.

At time t7, the transfer transistor 123 of the pixel circuit 41 is turned on by the transfer signal TX of Hi, and the electric charge generated by the photodiode 121 is transferred to the FD 125.

Then, following the transition of the initialization signal INI2 to Low, the initialization signal INI1 is returned to Low, and then the comparison between the reference signal REF and the pixel signal SIG (sweep of the reference signal REF) is started. At this point, the output signal VCO is Hi because the reference signal REF is larger than the pixel signal SIG.

Then, at the time t8 when it is determined that the reference signal REF and the pixel signal SIG are the same, the output signal VCO is inverted (transitioned to Low). When the output signal VCO is inverted, the positive feedback circuit 63 speeds up the inversion of the output signal VCO. Further, the data storage unit 52 latch-stores the time data (N-bit DATA [1] to DATA [N]) at the time when the output signal VCO is inverted.

At time t9, which is the start time of the signal write period and the signal read period, the voltage of the reference signal REF supplied to the gate of the transistor 81 of the comparison circuit 51 is at a level at which the transistor 81 is turned off (standby voltage V _stb). ) Is reduced. As a result, the current consumption of the comparison circuit 51 during the signal reading period is suppressed.

At time t10, the WORD signal that controls the read timing becomes Hi, and the time data (N-bit DATA [1] to DATA [N]) stored in the latch is output from the latch control circuit 71 of the data storage unit 52. To. The time data acquired here is the D-phase data of the signal level at the time of CDS processing. The time t11 is in the same state as the time t1 described above, and is driven by the next 1V (1 vertical scanning period).

According to the above-mentioned drive of the pixel 21, the reset level P phase data is first acquired and then read out to the output unit 28, and then the signal level D phase data is acquired and the output unit 28 is obtained. Is read to. The output unit 28 holds the P-phase data in the internal frame memory, and performs CDS processing together with the D-phase data supplied later. Any method can be selected as the method for performing CDS processing. For example, the data storage unit 52 may hold the P-phase data inside the data storage unit 52 and output the P-phase data simultaneously or alternately with the D-phase data so that the output unit 28 performs the CDS processing.

By the above operation, each pixel 21 of the pixel array unit 22 of the solid-state image sensor 1 can perform a global shutter operation in which all pixels are reset at the same time and all the pixels are exposed at the same time. Since all the pixels can be exposed and read at the same time, there is usually no need for a holding unit provided in the pixel to hold the charge until the charge is read. Further, in the configuration of the pixel 21, the selection transistor for selecting the pixel for outputting the pixel signal SIG, which is required in the column parallel readout type solid-state image sensor, is not required.

In driving the pixel 21 described with reference to FIG. 6, the emission transistor 122 is always controlled to be off. However, as shown by the broken line in FIG. 6, an arbitrary exposure period can be set by setting the emission signal OFG to Hi, turning on the emission transistor 122 once, and then turning it off at a desired time. It is possible.

<4. Second configuration example of the comparison circuit>
FIG. 7 is a circuit diagram showing a second configuration of the comparison circuit 51. Note that also in FIG. 7, the detailed circuit of the pixel circuit 41 is also shown together with the second configuration of the comparison circuit 51. The same applies to FIGS. 8 to 11 described later.

The second configuration of the comparison circuit 51 is the same as the first configuration shown in FIG. 5, except that two transistors 161 and 162 are added to the positive feedback circuit 63.

In the second configuration, the inverter circuit of the positive feedback circuit 63 in the first configuration is replaced with a two-input NOR circuit. A control signal TEST_VCO, which is a second input, is supplied to the gate of the transistor 161 composed of the MOSFET transistor and the gate of the transistor 162 composed of the NMOS transistor, which is not the conversion signal LVI which is the first input. ..

The source of the transistor 161 is connected to the second power supply voltage VDDL, and the drain of the transistor 161 is connected to the source of the transistor 104. The drain of the transistor 162 is connected to the output end of the comparison circuit 51, and the source of the transistor 162 is connected to GND.

In the comparison circuit 51 in the second configuration configured as described above, when the control signal TEST_VCO which is the second input is set to Hi, the output signal VCO can be set to Lo regardless of the state of the differential input circuit 61. it can.

When the bias voltage VBIAS is controlled to Lo level, the transistor 91 is cut off, and the initialization signals INI1 and INI2 are set to Hi, the output signal VCO becomes Hi regardless of the state of the differential input circuit 61. Therefore, by combining the forced Hi output of this output signal VCO and the forced Lo output of the control signal TEST_VCO described above, it is related to the state of the differential input circuit 61 and the pixel circuits 41 and DAC 25 which are the preceding stages thereof. The output signal VCO can be set to any value. With this function, for example, the circuit from the pixel 21 to the subsequent stage can be tested only by the electric signal input without relying on the optical input to the solid-state image sensor 1.

Further, for example, when the voltage of the pixel signal SIG falls below the final voltage of the reference signal REF due to a higher brightness than expected (for example, the sun image reflected within the angle of view of the solid-state imaging device 1), the output signal VCO of the comparison circuit 51 The comparison period ends with Hi, and the data storage unit 52 controlled by the output signal VCO cannot fix the value and loses the AD conversion function. In order to prevent the occurrence of such a state, the output signal VCO that has not yet been inverted to Lo can be forcibly inverted by inputting the Hi pulse control signal TEST_VCO at the end of sweeping the reference signal REF. it can. Since the data storage unit 52 latches and stores the time code immediately before the forced inversion, when the configuration of FIG. 7 is adopted, the ADC 42 eventually serves as an AD converter that clamps the output value for the luminance input above a certain level. Function.

<5. Third configuration example of the comparison circuit>
FIG. 8 is a circuit diagram showing a third configuration of the comparison circuit 51.

In the third configuration of the comparison circuit 51, in the differential input circuit 61, the source of the transistor 85 as a constant current source is connected to the negative bias voltage VSS lower than 0 [V] instead of GND. It is different from the second configuration shown in FIG. Other configurations are the same as those of the second configuration of FIG. 7. The negative bias voltage VSS is, for example, -1.8 [V].

In the third configuration of the comparison circuit 51, the operating range of the comparison circuit 51 is expanded by setting the source potential of the transistor 85 to a potential lower than 0V. Further, in accordance with the negative subtraction of the source potential of the transistor 85, the substrate voltage side of the photodiode 121 and the FD125 in the pixel circuit 41 is also set to the negative bias voltage VSS. Thereby, the saturated charge amount of each pixel 21 (pixel circuit 41) can be increased.

<6. Fourth configuration example of the comparison circuit>
FIG. 9 is a circuit diagram showing a fourth configuration of the comparison circuit 51.

In the fourth configuration of the comparison circuit 51, the transistors 83, 84, and 86 of the differential input circuit 61 shown in FIG. 8 are changed to the transistors 83', 84', and 86'. Other configurations are the same as those of the second configuration of FIG. 7.

In the third configuration shown in FIG. 8, the first power supply voltage VDDH is set to, for example, about 2.9 [V], and the transistors 83, 84, and 86 of the differential input circuit 61 have a film thickness. It is composed of thick high-voltage transistors.

On the other hand, in the fourth configuration of FIG. 9, the transistors 83', 84', and 86'are composed of low-voltage transistors having a thin film thickness, which are driven by a low voltage of 2 V or less. That is, in accordance with the fact that the source potential of the transistor 85 is pulled to the negative bias voltage VSS (-1.8 [V]), the first power supply voltage VDDH of 2.9 [V] is set to 1.1 [V]. By lowering the first power supply voltage to VDDH', the transistors 83, 84, and 86 of the differential input circuit 61 can be changed to the low voltage transistors 83', 84', and 86'. The potential difference of the entire comparison circuit 51 is 2.9 [V] from -1.8 [V] to 1.1 [V], and 2.9 [V] from 0 [V] to 2.9 [V]. It is the same as the first and second configurations with V].

In the fourth configuration, the thick high-voltage transistors 83, 84, and 86 are changed to the thin low-voltage transistors 83', 84', and 86', so that the comparison circuit 51 can be used. The circuit area can be reduced.

The second power supply voltage VDDL may remain at 1.1 [V], which is the same as in the first to third configurations, but the positive feedback circuit 63 has a voltage lower than the first power supply voltage VDDH'of the differential input circuit 61. Since it can be operated, the first power supply voltage VDDH may be lowered to a voltage lower than the first power supply voltage VDDH'in accordance with the reduction to the first power supply voltage VDDH'. As a result, further power saving can be achieved. The second power supply voltage VDDL'can be set to, for example, about 0.6 [V]. The bias voltage VBIAS is also lowered as the second power supply voltage VDDL'is lowered.

<7. Fifth configuration example of the comparison circuit>
FIG. 10 is a circuit diagram showing a fifth configuration of the comparison circuit 51.

Comparing the fifth configuration of the comparison circuit 51 with the fourth configuration of FIG. 9, the two transistors 161 and 162 are omitted in the positive feedback circuit 63, and the two-input NOR circuit is returned to the inverter circuit. Further, a transistor 163, which is a MIMO transistor, is newly added to the positive feedback circuit 63. The source of the transistor 163 is connected to the second power supply voltage VDDL', and the drain is connected to the source of the transistor 91 together with the drain of the transistors 102 and 103 and the gates of the transistors 104 and 105. A control signal xTEST_VCO, which is an inverted signal of the control signal TEST_VCO input to the NOR circuit, is supplied to the gate of the transistor 163. Other configurations are the same as those of the fourth configuration of FIG.

In the fifth configuration of the comparison circuit 51 of FIG. 10, the Lo control signal xTEST_VCO is provided with a test function capable of forcibly setting the output signal VCO of the comparison circuit 51 to Lo output regardless of the state of the differential input circuit 61. Is realized by supplying the gate of the transistor 163.

In other words, the fifth configuration of the comparison circuit 51 of FIG. 10 realizes the test function by a method different from that of the fourth configuration shown in FIG. When the Lo control signal xTEST_VCO is supplied to the gate of the transistor 163 with the initialization signal INI1 set to Lo, the comparison circuit 51 outputs the Lo output signal VCO. On the other hand, when the Hi control signal xTEST_VCO is supplied to the gate of the transistor 163 with the initialization signal INI1 set to Hi, the comparison circuit 51 outputs the Hi output signal VCO.

According to the fifth configuration of the comparison circuit 51 of FIG. 10, the test function can be realized with one less number of transistors than the fourth configuration shown in FIG.

Further, according to the fifth configuration of the comparison circuit 51 of FIG. 10, it is possible to prevent a malfunction that is a concern due to the reduction of the second power supply voltage VDDL of the positive feedback circuit 63 to the second power supply voltage VDDL'.

<8. 6th configuration example of comparison circuit>
FIG. 11 is a circuit diagram showing a sixth configuration of the comparison circuit 51.

Comparing the sixth configuration of the comparison circuit 51 with the fifth configuration of FIG. 10, the configuration of the differential input circuit 61 is different. Specifically, a transistor 165 is added between the transistors 81 and 83', and a transistor 166 is added between the transistors 82 and 84'.

Transistors 165 and 166 are composed of NMOS transistors, and a control signal Vh is supplied to the gates of the transistors 165 and 166. The source of the transistor 165 is connected to the drain of the transistor 81, and the drain of the transistor 165 is connected to the drain of the transistor 83'. The source of transistor 166 is connected to the drain of transistor 82, and the drain of transistor 166 is connected to the drain of transistor 84'.

In the fifth configuration shown in FIG. 10, since the transistors 83', 84', and 86'are directly connected to the transistors 81 or 82, the negative bias voltage VSS is set to the low voltage transistors 83', 84'. , And 86'can only be lowered to a voltage that can be tolerated.

Therefore, in the comparison circuit 51 of FIG. 11, the transistor 165 is inserted between the transistors 81 and 83', and the transistor 166 is inserted between the transistors 82 and 84', so that the transistors 81 and 83'are inserted. It is configured so that the space and the transistors 82 and 84'can be separated as needed. As a result, the negative bias voltage VSS can be lowered to a voltage that can be withstood by, for example, a high-voltage transistor.

According to the sixth configuration of the comparison circuit 51 of FIG. 11, the first power supply voltage VDDH'can be lowered to 1.1 [V] and the negative bias voltage VSS can be lowered to a voltage that can be withstood by the high-voltage transistor. The power consumption can be reduced while ensuring the saturated charge amount of each pixel 21 (pixel circuit 41). Further, since the low-voltage transistors 83', 84', and 86'are used, the circuit area can be reduced and the cost can be suppressed.

<Timing chart>
FIG. 12 is a timing chart illustrating the operation of the pixel 21 (pixel circuit 41) in the sixth configuration of the comparison circuit 51 shown in FIG.

The times t31 to t41 of the timing chart of FIG. 12 correspond to the times t1 to t11 of the timing chart of FIG. 6, respectively.

In the timing chart of FIG. 12, the control signal xTEST_VCO for the test function and the control signal Vh supplied to the gates of the transistors 165 and 166 as the withstand voltage relaxation transistors are added to the timing chart of FIG. Since the operations other than xTEST_VCO and the control signal Vh are the same as those of the timing chart of FIG. 6, the description thereof will be omitted.

As shown in FIG. 12, _{during the period when the reference signal REF is lowered to the standby voltage V stb} , the control signal Vh is Lo so that the transistors 83', 84', and 86'are not subjected to a high potential difference. In addition, the comparison circuit 51 is controlled. On the other hand, the control signal Vh is Hi while the reference signal REF is _{set to the reset voltage V rst} or the voltage V _u. The Hi voltage of the control signal Vh is determined by the first power supply voltage VDDH'of the differential input circuit 61 and the negative bias voltage VSS. For example, as described above, when the first power supply voltage VDDH'is 1.1 [V] and the negative bias voltage VSS is -1.8 [V], the voltage of the Hi control signal Vh is 0 [V]. Can be.

<9. Pixel sharing configuration example>
The comparison circuit 51 described so far has a configuration in which one ADC 42 is arranged in one pixel 21, but a plurality of pixels 21 may share one ADC 42.

FIG. 13 is a circuit diagram showing a configuration example of a comparison circuit 51 in the case of pixel sharing in which one ADC 42 is shared by a plurality of pixels 21.

FIG. 13 shows a configuration example of the comparison circuit 51 in the case where one ADC 42 is shared by the four pixels 21 of the pixel 21A, the pixel 21B, the pixel 21C, and the pixel 21D.

In FIG. 13, the configurations of the differential input circuit 61, the voltage conversion circuit 62, and the positive feedback circuit 63 constituting the comparison circuit 51 are the same as those of the sixth configuration shown in FIG.

In FIG. 13, pixel circuits 41A to 41D are provided in the four pixels 21A to 21D, respectively, and the photodiode 121q, the emission transistor 122q, and the transfer transistor 123q are individually provided in the pixel circuits 41A to 41D. Has been done. On the other hand, the reset transistor 174 and the FD175 are shared by the four pixels 21A to 21D.

In FIG. 13, the sixth configuration shown in FIG. 11 is adopted as the circuit configuration of the comparison circuit 51, but any of the other first to fifth configurations can also be adopted.

<10. Multiple board configuration 1>
In the above description, the solid-state image sensor 1 has been described as being formed on one semiconductor substrate 11, but the solid-state image sensor 1 is configured by separately forming circuits on a plurality of semiconductor substrates 11. You may.

FIG. 14 shows a conceptual diagram in which the solid-state image sensor 1 is configured by laminating two semiconductor substrates 11 of the upper substrate 11A and the lower substrate 11C.

At least a pixel circuit 41 including a photodiode 121 is formed on the upper substrate 11A. At least a data storage unit 52 for storing the time code and a time code transfer unit 23 are formed on the lower substrate 11C. The upper substrate 11A and the lower substrate 11C are joined by, for example, a metal bond such as Cu-Cu.

FIG. 15 shows an example of a circuit configuration formed on each of the upper substrate 11A and the lower substrate 11C.

A pixel circuit 41 and transistors 81, 82, 85, 165, and 166 of the differential input circuit 61 of the ADC 42 are formed on the upper substrate 11A. The circuit of the ADC 42 and the time code transfer unit 23 excluding the transistors 81, 82, 85, 165, and 166 are formed on the lower substrate 11C.

<11. Multiple board configuration 2>
Although FIGS. 14 and 15 have described an example in which the solid-state image sensor 1 is composed of two semiconductor substrates 11, it can also be composed of three semiconductor substrates 11.

FIG. 16 shows a conceptual diagram constituting the solid-state image sensor 1 by stacking three semiconductor substrates 11 of an upper substrate 11A, an intermediate substrate 11B, and a lower substrate 11C.

A pixel circuit 41 including a photodiode 121 and at least a part of a circuit of a comparison circuit 51 are formed on the upper substrate 11A. At least a data storage unit 52 for storing the time code and a time code transfer unit 23 are formed on the lower substrate 11C. The intermediate substrate 11B is formed with the remaining circuits of the comparison circuit 51 that are not arranged on the upper substrate 11A. The upper substrate 11A and the intermediate substrate 11B, and the intermediate substrate 11B and the lower substrate 11C are joined by, for example, a metal bond such as Cu-Cu.

FIG. 17 shows an example of circuit arrangement of each semiconductor substrate 11 when the solid-state image sensor 1 is formed of three semiconductor substrates 11.

In the example of FIG. 17, the circuit arranged on the upper board 11A is the same as the circuit of the upper board 11A shown in FIG. 15, and the remaining circuits of the comparison circuit 51 are arranged on the intermediate board 11B and are arranged with the data storage unit 52. The time code transfer unit 23 is arranged on the lower board 11C.

<12. Application example to electronic devices>
The present disclosure is not limited to application to a solid-state image sensor. That is, the present disclosure applies to an image capture unit (photoelectric conversion unit) such as an image pickup device such as a digital still camera or a video camera, a portable terminal device having an image pickup function, or a copier that uses a solid-state image sensor as an image reader. It can be applied to all electronic devices that use a solid-state image sensor. The solid-state image sensor may be formed as a single chip, or may be a modular form having an image pickup function in which an image pickup unit and a signal processing unit or an optical system are packaged together.

FIG. 18 is a block diagram showing a configuration example of an image pickup apparatus as an electronic device according to the present disclosure.

The image pickup device 800 of FIG. 18 includes an optical unit 801 including a lens group, a solid-state image pickup device (imaging device) 802 adopting the configuration of the solid-state image pickup device 1 of FIG. 1, and a DSP (Digital Signal) which is a camera signal processing circuit. Processor) circuit 803 is provided. The image pickup apparatus 800 also includes a frame memory 804, a display unit 805, a recording unit 806, an operation unit 807, and a power supply unit 808. The DSP circuit 803, the frame memory 804, the display unit 805, the recording unit 806, the operation unit 807, and the power supply unit 808 are connected to each other via the bus line 809.

The optical unit 801 captures incident light (image light) from the subject and forms an image on the image pickup surface of the solid-state image pickup device 802. The solid-state image sensor 802 converts the amount of incident light imaged on the imaging surface by the optical unit 801 into an electric signal in pixel units and outputs it as a pixel signal. As the solid-state image sensor 802, the solid-state image sensor 1 shown in FIG. 1, that is, a solid-state image sensor having a comparison circuit 51 that reduces power consumption while improving the determination speed at the time of AD conversion of a pixel signal can be used. it can.

The display unit 805 is composed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state image sensor 802. The recording unit 806 records the moving image or still image captured by the solid-state image sensor 802 on a recording medium such as a hard disk or a semiconductor memory.

The operation unit 807 issues operation commands for various functions of the image pickup apparatus 800 under the operation of the user. The power supply unit 808 appropriately supplies various power sources serving as operating power sources for the DSP circuit 803, the frame memory 804, the display unit 805, the recording unit 806, and the operation unit 807 to these supply targets.

As described above, by using the solid-state image sensor 1 that employs any of the first to sixth configurations of the comparison circuit 51 described above as the solid-state image sensor 802, the determination speed of AD conversion can be increased while increasing the speed. Power consumption can be reduced. Therefore, even in the image pickup device 800 such as a video camera, a digital still camera, and a camera module for a mobile device such as a mobile phone, high-speed shooting and low power consumption can be realized.

In the above description, the comparison circuit 51 and the ADC 42 have been described as parts incorporated in the solid-state image sensor 1, but they can be products (comparator, AD converter) that are distributed independently.

Further, the present disclosure is applicable not only to the solid-state image sensor but also to all semiconductor devices having other semiconductor integrated circuits.

The embodiments of the present disclosure are not limited to the embodiments described above, and various modifications can be made without departing from the gist of the present disclosure.

For example, in each of the circuit configurations described above, it is possible to realize a circuit configuration in which the polarities of the transistors (NMOS transistor and MOSFET transistor) are exchanged. In that case, the control signal input to the transistor is a signal in which Hi and Low are opposite.

In each of the above-described embodiments, the reference signal REF has been described as a slope signal whose level (voltage) monotonically decreases with the passage of time, but the reference signal REF has a monotonous level (voltage) with the passage of time. It can also be an increasing slope signal.

In each of the above-described embodiments, when the ADC 42 is shared, an example in which the ADC 42 is shared by the four pixels 21 has been described, but the number of shared pixels 21 is not limited to four, and other numbers (for example,). , 8).

In addition, a form in which all or a part of the plurality of embodiments described above can be combined can be adopted. It is also possible to appropriately combine other embodiments not described in the above-described embodiment.

It should be noted that the effects described in the present specification are merely examples and are not limited, and effects other than those described in the present specification may be obtained.

The present disclosure may also have the following structure.
(1)
A differential input circuit that operates at the first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal.
It operates at a second power supply voltage lower than the first power supply voltage, and the comparison result signal representing the comparison result of the voltage of the input signal and the reference signal is inverted based on the output signal from the differential input circuit. A positive feedback circuit that speeds up the transition speed when
A voltage conversion circuit for converting the output signal of the differential input circuit into a signal corresponding to the second power supply voltage is provided.
A comparator configured such that the source voltage of the differential input circuit is a voltage lower than 0V.
(2)
The comparator according to (1), wherein the differential input circuit includes a first transistor and a second transistor constituting a current mirror, and the first transistor and the second transistor are composed of low-voltage transistors. ..
(3)
The comparator according to (2), wherein the low-voltage transistor is driven by the first power supply voltage of 2 V or less.
(4)
The differential input circuit
The third transistor to which the reference signal is input and
The fourth transistor to which the input signal is input and
The comparator according to (2) or (3) above, further comprising a fifth transistor and a sixth transistor for turning on / off the connection between the first transistor and the second transistor and the third transistor and the fourth transistor.
(5)
The positive feedback circuit receives an input of a control signal different from the output signal of the differential input circuit, and inverts the comparison result signal based on the control signal regardless of the output signal of the differential input circuit. The comparator according to any one of (1) to (4) above.
(6)
The positive feedback circuit
An inverter circuit that inverts the output signal of the differential input circuit to generate the comparison result signal, and
The comparator according to (5), further comprising a transistor that supplies the second power supply voltage to the inverter circuit based on the control signal.
(7)
The comparator according to (5) above, wherein the positive feedback circuit has a NOR circuit that receives the output signal of the differential input circuit and the control signal as inputs.
(8)
A differential input circuit that operates at the first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal.
It operates at a second power supply voltage lower than the first power supply voltage, and the comparison result signal representing the comparison result of the voltage of the input signal and the reference signal is inverted based on the output signal from the differential input circuit. A positive feedback circuit that speeds up the transition speed when
It has a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.
A comparator configured such that the source voltage of the differential input circuit is a voltage lower than 0V, and
An AD converter including a data storage unit that stores a time code when the comparison result signal is inverted.
(9)
A differential input circuit that operates at the first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal.
It operates at a second power supply voltage lower than the first power supply voltage, and the comparison result signal representing the comparison result of the voltage of the input signal and the reference signal is inverted based on the output signal from the differential input circuit. A positive feedback circuit that speeds up the transition speed when
It has a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.
A comparator configured such that the source voltage of the differential input circuit is a voltage lower than 0V, and
An AD converter including a data storage unit that stores a time code when the comparison result signal is inverted, and
A solid-state imaging device including a pixel circuit that outputs a charge signal generated by receiving light incident on a pixel and performing photoelectric conversion as the input signal to the differential input circuit.
(10)
The solid-state image sensor according to (9) above, wherein the AD converter is arranged for each pixel.
(11)
The solid-state image sensor according to (9), wherein the AD converter is shared by a plurality of the pixels.
(12)
The solid-state image sensor according to (9) or (10), which is composed of a plurality of semiconductor substrates.
(13)
A differential input circuit that operates at the first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal.
It operates at a second power supply voltage lower than the first power supply voltage, and the comparison result signal representing the comparison result of the voltage of the input signal and the reference signal is inverted based on the output signal from the differential input circuit. A positive feedback circuit that speeds up the transition speed when
It has a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.
A comparator configured such that the source voltage of the differential input circuit is a voltage lower than 0V, and
An AD converter including a data storage unit that stores a time code when the comparison result signal is inverted, and
An electronic device including a solid-state imaging device including a pixel circuit that outputs a charge signal generated by receiving light incident on a pixel and performing photoelectric conversion as the input signal to the differential input circuit.
(14)
The source of the differential input circuit is provided with a differential input circuit that operates at a first power supply voltage, a positive feedback circuit that operates at a second power supply voltage lower than the first power supply voltage, and a voltage conversion circuit. The differential input circuit of the comparator configured so that the voltage is lower than 0V outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal.
The voltage conversion circuit converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.
The transition speed when the positive feedback circuit inverts the comparison result signal representing the voltage comparison result of the input signal and the reference signal based on the output signal of the differential input circuit converted by the voltage conversion circuit. How to control the comparator to speed up.

1 Solid-state imaging device, 11 semiconductor substrate, 21 pixels, 22 pixel array unit, 23 time code transfer unit, 26 time code generator, 28 output unit, 41 pixel circuit, 42 ADC, 51 comparison circuit, 52 data storage unit, 61 Differential input circuit, 62 Voltage conversion circuit, 63 Positive feedback circuit, 71 Latch control circuit, 72 Latch storage, 81 to 86,91 transistors, 101 to 105, 161 to 163, 165,166 transistors, 800 image pickup device, 802 Solid-state imaging device

Claims (12)

A differential input circuit that operates at the first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal.
It operates at a second power supply voltage that is the same as or lower than the first power supply voltage, and represents a comparison result of the voltages of the input signal and the reference signal based on the output signal from the differential input circuit. A positive feedback circuit that speeds up the transition speed when the comparison result signal is inverted,
A voltage conversion circuit for converting the output signal of the differential input circuit into a signal corresponding to the second power supply voltage is provided.
The differential input circuit
The first and second transistors that make up the current mirror,
The third transistor to which the reference signal is input to the gate and
The fourth transistor to which the input signal is input to the gate,
The fifth transistor as a constant current source and
With the 6th transistor that outputs the output signal
Including
The first, second and sixth transistors are composed of MIMO transistors.
The third to fifth transistors are composed of NMOS transistors.
The sources of the first, second and sixth transistors are connected to the first power supply voltage of 2V or less.
The source of the fifth transistor is connected to a voltage lower than 0V and
The third transistor is connected between the drain of the first transistor and the drain of the fifth transistor.
The fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor.
The sixth transistor is a comparator configured by connecting a gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit. The differential input circuit
The comparator of claim 1, further comprising a seventh transistor and an eighth transistor for turning on and off the connection between said first and second transistors the third transistor and the fourth transistor. The positive feedback circuit receives an input of a control signal different from the output signal of the differential input circuit, and inverts the comparison result signal based on the control signal regardless of the output signal of the differential input circuit. The comparator according to claim 1. The positive feedback circuit
An inverter circuit that inverts the output signal of the differential input circuit to generate the comparison result signal, and
The comparator according to claim 3 , further comprising a transistor that supplies the second power supply voltage to the inverter circuit based on the control signal. The comparator according to claim 3 , wherein the positive feedback circuit includes a NOR circuit that receives the output signal of the differential input circuit and the control signal as inputs. A differential input circuit that operates at the first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal.
It operates at a second power supply voltage that is the same as or lower than the first power supply voltage, and represents a comparison result of the voltages of the input signal and the reference signal based on the output signal from the differential input circuit. A positive feedback circuit that speeds up the transition speed when the comparison result signal is inverted,
It has a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.
The differential input circuit
The first and second transistors that make up the current mirror,
The third transistor to which the reference signal is input to the gate and
The fourth transistor to which the input signal is input to the gate,
The fifth transistor as a constant current source and
With the 6th transistor that outputs the output signal
Including
The first, second and sixth transistors are composed of MIMO transistors.
The third to fifth transistors are composed of NMOS transistors.
The sources of the first, second and sixth transistors are connected to the first power supply voltage of 2V or less.
The source of the fifth transistor is connected to a voltage lower than 0V and
The third transistor is connected between the drain of the first transistor and the drain of the fifth transistor.
The fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor.
The sixth transistor includes a comparator configured by connecting a gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit.
An AD converter including a data storage unit that stores a time code when the comparison result signal is inverted. A differential input circuit that operates at the first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal.
It operates at a second power supply voltage that is the same as or lower than the first power supply voltage, and represents a comparison result of the voltages of the input signal and the reference signal based on the output signal from the differential input circuit. A positive feedback circuit that speeds up the transition speed when the comparison result signal is inverted,
It has a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.
The differential input circuit
The first and second transistors that make up the current mirror,
The third transistor to which the reference signal is input to the gate and
The fourth transistor to which the input signal is input to the gate,
The fifth transistor as a constant current source and
With the 6th transistor that outputs the output signal
Including
The first, second and sixth transistors are composed of MIMO transistors.
The third to fifth transistors are composed of NMOS transistors.
The sources of the first, second and sixth transistors are connected to the first power supply voltage of 2V or less.
The source of the fifth transistor is connected to a voltage lower than 0V and
The third transistor is connected between the drain of the first transistor and the drain of the fifth transistor.
The fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor.
The sixth transistor includes a comparator configured by connecting a gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit.
An AD converter including a data storage unit that stores a time code when the comparison result signal is inverted, and
A solid-state imaging device including a pixel circuit that outputs a charge signal generated by receiving light incident on a pixel and performing photoelectric conversion as the input signal to the differential input circuit. The solid-state image sensor according to claim 7 , wherein the AD converter is arranged for each pixel. The solid-state image sensor according to claim 7 , wherein the AD converter is shared by a plurality of the pixels. The solid-state image sensor according to claim 7 , which is composed of a plurality of semiconductor substrates. A differential input circuit that operates at the first power supply voltage and outputs a signal when the voltage of the input signal is higher than the voltage of the reference signal.
It operates at a second power supply voltage that is the same as or lower than the first power supply voltage, and represents a comparison result of the voltages of the input signal and the reference signal based on the output signal from the differential input circuit. A positive feedback circuit that speeds up the transition speed when the comparison result signal is inverted,
It has a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.
The differential input circuit
The first and second transistors that make up the current mirror,
The third transistor to which the reference signal is input to the gate and
The fourth transistor to which the input signal is input to the gate,
The fifth transistor as a constant current source and
With the 6th transistor that outputs the output signal
Including
The first, second and sixth transistors are composed of MIMO transistors.
The third to fifth transistors are composed of NMOS transistors.
The sources of the first, second and sixth transistors are connected to the first power supply voltage of 2V or less.
The source of the fifth transistor is connected to a voltage lower than 0V and
The third transistor is connected between the drain of the first transistor and the drain of the fifth transistor.
The fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor.
The sixth transistor includes a comparator configured by connecting a gate to the drain of the second transistor and connecting the drain to the voltage conversion circuit.
An AD converter including a data storage unit that stores a time code when the comparison result signal is inverted, and
An electronic device including a solid-state imaging device including a pixel circuit that outputs a charge signal generated by receiving light incident on a pixel and performing photoelectric conversion as the input signal to the differential input circuit. A differential input circuit that operates at a first power supply voltage, a positive feedback circuit that operates at a second power supply voltage that is equal to or lower than the first power supply voltage, and a voltage conversion circuit are provided.
The differential input circuit
The first and second transistors that make up the current mirror,
The third transistor where the reference signal is input to the gate, and
The 4th transistor where the input signal is input to the gate,
The fifth transistor as a constant current source and
With the sixth transistor that outputs the output signal of the differential input circuit
Including
The first, second and sixth transistors are composed of MIMO transistors.
The third to fifth transistors are composed of NMOS transistors.
The sources of the first, second and sixth transistors are connected to the first power supply voltage of 2V or less.
The source of the fifth transistor is connected to a voltage lower than 0V and
The third transistor is connected between the drain of the first transistor and the drain of the fifth transistor.
The fourth transistor is connected between the drain of the second transistor and the drain of the fifth transistor.
The sixth transistor has a gate connected to the drain of said second transistor, said differential input circuit of the comparator which is constructed by connecting the drain to the voltage conversion circuit, the voltage is the reference signal of the input signal Outputs a signal when it is higher than the voltage of
It said voltage conversion circuit converts the output signal, the signal corresponding to the second power supply voltage,
Transition when the positive feedback circuit, based on said output signal of said differential input circuit which has been converted by said voltage conversion circuit, the comparison result signal representative of the comparison result of the voltage of the input signal and the reference signal is inverted How to control the comparator to increase the speed.

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