JP6867594B2 - Random number generation circuit and control method of random number generation circuit - Google Patents

Description

The present invention relates to a random number generation circuit and a method for controlling the random number generation circuit.

As one of the methods for generating random numbers using a latch circuit, there is a method for utilizing the metastability (metastability) of the latch circuit. Metastability is a characteristic in which the output value becomes uncertain when sampling by a clock signal occurs when the logic level of the data signal input to the latch circuit is between the H (High) level and the L (Low) level. is there.

International Publication No. 2011/117929 Pamphlet Special Table 2005-510923 Japanese Unexamined Patent Publication No. 2012-129784

However, in the method using the metastability of the latch circuit, it is difficult to match the sampling timing with the period during which the metastability occurs (hereinafter referred to as the metastable period), and the sampling timing may deviate from the metastable period. If the sampling timing deviates from the metastable period, the output of the latch circuit may be biased to the H level or the L level, and the quality of the generated random numbers may deteriorate.

In one aspect, the present invention aims to suppress deterioration in the quality of random numbers.

In one embodiment, it receives an input signal and an adjustment signal, outputs a first signal and a second signal based on the input signal, and outputs the first signal or the adjustment signal based on the adjustment signal. The adjusting unit for adjusting the phase of the second signal, the first signal, and the second signal are received, and based on the signal level of the first signal at the sampling timing by the second signal, Upon receiving three or more odd latch circuits that output the first value or the second value, respectively, and the first value or the second value output by each of the odd latch circuits, the first value or the second value is received. When all of the odd number of latch circuits output the same value, the same value is output, and when at least one of the odd number of latch circuits outputs a different value, the first value and the first value are output. Of the two values, the output circuit that outputs the smaller number of outputs and the odd number of the first value or the second value output by each of the odd number latch circuits are received. Based on a detection circuit that outputs a detection result indicating whether or not all of the latch circuits of the above output the same value, and the detection result and the output value of the output circuit, the sampling timing is an odd number. The sampling timing is determined by determining whether or not the latch circuit is within the semi-stable state, and changing the value of the adjustment signal based on the determination result of whether or not the sampling timing is within the period. A control circuit for adjusting the above period and a random number generation circuit having the above-mentioned period are provided.

Also, in one embodiment, a method of controlling a random number generation circuit is provided.

On one aspect, deterioration of the quality of random numbers can be suppressed, and the factors that generate the generated random numbers can also be known.

It is a figure which shows an example of the random number generation circuit of 1st Embodiment. It is a figure which shows an example of the random number generation circuit of 2nd Embodiment. It is a figure which shows the relationship of an example of the output value of each latch circuit, the detection result match, and the output value RND. It is a figure which shows the adjustment example of a sampling timing. It is a flowchart which shows the flow of an example of a sampling timing adjustment process. It is a flowchart which shows an example about each process of FIG. It is a timing chart which shows an example of time change of each signal at the time of random number generation of a random number generation circuit. It is a figure which shows an example of the random number generation circuit of 3rd Embodiment. It is a figure which shows an example of the random number generation circuit of 4th Embodiment. It is a figure which shows an example of LFSR. It is a figure which shows an example of the random number generation circuit of 5th Embodiment. It is a figure which shows an example of a delay selection circuit and a capacitance circuit. It is a figure which shows the setting example of a sampling timing and the setting example of a load capacity by a load capacity variable circuit. It is a figure which shows the metastable period when the addition start timing of a load capacity is determined as shown in FIG. It is a flowchart which shows the flow of an example of the setting process of the sampling timing and the addition start timing of a load capacity. It is a flowchart which shows an example about each process of FIG. 15 (the 1). It is a flowchart which shows an example about each process of FIG. 15 (the 2). It is a figure which shows an example of the random number generation circuit of 6th Embodiment. It is a figure which shows an example of the random number generation circuit of 7th Embodiment. It is a figure which shows an example of the random number generation circuit of 8th Embodiment. It is a figure which shows an example of the random number generation circuit of 9th Embodiment.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First Embodiment)
FIG. 1 is a diagram showing an example of a random number generation circuit according to the first embodiment.

The random number generation circuit 10 includes an adjustment unit 11 having adjustment circuits 11a and 11b, an odd number generation unit 12 having three or more odd number latch circuits 12a1, 12a2, ..., 12an, an output circuit 12b, and a detection circuit 12c. It has a control circuit 13.

The adjusting unit 11 receives an input signal and an adjusting signal. Hereinafter, the input signal will be described as being the clock signal CLK, but the input signal is not limited to the clock signal CLK. However, in order to increase the generation rate of random numbers, it is desirable to use a signal in which state transitions (transitions between H level and L level) frequently occur.

The clock signal CLK is supplied from, for example, a clock signal generation circuit (not shown) outside the random number generation circuit 10.
The adjusting unit 11 outputs two signals (hereinafter referred to as a data signal dt and a clock signal clk) based on the clock signal CLK, and adjusts the phase of the data signal dt or the clock signal clk based on the adjusting signal.

In the example of FIG. 1, the adjusting unit 11 has adjustment circuits 11a and 11b. The adjustment circuit 11a outputs a data signal dt whose phase of the clock signal CLK is adjusted based on the adjustment signal tsel1. The adjustment circuit 11b outputs a clock signal clk whose phase of the clock signal CLK is adjusted based on the adjustment signal tsel2. The adjustment circuits 11a and 11b are, for example, variable delay circuits capable of changing the delay amount based on the values of the adjustment signals tsel1 and tsel2. For example, as the values of the adjustment signals tsel1 and tsel2 increase, the delay amount increases.

The latch circuits 12a1 to 12an receive the data signal dt and the clock signal clk, respectively, and output H level or L level values based on the signal level of the data signal dt at the sampling timing by the clock signal clk. The H level corresponds to, for example, the power supply voltage, and the L level corresponds to the reference potential (for example, 0V).

The output circuit 12b receives the H level value or the L level value output by each of the latch circuits 12a1 to 12an. Then, when all of the latch circuits 12a1 to 12an output the same value, the output circuit 12b outputs the value. When at least one of the latch circuits 12a1 to 12an outputs a different value, the output circuit 12b outputs the smaller number of the H level value and the L level value output by the latch circuits 12a1 to 12an. Outputs the value of.

For example, in the latch circuits 12a1 to 12an, when the H level value is output more than the L level value, the output circuit 12b outputs the L level output value RND. On the contrary, when the L level value is output more than the H level value, the output circuit 12b outputs the H level output value RND.

This is because the value with the smaller number of outputs is more likely to be a random number (or the eligibility as a random number) than the value with the larger number of outputs. The value with the larger number of outputs is likely to be the value output due to the effect of skew, not the effect of metastability. When the value output due to the influence of skew is adopted as a random number, the value is biased and the quality as a random number is low.

The detection circuit 12c receives an H level value or an L level value output by each of the latch circuits 12a1 to 12an. Then, the detection circuit 12c outputs a detection result match indicating whether or not all of the latch circuits 12a1 to 12an output the same value. In the following description, when all the latch circuits 12a1 to 12an output the same value, the H level detection result match is output, and when at least one of the latch circuits 12a1 to 12an outputs a different value, the L level is output. It is assumed that the detection result match of is output.

Circuit examples of the output circuit 12b and the detection circuit 12c will be described later.
The control circuit 13 is, for example, an electronic circuit for a specific purpose such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). Further, the control circuit 13 may be a processor as an arithmetic processing device such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). The processor executes a program stored in memory such as RAM (Random Access Memory). The control circuit 13 may be a set of a plurality of processors.

In the control circuit 13, based on the detection result match and the output value RND, the sampling timing by the clock signal clk is within the period during which the latch circuits 12a1 to 12n are in the metastability state (semi-stable state) (within the metastable period). It is determined whether or not it is. Then, the control circuit 13 changes the values of the adjustment signals tsel1 and tsel2 based on the determination result, and adjusts the sampling timing within the metastable period.

FIG. 1 shows an example of adjusting the sampling timing by the clock signal clk when the data signal dt transitions from the L level to the H level.
When the sampling timing is timing t1, the latch circuits 12a1 to 12an all output L level values, so that the output circuit 12b outputs the L level output value RND and the detection circuit 12c outputs the H level detection result. Output the match. At this time, the control circuit 13 determines that the sampling timing is not within the metastable period, and changes the values of the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk with respect to the data signal dt. For example, the control circuit 13 delays the phase of the clock signal clk by fixing the value of the adjustment signal tsel1, increasing the value of the adjustment signal tsel2, and increasing the delay amount of the clock signal clk in the adjustment circuit 11b.

It is assumed that the sampling timing becomes, for example, timing t2 by delaying the phase of the clock signal clk. At the timing t2, it is assumed that the signal level of the data signal dt is higher than that at the L level, and at least one of the latch circuits 12a1 to 12an outputs the H level value. At this time, the L level detection result match is output from the detection circuit 12c. However, since the latch circuits 12a1 to 12an still output more L-level values than the H-level values, the output circuit 12b outputs the H-level output value RND. Also at this time, the control circuit 13 determines that the sampling timing is not within the metastable period, and changes the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk with respect to the data signal dt.

It is assumed that the sampling timing becomes, for example, the timing t3 by further delaying the phase of the clock signal clk. At the timing t3, the signal level of the data signal dt is near the middle between the L level and the H level, and among the latch circuits 12a1 to 12an, the one that outputs the L level value and the one that outputs the H level value are almost the same. Divide evenly. Therefore, the output circuit 12b outputs the L level output value RND and the H level output value RND with almost the same probability. Further, the detection circuit 12c outputs an L-level detection result match.

As described above, when the control circuit 13 changes the sampling timing in the order of timing t1, t2, t3, at timing t3, the same output value RND and detection result match as timing t2 can be obtained. There is. In that case, the control circuit 13 further delays the phase of the clock signal clk, and when the output value RND changes from the H level to the L level (for example, timing t4), the timing immediately before that (that is, timing t3) is changed. Judge that it is within the metastable period. Then, the control circuit 13 fixes the values of the adjustment signals tsel1 and tsel2 at the timing t3.

On the other hand, when the sampling timing is the timing t5, the latch circuits 12a1 to 12an all output the H level value. Therefore, the output circuit 12b is the H level output value RND, and the detection circuit 12c is the H level detection result match. Is output. At this time, the control circuit 13 determines that the sampling timing is not within the metastable period, and changes the adjustment signals tsel1 and tsel2 so as to advance the phase of the clock signal clk with respect to the data signal dt. For example, the control circuit 13 advances the phase of the clock signal clk by fixing the value of the adjustment signal tsel1, reducing the value of the adjustment signal tsel2, and reducing the delay amount of the clock signal clk in the adjustment circuit 11b.

It is assumed that the sampling timing becomes, for example, the timing t4 by advancing the phase of the clock signal clk. At the timing t4, the signal level of the data signal dt is lower than that at the H level, and it is assumed that at least one of the latch circuits 12a1 to 12an outputs the L level value. At this time, the detection circuit 12c outputs an L-level detection result match. However, since the latch circuits 12a1 to 12an still output more H-level values than the L-level values, the output circuit 12b outputs the L-level output value RND. Also at this time, the control circuit 13 determines that the sampling timing is not within the metastable period, and changes the adjustment signals tsel1 and tsel2 so as to advance the phase of the clock signal clk with respect to the data signal dt.

It is assumed that the sampling timing becomes, for example, the timing t3 by advancing the phase of the clock signal clk. At the timing t3, as described above, the output circuit 12b outputs the L level output value RND and the H level output value RND with almost the same probability. Further, the detection circuit 12c outputs an L-level detection result match.

When the control circuit 13 changes the sampling timing in the order of timings t5, t4, and t3, at timing t3, the same output value RND and detection result match as at timing t4 may be obtained. In that case, for example, when the phase of the clock signal clk is further advanced and the output value RND changes from the L level to the H level (timing t2), the timing immediately before that (that is, timing t3) is set. , Judge that it is within the metastable period. Then, the control circuit 13 fixes the values of the adjustment signals tsel1 and tsel2 at the timing t3.

Then, after that, the control circuit 13 supplies the fixed values of the adjustment signals tsel1 and tsel2 to the adjustment unit 11, and causes the random number generation unit 12 to generate a random number by metastability.
Examples of other adjustment methods for sampling timing will be described later.

As described above, in the random number generation circuit 10 and its control method of the first embodiment, the sampling timing is within the metastable period based on the output value RND obtained from the outputs of the latch circuits 12a1 to 12an and the detection result match. It can be determined whether or not it is. That is, the control circuit 13 can determine whether or not the latch circuits 12a1 to 12an are in the metastability state. Then, the control circuit 13 can adjust the phase of the data signal dt or the clock signal clk based on the determination result, and adjust the sampling timing to the metastable period.

In the metastable period, as described above, the H level output value RND and the L level output value RND are output with almost the same probability, and the output value RND becomes a high-quality random number. That is, the bias of the output value RND value is reduced, and the deterioration of the quality of the random number can be suppressed.

As a method of generating a random number using a latch circuit, there is a method of inputting an output pulse of a ring oscillator to a data terminal of a latch circuit, inputting a clock signal to a clock terminal, and generating a random number from the jitter of the output pulse. .. However, in this method, since the random number at the time of sampling has a dependency relationship with the immediately preceding sampling value, the generated random number includes periodicity. In the random number generation circuit 10 of the present embodiment utilizing metastability, the random numbers do not include periodicity.

(Second Embodiment)
FIG. 2 is a diagram showing an example of a random number generation circuit according to the second embodiment.
The random number generation circuit 20 includes adjustment circuits 21a and 21b, a random number generation unit 22, and a control circuit 23.

The adjustment circuits 21a and 21b have the same functions as the adjustment circuits 11a and 11b in the random number generation circuit 10 of the first embodiment.
The random number generation unit 22 includes a latch circuit 22a1,22a2, 22a3, an inverter circuit 22b1,22b2,22b3, an AND (logical product) circuit 22c1,22c2, 22c3, 22c4,22c5, and an OR (logical sum) circuit 22d1,22d2.

The latch circuits 22a1 to 22a3 are a data terminal (denoted as "D") that receives a data signal dt, a clock terminal (denoted as "CK") that receives a clock signal clk, and an output terminal ("Q", respectively. ”). The latch circuits 22a1 to 22a3 have the same functions as the latch circuits 12a1 to 12an in the random number generation circuit 10 of the first embodiment.

In the random number generation circuit 20 of the second embodiment, the output circuit 12b and the detection circuit in the random number generation circuit 10 of the first embodiment are provided by the inverter circuits 22b1 to 22b3, the AND circuits 22c1 to 22c5, and the OR circuits 22d1,22d2. The same function as 12c is realized.

The inverter circuit 22b1 inverts the logic level of the output value of the latch circuit 22a1, the inverter circuit 22b2 inverts the logic level of the output value of the latch circuit 22a2, and the inverter circuit 22b3 inverts the logic level of the output value of the latch circuit 22a3. Invert.

The AND circuit 22c1 outputs the operation result of the logical product of the output value of the latch circuit 22a1, the output value of the inverter circuit 22b2, and the output value of the inverter circuit 22b3. The AND circuit 22c2 outputs the operation result of the logical product of the output value of the latch circuit 22a2, the output value of the inverter circuit 22b1, and the output value of the inverter circuit 22b3. The AND circuit 22c3 outputs the operation result of the logical product of the output value of the latch circuit 22a3, the output value of the inverter circuit 22b1, and the output value of the inverter circuit 22b2. The AND circuit 22c4 outputs the calculation result of the logical product of the output values of the latch circuits 22a1 to 22a3. The AND circuit 22c5 outputs the calculation result of the logical product of the output values of the inverter circuits 22b1 to 22b3.

The OR circuit 22d1 outputs the calculation result of the logical sum of the output values of the AND circuits 22c1 to 22c4. The OR circuit 22d2 outputs the calculation result of the logical sum of the output values of the AND circuits 22c4 and 22c5.

The output value of the OR circuit 22d1 is the output value RND of the random number generation unit 22, and the output value of the OR circuit 22d2 is a detection result match indicating whether or not all of the latch circuits 22a1 to 22a3 output the same value.

The control circuit 23 has the same function as the control circuit 13 in the random number generation circuit 10 of the first embodiment. The control circuit 23 may be controlled from the outside of the random number generation circuit 20 by the control signal CTRL. Further, the control circuit 23 may output a signal ERR indicating an abnormal state when the output value RND is the same value as the predetermined number of cycles of the clock signal CLK.

FIG. 3 is a diagram showing an example relationship between the output value of each latch circuit, the detection result match, and the output value RND.
FIG. 3 shows the relationship between the output values of the latch circuits 22a1 to 22a3, the output value RND of the OR circuit 22d1, and the detection result match output by the OR circuit 22d2.

When all the output values of the latch circuits 22a1 to 22a3 are L level, the detection result match becomes H level and the output value RND becomes L level. When two of the output values of the latch circuits 22a1 to 22a3 are L level and one is H level, the detection result match is L level and the output value RND is H level. When two of the output values of the latch circuits 22a1 to 22a3 are H level and one is L level, the detection result match becomes L level and the output value RND becomes L level. When all the output values of the latch circuits 22a1 to 22a3 are H level, the detection result match becomes H level and the output value RND becomes H level.

The control circuit 23 can determine a random number generation factor based on the output value RND based on the combination of these detection result matches and the output value RND. In the following, a case where the sampling timing is adjusted within the metastable period when the data signal dt transitions from the L level to the H level will be described.

When the detection result match is H level and the output value RND is L level, it means that the phase of the clock signal clk is advanced with respect to the data signal dt due to skew, and the sampling timing is not within the metastable period. Therefore, the random number generation factor is not metastability but skew. Skew is a variation in delay time caused by noise due to voltage change or temperature change. When the output value RND as described above is obtained for each sampling timing, the output value RND is biased toward the L level value, and a random number having poor quality is obtained. Therefore, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2 (either of them may be used) so as to delay the phase of the clock signal clk with respect to the data signal dt.

When the detection result match is H level and the output value RND is H level, it means that the phase of the clock signal clk is delayed with respect to the data signal dt due to skew, and the sampling timing is not within the metastable period. Therefore, the random number generation factor is not metastability but skew. When the output value RND as described above is obtained for each sampling timing, the output value RND is biased toward the H level value, and a random number having poor quality is obtained. Therefore, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2 (either of them may be used) so as to advance the phase of the clock signal clk.

When the detection result match is L level and the output value RND is L level or H level, the output value RND is affected by skew or metastability. That is, the random number generation factor is skew or metastability.

In order to make the random number generation factor metastability, the control circuit 23 adjusts the sampling timing as follows, for example.
FIG. 4 is a diagram showing an example of adjusting the sampling timing.

FIG. 4 shows four examples of adjusting the sampling timing when the data signal dt transitions from the L level to the H level. Further, in the example of FIG. 4, the period ta when the signal level of the data signal dt is equal to or less than the voltage V1, the period tb when the signal level of the data signal dt is larger than the voltage V1 and less than the voltage V2, and the signal level of the data signal dt are The period tc during which the voltage is V2 or more and the voltage V3 or less is shown. Further, a period dt in which the signal level of the data signal dt is larger than the voltage V3 and less than the voltage V4 and a period te in which the signal level of the data signal dt is equal to or higher than the voltage V4 are shown. The voltages V1 to V4 are determined according to, for example, the characteristics of the latch circuits 22a1 to 22a3. The periods ta to te are determined according to, for example, the voltages V1 to V4 and the load capacitance of the data terminals of the latch circuits 22a1 to 22a3.

When the sampling timing is located within the period ta, the output values of the latch circuits 22a1 to 22a3 are all L level. When the sampling timing is located within the period tb, the output values of the latch circuits 22a1 to 22a3 are likely to be at the L level, but due to metastability, at least one output value of the latch circuits 22a1 to 22a3 is at the H level. May become. When the sampling timing is located within the period ct, the latch circuits 22a1 to 22a3 output the H level output value and the L level output value with almost the same probability due to the metastability. When the sampling timing is located within the period dt, the output value of the latch circuits 22a1 to 22a3 is likely to be H level, but due to metastability, at least one output value of the latch circuits 22a1 to 22a3 is set to L level. May become. When the sampling timing is located within the period te, the output values of the latch circuits 22a1 to 22a3 are all H level.

Of the periods ta to ct, the period suitable for generating high-quality random numbers is the period ct in which the latch circuits 22a1 to 22a3 are in the metastability state. Therefore, the control circuit 23 sets the period ct as the target period (setting target period) for setting the sampling timing, and adjusts the sampling timing by, for example, the following four timing setting methods.

(Method 1) When the sampling timing is within the period ta, the detection result match is H level and the output value RND is L level. In that case, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2, and sets the timing for delaying the phase of the clock signal clk with respect to the data signal dt.

It is desirable to make the amount of phase changed by one timing setting smaller in order to properly adjust the sampling timing to the set target period, but if it is made too small, the adjustment time becomes long.

The control circuit 23 stores the values of the adjustment signals tsel1 and tsel2 used in at least one previous timing setting in a storage unit (for example, a register) (not shown).

By delaying the phase of the clock signal clk, when the detection result match changes to the L level and the output value RND changes to the H level, the control circuit 23 further changes the values of the adjustment signals tsel1 and tsel2 to the data signal dt. On the other hand, the phase of the clock signal clk is delayed. This is because when the detection result match is the L level and the output value RND is the H level, the sampling timing may be within the period tc, which is the set target period, but may also be within the period tb.

By delaying the phase of the clock signal clk, when the detection result match changes to the L level and the output value RND changes to the L level, it means that the sampling timing is within the period tk or the period td. Therefore, the control circuit 23 accurately sets each subsequent sampling timing by using the values of the adjustment signals tsel1 and tsel2 used in the timing setting immediately before the timing setting performed this time. It can be adjusted to the target period.

(Method 2) In method 2, for example, in method 1, by delaying the phase of the clock signal clk, the detection result match does not change to the L level and the output value RND does not change to the L level, and the detection result match becomes the H level. , It is performed when the output value RND changes to the H level.

The control circuit 23 stores in the storage unit the values of the adjustment signals tsel1 and tsel2 when the detection result match changes to the H level and the output value RND changes to the H level. Then, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2, and advances the phase of the clock signal clk with respect to the data signal dt until the detection result match changes to the H level and the output value RND changes to the L level. The control circuit 23 stores the values of the adjustment signals tsel1 and tsel2 in the storage unit when the detection result match changes to the H level and the output value RND changes to the L level.

The control circuit 23 sets the values of the adjustment signals tsel1 and tsel2 at the timing when the detection result match becomes H level and the output value RND becomes L level and the timing when the detection result match becomes H level and the output value RND becomes H level. Obtained from the storage unit. Then, the control circuit 23 obtains the values of the adjustment signals tsel1 and tsel2 for adjusting the sampling timing to an intermediate timing between the two timings based on the acquired values. For example, the control circuit 23 obtains the values of the adjustment signals tsel1 and tsel2 that adjust the sampling timing to the intermediate timing of both timings by obtaining the average of the values of the adjustment signals tsel1 and tsel2 at both timings.

Then, the control circuit 23 supplies the obtained values of the adjustment signals tsel1 and tsel2 to the adjustment circuits 21a and 21b thereafter, so that each subsequent sampling timing becomes a timing substantially at the center of the periods tb to td. That is, the sampling timing can be adjusted within the set target period, which is the metastable period.

(Method 3) When the sampling timing in the initial state is within the period te, the detection result match is H level and the output value RND is H level. In that case, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2, and sets the timing for advancing the phase of the clock signal clk with respect to the data signal dt.

By advancing the phase of the clock signal clk, when the detection result match changes to the L level and the output value RND changes to the L level, the control circuit 23 further changes the values of the adjustment signals tsel1 and tsel2, and the data signal dt The phase of the clock signal clk is advanced with respect to. This is because when the detection result match is the L level and the output value RND is the L level, the sampling timing may be within the period tk, which is the set target period, but may also be within the period td.

By advancing the phase of the clock signal clk, when the detection result match changes to the L level and the output value RND changes to the H level, it means that the sampling timing is within the period tk or the period tb. Therefore, the control circuit 23 accurately sets each subsequent sampling timing by using the values of the adjustment signals tsel1 and tsel2 used in the timing setting immediately before the timing setting performed this time. It can be adjusted to the target period.

(Method 4) In the method 4, for example, in the method 3, by advancing the phase of the clock signal clk, the detection result match does not change to the L level and the output value RND does not change to the H level, and the detection result match becomes the H level. , This is performed when the output value RND changes to the L level.

The control circuit 23 stores in the storage unit the values of the adjustment signals tsel1 and tsel2 when the detection result match changes to the H level and the output value RND changes to the L level. Then, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2, and delays the phase of the clock signal clk with respect to the data signal dt until the detection result match changes to the H level and the output value RND changes to the H level. The control circuit 23 stores the values of the adjustment signals tsel1 and tsel2 in the storage unit when the detection result match changes to the H level and the output value RND changes to the H level.

The control circuit 23 sets the values of the adjustment signals tsel1 and tsel2 at the timing when the detection result match becomes H level and the output value RND becomes H level and the timing when the detection result match becomes H level and the output value RND becomes L level. Obtained from the storage unit. Then, the control circuit 23 obtains the values of the adjustment signals tsel1 and tsel2 for adjusting the sampling timing to an intermediate timing between the two timings based on the acquired values. For example, the control circuit 23 obtains the values of the adjustment signals tsel1 and tsel2 that adjust the sampling timing to the intermediate timing of both timings by obtaining the average of the values of the adjustment signals tsel1 and tsel2 at both timings.

Then, the control circuit 23 supplies the obtained values of the adjustment signals tsel1 and tsel2 to the adjustment circuits 21a and 21b thereafter, so that each subsequent sampling timing becomes a timing substantially at the center of the periods tb to td. That is, the sampling timing can be adjusted within the set target period, which is the metastable period.

Hereinafter, the flow of the process of adjusting the sampling timing using the above four methods will be described with a flowchart.
FIG. 5 is a flowchart showing a flow of an example of sampling timing adjustment processing.

The control circuit 23 supplies the initial values of the adjustment signals tsel1 and tsel2 to the adjustment circuits 21a and 21b to initialize the adjustment circuits 21a and 21b (step S1).
After that, the control circuit 23 detects the detection result match and the output value RND output from the random number generation unit 22 using the data signal dt and the clock signal clk output from the adjustment circuits 21a and 21b in the initial state. Then, the control circuit 23 determines the period including the sampling timing from the detection result match and the output value RND (step S2).

Then, the control circuit 23 sets the timing according to the method 1 or the method 3 shown in FIG. 4 according to the determined period (step S3).
The control circuit 23 determines whether or not the sampling timing can be set within the metastable period by the timing setting according to the method 1 or the method 3 (step S4). When the control circuit 23 determines that the above setting is possible, the control circuit 23 ends the adjustment process.

When the control circuit 23 determines that the above setting is not possible, the control circuit 23 sets the timing according to the method 2 or the method 4 shown in FIG. 4 (step S5), and ends the adjustment process.
FIG. 6 is a flowchart showing an example of each process of FIG.

As an example of the initialization process of step S1 of FIG. 5, the control circuit 23 supplies the initial values of the adjustment signals tsel1 and tsel2 to the adjustment circuits 21a and 21b, and sets the offset delay in the adjustment circuits 21a and 21b (step S10). ). As a result, the data signal dt and the clock signal clk become signals delayed by the offset delay with respect to the clock signal CLK.

As an example of the process of step S2 in FIG. 5, the following process is performed.
The adjustment circuits 21a and 21b receive the clock signal CLK, and the latch circuits 22a1 to 22a3 take in the data signal dt output by the adjustment circuit 21a at the sampling timing by the clock signal clk output by the adjustment circuit 21b (step S11).

The control circuit 23 determines a period including the sampling timing from the detection result match output by the random number generation unit 22 and the output value RND (step S12). When the detection result match is H level and the output value RND is L level, the control circuit 23 determines that the sampling timing is within the period ta shown in FIG. 4, and performs the process of step S14.

When the detection result match is L level and the output value RND is L level or H level, the control circuit 23 determines that the sampling timing is within the period tb to td shown in FIG. In that case, the control circuit 23 adjusts the sampling timing by changing the values of the adjustment signals tsel1 and tsel2 so that the sampling timing moves within the period ta (step S13).

When the detection result match is H level and the output value RND is H level, the control circuit 23 determines that the sampling timing is within the period te shown in FIG. In that case, the timing is set by the method 3 or the method 4 shown in FIG. 4, but the illustration is omitted in FIG.

As an example of the processing of steps S3 and S4 of FIG. 5, the following processing is performed.
The control circuit 23 changes the values of the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk with respect to the data signal dt (step S14).

Then, the adjustment circuits 21a and 21b receive the clock signal CLK, and the latch circuits 22a1 to 22a3 take in the data signal dt output by the adjustment circuit 21a at the sampling timing by the clock signal clk output by the adjustment circuit 21b (step S15). ..

Then, the control circuit 23 determines whether or not the detection result match is at the L level and the output value RND is at the L level (step S16).
When the detection result match is the L level and the output value RND is the L level, the sampling timing can be set within the metastable period by the timing setting of the method 1 of FIG. In this case, the control circuit 23 sets the values of the adjustment signals tsel1 and tsel2 used in the previous timing setting (step S17), and ends the adjustment process. The values of the adjustment signals tsel1 and tsel2 set in the process of step S17 are stored in the storage unit, for example, and the stored values are continuously set in the adjustment circuits 21a and 21b thereafter.

When it is determined in the process of step S16 that at least one of the detection result match and the output value RND is H level, the control circuit 23 determines whether the detection result match is H level and the output value RND is H level. Whether or not it is determined (step S18). When at least one of the detection result match and the output value RND is at the L level, the process from step S14 is repeated.

When it is determined in the process of step S18 that both the detection result match and the output value RND are H level, the sampling timing cannot be set within the metastable period by the timing setting of the method 1 of FIG. In that case, the following processing is performed as an example of the processing in step S5 of FIG.

The control circuit 23 stores the values of the adjustment signals tsel1 and tsel2 used for timing setting when both the detection result match and the output value RND reach the H level in the storage unit (step S19).

After that, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2 so as to advance the phase of the clock signal clk with respect to the data signal dt (step S20).
Then, the adjustment circuits 21a and 21b receive the clock signal CLK, and the latch circuits 22a1 to 22a3 take in the data signal dt output by the adjustment circuit 21a at the sampling timing by the clock signal clk output by the adjustment circuit 21b (step S21). ..

Then, the control circuit 23 determines whether or not the detection result match is at the H level and the output value RND is at the L level (step S22). When the detection result match is L level or the output value RND is H level, the processing from step S20 is repeated.

When the detection result match is H level and the output value RND is L level, the control circuit 23 stores the values of the adjustment signals tsel1 and tsel2 used for the timing setting at that time in the storage unit (step S23). ).

Then, the control circuit 23 acquires the values of the adjustment signals tsel1 and tsel2 stored in the processes of steps S19 and S23 from the storage unit. Then, based on the acquired values, the values of the adjustment signals tsel1 and tsel2 that adjust the sampling timing to the middle of each timing in which the determination process of steps S18 and S22 is “YES” are obtained. Then, the control circuit 23 sets the values of the obtained adjustment signals tsel1 and tsel2 in the adjustment circuits 21a and 21b (step S24). Then, the control circuit 23 ends the adjustment process. The values of the adjustment signals tsel1 and tsel2 set in the process of step S24 are stored in the storage unit, for example, and the stored values are continuously set in the adjustment circuits 21a and 21b thereafter.

Although not shown in FIG. 6, when the period including the sampling timing is determined to be the period te in the process of step S12, steps S14, S16, S18, S20, and S22 of steps S14 to S24 are described below. The changed process is performed as follows.

First, the control circuit 23 performs a process of changing the adjustment signals tsel1 and tsel2 so as to advance the phase of the clock signal clk with respect to the data signal dt, instead of the process of step S14.

Further, the control circuit 23 performs a process of determining whether or not the detection result match is the L level and the output value RND is the H level, instead of the process of step S16. When the detection result match is the L level and the output value RND is the H level, the control circuit 23 performs the process of step S17.

When the detection result match is H level or the output value RND is L level, the control circuit 23 determines whether the detection result match is H level and the output value RND is L level instead of the processing in step S18. Performs a process of determining whether or not. When the detection result match is H level and the output value RND is L level, the control circuit 23 performs the process of step S19.

When the detection result match is L level or the output value RND is H level, the control circuit 23 changes the adjustment signals tsel1 and tsel2 so as to advance the phase of the clock signal clk with respect to the above data signal dt. repeat.

Further, instead of the process of step S20, the control circuit 23 performs a process of changing the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk with respect to the data signal dt.

Further, the control circuit 23 determines whether or not both the detection result match and the output value RND are at the H level, instead of the processing in step S22. When both the detection result match and the output value RND are H level, the control circuit 23 performs the process of step S23. When at least one of the detection result match and the output value RND is at the L level, the control circuit 23 repeats the process of changing the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk.

FIG. 7 is a timing chart showing an example of time change of each signal at the time of random number generation of the random number generation circuit.
In FIG. 7, clock signals CLK, clk, data signal dt, output values of latch circuits 22a1 to 22a3, detection result match, output value RND, random number generation factor, control signal CTRL, adjustment signals tsel1, tsel2, and signal ERR times are shown. An example of change is shown. In FIG. 7, the output values of the latch circuits 22a1 to 22a3 are schematically shown collectively.

By adjusting the phase of the clock signal CLK by the adjustment circuits 21a and 21b, the clock signal clk and the data signal dt are generated. Then, the sampling timing by the clock signal clk is adjusted within the metastable period by the method shown in FIGS. 4 to 6, so that the output values of the latch circuits 22a1 to 22a3 become H after a period of indefiniteness. It is a level or L level value.

The detection result match and the output value RND also become H level or L level values after an indefinite period depending on the change in the output value of the latch circuits 22a1 to 22a3. The random number generation factor becomes metastability by adjusting the sampling timing by the clock signal clk within the metastable period as described above.

The control signal CTRL does not change when the random number is generated. Further, in FIG. 7, changes in the adjustment signals tsel1 and tsel2 during the adjustment of the sampling timing are not shown, but the control circuit 23 does not change the adjustment signals tsel1 and tsel2 after the adjustment of the sampling timing. Further, the control circuit 23 sets the signal ERR to the L level when the random number generation factor is metastability, and sets the signal ERR to the H level when the random number generation factor is skew.

The control circuit 23 may set the signal ERR to the H level and notify the outside that it is in an abnormal state when the output value RND is the same value as the predetermined number of cycles of the clock signal CLK.

As described above, the control circuit 23 can make the random number generation factor metastability by adjusting the sampling timing within the period ct, which is the metastable period, based on the detection result match and the output value RND. Therefore, the output value RND shown in FIG. 7 is a high-quality random number with reduced value bias and the like.

(Third Embodiment)
FIG. 8 is a diagram showing an example of a random number generation circuit according to the third embodiment. In FIG. 8, the same elements as those of the random number generation circuit 20 of the second embodiment shown in FIG. 2 are designated by the same reference numerals.

The random number generation circuit 30 of the third embodiment makes the delay amount of the clock signal clk supplied to each of the random number generation units 30a0, 30a1, ..., 30ai, ..., 30an and the random number generation units 30a to 30an different. It has delay circuits 30b1, 30b2, ..., 30bn.

The random number generation unit 30a0 includes an ExOR (exclusive OR) circuit 31a0 in addition to the elements included in the random number generation unit 22 of the random number generation circuit 20 of the second embodiment. The ExOR circuit 31a0 outputs the calculation result of the exclusive OR of the output value of the OR circuit 22d1 and the input value R0 supplied from the control circuit 30c. The output value of the ExOR circuit 31a0 is supplied to the ExOR circuit 31a1 of the random number generation unit 30a1 in the subsequent stage instead of the input value R0.

At the time of random number generation, the input value R0 is fixed to either the H level or the L level. At the time of testing the random number generation circuit 30, the input value R0 may be changed.
The other random number generation units 30a1 to 30an have the same circuit as the random number generation units 30a0.

In such a random number generation circuit 30, the output value of the ExOR circuit 31an of the random number generation unit 30an at the final stage becomes the output value RND. Further, each of the random number generation units 30a to 30an controls the detection result match output by the random number generation unit 22 of the random number generation circuit 20 of the second embodiment, the detection result corresponding to the output value RND, and the output value in the control circuit 30c. Supply to. For example, the random number generation unit 30a0 supplies the detection result match0 and the output value RND0 to the control circuit 30c.

The control circuit 30c is, for example, based on the detection result matchi and the output value RNDi supplied from the random number generation unit 30ai in which the delay with respect to the clock signal clk is an intermediate value among the random number generation units 30a to 30an. Determine the value of tsel2. The values of the adjustment signals tsel1 and tsel2 are determined by the methods shown in FIGS. 4 to 6 so that the sampling timing by the clock signal clk reaching the random number generation unit 30ai is within the metastable period.

In the random number generation circuit 30, by appropriately setting the delay time by the delay circuits 30b1 to 30bn, even if skew occurs due to a change in operating conditions or the like, the sampling timing in any of the random number generation units 30a to 30an is the metastable period. Increased chances of being inside. That is, the probability of random number generation due to metastability can be increased.

(Fourth Embodiment)
FIG. 9 is a diagram showing an example of a random number generation circuit according to the fourth embodiment. In FIG. 9, the same elements as those of the random number generation circuit 30 of the third embodiment shown in FIG. 8 are designated by the same reference numerals.

The random number generation circuit 40 of the fourth embodiment has an LFSR (Linear Feedback Shift Register) 41 having an input terminal in, a clock terminal ck, and an output terminal out.
The clock signal CLK is supplied to the clock terminal ck, and the output value of the ExOR circuit 31an of the random number generator 30an is supplied to the input terminal in. An output value RND which is a random number or a pseudo-random number is output from the output terminal out.

FIG. 10 is a diagram showing an example of LFSR.
The LFSR41 has a 16-bit shift register 41a and an ExOR circuit 41b, 41c, 41d, 41e.

The 16-bit shift register 41a captures the output value of the ExOR circuit 41b at a timing synchronized with the clock signal CLK supplied to the clock terminal ck. Then, the 16-bit shift register 41a shifts from "bit0" to "bit15" one bit at a time in synchronization with the clock signal CLK. Each of "bit0" to "bit15" represents a register.

The ExOR circuit 41b outputs the calculation result of the exclusive OR of the output value RNDn supplied to the input terminal in and the output value (feedback signal) of the ExOR circuit 41e. The ExOR circuit 41c outputs the operation result of the exclusive OR of the output value of the register represented by "bit13" and the output value of the register represented by "bit15". The ExOR circuit 41d outputs the calculation result of the exclusive OR of the output value of the register represented by "bit12" and the output value of the ExOR circuit 41c. The ExOR circuit 41e supplies the calculation result of the exclusive OR of the output value of the register represented by "bit10" and the output value of the ExOR circuit 41d to the ExOR circuit 41b as a feedback signal.

By the way, the LFSR that inputs the output value of the ExOR circuit 41e to the 16-bit shift register 41a without having the ExOR circuit 41b outputs a pseudo-random number having periodicity.
On the other hand, in the LFSR41 shown in FIG. 10, the output value of the ExOR circuit 31an of the random number generation unit 30an is supplied to one input terminal of the ExOR circuit 41b. During the period of the pseudo-random number, the output value becomes a random number due to metastability, so that the output value RND output by the LFSR41 becomes a random number having no periodicity. That is, it is possible to prevent the output value RND from becoming a pseudo-random number. Therefore, a high quality random number can be output.

Further, in the random number generation circuit 30 of the third embodiment, there is a possibility that a random number due to metastability is not output in each cycle of the clock signal CLK, but the random number generation circuit 40 having the LFSR41 as described above is a clock signal. Random numbers can be output in each cycle of CLK. That is, the random number generation rate can be improved.

If the output value RND output by the LFSR41 is the same as the predetermined number of cycles of the clock signal CLK, the control circuit 30c sets the signal ERR to the H level and notifies the outside that it is in an abnormal state. Good. Further, the control circuit 30c detects whether or not the output value of the random number generation unit 30an supplied to the input terminal in of the LFSR41 changes, and when the output value is the same value as the predetermined number of cycles of the clock signal CLK. The signal ERR may be set to H level.

Further, the random number generation circuit 20 of the second embodiment and the LFSR41 may be combined to supply the output value of the random number generation unit 22 to the input terminal in of the LFSR41.
Further, the above-mentioned LFSR41 is an example, and is not limited to the circuit configuration of FIG. For example, various modifications are possible, such as using a 32-bit shift register instead of the 16-bit shift register 41a.

(Fifth Embodiment)
By the way, the longer the metastable period, the easier it is to match the sampling timing. Further, even if the clock signal clk and the data signal dt are skewed due to temperature, voltage noise, or the like, if the metastable period is long, the possibility that the sampling timing can be maintained within the metastable period increases.

In the following, a random number generation circuit capable of expanding the metastable period will be described. The random number generation circuit of the fifth embodiment shown below can also be combined with the random number generation circuits 10, 20, 30, and 40 of the first to fourth embodiments described above. It will be described later.

FIG. 11 is a diagram showing an example of a random number generation circuit according to the fifth embodiment.
The random number generation circuit 50 includes an adjustment unit 51 having adjustment circuits 51a and 51b, a load capacitance variable circuit 52, a latch circuit 53, and a control circuit 54.

The adjusting unit 51 has the same function as the adjusting unit 11 in the random number generation circuit 10 of the first embodiment. In the following, the input signal will be described as being the clock signal CLK, but the input signal is not limited to the clock signal CLK.

The adjusting unit 51 outputs the data signal dt and the clock signal clk based on the clock signal CLK, and adjusts the phase of at least one of the data signal dt and the clock signal clk based on the adjusting signals tsel1 and tsel2.

The load capacitance variable circuit 52 gradually increases the load capacitance of the terminal to which the data signal dto is supplied in the latch circuit 53 from the start timing determined based on the selection signal csel supplied from the control circuit 54. The load capacitance variable circuit 52 includes a buffer 52a, a delay selection circuit 52b, and a capacitance circuit 52c1 to 52cn.

The buffer 52a blunts the waveform of the data signal dt and outputs the data signal dt with the data signal dt delayed.
The delay selection circuit 52b enables the capacitance circuits 52c1 to 52cn and adds a load capacitance at a timing based on the data signal dt and the selection signal csel.

The capacitive circuits 52c1 to 52cn are connected to the wiring through which the data signal dto propagates and are enabled or disabled by the delay selection circuit 52b.
The latch circuit 53 receives the data signal dto and the clock signal clk, and outputs an H level or L level output value RND based on the signal level of the data signal dto at the sampling timing by the clock signal clk.

The control circuit 54 is, for example, an electronic circuit for a specific purpose such as an ASIC or FPGA. Further, the control circuit 54 may be a processor as an arithmetic processing device such as a CPU or DSP. The processor executes a program stored in a memory such as RAM. The control circuit 54 may be a set of a plurality of processors.

The control circuit 54 outputs the adjustment signals tsel1 and tsel2 and the selection signal csel based on the output value RND. Further, the control circuit 54 may be controlled from the outside of the random number generation circuit 50 by the control signal CTRL. Further, the control circuit 54 may output a signal ERR indicating an abnormal state when the output value RND is the same value as the predetermined number of cycles of the clock signal CLK.

FIG. 12 is a diagram showing an example of a delay selection circuit and a capacitance circuit.
The delay selection circuit 52b includes delay circuits 60a1, 60a2, ..., 60am, selection circuits 60b, delay circuits 60c1 to 60c (n-1), OR circuits 60d1, 60d2, ..., 60dn, AND circuits 60e1, 60e2, ..., 60en. Has.

The delay circuits 60a1 to 60am are connected in series, and a data signal dt is supplied to the head delay circuit 60a1. The data signal dt delayed by each of the delay circuits 60a1 to 60am is supplied to the selection circuit 60b as the data signals dt1 to dtm.

The selection circuit 60b selects any one of the data signals dt, dt1 to dtm based on the signals ct0, ct1, ..., Ctm and outputs the data signals dts. The signals ct0 to ctm are signals included in the selection signal csel.

The delay circuits 60c1 to 60c (n-1) are connected in series, and a data signal dts is supplied to the head delay circuit 60c1. The data signals dts delayed in each of the delay circuits 60c1 to 60c (n-1) are supplied to one input terminal of the OR circuits 60d2 to 60dn.

A data signal dts is supplied to one input terminal of the OR circuit 60d1. A signal cton is supplied to the other input terminal of the OR circuits 60d1 to 60dn. The output signals of the OR circuits 60d1 to 60dn are supplied to one input terminal of the AND circuits 60e1 to 60en.

A signal ctoff is supplied to the other input terminal of the AND circuits 60e1 to 60en. The output signals of the AND circuits 60e1 to 60en are supplied to the capacitance circuits 52c1 to 52cn. The signals cton and ctoff are signals included in the selection signal csel.

The capacitance circuit 52c1 includes an inverter circuit 61, transistors 62, 63, 64, and a capacitor 65. The transistors 62 and 63 are n-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and the transistors 64 are p-channel MOSFETs.

The input terminal of the inverter circuit 61 is connected to the output terminal of the AND circuit 60e1, and the output terminal of the inverter circuit 61 is connected to the gate terminal of the transistors 62 and 64. The source terminal of the transistor 62 is grounded, and the drain terminal of the transistor 62 is connected to one of the source terminal of the transistor 63, the drain terminal of the transistor 64, and the capacitor 65. The drain terminal of the transistor 63 and the source terminal of the transistor 64 are connected to the wiring through which the data signal dto propagates. The other terminal of the capacitor 65 is grounded.

The capacitance circuits 52c2 to 52cn are also circuits similar to the capacitance circuits 52c1.
When both the signals cton and ctoff are at H level, the output values of the AND circuits 60e1 to 60en are also at H level. When the output values of the AND circuits 60e1 to 60en reach the H level, the transistors 62 are in the off state and the transistors 63 and 64 are in the on state, so that the capacitor 65 is electrically connected to the wiring through which the data signal dto propagates. .. That is, the capacitive circuits 52c1 to 52cn are valid.

When the signal ctoff is L level, the output values of the AND circuits 60e1 to 60en are also L level regardless of the value of the signal cton. When the output values of the AND circuits 60e1 to 60en reach the L level, the transistors 62 are turned on and the transistors 63 and 64 are turned off, so that the capacitor 65 is electrically disconnected from the wiring through which the data signal dto propagates. .. That is, the capacitive circuits 52c1 to 52cn are invalid.

When the signal cton is the L level and the signal ctoff is the H level, the output values of the AND circuits 60e1 to 60en are sequentially set to the H level when the data signal dts transitions to the H level. As a result, the capacitance circuits 52c1 to 52cn become effective in order from the capacitance circuit 52c1.

FIG. 13 is a diagram showing a sampling timing setting example and a load capacitance setting example by the load capacitance variable circuit. The voltage range Vmet is the voltage range of the data signal dto in which the latch circuit 53 is in the metastability state.

First, the control circuit 54 sets the signal ctoff shown in FIG. 12 to the L level, invalidates the capacitance circuits 52c1 to 52cn, and makes the load capacitance not added. Then, for example, the control circuit 54 changes the adjustment signals tsel1 and tsel2 to delay the phase of the clock signal clk from the state where the phase of the clock signal clk is advanced from the data signal dto. The control circuit 54 detects the output value RND, and stores the values of the adjustment signals tsel1 and tsel2 at the timing t10 when the output value RND changes from the L level to the H level in a storage unit (not shown).

After that, the control circuit 54 adds the load capacitance by setting both the signals ctoff and cton shown in FIG. 12 to the H level and enabling the capacitance circuits 52c1 to 52cn. Then, in the same manner as described above, the control circuit 54 delays the phase of the clock signal clk from the state in which the adjustment signals tsel1 and tsel2 are changed so that the phase of the clock signal clk is advanced from the data signal dto, for example. The control circuit 54 detects the output value RND, and stores the values of the adjustment signals tsel1 and tsel2 at the timing t12 when the output value RND changes from the L level to the H level in a storage unit (not shown).

Then, the control circuit 54 calculates the values of the adjustment signals tsel1 and tsel2 for adjusting the sampling timing to the middle of the timings t10 and t12 (timing t11) based on the stored values of the adjustment signals tsel1 and tsel2. For example, the control circuit 54 obtains the values of the adjustment signals tsel1 and tsel2 that match the sampling timing with the timing t11 by obtaining the average of the values of the adjustment signals tsel1 and tsel2 at the timings t10 and t12. The obtained value is stored in, for example, a storage unit.

The phase of the clock signal clk is advanced from the state where the phase of the clock signal clk is delayed from the data signal dto, and the sampling timing t11 is determined using the adjustment signals tsel1 and tsel2 of the timing at which the output value RND changes. You may.

Next, the control circuit 54 changes the values of the adjustment signals tsel1 and tsel2, and adjusts the sampling timing to the timing t10 again. Then, as shown in FIG. 13, the control circuit 54 changes the signals ct0 to ctm in a state where the signal ctoff is set to H level and the signal cton is set to L level, and the timing to start adding the load capacitance is set. I will accelerate. The waveform 66a shows the change in the data signal dto when the load capacitance addition start timing is delayed the most, and the waveform 66b shows the change in the data signal dto when the load capacitance addition start timing is the earliest. The load capacitance is gradually increased by the delay circuits 60c1 to 60c (n-1).

The control circuit 54 detects the output value RND, and determines the addition start timing based on the values of the signals ct0 to ctm when the output value RND changes from the H level to the L level. The control circuit 54 stores the values of the signals ct0 to ctm at this time in the storage unit. For example, the waveform 66c shows a change in the data signal dto when the load capacitance is added at the addition start timing according to the values of the signals ct0 to ctm stored in the storage unit.

At the time of subsequent random number generation, the control circuit 54 uses the values of the adjustment signals tsel1 and tsel2 for adjusting the sampling timing to the timing t11 and the values of the signals ct0 to ctm at the determined addition start timing, which are obtained by the above method. ..

FIG. 14 is a diagram showing a metastable period when the addition start timing of the load capacity is determined as shown in FIG. In addition, in FIG. 14, in addition to the metastable period tm1 of the waveform 66c shown in FIG. 13, the metastable period tm2 when the load capacitance shown in FIG. 13 is not added, and the case where the load capacitance is always added. The metastable period tm3 is also illustrated.

When the load capacitance by the capacitance circuits 52c1 to 52cn is always added, the rise of the data signal dto becomes gentle, and the metastable period tm3 which is the voltage range Vmet becomes longer than when the load capacitance is not added. However, the period from the start of the rise of the data signal dto to the entry into the voltage range Vmet becomes relatively long.

On the other hand, in the waveform 66c obtained by determining the load capacitance addition start timing as shown in FIG. 13, the load capacitance is always added during the period from the start of the rise of the data signal dto to the entry into the voltage range Vmet. It will be shorter than when it is done. As a result, the metastable period tm1 can be made longer than the metastable period tm3 when the same load capacity is always added.

Parameters such as the number and delay time of the delay circuits 60a1 to 60am and 60c1 to 60c (n-1) shown in FIG. 12, the number of capacitance circuits 52c1 to 52cn, and the capacitance value are calculated by, for example, a circuit simulation. It is decided based on the result. For example, in a circuit simulation, the above parameters are determined according to the adjustment accuracy and how long the metastable period to be set is to be set.

Hereinafter, the flow of the setting process of the sampling timing and the addition start timing of the load capacity will be described with a flowchart.
FIG. 15 is a flowchart showing a flow of an example of the setting process of the sampling timing and the addition start timing of the load capacitance.

The control circuit 54 outputs the initial values of the adjustment signals tsel1 and tsel2 that bring the phase of the clock signal clk ahead of the data signal dto without adding the load capacitance, and initializes the adjustment circuits 51a and 51b. (Step S30).

After that, the control circuit 54 changes the adjustment signals tsel1 and tsel2 to delay the phase of the clock signal clk (change the sampling timing). Then, the control circuit 54 detects the output value RND and stores the values of the adjustment signals tsel1 and tsel2 set at the timing when the output value RND changes from the L level to the H level in the storage unit (step S31).

Further, the control circuit 54 outputs the initial values of the adjustment signals tsel1 and tsel2 that bring the phase of the clock signal clk ahead of the data signal dto in a state where the load capacitance is added, and outputs the adjustment circuits 51a and 51b. Initialize (step S32).

After that, the control circuit 54 again performs the same processing as in step S31 (step S33).
Next, the control circuit 54 determines the value of the adjustment signal whose sampling timing is intermediate between the two timings based on the values of the adjustment signals tsel1 and tsel2 stored in the processes of steps S31 and S33 (step). S34).

After that, the control circuit 54 sets the timing for starting the addition of the input load (step S35).
16 and 17 are flowcharts showing an example of each process of FIG.

As an example of the initialization process of step S30 of FIG. 15, as shown in FIG. 16, the control circuit 54 first has a signal ct0 to ctm = “X”, a signal cton = “X”, and a signal ctoff = “L” ( Set to (L level) (step S40). “X” indicates that it may be H level or L level. Further, the control circuit 54 sets the initial values of the adjustment signals tsel1 and tsel2 that advance the phase of the clock signal clk from the data signal dto in the adjustment circuits 51a and 51b (step S41).

Next, as an example of the process of step S31 of FIG. 15, the process of steps S42 to S45 of FIG. 16 is performed.
The adjustment circuits 51a and 51b receive the clock signal CLK and output the data signal dt and the clock signal clk. The data signal dt is supplied to the load capacitance variable circuit 52. The latch circuit 53 takes in the data signal dto output by the load capacitance variable circuit 52 at the sampling timing by the clock signal clk (step S42).

Then, the control circuit 54 determines whether or not the output value RND is at the H level (step S43).
When the output value RND is not H level, the control circuit 54 changes the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk with respect to the data signal dto (step S44). After the process of step S44, the process of step S42 is performed again.

When the output value RND is H level, the control circuit 54 stores the values of the adjustment signals tsel1 and tsel2 set at the current sampling timing (for example, the timing t10 in FIG. 13) in the storage unit (step S45).

Next, as an example of the initialization process of step S32 of FIG. 15, as shown in FIG. 16, the control circuit 54 has signals ct0 to ctm = “X”, signal cton = “H” (H level), and signal ctoff. = Set to "H" (step S46). Further, the control circuit 54 sets the initial values of the adjustment signals tsel1 and tsel2 that advance the phase of the clock signal clk from the data signal dto in the adjustment circuits 51a and 51b (step S47).

Then, as an example of the process of step S33 of FIG. 15, the process of steps S48 to S51 of FIG. 16 is performed. The processing of steps S48 to S51 is the same as the processing of steps S42 to S45. However, the sampling timing at which the output value RND becomes the H level (for example, the timing t12 in FIG. 13) is different from the case where the load capacitance is not added.

After that, as an example of the process of step S34 in FIG. 15, the following process is performed.
The control circuit 54 determines the values of the adjustment signals tsel1 and tsel2 in which the sampling timing is in the middle of each sampling timing at which the output value RND becomes H level in the processing of steps S43 and S49, and stores them in the storage unit (step S52). ). In the process of step S52, the control circuit 54 sets the sampling timing to, for example, the timing t11 in FIG. 13, based on the values of the adjustment signals tsel1 and tsel2 stored in the processes of steps S45 and S51. Determine tsel2. Then, the control circuit 54 stores the determined adjustment signals tsel1 and tsel2 in the storage unit.

Next, as an example of the process of step S35 of FIG. 15, the process of steps S53 to S58 of FIG. 17 is performed.
The control circuit 54 sets the signal ct0 to ctm = “L”, the signal cton = “L”, and the signal ctoff = “H” (step S53). Further, the control circuit 54 sets the sampling timing to the timing t10 by using the values of the adjustment signals tsel1 and tsel2 stored in the process of step S45 (step S54).

After that, the adjustment circuits 51a and 51b receive the clock signal CLK and output the data signal dt and the clock signal clk. The data signal dt is supplied to the load capacitance variable circuit 52. The latch circuit 53 takes in the data signal dto output by the load capacitance variable circuit 52 at the sampling timing by the clock signal clk (step S55).

Then, the control circuit 54 determines whether or not the output value RND is at the L level (step S56). When the output value RND is not the L level, the control circuit 54 sets the signals ct0 to ctm to the H level in order from the signal ctm (step S57). After the process of step S57, the process of step S56 is performed again.

For example, when all the values of the signals ct0 to ctm are L level, the selection circuit 60b in FIG. 12 selects the data signal dtm having the largest delay time from the data signals dt to dtm and outputs it as the data signal dts. .. If the output value RND remains at H level, the control circuit 54 changes the value of the signal ctm to H level. As a result, the selection circuit 60b selects the data signal having the second largest delay time among the data signals dt to dtm and outputs it as the data signal dts. If the output value RND still remains at the H level, the control circuit 54 further changes the value of the signal ct (m-1) (not shown in FIG. 12) to the H level. As a result, the selection circuit 60b selects the data signal having the third largest delay time among the data signals dt to dtm and outputs it as the data signal dts. The control circuit 54 repeats such a process until the output value RND changes to the L level.

As a result, the timing for starting the addition of the load capacity is advanced. When the output value RND is the L level, the control circuit 54 stores the current values of the signals ct0 to ctm in the storage unit (step S58), and ends the setting process.

The order of the processes shown in FIGS. 15 to 17 is an example, and the order of the processes may be changed as appropriate. For example, after the processing of step S31, the addition start timing of the load capacity in step S35 may be set.

According to the random number generation circuit 50 and its control method of the fifth embodiment as described above, since the metastable period can be extended, it becomes easy to match the sampling timing, and a high-quality random number is generated by metastability. it can.

(Sixth Embodiment)
FIG. 18 is a diagram showing an example of a random number generation circuit according to the sixth embodiment. In FIG. 18, the same elements as those of the random number generation circuit 50 of the fifth embodiment shown in FIG. 11 are designated by the same reference numerals.

The random number generation circuit 70 of the sixth embodiment includes a latch circuit 71a0, 71a1, 71a2 ..., 71an, a delay circuit 71b1, 71b2 ..., 71bn, an ExOR circuit 71c0, 71c1, 71c2, ..., 71cn, and a control circuit 71d. Has.

The data signal dto output by the load capacitance variable circuit 52 is supplied to the data terminals of the latch circuits 71a to 71an. Further, clock signals clk delayed by different delay times are supplied to the respective clock terminals of the latch circuits 71a1 to 71an by the delay circuits 71b1 to 71bn connected in series.

Further, the ExOR circuits 71c to 71cn are connected in series, and the output value of the corresponding latch circuit of the latch circuits 71a to 71an is supplied to one input terminal of each of the ExOR circuits 71c to 71cn. The output value of the ExOR circuit in the previous stage is supplied to the other input terminals of the ExOR circuits 71c1 to 71cn. The input value R0 is supplied to the other input terminal of the first-stage ExOR circuit 71c0.

At the time of random number generation, the input value R0 is fixed to either the H level or the L level. At the time of testing the random number generation circuit 70, the input value R0 may be changed. The output value of the last-stage ExOR circuit 71cn becomes the output value RND. Further, the output values of the latch circuits 71a to 71an are supplied to the control circuit 71d.

The control circuit 71d is, for example, a process shown in FIG. 15 based on the output value supplied from the latch circuit in which the delay with respect to the clock signal clk is an intermediate value among the latch circuits 71a to 71an. The value of tsel2 and the selection signal csel is determined.

In the random number generation circuit 70, by appropriately setting the delay time by the delay circuits 71b1 to 71bn, even if skew occurs due to a change in operating conditions or the like, the sampling timing in any of the latch circuits 71a to 71an is within the metastable period. The possibility of becoming is increased. That is, the probability of random number generation due to metastability can be increased.

(7th Embodiment)
FIG. 19 is a diagram showing an example of a random number generation circuit according to the seventh embodiment. In FIG. 19, the same elements as those of the random number generation circuit 70 of the sixth embodiment shown in FIG. 18 are designated by the same reference numerals.

The random number generation circuit 80 of the seventh embodiment has an LFSR81 including an input terminal in, a clock terminal ck, and an output terminal out.
The clock signal CLK is supplied to the clock terminal ck, and the output value of the last-stage ExOR circuit 71cn is supplied to the input terminal in. An output value RND which is a random number or a pseudo-random number is output from the output terminal out.

The LFSR81 can be realized by, for example, the same circuit as the LFSR41 shown in FIG. During the period of the pseudo-random number, the output value of the ExOR circuit 71cn becomes a random number due to metastability, so that the output value RND output by the LFSR81 becomes a random number having no periodicity. That is, it is possible to prevent the output value RND from becoming a pseudo-random number. Therefore, a high quality random number can be output.

Further, in the random number generation circuit 70 of the sixth embodiment, there is a possibility that a random number due to metastability is not output in each cycle of the clock signal CLK, but the random number generation circuit 80 having the LFSR81 as described above is a clock signal. Random numbers can be output in each cycle of CLK. That is, the random number generation rate can be improved.

If the output value RND output by the LFSR81 is the same as the predetermined number of cycles of the clock signal CLK, the control circuit 71d sets the signal ERR to the H level and notifies the outside that it is in an abnormal state. Good. Further, the control circuit 71d detects whether or not the output value of the ExOR circuit 71cn supplied to the input terminal in of the LFSR81 changes, and when the output value is the same value as the predetermined number of cycles of the clock signal CLK. May set the signal ERR to H level.

Further, the random number generation circuit 50 and the LFSR81 of the fifth embodiment may be combined to supply the output value of the latch circuit 53 to the input terminal in of the LFSR81.
(8th Embodiment)
FIG. 20 is a diagram showing an example of a random number generation circuit according to the eighth embodiment. In FIG. 20, the same elements as those of the random number generation circuit 30 of the third embodiment shown in FIG. 8 and the random number generation circuit 50 of the fifth embodiment shown in FIG. 11 are designated by the same reference numerals. ..

The random number generation circuit 90 of the eighth embodiment is a circuit in which the load capacitance variable circuit 52 is applied to the random number generation circuit 30 of the third embodiment.
It is different from the random number generation circuit 30 in that the data signal dto output by the load capacitance variable circuit 52 is supplied to the random number generation units 30a to 30an instead of the data signal dt.

The control circuit 91 first starts adding the load capacitance based on the output value RNDi supplied from the random number generation unit 30ai in which the delay with respect to the clock signal clk is an intermediate value among the random number generation units 30a to 30an. To determine. For example, in the control circuit 91, the load capacitance variable circuit 52 is first set in a state where the load capacitance is not added by the selection signal csel, the values of the adjustment signals tsel1 and tsel2 are changed, and the output value RNDi is changed from the L level. The timing of changing to the H level is detected. Then, the control circuit 91 uses the values of the adjustment signals tsel1 and tsel2 at that timing to advance the start timing of adding the load capacitance by the selection signal csel, and the selection signal when the output value RNDi changes to the L level. Store the value of csel.

After that, the control circuit 91 supplies the stored selection signal csel value to the load capacitance variable circuit 52, and gradually increases the load capacitance at an additional start timing determined by the value. Then, the control circuit 91 determines the values of the adjustment signals tsel1 and tsel2 based on the detection result matchi and the output value RNDi. The values of the adjustment signals tsel1 and tsel2 are determined by the methods shown in FIGS. 4 to 6 so that the sampling timing by the clock signal clk reaching the random number generation unit 30ai is within the metastable period.

The random number generation circuit 90 of the eighth embodiment has the effect obtained by the random number generation circuit 30 of the third embodiment. Further, since the random number generation circuit 90 has the load capacitance variable circuit 52, the metastable period can be extended, so that the possibility that the sampling timing can be maintained within the metastable period increases. This makes it possible to generate higher quality random numbers.

The random number generation circuit 90 determines the sampling timing based on, for example, the detection result matchi and the output value RNDi. Therefore, in the load capacitance variable circuit 52 of FIG. 12, the OR circuits 60d1 to 60dn provided to enable the capacitance circuits 52c1 to 52cn at the same time when determining the sampling timing may not be provided.

(9th embodiment)
FIG. 21 is a diagram showing an example of a random number generation circuit according to the ninth embodiment. In FIG. 21, the same elements as those of the random number generation circuit 40 of the fourth embodiment shown in FIG. 9 and the random number generation circuit 90 of the eighth embodiment shown in FIG. 20 are designated by the same reference numerals. ..

The random number generation circuit 100 of the ninth embodiment is a circuit in which the LFSR 41 is applied to the random number generation circuit 90 of the eighth embodiment.
The random number generation circuit 100 of the ninth embodiment has the same effect as the random number generation circuit 90 of the eighth embodiment, and also has the same effect as the random number generation circuit 40 of the fourth embodiment. To be done.

Although description is omitted, it goes without saying that the load capacitance variable circuit 52 can be applied to the random number generation circuit 10 of the first embodiment and the random number generation circuit 20 of the second embodiment.
The random number generation circuits 10, 20, 30, 40, 50, 70, 80, 90, 100 of the first to ninth embodiments described above can be applied to various integrated circuits, systems, devices, and the like using random numbers. Is. For example, it can be used for generation of an encryption key using random numbers in the security field, dropout processing for preventing over-learning in deep learning using random numbers in the AI (Artificial Intelligence) field, and the like. Furthermore, it can also be used for big data analysis in which random numbers are used.

Although the random number generation circuit of the present invention and one aspect of the control method thereof have been described above based on the embodiments, these are merely examples and are not limited to the above description.

10 Random generator 11 Adjustment circuit 11a, 11b Adjustment circuit 12 Random generator 12a1-12an Latch circuit 12b Output circuit 12c Detection circuit 13 Control circuit CLK, clk Clock signal dt Data signal match Detection result tsel1, tsel2 Adjustment signal RND Output value

Claims (8)

It receives an input signal and an adjustment signal, outputs a first signal and a second signal based on the input signal, and outputs the first signal or the second signal based on the adjustment signal. The adjustment part that adjusts the phase and
The first signal and the second signal are received, and the first value or the second value is output, respectively, based on the signal level of the first signal at the sampling timing by the second signal. With 3 or more odd numbered latch circuits,
When each of the odd numbered latch circuits receives the first value or the second value and all of the odd numbered latch circuits output the same value, the same value is output and the odd number is output. When at least one of the latch circuits outputs a different value, the output circuit that outputs the smaller number of the first value and the second value is output.
The first value or the second value output by each of the odd-numbered latch circuits is received, and a detection result indicating whether or not all of the odd-numbered latch circuits output the same value is output. With the detection circuit
Based on the detection result and the output value of the output circuit, it is determined whether or not the sampling timing is within the period in which the odd number of latch circuits are in the metastable state, and the sampling timing is within the period. A control circuit that adjusts the sampling timing within the period by changing the value of the adjustment signal based on the determination result of whether or not
Random number generation circuit with. The control circuit delays the phase of the second signal with respect to the first signal by changing the value of the adjustment signal in a state where all of the odd number of latch circuits output the same value. Based on the detection result and the change in the output value of the output circuit when the speed is advanced, it is determined whether or not the sampling timing is within the period.
The random number generation circuit according to claim 1. The control circuit changes the value of the adjustment signal until all of the odd-numbered latch circuits output the second value, and then all of the odd-numbered latch circuits have the first value. Change the value of the adjustment signal until the value is output.
In the control circuit, the value of the adjustment signal at the first timing when all of the odd-numbered latch circuits are in a state of outputting the second value, and all of the odd-numbered latch circuits are said to be the first. Based on the value of the adjustment signal at the second timing in which the value of is output, the sampling is performed at the third timing within the period, which is intermediate between the first timing and the second timing. Adjust the timing,
The random number generation circuit according to claim 1 or 2. A first exclusive OR that outputs the calculation result of the exclusive OR of the odd number of latch circuits, the output circuit, the detection circuit, and the output value and the first input value of the output circuit. A circuit, a plurality of random number generators connected in series in multiple stages each having a circuit, and
It has a delay circuit that makes the delay amount of the second signal supplied to each of the plurality of random number generators different.
The first input value supplied to the first exclusive OR circuit of the first-stage random number generation unit among the plurality of random number generation units is the first value output by the control circuit or the first value. One of the second values,
The first input value supplied to the first exclusive OR circuit of the second and subsequent stages of the plurality of random number generation units is the first input value of the previous stage random number generation unit. This is the calculation result output by the exclusive OR circuit.
The random number generation circuit according to any one of claims 1 to 3. Further having a linear feedback shift register including a multi-bit shift register that captures a second input value in synchronization with the input signal.
The linear feedback shift register is an exclusive logic of the output value of the output circuit or a value based on the output value and a feedback signal generated by the exclusive OR of some of the plurality of bits. It has a second exclusive OR circuit that outputs the second input value that is the sum.
The random number generation circuit according to any one of claims 1 to 4. The load capacitance of the terminal to which the first signal is supplied in the odd-numbered latch circuits is gradually increased from the start timing determined based on the selection signal in response to the selection signal output by the control circuit. The random number generation circuit according to any one of claims 1 to 5, further comprising a load capacitance variable circuit. The control circuit sets the value of the selection signal in a state where the adjustment signal is fixed to the fifth value when the output value of the output circuit changes from the first value to the second value. By changing, the start timing is advanced, and the start timing is determined by the sixth value of the selection signal when the output value changes from the second value to the first value.
The random number generation circuit according to claim 6. In the control method of the random number generation circuit,
The adjustment unit of the random number generation circuit receives an input signal and an adjustment signal, outputs a first signal and a second signal based on the input signal, and outputs the first signal and the second signal based on the input signal, and based on the adjustment signal, the first signal. Adjust the phase of the 1st signal or the 2nd signal,
Three or more odd-numbered latch circuits included in the random number generation circuit receive the first signal and the second signal, and set the signal level of the first signal at the sampling timing by the second signal. Based on, the first value or the second value is output respectively,
When the output circuit of the random number generation circuit receives the first value or the second value output by each of the odd-numbered latch circuits, and all of the odd-numbered latch circuits output the same value. , When the same value is output and at least one of the odd-numbered latch circuits outputs a different value, the smaller number of the first value and the second value is output. Output,
The detection circuit included in the random number generation circuit receives the first value or the second value output by each of the odd-numbered latch circuits, and all of the odd-numbered latch circuits output the same value. Outputs the detection result indicating whether or not
Based on the detection result and the output value of the output circuit, the control circuit of the random number generation circuit determines whether or not the sampling timing is within the period in which the odd number of latch circuits are in the metastable state. Judgment is made, and the sampling timing is adjusted within the period by changing the value of the adjustment signal based on the determination result of whether or not the sampling timing is within the period.
How to control the random number generation circuit.

Images