JP2019053385A - Random number generation circuit and control method of random number generation circuit - Google Patents

Abstract

To prevent deterioration of quality of random numbers.SOLUTION: When all of an odd number of latch circuits 12a1 to 12an output the same value, an output circuit 12b outputs the value, and when at least one of the plurality of latch circuits outputs a different value, the output circuit 12b outputs a value of which the number of output is smaller. A detection circuit 12c outputs a detection result indicating whether all of the latch circuits 12a1 to 12an output the same value or not. A control circuit 13 determines whether sampling timing is in a period where the latch circuits 12a1 to 12an are in a quasi-stable state on the basis of the detection result and an output value of the detection circuit 12b, and changes values of adjustment signals tsel1 and tsel2 used by an adjustment unit 11 for adjusting phases of a data signal dt and a clock signal clk supplied to the latch circuits 12a1 to 12an, so as to adjust the sampling timing becoming in the period.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a random number generation circuit and a control method for the random number generation circuit.

  One technique for generating random numbers using a latch circuit is to use metastability (metastability) of the latch circuit. Metastability is a characteristic in which the output value becomes indeterminate when sampling by the clock signal occurs when the logic level of the data signal input to the latch circuit is between the H (High) level and the L (Low) level. is there.

International Publication No. 2011-117929 Pamphlet JP 2005-510923 A JP 2012-129784 A

  However, in the method using the metastability of the latch circuit, it is difficult to match the sampling timing to a period in which metastability occurs (hereinafter referred to as a metastable period), and the sampling timing may deviate from the metastable period. When the sampling timing deviates from the metastable period, the output of the latch circuit is biased to H level or L level, and the quality of the generated random number may be deteriorated.

  In one aspect, the present invention aims to suppress deterioration in quality of random numbers.

  In one embodiment, the input signal and the adjustment signal are received, the first signal and the second signal are output based on the input signal, and the first signal or the adjustment signal is output based on the adjustment signal. An adjustment unit that adjusts the phase of the second signal, the first signal, and the second signal, and based on the signal level of the first signal at the sampling timing of the second signal, Receiving three or more odd number of latch circuits that respectively output the first value or the second value, and the first value or the second value output by each of the odd number of latch circuits; When all of the odd number of latch circuits output the same value, the same value is output, and when at least one of the odd number of latch circuits outputs a different value, the first value and the first value The value of 2 is output An output circuit that outputs the smaller value and the first value or the second value output from each of the odd number of latch circuits, and the odd number of latch circuits all receive the same value. A period for which the odd number of latch circuits are in a metastable state based on a detection circuit that outputs a detection result indicating whether or not to output the signal, and the detection result and an output value of the output circuit A control circuit that adjusts the sampling timing within the period by changing the value of the adjustment signal based on a determination result of whether the sampling timing is within the period or not A random number generation circuit is provided.

  In one embodiment, a method for controlling a random number generation circuit is provided.

  In one aspect, deterioration of random number quality can be suppressed, and the generation factor of the generated random number can be known.

It is a figure which shows an example of the random number generation circuit of 1st Embodiment. It is a figure which shows an example of the random number generation circuit of 2nd Embodiment. It is a figure which shows the relationship of an example of the output value of each latch circuit, detection result match, and output value RND. It is a figure which shows the example of adjustment of a sampling timing. It is a flowchart which shows the flow of an example of the adjustment process of a sampling timing. It is a flowchart which shows an example about each process of FIG. It is a timing chart which shows an example of the time change of each signal at the time of random number generation of a random number generation circuit. It is a figure which shows an example of the random number generation circuit of 3rd Embodiment. It is a figure which shows an example of the random number generation circuit of 4th Embodiment. It is a figure which shows an example of LFSR. It is a figure which shows an example of the random number generation circuit of 5th Embodiment. It is a figure which shows an example of a delay selection circuit and a capacitive circuit. It is a figure which shows the setting example of a sampling timing, and the setting example of the load capacity | capacitance by a load capacity variable circuit. It is a figure which shows a metastable period when the addition start timing of load capacity | capacitance is determined like FIG. It is a flowchart which shows the flow of an example of a setting process of a sampling timing and the addition start timing of load capacity. 16 is a flowchart illustrating an example of each process in FIG. 15 (part 1). It is a flowchart which shows an example about each process of FIG. 15 (the 2). It is a figure which shows an example of the random number generation circuit of 6th Embodiment. It is a figure which shows an example of the random number generation circuit of 7th Embodiment. It is a figure which shows an example of the random number generation circuit of 8th Embodiment. It is a figure which shows an example of the random number generation circuit of 9th Embodiment.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a random number generation circuit according to the first embodiment.

  The random number generation circuit 10 includes an adjustment unit 11 including adjustment circuits 11a and 11b, a random number generation unit 12 including three or more odd number of latch circuits 12a1, 12a2, ..., 12an, an output circuit 12b, and a detection circuit 12c. And a control circuit 13.

  The adjustment unit 11 receives an input signal and an adjustment signal. In the following description, the input signal is described as being the clock signal CLK, but is not limited to the clock signal CLK. However, in order to increase the generation rate of random numbers, it is desirable to use a signal that frequently causes state transition (transition between H level and L level).

The clock signal CLK is supplied from, for example, a clock signal generation circuit (not shown) outside the random number generation circuit 10.
The adjustment unit 11 outputs two signals (hereinafter referred to as a data signal dt and a clock signal clk) based on the clock signal CLK, and adjusts the phase of the data signal dt or the clock signal clk based on the adjustment signal.

  In the example of FIG. 1, the adjustment unit 11 includes adjustment circuits 11a and 11b. The adjustment circuit 11a outputs a data signal dt in which the phase of the clock signal CLK is adjusted based on the adjustment signal tsel1. The adjustment circuit 11b outputs a clock signal clk in which the phase of the clock signal CLK is adjusted based on the adjustment signal tsel2. The adjustment circuits 11a and 11b are variable delay circuits that can change the delay amount based on the values of the adjustment signals tsel1 and tsel2, for example. For example, when the values of the adjustment signals tsel1 and tsel2 increase, the delay amount increases.

  Each of the latch circuits 12a1 to 12an receives the data signal dt and the clock signal clk, and outputs an H level or L level value based on the signal level of the data signal dt at the sampling timing based on the clock signal clk. The H level corresponds to, for example, a power supply voltage, and the L level corresponds to a reference potential (for example, 0 V).

  The output circuit 12b receives an H level value or an L level value output from each of the latch circuits 12a1 to 12an. When all of the latch circuits 12a1 to 12an output the same value, the output circuit 12b outputs the value. When at least one of the latch circuits 12a1 to 12an outputs a different value, the output circuit 12b has a smaller number of outputs among the H level value and the L level value output by the latch circuits 12a1 to 12an. The value of is output.

  For example, when the latch circuits 12a1 to 12an output more H level values than L level values, the output circuit 12b outputs an L level output value RND. On the contrary, when the L level value is output more than the H level value, the output circuit 12b outputs the H level output value RND.

  This is because the value with the smaller output number is more likely to be a random number (or eligibility as a random number) than the value with the larger output number. There is a high possibility that the value with the larger number of outputs is not the effect of metastability but the value output due to the effect of skew. When a value output due to the influence of skew is adopted as a random number, the value is biased and the quality as a random number is low.

  The detection circuit 12c receives an H level value or an L level value output from each of the latch circuits 12a1 to 12an. Then, the detection circuit 12c outputs a detection result match indicating whether or not all of the latch circuits 12a1 to 12an output the same value. In the following description, when all of the latch circuits 12a1 to 12an output the same value, an H level detection result match is output, and when at least one of the latch circuits 12a1 to 12an outputs a different value, the L level It is assumed that the detection result match is output.

Circuit examples of the output circuit 12b and the detection circuit 12c will be described later.
The control circuit 13 is, for example, an electronic circuit for a specific purpose such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The control circuit 13 may be a processor as an arithmetic processing unit such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor). The processor executes a program stored in a memory such as a RAM (Random Access Memory). The control circuit 13 may be a set of a plurality of processors.

  Based on the detection result match and the output value RND, the control circuit 13 determines that the sampling timing by the clock signal clk is within a period in which the latch circuits 12a1 to 12n are in the metastability state (metastable state) (within the metastable period). It is determined whether or not. The control circuit 13 adjusts the sampling timing within the metastable period by changing the values of the adjustment signals tsel1 and tsel2 based on the determination result.

FIG. 1 shows an example of adjustment of sampling timing by the clock signal clk when the data signal dt transitions from L level to H level.
Since the latch circuits 12a1 to 12an all output L level values when the sampling timing is timing t1, the output circuit 12b outputs the L level output value RND, and the detection circuit 12c detects the H level detection result. Outputs match. At this time, the control circuit 13 determines that the sampling timing is not within the metastable period, and changes the values of the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk with respect to the data signal dt. For example, the control circuit 13 fixes the value of the adjustment signal tsel1, increases the value of the adjustment signal tsel2, and delays the phase of the clock signal clk by increasing the delay amount of the clock signal clk in the adjustment circuit 11b.

  It is assumed that the sampling timing is, for example, timing t2 by delaying the phase of the clock signal clk. At timing t2, it is assumed that the signal level of the data signal dt is higher than that at the L level, and at least one of the latch circuits 12a1 to 12an outputs an H level value. At this time, an L level detection result match is output from the detection circuit 12c. However, since the latch circuits 12a1 to 12an still output more L level values than H level values, the output circuit 12b outputs the H level output value RND. Also at this time, the control circuit 13 determines that the sampling timing is not within the metastable period, and changes the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk with respect to the data signal dt.

  It is assumed that the sampling timing is, for example, timing t3 by further delaying the phase of the clock signal clk. At the timing t3, the signal level of the data signal dt is in the vicinity of the middle between the L level and the H level, and among the latch circuits 12a1 to 12an, the one that outputs the L level value and the one that outputs the H level value are almost. Divide evenly. Therefore, the output circuit 12b outputs the L-level output value RND and the H-level output value RND with substantially the same probability. The detection circuit 12c outputs an L level detection result match.

  As described above, when the control circuit 13 changes the sampling timing in the order of the timings t1, t2, and t3, when the output value RND and the detection result match are obtained at the timing t3, similar to the timing t2. There is. In that case, the control circuit 13 further delays the phase of the clock signal clk, and when the output value RND changes from the H level to the L level (for example, timing t4), the previous timing (that is, timing t3) It is determined that it is within the metastable period. Then, the control circuit 13 fixes the values of the adjustment signals tsel1 and tsel2 at the timing t3.

  On the other hand, when the sampling timing is timing t5, the latch circuits 12a1 to 12an all output H level values, so the output circuit 12b outputs the H level output value RND, and the detection circuit 12c detects the H level detection result match. Is output. At this time, the control circuit 13 determines that the sampling timing is not within the metastable period, and changes the adjustment signals tsel1 and tsel2 so that the phase of the clock signal clk is advanced with respect to the data signal dt. For example, the control circuit 13 advances the phase of the clock signal clk by fixing the value of the adjustment signal tsel1, reducing the value of the adjustment signal tsel2, and reducing the delay amount of the clock signal clk in the adjustment circuit 11b.

  It is assumed that the sampling timing is, for example, timing t4 by advancing the phase of the clock signal clk. At timing t4, it is assumed that the signal level of the data signal dt is lower than that at the H level, and at least one of the latch circuits 12a1 to 12an outputs an L level value. At this time, the detection circuit 12c outputs an L level detection result match. However, since the latch circuits 12a1 to 12an still output more H level values than L level values, the output circuit 12b outputs the L level output value RND. Also at this time, the control circuit 13 determines that the sampling timing is not within the metastable period, and changes the adjustment signals tsel1 and tsel2 so that the phase of the clock signal clk is advanced with respect to the data signal dt.

  It is assumed that the sampling timing is, for example, timing t3 by advancing the phase of the clock signal clk. At timing t3, as described above, the output circuit 12b outputs the L-level output value RND and the H-level output value RND with substantially the same probability. The detection circuit 12c outputs an L level detection result match.

  When the control circuit 13 changes the sampling timing in the order of timings t5, t4, and t3, the output value RND and the detection result match may be obtained at the timing t3, similar to the timing t4. In that case, the control circuit 13 further advances the phase of the clock signal clk, for example, and when the output value RND changes from the L level to the H level (timing t2), the previous timing (that is, timing t3) is It is determined that it is within the metastable period. Then, the control circuit 13 fixes the values of the adjustment signals tsel1 and tsel2 at the timing t3.

Thereafter, the control circuit 13 supplies the values of the fixed adjustment signals tsel1 and tsel2 to the adjustment unit 11, and causes the random number generation unit 12 to generate random numbers based on metastability.
Examples of other adjustment methods of the sampling timing will be described later.

  As described above, in the random number generation circuit 10 and the control method thereof according to the first embodiment, the sampling timing is within the metastable period based on the output value RND obtained from the outputs of the latch circuits 12a1 to 12an and the detection result match. It can be determined whether or not. That is, the control circuit 13 can determine whether or not the latch circuits 12a1 to 12an are in the metastability state. Then, the control circuit 13 can adjust the phase of the data signal dt or the clock signal clk based on the determination result to adjust the sampling timing to the metastable period.

  In the metastable period, as described above, the output value RND at the H level and the output value RND at the L level are output with almost the same probability, and the output value RND is a random number with good quality. That is, the deviation of the output value RND is reduced, and the deterioration of the random number quality can be suppressed.

  As a method of generating a random number using a latch circuit, there is a method of generating a random number from jitter of an output pulse by inputting an output pulse of a ring oscillator to a data terminal of the latch circuit and inputting a clock signal to the clock terminal. . However, in this method, since the random number at the time of sampling has a dependency relationship with the immediately preceding sampling value, the generated random number includes periodicity. In the random number generation circuit 10 of the present embodiment using metastability, the random number does not include periodicity.

(Second Embodiment)
FIG. 2 is a diagram illustrating an example of a random number generation circuit according to the second embodiment.
The random number generation circuit 20 includes adjustment circuits 21 a and 21 b, a random number generation unit 22, and a control circuit 23.

The adjustment circuits 21a and 21b have the same functions as the adjustment circuits 11a and 11b in the random number generation circuit 10 of the first embodiment.
The random number generator 22 includes latch circuits 22a1, 22a2, 22a3, inverter circuits 22b1, 22b2, 22b3, AND (logical product) circuits 22c1, 22c2, 22c3, 22c4, 22c5, and OR (logical sum) circuits 22d1, 22d2.

  Each of the latch circuits 22a1 to 22a3 includes a data terminal (denoted as “D”) that receives the data signal dt, a clock terminal (denoted as “CK”) that receives the clock signal clk, and an output terminal (“Q”). ”). The latch circuits 22a1 to 22a3 have the same function as the latch circuits 12a1 to 12an in the random number generation circuit 10 of the first embodiment.

  In the random number generation circuit 20 of the second embodiment, an output circuit 12b and a detection circuit in the random number generation circuit 10 of the first embodiment are configured by inverter circuits 22b1 to 22b3, AND circuits 22c1 to 22c5, and OR circuits 22d1 and 22d2. The same function as 12c is realized.

  Inverter circuit 22b1 inverts the logic level of the output value of latch circuit 22a1, inverter circuit 22b2 inverts the logic level of the output value of latch circuit 22a2, and inverter circuit 22b3 inverts the logic level of the output value of latch circuit 22a3. Invert.

  The AND circuit 22c1 outputs a logical product operation result of the output value of the latch circuit 22a1, the output value of the inverter circuit 22b2, and the output value of the inverter circuit 22b3. The AND circuit 22c2 outputs a logical product operation result of the output value of the latch circuit 22a2, the output value of the inverter circuit 22b1, and the output value of the inverter circuit 22b3. The AND circuit 22c3 outputs a logical product operation result of the output value of the latch circuit 22a3, the output value of the inverter circuit 22b1, and the output value of the inverter circuit 22b2. The AND circuit 22c4 outputs a logical product operation result of the output values of the latch circuits 22a1 to 22a3. The AND circuit 22c5 outputs a logical product operation result of the output values of the inverter circuits 22b1 to 22b3.

  The OR circuit 22d1 outputs a logical sum operation result of the output values of the AND circuits 22c1 to 22c4. The OR circuit 22d2 outputs a logical sum operation result of the output values of the AND circuits 22c4 and 22c5.

  The output value of the OR circuit 22d1 is the output value RND of the random number generator 22, and the output value of the OR circuit 22d2 is a detection result match indicating whether all of the latch circuits 22a1 to 22a3 output the same value.

  The control circuit 23 has the same function as the control circuit 13 in the random number generation circuit 10 according to the first embodiment. The control circuit 23 may be controlled from the outside of the random number generation circuit 20 by the control signal CTRL. The control circuit 23 may output a signal ERR indicating an abnormal state when the output value RND is the same value for the predetermined number of cycles of the clock signal CLK.

FIG. 3 is a diagram illustrating an example relationship between the output value of each latch circuit, the detection result match, and the output value RND.
FIG. 3 shows the relationship between the output values of the latch circuits 22a1 to 22a3, the output value RND of the OR circuit 22d1, and the detection result match output from the OR circuit 22d2.

  When the output values of the latch circuits 22a1 to 22a3 are all at the L level, the detection result match is at the H level and the output value RND is at the L level. When two of the output values of the latch circuits 22a1 to 22a3 are L level and one is H level, the detection result match is L level and the output value RND is H level. When two of the output values of the latch circuits 22a1 to 22a3 are H level and one is L level, the detection result match is L level and the output value RND is L level. When the output values of the latch circuits 22a1 to 22a3 are all at the H level, the detection result match is at the H level and the output value RND is at the H level.

  Based on the combination of the detection result match and the output value RND, the control circuit 23 can determine a random number generation factor based on the output value RND. Hereinafter, a case where the sampling timing is adjusted within the metastable period when the data signal dt transitions from the L level to the H level will be described.

  When the detection result match is H level and the output value RND is L level, it indicates that the phase of the clock signal clk is advanced with respect to the data signal dt due to skew, and the sampling timing is not within the metastable period. Therefore, the random number generation factor is not a metastability but a skew. Skew is variation in delay time caused by noise due to voltage change or temperature change. When the output value RND as described above is obtained at each sampling timing, the output value RND is biased to an L level value, and a poor quality random number is obtained. For this reason, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2 (which may be either) so as to delay the phase of the clock signal clk with respect to the data signal dt.

  When the detection result match is H level and the output value RND is H level, it indicates that the phase of the clock signal clk is delayed with respect to the data signal dt due to skew, and the sampling timing is not within the metastable period. Therefore, the random number generation factor is not a metastability but a skew. When the output value RND as described above is obtained at each sampling timing, the output value RND is biased to an H level value, and a poor quality random number is obtained. Therefore, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2 (whichever is acceptable) so as to advance the phase of the clock signal clk.

  When the detection result match is L level and the output value RND is L level or H level, the output value RND is affected by skew or metastability. That is, the random number generation factor is skew or metastability.

In order to make the random number generation factor metastability, the control circuit 23 adjusts the sampling timing as follows, for example.
FIG. 4 is a diagram illustrating an example of adjusting the sampling timing.

  FIG. 4 shows four examples of adjusting the sampling timing when the data signal dt transitions from the L level to the H level. In the example of FIG. 4, the period ta in which the signal level of the data signal dt is equal to or lower than the voltage V1, the period tb in which the signal level of the data signal dt is higher than the voltage V1 and lower than the voltage V2, and the signal level of the data signal dt is A period tc in which the voltage is not less than V2 and not more than voltage V3 is shown. Further, a period td in which the signal level of the data signal dt is higher than the voltage V3 and lower than the voltage V4, and a period te in which the signal level of the data signal dt is equal to or higher than the voltage V4 are shown. The voltages V1 to V4 are determined according to the characteristics of the latch circuits 22a1 to 22a3, for example. The periods ta to te are determined according to, for example, the voltages V1 to V4 and the load capacitance of the data terminals of the latch circuits 22a1 to 22a3.

  When the sampling timing is located within the period ta, the output values of the latch circuits 22a1 to 22a3 are all at the L level. When the sampling timing is located within the period tb, the output values of the latch circuits 22a1 to 22a3 are likely to be at the L level, but at least one output value of the latch circuits 22a1 to 22a3 is at the H level due to metastability. There is a case. When the sampling timing is located within the period tc, the latch circuits 22a1 to 22a3 output the H level output value and the L level output value with substantially the same probability due to metastability. When the sampling timing is located within the period td, the output values of the latch circuits 22a1 to 22a3 are likely to be at the H level, but at least one output value of the latch circuits 22a1 to 22a3 is at the L level due to metastability. There is a case. When the sampling timing is located within the period te, the output values of the latch circuits 22a1 to 22a3 are all at the H level.

  Of the periods ta to tc, the period suitable for generating a high-quality random number is the period tc in which the latch circuits 22a1 to 22a3 are in the metastability state. For this reason, the control circuit 23 sets the period tc as a target period (setting target period) for setting the sampling timing, and adjusts the sampling timing by, for example, the following four timing setting methods.

  (Method 1) When the sampling timing is within the period ta, the detection result match is H level and the output value RND is L level. In this case, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2, and performs timing setting for delaying the phase of the clock signal clk with respect to the data signal dt.

  Although it is desirable to make the amount of phase changed by one timing setting smaller in order to appropriately match the sampling timing with the set target period, if it is made too small, the adjustment time becomes longer.

  Note that the control circuit 23 stores the values of the adjustment signals tsel1 and tsel2 used in at least the previous timing setting in a not-shown storage unit (for example, a register).

  By delaying the phase of the clock signal clk, when the detection result match is changed to the L level and the output value RND is changed to the H level, the control circuit 23 further changes the values of the adjustment signals tsel1 and tsel2 to the data signal dt. In contrast, the phase of the clock signal clk is delayed. This is because when the detection result match is L level and the output value RND is H level, the sampling timing may be within the period tc which is the set target period, but may also be within the period tb.

  By delaying the phase of the clock signal clk, when the detection result match changes to L level and the output value RND changes to L level, it means that the sampling timing is within the period tc or the period td. For this reason, the control circuit 23 uses the values of the adjustment signals tsel1 and tsel2 that were used in the timing setting performed immediately before the timing setting performed this time, so that each subsequent sampling timing can be accurately set. It can be adjusted to the target period.

  (Method 2) In Method 2, for example, by delaying the phase of the clock signal clk in Method 1, the detection result match does not change to the L level and the detection result match does not change to the L level. This is performed when the output value RND changes to H level.

  The control circuit 23 stores the values of the adjustment signals tsel1 and tsel2 when the detection result match is H level and the output value RND is H level in the storage unit. Then, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2, and advances the phase of the clock signal clk with respect to the data signal dt until the detection result match changes to H level and the output value RND changes to L level. The control circuit 23 stores the values of the adjustment signals tsel1 and tsel2 when the detection result match is changed to the H level and the output value RND is changed to the L level in the storage unit.

  The control circuit 23 sets the values of the adjustment signals tsel1 and tsel2 at the timing when the detection result match becomes H level and the output value RND becomes L level, and when the detection result match becomes H level and the output value RND becomes H level. Obtained from the storage unit. Then, the control circuit 23 obtains values of the adjustment signals tsel1 and tsel2 that adjust the sampling timing to an intermediate timing between both timings based on the acquired value. For example, the control circuit 23 calculates the average of the values of the adjustment signals tsel1 and tsel2 at both timings, thereby determining the values of the adjustment signals tsel1 and tsel2 that match the sampling timing to the intermediate timing between the two timings.

  Then, the control circuit 23 supplies the calculated values of the adjustment signals tsel1 and tsel2 to the adjustment circuits 21a and 21b thereafter, so that the subsequent sampling timings are substantially at the center of the periods tb to td. That is, the sampling timing can be adjusted within the set target period that is the metastable period.

  (Method 3) When the sampling timing in the initial state is within the period te, the detection result match is H level and the output value RND is H level. In that case, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2 and performs timing setting for advancing the phase of the clock signal clk with respect to the data signal dt.

  When the detection result match is changed to the L level and the output value RND is changed to the L level by advancing the phase of the clock signal clk, the control circuit 23 further changes the values of the adjustment signals tsel1, tsel2, and the data signal dt. Advances the phase of the clock signal clk. This is because when the detection result match is L level and the output value RND is L level, the sampling timing may be within the period tc, which is the set target period, or may be within the period td.

  By advancing the phase of the clock signal clk, when the detection result match changes to L level and the output value RND changes to H level, it means that the sampling timing is within the period tc or the period tb. For this reason, the control circuit 23 uses the values of the adjustment signals tsel1 and tsel2 that were used in the timing setting performed immediately before the timing setting performed this time, so that each subsequent sampling timing can be accurately set. It can be adjusted to the target period.

  (Method 4) In Method 4, for example, the phase of the clock signal clk is advanced in Method 3, so that the detection result match does not change to L level and the output value RND does not change to H level, and the detection result match is H level. This is performed when the output value RND changes to L level.

  The control circuit 23 stores the values of the adjustment signals tsel1 and tsel2 when the detection result match is changed to H level and the output value RND is changed to L level in the storage unit. Then, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2, and delays the phase of the clock signal clk with respect to the data signal dt until the detection result match is changed to H level and the output value RND is changed to H level. The control circuit 23 stores the values of the adjustment signals tsel1 and tsel2 when the detection result match is changed to H level and the output value RND is changed to H level in the storage unit.

  The control circuit 23 sets the values of the adjustment signals tsel1 and tsel2 at the timing when the detection result match becomes the H level and the output value RND becomes the H level and the timing when the detection result match becomes the H level and the output value RND becomes the L level. Obtained from the storage unit. Then, the control circuit 23 obtains values of the adjustment signals tsel1 and tsel2 that adjust the sampling timing to an intermediate timing between both timings based on the acquired value. For example, the control circuit 23 calculates the average of the values of the adjustment signals tsel1 and tsel2 at both timings, thereby determining the values of the adjustment signals tsel1 and tsel2 that match the sampling timing to the intermediate timing between the two timings.

  Then, the control circuit 23 supplies the calculated values of the adjustment signals tsel1 and tsel2 to the adjustment circuits 21a and 21b thereafter, so that the subsequent sampling timings are substantially at the center of the periods tb to td. That is, the sampling timing can be adjusted within the set target period that is the metastable period.

Hereinafter, the flow of processing for adjusting the sampling timing using the above four methods will be described with reference to flowcharts.
FIG. 5 is a flowchart showing an example of the flow of sampling timing adjustment processing.

The control circuit 23 supplies initial values of the adjustment signals tsel1 and tsel2 to the adjustment circuits 21a and 21b to initialize the adjustment circuits 21a and 21b (step S1).
Thereafter, the control circuit 23 detects the detection result match and the output value RND output from the random number generator 22 using the data signal dt and the clock signal clk output from the adjustment circuits 21a and 21b in the initial state. Then, the control circuit 23 determines a period including the sampling timing from the detection result match and the output value RND (step S2).

Then, the control circuit 23 performs timing setting by the method 1 or the method 3 shown in FIG. 4 according to the determined period (step S3).
The control circuit 23 determines whether the sampling timing can be set within the metastable period by the timing setting by the method 1 or the method 3 (step S4). When the control circuit 23 determines that the above setting is possible, the control process ends.

If the control circuit 23 determines that the above setting is not possible, the control circuit 23 performs timing setting by the method 2 or 4 shown in FIG. 4 (step S5), and ends the adjustment process.
FIG. 6 is a flowchart illustrating an example of each process in FIG.

  As an example of the initialization process in step S1 of FIG. 5, the control circuit 23 supplies initial values of the adjustment signals tsel1 and tsel2 to the adjustment circuits 21a and 21b to set an offset delay in the adjustment circuits 21a and 21b (step S10). ). As a result, the data signal dt and the clock signal clk become signals delayed by the offset delay with respect to the clock signal CLK.

The following process is performed as an example of the process of step S2 of FIG.
The adjustment circuits 21a and 21b receive the clock signal CLK, and the latch circuits 22a1 to 22a3 take in the data signal dt output from the adjustment circuit 21a at the sampling timing based on the clock signal clk output from the adjustment circuit 21b (step S11).

  The control circuit 23 determines a period including the sampling timing from the detection result match output from the random number generator 22 and the output value RND (step S12). When the detection result match is at the H level and the output value RND is at the L level, the control circuit 23 determines that the sampling timing is within the period ta shown in FIG. 4, and performs the process of step S14.

  When the detection result match is L level and the output value RND is L level or H level, the control circuit 23 determines that the sampling timing is within the period tb to td shown in FIG. In that case, the control circuit 23 adjusts the sampling timing by changing the values of the adjustment signals tsel1 and tsel2 so that the sampling timing moves within the period ta (step S13).

  If the detection result match is H level and the output value RND is H level, the control circuit 23 determines that the sampling timing is within the period te shown in FIG. In this case, timing setting is performed by the method 3 or the method 4 shown in FIG. 4, but the illustration is omitted in FIG.

The following processing is performed as an example of the processing of steps S3 and S4 in FIG.
The control circuit 23 changes the values of the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk with respect to the data signal dt (step S14).

  Then, the adjustment circuits 21a and 21b receive the clock signal CLK, and the latch circuits 22a1 to 22a3 capture the data signal dt output from the adjustment circuit 21a at the sampling timing based on the clock signal clk output from the adjustment circuit 21b (step S15). .

Then, the control circuit 23 determines whether or not the detection result match is L level and the output value RND is L level (step S16).
When the detection result match is L level and the output value RND is L level, the sampling timing can be set within the metastable period by the timing setting of the method 1 in FIG. In this case, the control circuit 23 sets the values of the adjustment signals tsel1 and tsel2 used in the previous timing setting (step S17), and ends the adjustment process. The values of the adjustment signals tsel1, tsel2 set in step S17 are stored in, for example, the storage unit, and thereafter the stored values are continuously set in the adjustment circuits 21a, 21b.

  If it is determined in step S16 that at least one of the detection result match and the output value RND is at the H level, the control circuit 23 determines whether the detection result match is at the H level and the output value RND is at the H level. It is determined whether or not (step S18). When at least one of the detection result match and the output value RND is at L level, the processing from step S14 is repeated.

  If it is determined in step S18 that both the detection result match and the output value RND are at the H level, the sampling timing cannot be set within the metastable period by the timing setting of the method 1 in FIG. In that case, the following process is performed as an example of the process of step S5 of FIG.

  The control circuit 23 causes the storage unit to store the values of the adjustment signals tsel1 and tsel2 used for timing setting when both the detection result match and the output value RND become H level (step S19).

Thereafter, the control circuit 23 changes the values of the adjustment signals tsel1 and tsel2 so that the phase of the clock signal clk is advanced with respect to the data signal dt (step S20).
Then, the adjustment circuits 21a and 21b receive the clock signal CLK, and the latch circuits 22a1 to 22a3 take in the data signal dt output from the adjustment circuit 21a at the sampling timing based on the clock signal clk output from the adjustment circuit 21b (step S21). .

  Then, the control circuit 23 determines whether or not the detection result match is H level and the output value RND is L level (step S22). If the detection result match is L level or the output value RND is H level, the processing from step S20 is repeated.

  When the detection result match is H level and the output value RND is L level, the control circuit 23 stores the values of the adjustment signals tsel1, tsel2 used for the timing setting at that time in the storage unit (step S23). ).

  And the control circuit 23 acquires the value of adjustment signal tsel1, tsel2 memorize | stored by the process of step S19, S23 from a memory | storage part. Based on the acquired values, the values of the adjustment signals tsel1 and tsel2 for adjusting the sampling timing to the middle of the timings at which the determination processing in steps S18 and S22 is “YES” are obtained. Then, the control circuit 23 sets the values of the obtained adjustment signals tsel1 and tsel2 in the adjustment circuits 21a and 21b (step S24). Then, the control circuit 23 ends the adjustment process. The values of the adjustment signals tsel1, tsel2 set in the process of step S24 are stored in, for example, the storage unit, and thereafter the stored values are continuously set in the adjustment circuits 21a, 21b.

  Although not shown in FIG. 6, when the period including the sampling timing is determined to be the period te in the process of step S <b> 12, steps S <b> 14, S <b> 16, S <b> 18, S <b> 20, and S <b> 22 will be described below from among steps S <b> 14 to S < The process changed as follows is performed.

  First, the control circuit 23 performs a process of changing the adjustment signals tsel1 and tsel2 so that the phase of the clock signal clk is advanced with respect to the data signal dt instead of the process of step S14.

  In addition, the control circuit 23 performs a process of determining whether or not the detection result match is L level and the output value RND is H level instead of the process of step S16. When the detection result match is L level and the output value RND is H level, the control circuit 23 performs the process of step S17.

  When the detection result match is H level or the output value RND is L level, the control circuit 23 determines whether the detection result match is H level and the output value RND is L level instead of the process of step S18. Processing to determine whether or not. If the detection result match is at the H level and the output value RND is at the L level, the control circuit 23 performs the process of step S19.

  When the detection result match is L level or the output value RND is H level, the control circuit 23 changes the adjustment signals tsel1 and tsel2 so that the phase of the clock signal clk is advanced with respect to the data signal dt. repeat.

  Further, the control circuit 23 performs a process of changing the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk with respect to the data signal dt instead of the process of step S20.

  Further, the control circuit 23 determines whether or not both the detection result match and the output value RND are at the H level, instead of the process of step S22. When both the detection result match and the output value RND are at the H level, the control circuit 23 performs the process of step S23. When at least one of the detection result match and the output value RND is at the L level, the control circuit 23 repeats the process of changing the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk.

FIG. 7 is a timing chart showing an example of a time change of each signal when the random number generation circuit generates a random number.
FIG. 7 shows clock signals CLK and clk, data signal dt, output values of latch circuits 22a1 to 22a3, detection result match, output value RND, random number generation factor, control signal CTRL, adjustment signals tsel1, tsel2, and time of signal ERR. An example of the change is shown. In FIG. 7, the output values of the latch circuits 22a1 to 22a3 are schematically shown collectively.

  The clock signal clk and the data signal dt are generated by adjusting the phase of the clock signal CLK by the adjusting circuits 21a and 21b. Then, the sampling timing by the clock signal clk is adjusted within the metastable period by the method shown in FIGS. 4 to 6, so that the output values of the latch circuits 22 a 1 to 22 a 3 are changed to H after passing through an indefinite period. Level or L level value.

  The detection result match and the output value RND also become H level or L level values after an indefinite period according to changes in the output values of the latch circuits 22a1 to 22a3. As described above, the random number generation factor becomes metastability by adjusting the sampling timing by the clock signal clk within the metastable period.

  The control signal CTRL does not change during random number generation. In FIG. 7, the change of the adjustment signals tsel1 and tsel2 during the adjustment of the sampling timing is not shown, but the control circuit 23 does not change the adjustment signals tsel1 and tsel2 after the adjustment of the sampling timing. The control circuit 23 sets the signal ERR to L level when the random number generation factor is metastability, and sets the signal ERR to H level when the random number generation factor is skew.

  Note that when the output value RND is the same value for a predetermined number of cycles of the clock signal CLK, the control circuit 23 may notify the outside that the signal ERR is at the H level and is in an abnormal state.

  As described above, the control circuit 23 can make the random number generation factor metastability by adjusting the sampling timing within the period tc which is a metastable period based on the detection result match and the output value RND. For this reason, the output value RND shown in FIG. 7 is a high-quality random number with reduced value deviation and the like.

(Third embodiment)
FIG. 8 is a diagram illustrating an example of a random number generation circuit according to the third embodiment. In FIG. 8, the same elements as those in the random number generation circuit 20 of the second embodiment shown in FIG.

  The random number generation circuit 30 according to the third embodiment varies the delay amount of the clock signal clk supplied to each of the random number generation units 30a0, 30a1, ..., 30ai, ..., 30an and the random number generation units 30a0 to 30an. Delay circuits 30b1, 30b2,..., 30bn are included.

  The random number generation unit 30a0 includes an ExOR (exclusive OR) circuit 31a0 in addition to the elements included in the random number generation unit 22 of the random number generation circuit 20 of the second embodiment. The ExOR circuit 31a0 outputs an exclusive OR operation result of the output value of the OR circuit 22d1 and the input value R0 supplied from the control circuit 30c. The output value of the ExOR circuit 31a0 is supplied to the ExOR circuit 31a1 of the random number generation unit 30a1 at the subsequent stage instead of the input value R0.

At the time of random number generation, the input value R0 is fixed to one of the H level and the L level. When the random number generation circuit 30 is tested, the input value R0 may be changed.
The other random number generation units 30a1 to 30an are circuits similar to the random number generation unit 30a0.

  In such a random number generation circuit 30, the output value of the ExOR circuit 31an of the last-stage random number generation unit 30an becomes the output value RND. Each of the random number generation units 30a0 to 30an outputs the detection result match output from the random number generation unit 22 of the random number generation circuit 20 of the second embodiment, the detection result corresponding to the output value RND, and the output value to the control circuit 30c. To supply. For example, the random number generation unit 30a0 supplies the detection result match0 and the output value RND0 to the control circuit 30c.

  The control circuit 30c, for example, adjusts the adjustment signal tsel1, based on the detection result matchi and the output value RNDi supplied from the random number generation unit 30ai whose delay with respect to the clock signal clk is an intermediate value among the random number generation units 30a0 to 30an. Determine the value of tsel2. The values of the adjustment signals tsel1 and tsel2 are determined by the method shown in FIGS. 4 to 6 so that the sampling timing by the clock signal clk reaching the random number generation unit 30ai is within the metastable period.

  In the random number generation circuit 30, by appropriately setting the delay time by the delay circuits 30b1 to 30bn, the sampling timing in any of the random number generation units 30a0 to 30an is set to the metastable period even if a skew occurs due to a change in operating conditions or the like. The possibility of becoming inside increases. That is, the probability of random numbers generated by metastability can be increased.

(Fourth embodiment)
FIG. 9 is a diagram illustrating an example of a random number generation circuit according to the fourth embodiment. In FIG. 9, the same elements as those of the random number generation circuit 30 of the third embodiment shown in FIG.

The random number generation circuit 40 according to the fourth embodiment includes an LFSR (Linear Feedback Shift Register) 41 having an input terminal in, a clock terminal ck, and an output terminal out.
The clock signal CLK is supplied to the clock terminal ck, and the output value of the ExOR circuit 31an of the random number generation unit 30an is supplied to the input terminal in. An output value RND that is a random number or a pseudo-random number is output from the output terminal out.

FIG. 10 is a diagram illustrating an example of the LFSR.
The LFSR 41 includes a 16-bit shift register 41a and ExOR circuits 41b, 41c, 41d, and 41e.

  The 16-bit shift register 41a takes in the output value of the ExOR circuit 41b at a timing synchronized with the clock signal CLK supplied to the clock terminal ck. The 16-bit shift register 41a shifts bit by bit from “bit0” to “bit15” at a timing synchronized with the clock signal CLK. Each of “bit0” to “bit15” represents a register.

  The ExOR circuit 41b outputs an exclusive OR operation result of the output value RNDn supplied to the input terminal in and the output value (feedback signal) of the ExOR circuit 41e. The ExOR circuit 41c outputs an exclusive OR operation result of the output value of the register represented by “bit13” and the output value of the register represented by “bit15”. The ExOR circuit 41d outputs an exclusive OR operation result of the output value of the register represented by “bit12” and the output value of the ExOR circuit 41c. The ExOR circuit 41e supplies an exclusive OR operation result of the output value of the register represented by “bit10” and the output value of the ExOR circuit 41d as a feedback signal to the ExOR circuit 41b.

By the way, the LFSR that does not have the ExOR circuit 41b and inputs the output value of the ExOR circuit 41e to the 16-bit shift register 41a outputs a pseudo-random number having periodicity.
On the other hand, in the LFSR 41 shown in FIG. 10, the output value of the ExOR circuit 31an of the random number generation unit 30an is supplied to one input terminal of the ExOR circuit 41b. Since the output value becomes a random number due to metastability during the period of the pseudo random number, the output value RND output from the LFSR 41 becomes a random number having no periodicity. That is, it can be avoided that the output value RND becomes a pseudo-random number. For this reason, random numbers with good quality can be output.

  In the random number generation circuit 30 according to the third embodiment, random numbers due to metastability may not be output in each cycle of the clock signal CLK. However, the random number generation circuit 40 having the LFSR 41 as described above may Random numbers can be output at each cycle of CLK. That is, the random number generation rate can be improved.

  When the output value RND output from the LFSR 41 is the same value as the predetermined number of cycles of the clock signal CLK, the control circuit 30c sets the signal ERR to the H level to notify the outside that it is in an abnormal state. Good. In addition, the control circuit 30c detects whether or not the output value of the random number generation unit 30an supplied to the input terminal in of the LFSR 41 changes, and the output value is the same number of cycles of the clock signal CLK. Alternatively, the signal ERR may be set to H level.

Further, the random number generation circuit 20 of the second embodiment and the LFSR 41 may be combined so that the output value of the random number generation unit 22 is supplied to the input terminal in of the LFSR 41.
Further, the above LFSR 41 is an example and is not limited to the circuit configuration of FIG. For example, various modifications such as using a 32-bit shift register instead of the 16-bit shift register 41a are possible.

(Fifth embodiment)
By the way, the longer the metastable period, the easier it is to match the sampling timing. Further, even if the clock signal clk and the data signal dt are skewed due to temperature, voltage noise, or the like, if the metastable period is long, the possibility that the sampling timing can be maintained within the metastable period is increased.

  Hereinafter, a random number generation circuit capable of extending the metastable period will be described. The random number generation circuit of the fifth embodiment shown below can be combined with the random number generation circuits 10, 20, 30, and 40 of the first to fourth embodiments described above. It will be described later.

FIG. 11 is a diagram illustrating an example of a random number generation circuit according to the fifth embodiment.
The random number generation circuit 50 includes an adjustment unit 51 including adjustment circuits 51 a and 51 b, a load capacitance variable circuit 52, a latch circuit 53, and a control circuit 54.

  The adjustment unit 51 has the same function as the adjustment unit 11 in the random number generation circuit 10 of the first embodiment. In the following description, it is assumed that the input signal is the clock signal CLK, but the input signal is not limited to the clock signal CLK.

  The adjustment unit 51 outputs the data signal dt and the clock signal clk based on the clock signal CLK, and adjusts the phase of at least one of the data signal dt and the clock signal clk based on the adjustment signals tsel1 and tsel2.

  The load capacitance variable circuit 52 gradually increases the load capacitance of the terminal to which the data signal dto is supplied in the latch circuit 53 from the start timing determined based on the selection signal csel supplied from the control circuit 54. The load capacitance variable circuit 52 includes a buffer 52a, a delay selection circuit 52b, and capacitance circuits 52c1 to 52cn.

The buffer 52a outputs a data signal dto obtained by blunting the waveform of the data signal dt and delaying the data signal dt.
The delay selection circuit 52b enables the capacitance circuits 52c1 to 52cn and adds a load capacitance at a timing based on the data signal dt and the selection signal csel.

The capacitor circuits 52c1 to 52cn are connected to a wiring through which the data signal dto propagates, and are enabled or disabled by the delay selection circuit 52b.
The latch circuit 53 receives the data signal dto and the clock signal clk, and outputs an H-level or L-level output value RND based on the signal level of the data signal dto at the sampling timing based on the clock signal clk.

  The control circuit 54 is a specific purpose electronic circuit such as an ASIC or FPGA. The control circuit 54 may be a processor as an arithmetic processing unit such as a CPU or a DSP. The processor executes a program stored in a memory such as a RAM. The control circuit 54 may be a set of a plurality of processors.

  The control circuit 54 outputs the adjustment signals tsel1, tsel2 and the selection signal csel based on the output value RND. The control circuit 54 may be controlled from the outside of the random number generation circuit 50 by the control signal CTRL. The control circuit 54 may output a signal ERR indicating an abnormal state when the output value RND is the same value as the predetermined number of cycles of the clock signal CLK.

FIG. 12 is a diagram illustrating an example of the delay selection circuit and the capacitor circuit.
The delay selection circuit 52b includes delay circuits 60a1, 60a2, ..., 60am, a selection circuit 60b, delay circuits 60c1 to 60c (n-1), OR circuits 60d1, 60d2, ..., 60dn, AND circuits 60e1, 60e2, ..., 60en. Have

  The delay circuits 60a1 to 60am are connected in series, and the data signal dt is supplied to the head delay circuit 60a1. The data signal dt delayed by each of the delay circuits 60a1 to 60am is supplied to the selection circuit 60b as the data signals dt1 to dtm.

  The selection circuit 60b selects any one of the data signals dt, dt1 to dtm based on the signals ct0, ct1,..., Ctm and outputs the data signal dts. The signals ct0 to ctm are signals included in the selection signal csel.

  The delay circuits 60c1 to 60c (n-1) are connected in series, and the data signal dts is supplied to the head delay circuit 60c1. The data signal dts delayed by each of the delay circuits 60c1 to 60c (n-1) is supplied to one input terminal of the OR circuits 60d2 to 60dn.

  The data signal dts is supplied to one input terminal of the OR circuit 60d1. The signal cton is supplied to the other input terminals of the OR circuits 60d1 to 60dn. The output signals of the OR circuits 60d1 to 60dn are supplied to one input terminal of the AND circuits 60e1 to 60en.

  A signal ctoff is supplied to the other input terminals of the AND circuits 60e1 to 60en. Output signals of the AND circuits 60e1 to 60en are supplied to the capacitor circuits 52c1 to 52cn. The signals cton and ctoff are signals included in the selection signal csel.

  The capacitor circuit 52c1 includes an inverter circuit 61, transistors 62, 63, and 64, and a capacitor 65. The transistors 62 and 63 are n-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and the transistor 64 is a p-channel MOSFET.

  The input terminal of the inverter circuit 61 is connected to the output terminal of the AND circuit 60e1, and the output terminal of the inverter circuit 61 is connected to the gate terminals of the transistors 62 and 64. The source terminal of the transistor 62 is grounded, and the drain terminal of the transistor 62 is connected to the source terminal of the transistor 63, the drain terminal of the transistor 64, and one terminal of the capacitor 65. The drain terminal of the transistor 63 and the source terminal of the transistor 64 are connected to a wiring through which the data signal dto propagates. The other terminal of the capacitor 65 is grounded.

The capacitor circuits 52c2 to 52cn are similar to the capacitor circuit 52c1.
When the signals cton and ctoff are both at the H level, the output values of the AND circuits 60e1 to 60en are also at the H level. When the output values of the AND circuits 60e1 to 60en are at the H level, the transistor 62 is turned off and the transistors 63 and 64 are turned on, so that the capacitor 65 is electrically connected to the wiring through which the data signal dto propagates. . That is, the capacitance circuits 52c1 to 52cn are effective.

  When the signal ctoff is at the L level, the output values of the AND circuits 60e1 to 60en are also at the L level regardless of the value of the signal cton. When the output values of the AND circuits 60e1 to 60en are at the L level, the transistor 62 is turned on and the transistors 63 and 64 are turned off, so that the capacitor 65 is electrically disconnected from the wiring through which the data signal dto propagates. . That is, the capacitance circuits 52c1 to 52cn are disabled.

  When the signal cton is at the L level and the signal ctoff is at the H level, the output values of the AND circuits 60e1 to 60en sequentially become the H level when the data signal dts transitions to the H level. As a result, the capacitance circuits 52c1 to 52cn become effective in order from the capacitance circuit 52c1.

  FIG. 13 is a diagram illustrating an example of setting the sampling timing and an example of setting the load capacitance by the load capacitance variable circuit. The voltage range Vmet is a voltage range of the data signal dto in which the latch circuit 53 is in a metastability state.

  First, the control circuit 54 sets the signal ctoff shown in FIG. 12 to the L level, invalidates the capacitance circuits 52c1 to 52cn, and does not add a load capacitance. Then, for example, the control circuit 54 changes the adjustment signals tsel1 and tsel2 to delay the phase of the clock signal clk from the state where the phase of the clock signal clk is advanced from the data signal dto. The control circuit 54 detects the output value RND, and stores the values of the adjustment signals tsel1 and tsel2 at the timing t10 when the output value RND changes from the L level to the H level in a storage unit (not shown).

  Thereafter, the control circuit 54 sets both the signals ctoff and cton shown in FIG. 12 to the H level, enables the capacitance circuits 52c1 to 52cn, and adds the load capacitance. Then, similarly to the above, the control circuit 54 changes the adjustment signals tsel1 and tsel2, for example, and delays the phase of the clock signal clk from the state where the phase of the clock signal clk is advanced from the data signal dto. The control circuit 54 detects the output value RND, and stores the values of the adjustment signals tsel1 and tsel2 at the timing t12 when the output value RND changes from the L level to the H level in a storage unit (not shown).

  Then, based on the stored values of the adjustment signals tsel1 and tsel2, the control circuit 54 calculates the values of the adjustment signals tsel1 and tsel2 for adjusting the sampling timing to the middle of the timings t10 and t12 (timing t11). For example, the control circuit 54 obtains the values of the adjustment signals tsel1 and tsel2 that match the sampling timing with the timing t11 by obtaining the average of the values of the adjustment signals tsel1 and tsel2 at the timings t10 and t12. The obtained value is stored in the storage unit, for example.

  The phase of the clock signal clk is advanced from the state in which the phase of the clock signal clk is delayed from that of the data signal dto, and the sampling timing t11 is determined using the adjustment signals tsel1 and tsel2 of the timing at which the output value RND changes. May be.

  Next, the control circuit 54 changes the values of the adjustment signals tsel1 and tsel2, and adjusts the sampling timing to the timing t10 again. Then, as shown in FIG. 13, the control circuit 54 changes the signals ct0 to ctm and changes the signal ct0 to ctm in a state where the signal ctoff is set to the H level and the signal cton is set to the L level. I'll speed up. A waveform 66a shows a change in the data signal dto when the load capacitor addition start timing is most delayed, and a waveform 66b shows a change in the data signal dto when the load capacitor addition start timing is earliest. The load capacity is increased stepwise by the delay circuits 60c1 to 60c (n-1).

  The control circuit 54 detects the output value RND, and determines the addition start timing based on the values of the signals ct0 to ctm when the output value RND changes from the H level to the L level. The control circuit 54 stores the values of the signals ct0 to ctm at this time in the storage unit. For example, the waveform 66c shows a change in the data signal dto when the load capacitance is added at the addition start timing based on the values of the signals ct0 to ctm stored in the storage unit.

  At the time of subsequent random number generation, the control circuit 54 uses the values of the adjustment signals tsel1 and tsel2 for adjusting the sampling timing to the timing t11 and the values of the signals ct0 to ctm at the determined additional start timing obtained by the above method. .

  FIG. 14 is a diagram showing a metastable period when the load capacity addition start timing is determined as shown in FIG. In addition to the metastable period tm1 of the waveform 66c shown in FIG. 13, FIG. 14 shows the metastable period tm2 when there is no load capacity addition shown in FIG. 13 and the case where the load capacity is always added. The metastable period tm3 is also illustrated.

  When the load capacitances are always added by the capacitance circuits 52c1 to 52cn, the rise of the data signal dto becomes gentle, and the metastable period tm3 that is the voltage range Vmet becomes longer than when the load capacitance is not added. However, the period from the start of the rise of the data signal dto until the voltage range Vmet is entered is relatively long.

  On the other hand, in the waveform 66c obtained by determining the load capacitor addition start timing as shown in FIG. 13, the load capacitance is always added during the period from the start of the rise of the data signal dto to the voltage range Vmet. It becomes shorter than the case where it is doing. As a result, the metastable period tm1 can be made longer than the metastable period tm3 when the same load capacity is always added.

  The parameters such as the number and delay time of the delay circuits 60a1 to 60am and 60c1 to 60c (n-1) and the number and capacitance value of the capacitor circuits 52c1 to 52cn shown in FIG. 12 are calculated by circuit simulation, for example. It is determined based on the result. For example, in the circuit simulation, the above parameters are determined depending on how long the adjustment accuracy and the metastable period to be set are increased.

A flow of setting processing of sampling timing and load capacity addition start timing will be described below with reference to flowcharts.
FIG. 15 is a flowchart illustrating an exemplary flow of setting processing of sampling timing and load capacity addition start timing.

  The control circuit 54 outputs initial values of the adjustment signals tsel1 and tsel2 that make the phase of the clock signal clk advance from the data signal dto without adding a load capacitance, and initializes the adjustment circuits 51a and 51b. (Step S30).

  Thereafter, the control circuit 54 changes the adjustment signals tsel1 and tsel2 to delay the phase of the clock signal clk (change the sampling timing). Then, the control circuit 54 detects the output value RND, and stores the values of the adjustment signals tsel1 and tsel2 set at the timing when the output value RND changes from the L level to the H level in the storage unit (step S31).

  Further, the control circuit 54 outputs initial values of the adjustment signals tsel1 and tsel2 for setting the phase of the clock signal clk ahead of the data signal dto in the state where the load capacitance is added, and the adjustment circuits 51a and 51b are output. Initialization is performed (step S32).

Thereafter, again, the control circuit 54 performs the same process as step S31 (step S33).
Next, based on the values of the adjustment signals tsel1 and tsel2 stored in the processes of steps S31 and S33, the control circuit 54 determines the value of the adjustment signal whose sampling timing is an intermediate timing between the two timings (step). S34).

Thereafter, the control circuit 54 sets the input load addition start timing (step S35).
16 and 17 are flowcharts showing an example of each process of FIG.

  As an example of the initialization process in step S30 of FIG. 15, as shown in FIG. 16, the control circuit 54 firstly has a signal ct0 to ctm = “X”, a signal cton = “X”, and a signal ctoff = “L” ( L level) (step S40). “X” represents that it may be at the H level or the L level. Further, the control circuit 54 sets initial values of the adjustment signals tsel1 and tsel2 that advance the phase of the clock signal clk relative to the data signal dto in the adjustment circuits 51a and 51b (step S41).

Next, as an example of the process in step S31 in FIG. 15, the processes in steps S42 to S45 in FIG. 16 are performed.
The adjustment circuits 51a and 51b receive the clock signal CLK and output a data signal dt and a clock signal clk. The data signal dt is supplied to the load capacitance variable circuit 52. The latch circuit 53 takes in the data signal dto output from the variable load capacitance circuit 52 at the sampling timing based on the clock signal clk (step S42).

Then, the control circuit 54 determines whether or not the output value RND is at the H level (step S43).
When the output value RND is not at the H level, the control circuit 54 changes the adjustment signals tsel1 and tsel2 so as to delay the phase of the clock signal clk with respect to the data signal dto (step S44). After the process of step S44, the process of step S42 is performed again.

  When the output value RND is at the H level, the control circuit 54 stores the values of the adjustment signals tsel1, tsel2 set at the current sampling timing (for example, timing t10 in FIG. 13) in the storage unit (step S45).

  Next, as an example of the initialization process in step S32 of FIG. 15, as shown in FIG. 16, the control circuit 54 performs signals ct0 to ctm = “X”, signal cton = “H” (H level), signal ctoff. = "H" is set (step S46). Further, the control circuit 54 sets initial values of the adjustment signals tsel1 and tsel2 that advance the phase of the clock signal clk relative to the data signal dto in the adjustment circuits 51a and 51b (step S47).

  And the process of FIG.16 S48-S51 is performed as an example of the process of FIG.15 S33. The process of steps S48 to S51 is the same as the process of steps S42 to S45. However, the sampling timing at which the output value RND becomes H level (for example, timing t12 in FIG. 13) is different from the case where no load capacitance is added.

Thereafter, the following processing is performed as an example of the processing in step S34 in FIG.
The control circuit 54 determines the values of the adjustment signals tsel1 and tsel2 that make the sampling timing intermediate between the sampling timings at which the output value RND becomes H level in the processing of steps S43 and S49, and stores them in the storage unit (step S52). ). In the process of step S52, the control circuit 54 adjusts the sampling timing to the timing t11 in FIG. 13, for example, based on the values of the adjustment signals tsel1 and tsel2 stored in the processes of steps S45 and S51. Determine tsel2. Then, the control circuit 54 stores the determined adjustment signals tsel1 and tsel2 in the storage unit.

Next, steps S53 to S58 in FIG. 17 are performed as an example of step S35 in FIG.
The control circuit 54 sets the signals ct0 to ctm = “L”, the signal cton = “L”, and the signal ctoff = “H” (step S53). Further, the control circuit 54 sets the sampling timing to the timing t10 using the values of the adjustment signals tsel1 and tsel2 stored in the process of step S45 (step S54).

  Thereafter, the adjustment circuits 51a and 51b receive the clock signal CLK and output the data signal dt and the clock signal clk. The data signal dt is supplied to the load capacitance variable circuit 52. The latch circuit 53 takes in the data signal dto output from the load capacitance variable circuit 52 at the sampling timing based on the clock signal clk (step S55).

  Then, the control circuit 54 determines whether or not the output value RND is at the L level (step S56). If the output value RND is not at the L level, the control circuit 54 sets the signals ct0 to ctm to the H level sequentially from the signal ctm (step S57). After the process of step S57, the process of step S56 is performed again.

  For example, when the values of the signals ct0 to ctm are all at the L level, the selection circuit 60b in FIG. 12 selects the data signal dtm having the longest delay time from the data signals dt to dtm and outputs it as the data signal dts. . When output value RND remains at the H level, control circuit 54 changes the value of signal ctm to the H level. Thereby, the selection circuit 60b selects the data signal having the second largest delay time from the data signals dt to dtm and outputs the data signal as the data signal dts. If the output value RND still remains at the H level, the control circuit 54 further changes the value of the signal ct (m−1) (not shown in FIG. 12) to the H level. Thereby, the selection circuit 60b selects the data signal with the third largest delay time from the data signals dt to dtm and outputs the data signal as the data signal dts. The control circuit 54 repeats such processing until the output value RND changes to the L level.

  As a result, the load capacity addition start timing is advanced. When the output value RND is at the L level, the control circuit 54 stores the values of the current signals ct0 to ctm in the storage unit (step S58) and ends the setting process.

  Note that the order of the processes in FIGS. 15 to 17 is an example, and the order of the processes may be changed as appropriate. For example, the load capacity addition start timing in step S35 may be set after the process in step S31.

  According to the random number generation circuit 50 and the control method thereof according to the fifth embodiment as described above, the metastable period can be extended, so that the sampling timing can be easily matched, and high-quality random numbers are generated by metastability. it can.

(Sixth embodiment)
FIG. 18 is a diagram illustrating an example of a random number generation circuit according to the sixth embodiment. In FIG. 18, the same elements as those in the random number generation circuit 50 of the fifth embodiment shown in FIG.

  The random number generation circuit 70 of the sixth embodiment includes latch circuits 71a0, 71a1, 71a2, ..., 71an, delay circuits 71b1, 71b2, ..., 71bn, ExOR circuits 71c0, 71c1, 71c2,. Have

  The data signal dto output from the load capacitance variable circuit 52 is supplied to the data terminals of the latch circuits 71a0 to 71an. Further, the clock signals clk delayed by delay times that differ depending on the delay circuits 71b1 to 71bn connected in series are supplied to the clock terminals of the latch circuits 71a1 to 71an.

  Further, the ExOR circuits 71c0 to 71cn are connected in series, and the output value of the corresponding latch circuit among the latch circuits 71a0 to 71an is supplied to one input terminal of each of the ExOR circuits 71c0 to 71cn. The output value of the previous ExOR circuit is supplied to the other input terminal of each of the ExOR circuits 71c1 to 71cn. The input value R0 is supplied to the other input terminal of the first-stage ExOR circuit 71c0.

  At the time of random number generation, the input value R0 is fixed to one of the H level and the L level. When the random number generation circuit 70 is tested, the input value R0 may be changed. The output value of the final-stage ExOR circuit 71cn becomes the output value RND. The output values of the latch circuits 71a0 to 71an are supplied to the control circuit 71d.

  For example, the control circuit 71d performs the adjustment signal tsel1, in the process shown in FIG. 15, based on the output value supplied from the latch circuit in which the delay with respect to the clock signal clk is an intermediate value among the latch circuits 71a0 to 71an. The values of tsel2 and selection signal csel are determined.

  In the random number generation circuit 70, by appropriately setting the delay time by the delay circuits 71b1 to 71bn, the sampling timing in any of the latch circuits 71a0 to 71an is within the metastable period even if a skew occurs due to a change in operating conditions or the like. The possibility that becomes. That is, the probability of random numbers generated by metastability can be increased.

(Seventh embodiment)
FIG. 19 is a diagram illustrating an example of a random number generation circuit according to the seventh embodiment. 19, the same elements as those in the random number generation circuit 70 according to the sixth embodiment shown in FIG.

The random number generation circuit 80 according to the seventh embodiment includes an LFSR 81 having an input terminal in, a clock terminal ck, and an output terminal out.
A clock signal CLK is supplied to the clock terminal ck, and an output value of the ExOR circuit 71cn at the last stage is supplied to the input terminal in. An output value RND that is a random number or a pseudo-random number is output from the output terminal out.

  The LFSR 81 can be realized by the same circuit as the LFSR 41 shown in FIG. 10, for example. The output value RND output from the LFSR 81 becomes a random number having no periodicity because the output value of the ExOR circuit 71cn becomes a random number due to metastability during the period of the pseudo random number. That is, it can be avoided that the output value RND becomes a pseudo-random number. For this reason, random numbers with good quality can be output.

  In the random number generation circuit 70 of the sixth embodiment, random numbers due to metastability may not be output in each cycle of the clock signal CLK. However, the random number generation circuit 80 having the LFSR 81 as described above may Random numbers can be output at each cycle of CLK. That is, the random number generation rate can be improved.

  When the output value RND output from the LFSR 81 is the same value as the predetermined number of cycles of the clock signal CLK, the control circuit 71d sets the signal ERR to the H level to notify the outside that the state is abnormal. Good. Also, the control circuit 71d detects whether or not the output value of the ExOR circuit 71cn supplied to the input terminal in of the LFSR 81 changes, and when the output value is the same number of cycles of the clock signal CLK, May set the signal ERR to the H level.

Further, the random number generation circuit 50 of the fifth embodiment and the LFSR 81 may be combined to supply the output value of the latch circuit 53 to the input terminal in of the LFSR 81.
(Eighth embodiment)
FIG. 20 is a diagram illustrating an example of a random number generation circuit according to the eighth embodiment. 20, the same reference numerals are given to the same elements as those of the random number generation circuit 30 of the third embodiment shown in FIG. 8 and the random number generation circuit 50 of the fifth embodiment shown in FIG. .

A random number generation circuit 90 according to the eighth embodiment is a circuit in which a load capacitance variable circuit 52 is applied to the random number generation circuit 30 according to the third embodiment.
Unlike the random number generation circuit 30, the random number generation units 30a0 to 30an are supplied with the data signal dto output from the load capacitance variable circuit 52 instead of the data signal dt.

  For example, based on the output value RNDi supplied from the random number generation unit 30ai in which the delay with respect to the clock signal clk is an intermediate value among the random number generation units 30a0 to 30an, the control circuit 91 first adds the load capacitor addition start timing. To decide. For example, the control circuit 91 first sets the load capacitance variable circuit 52 in a state in which no load capacitance is added according to the selection signal csel, changes the values of the adjustment signals tsel1, tsel2, and the output value RNDi changes from the L level. The timing to change to the H level is detected. Then, the control circuit 91 uses the values of the adjustment signals tsel1, tsel2 at that timing to advance the load capacitor addition start timing by the selection signal csel, and the selection signal when the output value RNDi changes to the L level. Store the value of csel.

  Thereafter, the control circuit 91 supplies the stored value of the selection signal csel to the load capacitance variable circuit 52, and increases the load capacitance stepwise at an additional start timing determined by the value. Then, the control circuit 91 determines the values of the adjustment signals tsel1 and tsel2 based on the detection result matchi and the output value RNDi. The values of the adjustment signals tsel1 and tsel2 are determined by the method shown in FIGS. 4 to 6 so that the sampling timing by the clock signal clk reaching the random number generation unit 30ai is within the metastable period.

  The random number generation circuit 90 of the eighth embodiment has the effect obtained by the random number generation circuit 30 of the third embodiment. Furthermore, since the random number generation circuit 90 includes the load capacitance variable circuit 52, the metastable period can be expanded, so that the possibility that the sampling timing can be maintained within the metastable period is increased. As a result, a random number with higher quality can be generated.

  The random number generation circuit 90 determines the sampling timing based on, for example, the detection result matchi and the output value RNDi. Therefore, in the load capacitance variable circuit 52 of FIG. 12, when determining the sampling timing, the OR circuits 60d1 to 60dn provided to enable the capacitance circuits 52c1 to 52cn at the same time are not necessary.

(Ninth embodiment)
FIG. 21 is a diagram illustrating an example of a random number generation circuit according to the ninth embodiment. In FIG. 21, the same elements as those of the random number generation circuit 40 of the fourth embodiment shown in FIG. 9 and the random number generation circuit 90 of the eighth embodiment shown in FIG. .

The random number generation circuit 100 according to the ninth embodiment is a circuit in which the LFSR 41 is applied to the random number generation circuit 90 according to the eighth embodiment.
The random number generation circuit 100 according to the ninth embodiment can obtain the same effect as the random number generation circuit 90 according to the eighth embodiment and the same effect as the random number generation circuit 40 according to the fourth embodiment. It is done.

Needless to say, the load capacitance variable circuit 52 can be applied to the random number generation circuit 10 of the first embodiment and the random number generation circuit 20 of the second embodiment, although the description is omitted.
The random number generation circuits 10, 20, 30, 40, 50, 70, 80, 90, 100 of the first to ninth embodiments described above can be applied to various integrated circuits, systems, devices, and the like that use random numbers. It is. For example, it can be used for generating a cryptographic key using random numbers in the security field, dropout processing for preventing overlearning in deep learning using random numbers in the AI (Artificial Intelligence) field, and the like. Furthermore, it can be used for big data analysis in which random numbers are used.

  As described above, one aspect of the random number generation circuit and the control method thereof according to the present invention has been described based on the embodiment, but these are only examples and are not limited to the above description.

DESCRIPTION OF SYMBOLS 10 Random number generation circuit 11 Adjustment part 11a, 11b Adjustment circuit 12 Random number generation part 12a1-12an Latch circuit 12b Output circuit 12c Detection circuit 13 Control circuit CLK, clk Clock signal dt Data signal match detection result tsel1, tsel2 Adjustment signal RND Output value

Claims (8)

The input signal and the adjustment signal are received, and the first signal and the second signal are output based on the input signal, and the first signal or the second signal is output based on the adjustment signal. An adjustment unit for adjusting the phase;
Receiving the first signal and the second signal, respectively outputting a first value or a second value based on a signal level of the first signal at a sampling timing by the second signal; Three or more odd number of latch circuits;
When each of the odd number of latch circuits receives the first value or the second value output, and all the odd number of latch circuits output the same value, the same value is output, and the odd number An output circuit that outputs a smaller value of the first value and the second value when at least one of the plurality of latch circuits outputs a different value;
Each of the odd number of latch circuits receives the first value or the second value, and outputs a detection result indicating whether all of the odd number of latch circuits output the same value. A detection circuit;
Based on the detection result and the output value of the output circuit, it is determined whether the sampling timing is within a period in which the odd number of latch circuits are in a metastable state, and the sampling timing is within the period. A control circuit that adjusts the sampling timing within the period by changing the value of the adjustment signal based on the determination result of whether or not
A random number generating circuit. The control circuit delays the phase of the second signal with respect to the first signal by changing the value of the adjustment signal in a state where all of the odd number of latch circuits output the same value. Determining whether or not the sampling timing is within the period based on the detection result and the change in the output value of the output circuit at an earlier stage;
The random number generation circuit according to claim 1. The control circuit changes the value of the adjustment signal until all of the odd number of latch circuits output the second value, and then all of the odd number of latch circuits have the first value. Change the value of the adjustment signal until the value is output.
The control circuit includes a value of the adjustment signal at a first timing when all of the odd number of latch circuits are in a state of outputting the second value, and all of the odd number of latch circuits are the first value. Based on the value of the adjustment signal at the second timing at which the value is output, the sampling is performed at a third timing within the period that is intermediate between the first timing and the second timing. Adjust the timing,
The random number generation circuit according to claim 1 or 2. A first exclusive OR that outputs an operation result of an exclusive OR of the output value of the output circuit and the first input value of the odd number of latch circuits, the output circuit, the detection circuit, and the output circuit. A plurality of random number generators connected in series in a plurality of stages each having a circuit;
A delay circuit that varies a delay amount of the second signal supplied to each of the plurality of random number generation units,
The first input value supplied to the first exclusive OR circuit of the first stage random number generation unit of the plurality of random number generation units is the first value output from the control circuit or the first value One of the second values,
The first input value supplied to the first exclusive OR circuit of the second and subsequent random number generation units of the plurality of random number generation units is the first input value of the random number generation unit of the previous stage. The operation result output by the exclusive OR circuit;
The random number generation circuit according to claim 1. A linear feedback shift register including a multi-bit shift register that captures a second input value in synchronization with the input signal;
The linear feedback shift register includes an exclusive logic of the output value of the output circuit or a value based on the output value and a feedback signal generated by exclusive OR of some bits of the plurality of bits. A second exclusive OR circuit that outputs the second input value that is a sum;
The random number generation circuit according to any one of claims 1 to 4.   The selection signal output from the control circuit is received, and the load capacitance of the terminal to which the first signal is supplied in the odd number of latch circuits is increased stepwise from the start timing determined based on the selection signal. The random number generation circuit according to claim 1, further comprising a load capacitance variable circuit. The control circuit fixes the value of the selection signal in a state where the adjustment signal is fixed to a fifth value when the output value of the output circuit changes from the first value to the second value. The start timing is changed, and the start timing is determined based on the sixth value of the selection signal when the output value changes from the second value to the first value.
The random number generation circuit according to claim 6. In the control method of the random number generation circuit,
The adjustment unit included in the random number generation circuit receives the input signal and the adjustment signal, outputs the first signal and the second signal based on the input signal, and outputs the first signal and the second signal based on the adjustment signal. Adjusting the phase of the first signal or the second signal;
An odd number of three or more latch circuits included in the random number generation circuit receive the first signal and the second signal, and set the signal level of the first signal at the sampling timing of the second signal. Based on the first value or the second value, respectively,
The output circuit included in the random number generation circuit receives the first value or the second value output from each of the odd number of latch circuits, and all the odd number of latch circuits output the same value. When the same value is output and at least one of the odd number of latch circuits outputs a different value, the value that is output with the smaller number of the first value and the second value. Output
The detection circuit included in the random number generation circuit receives the first value or the second value output from each of the odd number of latch circuits, and all the odd number of latch circuits output the same value. Output a detection result indicating whether or not
The control circuit included in the random number generation circuit determines whether the sampling timing is within a period in which the odd number of latch circuits are in a metastable state based on the detection result and the output value of the output circuit. Determining and changing the value of the adjustment signal based on the determination result of whether or not the sampling timing is within the period, and adjusting the sampling timing within the period;
Control method of random number generation circuit.

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