JP6855004B2 - Display device and manufacturing method of display device - Google Patents

Description

The present disclosure relates to a display device and a method for manufacturing the display device.

For example, a display device for displaying an image using an organic light emitting element (OLED, Organic Light Emitting Diode) has been proposed (see Patent Document 1 and Patent Document 2). The OLED display device is abbreviated as a display device.

The display device includes a display area in which a large number of pixels are arranged in a matrix. In the case of a color display device, one pixel includes, for example, one red, one blue, and one green sub-pixel, for a total of three sub-pixels.

Each sub-pixel includes a pixel circuit that controls the current supplied to the organic light emitting element. The organic light emitting element emits light with brightness based on the current supplied by the pixel circuit. The organic light emitting element continues to emit light while the display area displays one screen.

JP-A-2007-114425 Japanese Unexamined Patent Publication No. 2013-200580

The pixel circuit supplies the organic light emitting element with a current corresponding to the image signal in order to cause the organic light emitting element to emit light with a brightness corresponding to the image signal. The current corresponding to this image signal may not match the drive current actually supplied to the organic light emitting element. Due to such a mismatch, the brightness of the organic light emitting element may become non-uniform in the display panel (so-called brightness unevenness). Image quality deteriorates when brightness unevenness occurs.

In one aspect, it is an object of the present invention to provide a display device that suppresses deterioration of image quality.

One aspect of the display device of the present disclosure is to supply a pixel having an organic light emitting element and a pixel circuit for controlling a current supplied to the organic light emitting element, and a first signal for controlling the pixel circuit to the pixel circuit. , A first wiring and a second wiring, and a third wiring that supplies a second signal for controlling the pixel circuit to the pixel circuit. The first wiring to the third wiring are arranged in the region where the pixel circuit is arranged and in the first direction, and the third wiring is the first wiring and the first wiring. It is arranged between the wiring of 2. The plurality of pixels are arranged in a matrix of M (M is an integer of 2 or more) rows and N (N is an integer of 2 or more) columns. The first direction is a row direction, and the first wiring and the second wiring are the first signals to each pixel circuit of a plurality of pixels arranged in one row in the M row. The third wiring supplies the second signal to the pixel circuits of the plurality of pixels arranged in the one row, and further, the outside of the display area in which the plurality of pixels are arranged. It has a drive circuit for driving each pixel circuit of the plurality of pixels based on the first signal and the second signal. The drive circuit supplies the same first signal to the first wiring and the second wiring, and supplies the second signal to the third wiring.

According to one aspect, it is possible to provide a display device that suppresses deterioration of image quality.

It is an external view of a display device. It is a figure which shows typically the plurality of pixels, and the drive circuit which drives these a plurality of pixels. It is a figure explaining a pixel schematically. It is an equivalent circuit diagram of a pixel circuit. It is a schematic plan view of the sub-pixel. It is a schematic cross-sectional view of a sub-pixel. It is a schematic cross-sectional view of a sub-pixel. It is an equivalent circuit diagram of the pixel circuit of the comparative example. It is a schematic plan view of the sub-pixel of the comparative example. It is explanatory drawing explaining the occurrence state of a feedthrough phenomenon. It is explanatory drawing explaining the reason why a feedthrough phenomenon can be prevented. It is a graph explaining the influence of variation of parasitic capacitance Cp. It is explanatory drawing explaining the effect of reducing the binding parasitic capacitance of an active layer. It is explanatory drawing explaining the effect of reducing the binding parasitic capacitance of an active layer. It is explanatory drawing explaining the comparative example of the effect of reducing the binding parasitic capacitance of an active layer. It is explanatory drawing explaining the effect of reducing the number of contact holes. It is explanatory drawing explaining the comparative example of the effect of reducing the number of contact holes. It is explanatory drawing explaining the effect of miniaturizing a sub-pixel. It is explanatory drawing explaining the effect which simplifies the Scan drive circuit. It is explanatory drawing explaining the comparative example of the effect which simplifies the Scan drive circuit. It is a hardware block diagram of a display device. It is a block diagram of a driver IC. It is a time chart which shows the control signal of a pixel circuit. It is explanatory drawing explaining the operation of a pixel circuit. It is explanatory drawing explaining the operation of a pixel circuit. It is explanatory drawing explaining the operation of a pixel circuit. It is explanatory drawing explaining the manufacturing process of a display panel. It is explanatory drawing explaining the manufacturing process of a display panel. It is explanatory drawing explaining the manufacturing process of a display panel. It is explanatory drawing explaining the manufacturing process of a display panel. It is explanatory drawing explaining the manufacturing process of a display panel. It is explanatory drawing explaining the manufacturing process of a display panel. It is explanatory drawing explaining the manufacturing process of a display panel. It is a schematic plan view of the sub-pixel of Embodiment 2. It is a schematic plan view of the sub-pixel of Embodiment 3. It is a schematic cross-sectional view of the sub-pixel of Embodiment 3. It is an equivalent circuit diagram of the 6T1C source follower type (6T1C_S) pixel circuit for verification. It is a time chart which shows the control signal of a pixel circuit. It is explanatory drawing explaining the state of the 6T1C_S pixel circuit for verification after inputting the signal pattern shown in FIG. 38. It is a graph which shows the data voltage dependence of the drain current Ids of a drive transistor. It is a graph which shows the Cp / (Cp + Cst) dependence of the drain current Ids of a drive transistor.

Hereinafter, embodiments of the display device will be described with reference to the drawings as appropriate. The ordinal numbers such as "first" and "second" in the description and claims are added to clarify the relationship between the elements and to prevent confusion between the elements. Therefore, these ordinal numbers do not limit the elements numerically.

Also, the term "connection" means that there is an electrical connection between the objects to be connected. “Electrically connected” also includes the case where the objects to be connected are connected via electrical elements such as electrodes, wirings, resistors, and capacitors. The terms "electrode" and "wiring" do not functionally limit these components. For example, the "wiring" can also be used as part of the "electrode". On the contrary, the "electrode" can also be used as a part of the "wiring".

[Embodiment 1]
FIG. 1 is an external view of the display device 10. FIG. 2 is a diagram schematically illustrating a plurality of pixels 31 and a drive circuit 20 for driving the plurality of pixels 31. FIG. 3 is a diagram schematically illustrating the pixel 31. The outline of the first embodiment will be described with reference to FIGS. 1 to 3.

FIG. 1 is a view of the display device 10 as viewed from the front side, that is, the side of the surface on which the image is displayed. The display device 10 is a device that displays a still image and a moving image. The display device 10 is used by incorporating it into an electronic device. Electronic devices include, for example, smartphones, tablet terminals, personal computers, televisions, and the like. The display device 10 of the present embodiment is an OLED display panel. In the following description, the top, bottom, left and right orientations of each figure will be used.

The display device 10 includes a TFT substrate 16, a second substrate 12, a driver IC 13, a power supply device 24, and an FPC (Flexible Printed Circuits) 14. The TFT substrate 16 includes a display region 15, a cathode electrode 19, a drive circuit 20, and wiring (not shown) on one side. The TFT substrate 16 is, for example, a glass substrate.

The second substrate 12 is a substrate that covers the display area 15 and the drive circuit 20 via a space. The second substrate 12 is, for example, a glass substrate. The TFT substrate 16 and the second substrate 12 may be flexible substrates using an organic film or the like as the substrate. The space between the TFT substrate 16 and the second substrate 12 is airtightly sealed by the sealing material 25. The sealing material 25 surrounds the display area 15 and the drive circuit 20.

The driver IC 13 is an integrated circuit mounted on the TFT substrate 16 using an anisotropic conductive film. The function of the driver IC 13 will be described later.

The FPC 14 is a flexible substrate connected to the TFT substrate 16. Wiring (not shown) included in the TFT substrate 16 connects the FPC 14, the driver IC 13, and the drive circuit 20. The display device 10 acquires an image signal from the control device of the electronic device via the FPC 14.

The display area 15 includes a large number of pixels 31 (see FIG. 2) arranged in a matrix. The display area 15 is covered by the cathode electrode 19. The pixel 31 includes a sub-pixel 32 (see FIG. 2). The structure of the pixel 31 and the sub-pixel 32 will be described later.

The structure in which the organic light emitting element 34 emits light in the surface direction of the TFT substrate 16 and the second substrate 12 is referred to as a top emission structure. On the other hand, a structure that emits light toward the back surface of the TFT substrate 16 and the second substrate 12 is called a bottom emission structure. In the top emission structure, the pixel circuit 33 can be formed by using the entire region of the sub-pixel 32.

The sub-pixel 32 includes an organic light emitting element 34 (see FIG. 3) and a pixel circuit 33 (see FIG. 3) that controls a current supplied to the organic light emitting element 34. The organic light emitting element 34 emits light based on the current supplied by the pixel circuit 33. The pixel circuit 33 will be described later.

The cathode electrode 19 is a common electrode connected to each sub-pixel 32. The cathode electrode 19 is an electrode made of a transparent or translucent material such as ITO (Indium Tin Oxide), transparent conductive ink or graphene. The cathode electrode 19 is the cathode electrode of the organic light emitting device 34 of the present embodiment.

The drive circuit 20 includes a Scan (scanning line) drive circuit 21, a data drive circuit 22, and an emission (hereinafter referred to as Em) drive circuit 23. The drive circuit 20 is formed by a thin film transistor (TFT) process. The outline of the drive circuit 20 will be described below.

The Scan drive circuit 21 is located outside the display area 15 along the left side of the display area 15. The Scan drive circuit 21 sequentially drives a plurality of pixels 31 arranged in each row in row units to control light emission. In other words, the Scan drive circuit 21 controls the light emission of the pixel 31 by driving the wiring extending in the lateral direction from the Scan drive circuit 21. Hereinafter, this wiring will be appropriately referred to as a scanning line. The Scan drive circuit 21 is a circuit that selects and drives the scanning line of the display area 15 based on the image signal acquired via the FPC 14. The scanning line is along a plurality of pixels 31 arranged in the first direction indicated by the arrow DRC1 in the left-right direction in FIG. That is, the scanning line extends along the plurality of sub-pixels 32 arranged in the first direction. The brightness of the pixels 31 arranged on one scanning line changes at the same time. That is, the brightness of the sub-pixels 32 arranged on one scanning line changes at the same time.

The vertical arrow DRC2 in FIG. 1 indicates a second direction. The Scan drive circuit 21 switches the driving scan line in the second direction. The order in which the Scan drive circuit 21 switches the scanning lines may be either from the upper side to the lower side of the display area 15 or from the lower side to the upper side. Further, the Scan drive circuit 21 may switch the scanning lines in any order. In the following description, the first direction may be referred to as the scanning line direction, and the second direction may be referred to as the scanning direction.

As described above, the first direction and the second direction are orthogonal to each other. By using such a display area 15, it is possible to provide a display device 10 for displaying an image in the display area 15 by using a commonly used image signal.

The data drive circuit 22 is located outside the display area 15 along the lower side of the display area 15. The data drive circuit 22 simultaneously outputs a signal indicating the brightness of the sub-pixel 32 to each sub-pixel 32 in one line.

The Em drive circuit 23 is located outside the display area 15 along the right side of the display area 15. Similar to the Scan drive circuit 21, the Em drive circuit 23 is a circuit that sequentially changes the signal output line by line. Primarily, its signal output puts the switching transistor on (connected) during the light emission period.

The power supply device 24 is located outside the TFT substrate 16. The power supply device 24 is a device that supplies a voltage to each power supply line on the TFT substrate 16 via the FPC 14.

The details of the operation of the Scan drive circuit 21, the data drive circuit 22, the Em drive circuit 23, and the power supply device 24 will be described later.

FIG. 2 is a diagram schematically illustrating a plurality of pixels 31 and a drive circuit 20 for driving the plurality of pixels 31. The left-right direction in FIG. 2 is the above-mentioned first direction, that is, the direction in which the scanning line extends (scanning line direction). Further, the vertical direction in FIG. 2 is the above-mentioned second direction, that is, a direction for sequentially scanning (scanning direction).

Sub-pixels 32 are arranged in a matrix of M rows and N × 3 columns in the display area 15 (see FIG. 1). Here, M and N are integers of 2 or more. As will be described later, the three sub-pixels 32 constitute one pixel 31. Therefore, the pixels 31 of M rows and N columns are arranged in the display area 15.

FIG. 3 is a diagram schematically illustrating the pixel 31. The left-right direction in FIG. 3 is the above-mentioned first direction, that is, the scanning line direction. Further, the vertical direction in FIG. 3 is the above-mentioned second direction, that is, the scanning direction.

The pixel 31 includes three sub-pixels 32. The sub-pixel 32 includes a pixel circuit 33 and an organic light emitting element 34. One sub-pixel 32 is one of the pixels 31 divided into three by vertical lines. In the following description, the i-th sub-pixel 32 counted from the top and the j-th sub-pixel 32 counted from the left will be referred to as the sub-pixel 32 (i, j). When it is not necessary to specify the position, it is described as the sub-pixel 32. As shown in FIG. 3, one pixel 31 includes three sub-pixels 32 of sub-pixel 32 (i, j-1), sub-pixel 32 (i, j) and sub-pixel 32 (i, j + 1). ..

In FIG. 3, the sub-pixel 32 is shown as a rectangle. The display device 10 does not include a substantive object that indicates a boundary between the sub-pixels 32. One sub-pixel 32 of the present embodiment indicates one rectangular area when the display area 15 is divided into a matrix corresponding to the number of sub-pixels 32. Adjacent sub-pixels 32 are arranged without gaps.

The description will be continued with reference to FIGS. 2 and 3. The pixel 31 is connected to a first wiring 41, a second wiring 42, and a third wiring 43 that cross the arrangement area of the pixel 31 in the left-right direction. All three sub-pixels 32 included in one pixel 31 are connected to the three wires of the first wire 41, the second wire 42, and the third wire 43. That is, the three sub-pixels 32 included in the one pixel 31 share the three wirings of the first wiring 41, the second wiring 42, and the third wiring 43.

The first wiring 41 to the third wiring 43 are also referred to as the first signal wiring 41 to the third signal wiring 43. Further, the first wiring 41 is also referred to as a first scanning signal line 41, the second wiring 42 is also referred to as a second scanning signal line 42, and the third wiring 43 is also referred to as a light emission control line 43.

FIG. 2 shows a case where the first wiring 41 is arranged on the lower side and the second wiring 42 is arranged on the upper side. The first wiring 41 may be arranged on the upper side, and the second wiring 42 may be arranged on the lower side.

In the following drawings, the first wiring 41 will be referred to as Scan1, the second wiring 42 will be referred to as Scan2, and the third wiring 43 will be referred to as Em. Further, the i-th first wiring 41 counting from the top is Scan1 (i), the i-th second wiring 42 counting from the top is Scan2 (i), and the i-th third wiring 43 counting from the top. Is described as EM (i).

The pixel 31 is connected to a power supply line 45 that vertically traverses the pixel 31. The power line 45 includes a data power line 455. All three sub-pixels 32 included in the pixel 31 are connected to the power line 45. That is, all three sub-pixels 32 included in the pixel 31 are also connected to their respective data power supply lines 455.

In the following figures, the data power line 455 is referred to as Vdata. The j-th data power line 455 counted from the left is referred to as Vdata (j).

The Scan drive circuit 21 is located on the left side of the sub-pixels 32 arranged in a matrix, that is, the display area 15. The data drive circuit 22 is located below the sub-pixels 32 arranged in a matrix. The Em drive circuit 23 is located on the left side of the sub-pixels 32 arranged in a matrix.

M branch source wirings 44 extend to the right from the Scan drive circuit 21. The Scan drive circuit 21 supplies (also referred to as an output) a first signal for controlling the pixel circuit 33 to the branch source wiring 44. The branch source wiring 44 is branched into a first wiring 41 and a second wiring 42 between the Scan drive circuit 21 and the first sub-pixel 32. That is, the number of the first wiring 41 is M, and the number of the second wiring 42 is also M. The first wiring 41 and the second wiring 42 supply the first signal for controlling the pixel circuit 33 to the sub-pixel 32.

M third wires 43 extend to the left from the Em drive circuit 23. The Em drive circuit 23 supplies a second signal for controlling the pixel circuit 33 to the third wiring 43. The third wiring 43 supplies the second signal to the sub-pixel 32. The third wiring 43 does not intersect the first wiring 41, the second wiring 42, and the branch source wiring 44. The i-th third wiring 43 is located between the i-th first wiring 41 and the i-th second wiring 42.

Therefore, the first wiring 41 supplies the first signal for controlling the pixel circuit 33 to the pixel 31. The second wiring 42 also supplies the first signal for controlling the pixel circuit 33 to the pixel 31. The third wiring 43 supplies the pixel 31 with a second signal for controlling the pixel circuit 33.

As described above, the pixel 31 has an organic light emitting element 34 and a pixel circuit 33 that controls a current supplied to the organic light emitting element 34. The display device 10 has a first wiring 41 and a second wiring 42 that supply the first signal for controlling the pixel circuit 33 to the pixel circuit 33. The display device 10 has a third wiring 43 that supplies a second signal for controlling the pixel circuit 33 to the pixel circuit 33. The first wiring 41 to the third wiring 43 are arranged in the region where the pixel circuit 33 is arranged and in the first direction (DRC1). The third wiring 43 is arranged between the first wiring 41 and the second wiring 42.

The first signal is a so-called scanning signal. The first signal stores (also referred to as holding or writing) a voltage (charge) corresponding to an image (in other words, a pixel value, emission brightness) in a holding capacity 47 (see FIG. 4) in the pixel circuit 33. It is a signal that controls processing (also called a Scan signal). In addition, the first signal is a signal that controls the pixel circuit 33 to control the process of detecting the threshold value of the drive transistor 56 (see FIG. 4) that controls the current supplied to the organic light emitting element 34. .. The process of detecting the threshold value of the drive transistor 56 is also referred to as a process of compensating for the threshold value (threshold value compensation).

The second signal is, for example, a signal (also referred to as an Em signal) that controls the pixel circuit 33 to control light emission or non-light emission of the organic light emitting element 34.

As will be described in detail in FIGS. 4, 14, and 15, by arranging the first wirings 41 to 3 as shown in FIGS. 2 and 3, the first wiring in the sub-pixel 32 can be arranged. It is possible to prevent the wiring 41 to the third wiring 43 from becoming complicated. By this suppression, a part of the connection wiring (also called a wiring node) connecting the transistors in the pixel circuit 33 can be shortened. Further, it is possible to prevent a part of the connection wiring from intersecting with at least one of the first wiring 41 to the third wiring 43. A part of this connection wiring is a part that is sensitive to the characteristics of the pixel circuit 33, for example, a part that affects the emission brightness of the organic light emitting element 34.

Here, when the signal wiring (for example, the first wiring 41 to the third wiring 43) and the connection wiring intersect, a parasitic capacitance is generated at this intersecting portion. This parasitic capacitance may make the actual amount of charge held in the holding capacitance 47 of the pixel circuit 33 different from the original amount of charge corresponding to the emission brightness of the organic light emitting element 34. As a result, the drive current of the organic light emitting element 34 may change, and the organic light emitting element 34 may emit light with a brightness different from the target emission brightness.

However, as described above, since it is possible to suppress the complicated routing of the first wiring 41 to the third wiring 43, it is possible to suppress the generation of parasitic capacitance and suppress the change in the current value of the drive current. As a result, uneven brightness can be suppressed and deterioration of image quality can be suppressed.

As described above, the first wiring 41 and the second wiring 42 supply the first signal to each pixel circuit 33 of the plurality of pixels 31 arranged in one row in the M row. The third wiring 43 supplies a second signal to each pixel circuit 33 of the plurality of pixels 31 arranged in one row in the M row.

By supplying a signal to the pixels 31 of the display area 15 in this way, it is possible to provide a display device 10 for displaying an image in the display area 15 by using a generally used image signal.

The display device 10 is arranged outside the display area 15 in which the plurality of pixels 31 are arranged, and is a drive circuit 20 that drives each pixel circuit 33 of the plurality of pixels 31 based on the first signal and the second signal. Has. The Scan drive circuit 21 supplies the same first signal to the first wiring 41 and the second wiring 42. The Scan drive circuit 21 supplies a second signal to the third wiring 43.

By using such a drive circuit 20, it is possible to provide a display device 10 having less brightness unevenness without using a dedicated driver IC 13 and a drive circuit 20 or the like.

The Scan drive circuit 21 is connected to the branch source wiring 44 that branches into the first wiring 41 and the second wiring 42. The Scan drive circuit 21 supplies the first signal to the branch source wiring 44. In the area between the display area 15 and the arrangement area of the Scan drive circuit 21, the branch source wiring 44 branches into the first wiring 41 and the second wiring 42.

By using such a branch, it is possible to provide a high-quality display device 10 with less uneven brightness without widening the frame area around the display area 15.

The display device 10 has M branch source wires 44 and M third wires 43. The first wiring 41 and the second wiring 42 of the branch source wiring 44 of the i-th (i is an integer of 1 to M) are first connected to the pixel circuits 33 of the plurality of pixels 31 arranged in the i-th row. Supply the signal of. The third wiring 43 of the third supplies a second signal to each pixel circuit 33 of the plurality of pixels 31 arranged in the i-th row.

By using such wiring, it is possible to provide a display device 10 that displays an image in the display area 15 by using a commonly used image signal.

N × 3 data power lines 455 extend from the data drive circuit 22 toward the sub-pixel 32. The data drive circuit 22 simultaneously outputs a signal indicating the brightness of the sub-pixel 32 to each sub-pixel 32 in one line.

The power supply device 24 supplies power to the TFT substrate 16. One power line 45 extends toward the sub-pixel 32. The power line 45 is branched into N × 3 lines from the first sub-pixel 32. The power supply line 45 includes, for example, a high power supply line 451, a low power supply line 452, a reset power supply line 453, and a reference power supply line 454 (see FIG. 4), which will be described later. The power supply line 45 branched into N × 3 lines includes the same type and number of power supply lines 45 as the branch source.

The N × 3 sub-pixels 32 arranged in one line in the left-right direction share the first wiring 41, the second wiring 42, and the third wiring 43. That is, for example, the N × 3 sub-pixels 32 in the i-th row are connected to all of the i-th first wiring 41, the i-th second wiring 42, and the i-th third wiring 43. In addition, i is an integer of 1 or more and M or less.

The M sub-pixels 32 arranged in a row in the vertical direction share the power supply line 45 including the data line 455. That is, for example, the M sub-pixels 32 in the j-th row are connected to one of the power supply lines 45 branched from the first sub-pixel 32. That is, the M sub-pixels 32 in the j-th row are connected to all the power supply lines 45 including the branched power supply lines 45. Further, the M sub-pixels 32 in the j-th column are connected to the j-th data line 455.

FIG. 4 is an equivalent circuit diagram of the pixel circuit 33. The pixel circuit 33 is connected to the organic light emitting element 34. The pixel circuit 33 has a first transistor 51, a second transistor 52, and a third transistor 53. The pixel circuit 33 further includes a fourth transistor 54, a fifth transistor 55, a drive transistor 56, and a holding capacity 47. The holding capacity 47 has a function of keeping the brightness of the organic light emitting element 34 constant for a time when the display area 15 displays one screen.

FIG. 4 shows a pixel circuit 33 and an organic light emitting element 34 included in one sub-pixel 32. The components of the pixel circuit 33 included in the one sub-pixel 32 are located inside the rectangular region of the one sub-pixel 32 described with reference to FIG.

In the following figure, the first transistor 51 is T1, the second transistor 52 is T2, the third transistor 53 is T3, the fourth transistor 54 is T4, the fifth transistor 55 is T5, and the drive transistor. 56 is indicated by the symbol T6, and the holding capacity 47 is indicated by the symbol Cst.

The pixel circuit 33 includes a first wiring 41, a second wiring 42, a third wiring 43, a high power supply line 451 and a reset power supply line 453, a reference power supply line 454, a data line 455, and an anode electrode of the organic light emitting element 34. 18 (see FIG. 6) are connected. A low power supply line 452 is connected to the cathode electrode of the organic light emitting element 34.

The high power line 451 supplies a high power voltage VDD. The low power line 452 supplies a low power voltage VSS. The reset power line 453 supplies the reset voltage Vrst. The reference power line 454 supplies the reference voltage Vref. As described above, the data line 455 supplies a signal (also referred to as a data signal) indicating the brightness of the sub-pixel 32.

In the present embodiment, the potentials of the low power supply line 452, the reset power supply line 453, and the reference power supply line 454 are set lower than the potential of the high power supply line 451. Further, for example, the reset power supply line 453 and the reference power supply line 454 are shared.

The first transistor 51 is connected to the reference power line 454, the second transistor 52, and the first terminal of the holding capacity 47. The second transistor 52 is connected to the first terminal of the holding capacity 47, the gate electrode of the drive transistor 56 (hereinafter, abbreviated as gate), and the third transistor 53. The third transistor 53 is connected to the data line 455, the gate of the drive transistor 56, and the second transistor 52.

The fourth transistor 54 is connected to the high power supply line 451 and the second terminal of the holding capacity 47 and the source electrode (hereinafter, abbreviated as source) of the drive transistor 56.

The drain electrode of the drive transistor 56 (hereinafter, abbreviated as drain) is connected to the anode electrode of the organic light emitting element 34 and the fifth transistor 55. The fifth transistor 55 is connected to the reset power supply line 453 and the drain of the drive transistor 56.

The first wiring 41 is connected to the gate of the first transistor 51. The second wiring 42 is connected to the gate of the third transistor 53 and the gate of the fifth transistor 55. The third wiring 43 is connected to the gate of the second transistor 52 and the gate of the fourth transistor 54.

The drive transistor 56 controls the current supplied to the organic light emitting element 34. The details of the operation of the pixel circuit 33 will be described later.

The pixel circuit 33 will be described in another expression by focusing on the first transistor 51, the second transistor 52, and the third transistor 53. The first transistor 51, the second transistor 52, and the third transistor 53 are connected in series. The connection point between the second transistor 52 and the third transistor 53 is connected to the gate of the drive transistor 56.

As described above, the pixel circuit 33 includes a drive transistor 56 that controls a current supplied to the organic light emitting element 34. The pixel circuit 33 has first, second, and third transistors 51, 52, and 53 connected in series. The first, second, and third transistors 51, 52, and 53 are connected in series in this order. The connection point between the second transistor 52 and the third transistor 53 is connected to the gate of the drive transistor 56. The first, third, and second wirings 41, 43, and 42 are connected to the gates of the first to third transistors 51 to 53, respectively, in this order.

By using the pixel circuit 33 configured in this way, the area required for laying out the transistors and the like is reduced. As a result, it is possible to provide a display device 10 having a small area of pixels 31, that is, a high-definition display device 10.

As described above, the pixel circuit 33 has fourth and fifth transistors 54 and 55 and a holding capacity 47. The fourth transistor 54 is connected between the high power supply line 451 and the drive transistor 56. The organic light emitting element 34 is connected between the drive transistor 56 and the low power supply line 452 having a potential lower than that of the high power supply line 451. The fifth transistor 55 is connected between the connection point between the drive transistor 56 and the organic light emitting element 34 and the reset power supply line 453 having a potential lower than that of the high power supply line 451. The holding capacitance 47 is connected between the connection point between the first transistor 51 and the second transistor 52 and the connection point between the fourth transistor 54 and the drive transistor 56. The first transistor 51 is connected between the reference power supply line 454 and the second transistor 52. The third transistor 53 is connected between the data line 455 that supplies the voltage applied to the gate of the drive transistor 56 and the second transistor 52. The second wiring 42 is connected to the gate of the third transistor 53 and the gate of the fifth transistor 55. The third wiring 43 is connected to the gate of the second transistor 52 and the gate of the fourth transistor 54.

The first power supply line is, for example, a high power supply line 451, the second power supply line is, for example, a low power supply line 452, the third power supply line is, for example, a reset power supply line 453, and the fourth power supply line. The line 454 is, for example, a reference power line 454, and the fifth power line 455 is, for example, a data line 455.

By using the pixel circuit 33 configured in this way, it is possible to prevent the image retention phenomenon and the leakage light emission phenomenon. As a result, it is possible to provide a display device 10 having a high image quality. The image retention phenomenon and the leakage light emission phenomenon will be described later. Further, the reason why the image retention phenomenon can be prevented by the pixel circuit 33 of the present embodiment will also be described later.

FIG. 5 is a schematic plan view of the sub-pixel 32. 6 and 7 are schematic cross-sectional views of the sub-pixel 32. In the schematic plan view below, the area of the holding capacitance, the channel length of the driving transistor, the thickness and spacing of each pattern, and the aspect ratio of the sub-pixel 32 are substantially the same. FIG. 5 is an enlarged view showing a portion corresponding to one sub-pixel 32 and its periphery as viewed from the front side of the display device 10. FIG. 6 is a schematic cross-sectional view of the sub-pixel 32 cut along the VI-VI line in FIG. FIG. 7 is a schematic cross-sectional view of the sub-pixel 32 cut along the line VII-VII in FIG.

The alternate long and short dash line in FIG. 5 indicates the boundary of the sub-pixel 32. As described above, the display device 10 does not include a substantive object that indicates the boundary between the sub-pixels 32. Therefore, the one-point difference line in FIG. 5 is a virtual line for explanation, and does not show a substantive object.

The structure of the display device 10 will be described with reference to FIGS. 5 to 7. First, the outline of the cross-sectional structure of the sub-pixel 32 will be described with reference to FIGS. 6 and 7. The sub-pixel 32 includes a first substrate 11, an underlying insulating layer 61, an active layer 62, a gate insulating layer 63, a gate 64 (also referred to as a gate electrode 64 and a gate portion 64), an interlayer insulating layer 65, and a drain 66 (drain electrode 66, It also includes a drain portion 66), a flattening layer 67, an anode electrode 18, and a first insulating portion 69. The sub-pixel 32 is provided with an organic light emitting layer (not shown) on the upper side of the first insulating portion 69. The display device 10 includes a cathode electrode 19 (see FIG. 1) and a second substrate 12 (see FIG. 1) that cover the organic light emitting layer of the sub-pixels 32 arranged in a matrix and the first insulating portion 69. In FIGS. 5 to 7, the organic light emitting layer, the cathode electrode 19, and the second substrate 12 are not shown.

The first substrate 11 is a rectangular glass substrate. The base insulating layer 61 is located on the first substrate 11. The base insulating layer 61 is a layer having a uniform thickness that covers one surface of the first substrate 11. The base insulating layer 61 is a layer made of an insulator such as silicon oxide.

The active layer 62 is located above the underlying insulating layer 61. As shown in FIG. 5, the active layer 62 in one sub-pixel 32 has a first portion 621 and a second portion 622.

The first portion 621 has a start end portion at the lower left of the sub-pixel 32, extends upward along the long side of the sub-pixel 32, and turns upward again at a position bent to the right near the center of the long side of the sub-pixel 32. Extends to, through the L-shaped region, beyond the upper edge of the region of the sub-pixel 32, and further upwards. The second portion 622 is an extension of the first portion of the lower adjacent sub-pixel 32. The second portion 622 extends upward through a U-shaped portion that enters from the lower edge of the sub-pixel 32 and is open on the right side, and has an end portion on the right side of the L-shaped portion of the first portion 621.

That is, the first portion 621 and the second portion 622 are continuous in the two sub-pixels 32 adjacent in the vertical direction. One sub-pixel 32 is both a first portion 621 shared with adjacent sub-pixels 32 on the upper side and a second portion 622 shared with adjacent sub-pixels 32 on the lower side. including.

The active layer 62 is a layer made of a thin film semiconductor such as a polysilicon semiconductor. Alternatively, the active layer 62 is a layer made of InGaZnO, which is an oxide semiconductor. The material of the wiring connecting the transistors and the material of the wiring connecting the transistors and the holding capacity 47 may be not only the active layer of the semiconductor but also a metal.

The explanation will be continued by returning to FIGS. 6 and 7. The gate insulating layer 63 covers the entire surface of the active layer 62 and the underlying insulating layer 61 that is not covered by the active layer 62. The gate insulating layer 63 is an insulating layer such as silicon oxide.

The gate 64 is located on the gate insulating layer 63. As shown in FIG. 5, the gate 64 includes a first wiring 41, a second wiring 42, a third wiring 43, an L-shaped region, and a rectangular region. The first wiring 41, the second wiring 42, and the third wiring 43 have a strip shape extending in the left-right direction. The first wiring 41, the second wiring 42, and the third wiring 43 extend beyond the right and left boundaries of the sub-pixel 32 to the adjacent sub-pixel 32. The first wiring 41 is located above the third wiring 43. The second wiring 42 is located below the third wiring 43.

As described above, the first wiring 41 is arranged on the first side, which is the upper side of the pixel 31. The second wiring 42 is arranged on the second side facing one side, which is the first side, in the same pixel 31 as the above-mentioned pixel 31. The third wiring 43 is arranged near the center between the first wiring 41 and the second wiring 42.

By arranging the first wirings 41 to the third wirings 43, it is possible to prevent the first wirings 41 to the third wirings 43 from becoming complicated to be routed in the sub-pixel 32.

By using the first wiring 41, the second wiring 42, and the third wiring 43 in such an arrangement, it is possible to prevent the generation of parasitic capacitance due to the intersection of the wirings. As a result, it is possible to provide a high-quality display device 10 with less uneven brightness.

As shown in FIG. 5, the L-shaped region of the gate 64 shown on the upper side of the drawing is located between the first wiring 41 and the third wiring 43. The L-shaped region of the gate 64 overlaps with the L-shaped region of the active layer 62 described above. The L-shaped region of the gate 64 is slightly smaller than the L-shaped region of the active layer 62. Therefore, the edge of the L-shaped region of the active layer 62 does not overlap with the L-shaped region of the gate 64.

The portion where the L-shaped region of the active layer 62 and the L-shaped region of the gate 64 face each other and the gate insulating layer 63 between them form a holding capacity 47 (see reference numeral CST). As described above, the holding capacity 47 is arranged in the region between the first wiring 41 and the third wiring 43.

Since the holding capacity 47 is arranged in the region between the first wiring 41 and the third wiring 43, the arrangement of the transistors can be optimized and the pixel area can be reduced. The details will be described with reference to FIG.

The rectangular area of the gate 64 shown on the lower side of FIG. 5 is located between the third wiring 43 and the second wiring 42. The rectangular area of the gate 64 covers the U-shaped portion of the active layer 62.

The material of the gate 64 is, for example, a conductor such as pure metal, alloy or ITO. The gate 64 may be a laminate of a plurality of metals, alloys, ITO or the like.

The explanation will be continued by returning to FIGS. 6 and 7. The interlayer insulating layer 65 covers the gate 64 and the gate insulating layer 63 that is not covered by the gate 64. The upper surface of the interlayer insulating layer 65 has irregularities that reflect the shape of the lower layer. The interlayer insulating layer 65 is a layer made of an insulator such as silicon oxide.

As described above, in the sub-pixel 32, the first wiring 41, the second wiring 42, the third wiring 43, the L-shaped region, and the rectangular region are separated from each other. A gate insulating layer 63 insulates the lower side of the gate 64. An interlayer insulating layer 65 insulates the upper side of the gate 64. Therefore, the first wiring 41 and the second wiring 42 are insulated from each other in the pixel circuit 33. By this insulation, the first wiring 41 and the second wiring 42 can be electrically brought into a non-contact state, and the same signal can be supplied to the first wiring 41 and the second wiring 42, which are different wirings.

The drain 66 is located on the interlayer insulating layer 65. The drain 66 is connected to the active layer 62 via the first conductive portion 71. As shown in FIG. 5, the high power supply line 451, the reference power supply line 454, and the data line 455 are formed by the drain layer, respectively.

The high power supply line 451 and the reference power supply line 454 and the data line 455 have a strip shape extending in the vertical direction. The right side is the high power line 451, the center is the reference power line 454, and the left side is the data line 455. The high power supply line 451 and the reference power supply line 454 and the data line 455 extend beyond the upper and lower boundaries of the sub-pixel 32 to the adjacent sub-pixel 32. The planar arrangement of the first conductive portion 71 will be described later.

The material of the drain 66 is, for example, a conductor such as pure metal, alloy or ITO. The drain 66 may be a laminate of a plurality of metals, alloys, ITO or the like. The material of the drain 66 may be different from the material of the gate 64. Further, the material of the drain 66 may be the same as the material of the gate 64.

As described above, the high power supply line 451 and the reference power supply line 454 and the data line 455 are arranged in the second direction. By using the pixel circuit 33 in which the power line 45 is arranged in this way, the layout of the pixel 31 can be optimized. As a result, it is possible to provide a display device 10 having a small area of pixels 31, that is, a high-definition display device 10.

The explanation will be continued by returning to FIGS. 6 and 7. The flattening layer 67 covers the drain 66 and the interlayer insulating layer 65 that is not covered by the drain 66. The upper surface of the flattening layer 67 is flat. The flattening layer 67 is a layer made of an organic material such as a photosensitive acrylic resin.

The anode electrode 18 is located on the flattening layer 67. The anode electrode 18 has a shape separated for each sub-pixel 32, and partially covers the flattening layer 67.

The anode electrode 18 is connected to the drain 66 via the second conductive portion 72. The planar arrangement of the second conductive portion 72 will be described later.

The first insulating portion 69 is located above the anode electrode 18. The first insulating portion 69 is provided with an opening 691 that does not cover the anode electrode 18. In the following description, the first insulating portion 69 excluding the opening 691 will be referred to as a non-opening 692. The first insulating portion 69 is a layer made of an organic material.

The opening 691 is covered with an organic light emitting layer (not shown). The organic light emitting layer is a layer of an organic compound that emits light when an electric current flows. The cathode electrode 19 (see FIG. 1) covers the organic light emitting layer and the first insulating portion 69.

The relationship between the pixel circuit 33 described with reference to FIG. 4 and the structure of the sub-pixel 32 described with reference to FIGS. 5 to 7 will be described.

The cathode electrode 19 is connected to the low power line 452 outside the display area 15 (see FIG. 1). The anode electrode 18 is connected to the source of the drive transistor 56 via the second conductive portion 72 and the drain 66. The first wiring 41, the second wiring 42, the third wiring 43, the high power supply line 451 and the reference power supply line 454 and the data line 455 are described because they use the same numbers in FIGS. 4 to 7. Is omitted.

The arrangement of the transistors in the sub-pixel 32 will be described. A portion of the active layer 62 that overlaps the first wiring 41 (also referred to as an intersecting portion) forms a channel region of the first transistor 51. The active layer 62 overlaps with the third wiring 43 at two points. The active layer 62 of the overlapping portion on the left side of these forms a channel region of the second transistor 52. Further, the active layer 62 of the overlapping portion on the right side forms a channel region of the fourth transistor 54.

The active layer 62 overlaps with the second wiring 42 at two points. The active layer 62 of the overlapping portion on the left side of these forms a channel region of the third transistor 53. Further, the active layer 62 of the overlapping portion on the right side forms a channel region of the fifth transistor 55. A portion of the U-shape formed by the active layer 62 rotated 90 ° clockwise forms a channel region of the drive transistor 56.

The channel region of the first transistor 51 and the channel region of the second transistor 52 are connected via the active layer 62. In the following description, the active layer 62 connecting the channel region of the first transistor 51 and the channel region of the second transistor 52 will be referred to as the first connection wiring. The first connection wiring extends upward from the channel region of the second transistor 52, that is, in the second direction, and connects to the channel region of the first transistor 51 via an L-shaped region. The first connection wiring is an active layer 62 whose resistance value is lowered by adding impurities.

The channel region of the second transistor 52 and the channel region of the third transistor 53 are connected via the active layer 62. In the following description, the active layer 62 connecting the channel region of the second transistor 52 and the channel region of the third transistor 53 will be referred to as a second connection wiring. The second connection wiring extends upward along the long side of the sub-pixel 32 from the channel region of the third transistor 53, that is, in the second direction, and bends to the right near the center of the long side direction of the sub-pixel 32. It is connected to the channel region of the second transistor 52. The second connection wiring is also the active layer 62 whose resistance value is lowered by adding impurities.

As described above, the first connection wiring and the second connection wiring are composed of the active layer 62 of the semiconductor. In this way, the layout of the pixels can be optimized by using the active layer 62 of the semiconductor that forms a part of the transistor for wiring. As a result, it is possible to provide a display device 10 having a small area of pixels 31, that is, a high-definition display device 10.

Since the order of the layers is from bottom to top, the active layer 62, the gate insulating layer 63, and the gate layer 64, a channel region is formed in the region where the pattern of the active layer 62 and the pattern of the gate 64 intersect, and corresponds to the channel region. The pattern of the gate 64 in the region is functioning as the gate of the transistor. The gate of the first transistor 51 is connected to the first wiring 41. The gates of the second transistor 52 and the fourth transistor 54 are connected to the third wiring 43. The gates of the third transistor 53 and the fifth transistor 55 are connected to the second wiring 42.

As described above, the first wiring 41 and the second wiring 42 supply the first signal. The third wiring 43 supplies the second signal. Each transistor from the first transistor 51 to the fifth transistor 55 operates as a switch for switching between a conduction state and a cutoff state between the source and the drain. The details of the operation of the pixel circuit 33 will be described later.

As described above, the display device 10 has a first connection wiring for connecting the channel region of the first transistor 51 and the channel region of the second transistor 52. The display device 10 has a second connection wiring that connects the channel region of the second transistor 52 and the channel region of the third transistor 53. The first connection wiring and the second connection wiring are arranged in the second direction intersecting the first direction.

By using such a connection wiring, it is possible to prevent the generation of parasitic capacitance due to the intersection of the wirings. As a result, it is possible to provide a high-quality display device 10 with less uneven brightness.

Since the first connection wiring and the second connection wiring are arranged in the second direction (direction of DRC2 in FIG. 1), the layout of the long portion of the channel region of the transistor can be arranged in the vertical direction.

The effect of the display device 10 of the present embodiment having the structure described above will be described with reference to a comparative example. The description of the parts common to the comparative example and the present embodiment will be omitted.

The structure of the comparative example will be described. FIG. 8 is an equivalent circuit diagram of the pixel circuit 933 of the comparative example. The pixel circuit 933 of the comparative example will be described. The description of the parts common to the pixel circuit 33 of the present embodiment shown in FIG. 4 will be omitted. Further, the transistors and capacitances constituting the equivalent circuit are described using the same numbers as the corresponding transistor and capacitance numbers of the pixel circuit 33 of the present embodiment.

The scan line 40, the third wiring 943, the high power supply line 9451, the reset power supply line 9453, the reference power supply line 9454, the data line 9455, and the anode electrode of the organic light emitting element 934 are connected to the pixel circuit 933. A low power supply line 9452 is connected to the cathode electrode of the organic light emitting element 934.

The high power line 9451 supplies a high power voltage VDD. The low power line 9452 supplies a low power voltage VSS. The reset power line 9453 supplies the reset voltage Vrst. The reference power line 9454 supplies a reference voltage Vref. The data line 9455 supplies a signal indicating the brightness of the sub-pixel 932.

The Scan drive circuit of the comparative example (not shown) supplies the first signal to the pixel circuit 933 via the Scan line 40. The Em drive circuit of the comparative example (not shown) supplies a second signal to the pixel circuit 933 via the third wiring 943.

The first transistor 51 is connected to the reference power supply line 9454, the second transistor 52, and the first terminal of the holding capacity 47. The second transistor 52 is connected to the first terminal of the holding capacity 47, the third transistor 53, and the gate of the drive transistor 56. The third transistor 53 is connected to the gate of the data line 9455, the second transistor 52, and the drive transistor 56.

The fourth transistor 54 is connected to the high power supply line 9451, the second terminal of the holding capacity 47, and the source of the drive transistor 56.

The drain of the drive transistor 56 is connected to the anode electrode of the organic light emitting element 34 and the fifth transistor 55. The fifth transistor 55 is connected to the reset power supply line 9453 and the drain of the drive transistor 56.

The Scan line 40 is connected to the gate of the first transistor 51, the gate of the second transistor 52, and the gate of the fourth transistor 54. The second wiring 942 is connected to the gate of the third transistor 53 and the gate of the fifth transistor 55.

The main differences between the pixel circuit 933 of the comparative example and the pixel circuit 33 of the present embodiment will be described. In the present embodiment, one distribution source wiring 44 (see FIG. 2) output from the Scan drive circuit 21 is branched into two outside the pixel circuit 33. Specifically, the branch point is arranged in the region between the display region 15 and the drive circuit 20. In the comparative example, one Scan line 40 output from the Scan drive circuit of the comparative example (not shown) is branched into two inside the pixel circuit 933.

FIG. 9 is a schematic plan view of the sub-pixel 932 of the comparative example. FIG. 9 is an enlarged view showing a portion corresponding to the sub-pixel 932 of one comparative example and its periphery as viewed from the front side of the display device of the comparative example (not shown). The description of the parts common to the pixel circuit 33 of the present embodiment shown in FIG. 5 will be omitted. Sub-pixel 932 includes an active layer 962, a gate 964 and a drain 966.

As shown in FIG. 9, the active layer 962 in one sub-pixel 932 has a first portion 9621, a second portion 9622, and a third portion 9623. The first portion 9621 has a starting end at the lower left of the sub-pixel 932, extends to the right along the short side of the sub-pixel 932, and bends upward near the center of the short side of the sub-pixel 932 to form the sub-pixel 932. It makes a U-turn counterclockwise on the upper side and extends downward, and has an end portion on the upper right side of the start end portion.

The second portion 9622 has one end at the lower right of the sub-pixel 932, extends upward, extends further upward through a U-shaped portion having an opening on the right side, and a position where the first portion makes a U-turn. It has a terminal on the right side of. The third portion 9623 is substantially rectangular and is located at the upper end of the sub-pixel 932.

As shown in FIG. 9, the gate 964 includes a Scan line 40, a third wire 943, an L-shaped region and a rectangular region. The Scan line 40 includes a strip-shaped portion and an L-shaped portion. The strip-shaped portion extends beyond the right and left boundaries of the sub-pixel 932 to the adjacent sub-pixel 932. The L-shaped portion extends upward from the band-shaped portion along the left side of the sub-pixel 932, and is bent to the right at a position about one-third from the bottom of the sub-pixel 932.

The third wiring 943 includes a strip-shaped portion and a T-shaped portion. The strip-shaped portion extends beyond the right and left boundaries of the sub-pixel 932 to the adjacent sub-pixel 932. The T-shaped portion is branched to the left and right at a position extending downward from the vicinity of the center of the strip-shaped portion. The branched left portion intersects the first portion 9621 of the active layer 962. The branched right portion intersects the second portion 9622 of the active layer 962.

The L-shaped region of the gate 964 is located between the third wire 943 and the upper side of the sub-pixel 932. The L-shaped region of the gate 964 overlaps the third portion 9623 of the active layer 962 described above. The L-shaped region of the gate 964 is slightly smaller than the third portion 9623. Therefore, the edge of the third portion 9623 does not overlap the L-shaped region of the gate 964. A portion of the gate 964 where the L-shaped region and the third region 9623 face each other and a gate insulating layer (not shown) between them form a holding capacity 47.

The rectangular area of the gate 964 is located between the third wire 943 and the Scan line 40. The rectangular region of the gate 964 covers the U-shaped portion of the second portion 9622 of the active layer 962.

As shown in FIG. 9, the drain layer forms a high power supply line 9451, a reference power supply line 9454, and a data line 9455, respectively.

The high power supply line 9451, the reference power supply line 9454, and the data line 9455 have a strip shape extending in the vertical direction. The right side is the high power line 9451, the center is the reference power line 9454, and the left side is the data line 9455. The high power line 9451, the reference power line 9454, and the data line 9455 extend beyond the upper and lower boundaries of the sub-pixel 932 to the adjacent sub-pixel 932.

The parts of the drain 966 other than the high power supply line 9451, the reference power supply line 9454, and the data line 9455 will be described later.

Here, the holding capacitance 47 and the second transistor 52 are connected via the connection drain layer 966a.
The relationship between the pixel circuit 933 of the comparative example described with reference to FIG. 8 and the structure of the sub-pixel 932 of the comparative example described with reference to FIG. 9 will be described. The Scan line 40, the third wiring 943, the high power supply line 9451, the reference power supply line 9454, and the data line 9455 use the same names in FIGS. 8 and 9, and thus the description thereof will be omitted.

Of the first portion 9621 of the active layer 962, the portion overlapping the L-shaped portion of the Scan line 40 forms the channel region of the first transistor 51. The portion of the first portion 9621 that overlaps the third wiring 943 below the U-turn position forms the channel region of the second transistor 52. The portion of the first portion 9621 that overlaps the strip-shaped portion of the Scan line 40 forms a channel region of the third transistor 53.

The portion of the second portion 9622 of the active layer 962 that overlaps with the third wiring 943 forms the channel region of the fourth transistor 54. The U-shaped portion of the second portion 9622 forms the channel region of the drive transistor 56.

Also in the comparative example, the active layer 962 connecting the channel region of the first transistor 51 and the channel region of the second transistor 52 is described as the first connection wiring. Further, the active layer 962 connecting the channel region of the second transistor 52 and the channel region of the third transistor 53 is described as the second connection wiring. The first connection wiring and the second connection wiring are active layers 962 whose resistance value is lowered by adding impurities.

[Effect of preventing uneven brightness due to feedthrough phenomenon]
The effect of preventing luminance unevenness due to the feedthrough phenomenon of the present embodiment will be described. In FIG. 9, it is assumed that the connecting drain layer 966a includes a metal member. Further, the third wiring 943 is made of metal. An insulating layer (not shown) is arranged between the connection drain layer 966a and the third wiring 943. In such a configuration, a parasitic capacitance is formed at a portion (see reference numeral F) where the connection drain layer 966a connecting the holding capacitance 47 and the second transistor 52 and the third wiring 943 intersect. In the following description, the portion of the parasitic capacitance thus formed will be referred to as the parasitic capacitance forming portion F. As shown in FIG. 9, in the sub-pixel 932 of the comparative example, the parasitic capacitance forming portion F is located above the channel portion of the second transistor 52.

FIG. 10 is an explanatory diagram illustrating a state in which the feedthrough phenomenon occurs. FIG. 10 shows an equivalent circuit of the pixel circuit 933 when the organic light emitting element 934 of the comparative example is in the light emitting state. Only the transistor in the conductive state is shown, and the first transistor 51 (see FIG. 8), the third transistor 53 (see FIG. 8), and the fifth transistor 55 (see FIG. 8) are in the cutoff state and are not shown. To do.

When the Em signal falls from H to L at the beginning of the light emission period t3, the second transistor 52 of the pixel circuit 933 changes from the cutoff state to the conductive state, and is in the state shown in FIG. The organic light emitting element 934 starts light emission when the pixel circuit 33 is in the state shown in FIG.

The drain current Ids flows from the source of the drive transistor 56 toward the drain. The drain current Ids changes according to the potential difference between the gate and the source of the drive transistor 56.

The drain current Ids flows from the anode electrode of the organic light emitting device 934 to the cathode electrode. The organic light emitting element 934 emits light with a brightness corresponding to the amount of current flowing from the anode electrode to the cathode electrode.

The source and drain of the second transistor 52 are in the state of floating nodes that do not conduct with each power supply, other transistors, or the like. On the other hand, a parasitic capacitance Cp is generated between the wiring connecting the source or drain of the holding capacitance 47 and the second transistor 52 and the third wiring 943, that is, in the parasitic capacitance forming portion F shown in FIG.

When the Em signal falls from H to L, a feedthrough phenomenon occurs in which the potential of the floating node is changed via the parasitic capacitance Cp. The feedthrough phenomenon is a phenomenon in which electric charges in a floating node move through a parasitic capacitance or a capacitance such as a gate insulating film. The cause of the feedthrough phenomenon in the comparative example is the parasitic capacitance Cp in FIG.

Due to the feedthrough phenomenon, the gate-source voltage Vgs of the drive transistor 56 fluctuates. As a result, the drive current Ids fluctuates, and the emission brightness of the organic light emitting element 934 also fluctuates. That is, in the display device of the comparative example, the brightness unevenness occurs due to the feedthrough phenomenon.

In the display device 10 of the present embodiment, it is possible to prevent the occurrence of luminance unevenness due to the feedthrough phenomenon. FIG. 11 is an explanatory diagram illustrating the reason why the feedthrough phenomenon can be prevented. FIG. 11 shows two consecutive sub-pixels 32 of the present embodiment.

In the sub-pixel 932 of the comparative example shown in FIG. 9, the holding capacitance 47 and the second transistor 52 are connected via the connection drain layer 966a, and the connection drain layer 966a and the third wiring 943 are connected to FIG. It intersects at the region indicated by the symbol F inside.

On the other hand, in the present embodiment of FIG. 11, the first wiring 41, the second wiring 42, and the third wiring 43 cross the plurality of sub-pixels 32. Then, in FIG. 11, the wiring portion connecting the second transistor 52 and the holding capacitance 47 is directly connected in the pattern of the active layer 62, and does not intersect with the gate layer 64 or the drain layer 66. Therefore, the sub-pixel 32 of the present embodiment does not have the parasitic capacitance forming portion F. Therefore, in the sub-pixel 32 of the present embodiment, the parasitic capacitance Cp by the parasitic capacitance forming portion F does not occur.

As described above, the cause of the feedthrough phenomenon in the comparative example is the parasitic capacitance Cp. The display device 10 of the present embodiment does not have a parasitic capacitance forming portion F. It is true that the second transistor 52 of the present embodiment has a capacitance due to the gate insulating film between the gate 64 and the active layer 62, but the components thereof are the same in the comparative example and the present embodiment. is there.

As described above, the display device 10 of the present embodiment can suppress the luminance unevenness due to the feedthrough phenomenon. As a result, deterioration of image quality can be suppressed.

Further, the parasitic capacitance Cp will be described. The magnitude of the parasitic capacitance Cp is proportional to the area where the third wiring 943 and the drain 966 face each other. Therefore, the size of the parasitic capacitance Cp changes depending on the width of the third wiring 943 and the width of the drain 966 in the parasitic capacitance forming portion F. That is, the magnitude of the parasitic capacitance Cp between the sub-pixels 932 varies due to the influence of the manufacturing error. For example, in the manufacturing process of the TFT, in the etching process of mainly processing the pattern, the in-plane distribution of the pattern occurs in the dimensions of the pattern.

FIG. 12 is a graph illustrating the effect of variation in parasitic capacitance Cp. The horizontal axis of FIG. 12 is Cp / (Cp + Cst). As described above, Cp is a parasitic capacitance and Cst is a stray capacitance 47. The horizontal axis of FIG. 12 is dimensionless. The vertical axis of FIG. 12 is the drain current Ids of the drive transistor 56. The unit of the vertical axis in FIG. 12 is ampere. The solid line in FIG. 12 shows the relationship between Cp / (Cp + Cst) and Ids. The method for deriving the relationship between Cp / (Cp + Cst) and the drain current Ids is shown below.

From the mathematical formula of the drain current in the saturation region of the semiconductor device (TFT), Ids is represented by the equation (1). The saturation region indicates an application condition in which the drain-source voltage is sufficiently larger than the gate-source voltage.

As shown in equation (1), Ids is determined by the gate-source voltage Vgs of the drive transistor, but the source voltage Vs of the drive transistor is connected to VDD during the light emission period.

The gate voltage Vg of the remaining drive transistor is derived. Equation (2) holds based on the charge conservation law when the second transistor 52 conducts from the cutoff at both ends of the holding capacitance 47 and the three nodes of the Em signal terminal.

From the above equations (1) and (2), the relationship between Cp / (Cp + Cst) and the drain current Ids can be obtained. The graph of FIG. 12 is an example when the data voltage Vdata = +2.25V.

The effect when Cp / (Cp + Cst) varies by plus or minus 5% around 0.0060 will be described as an example. As shown in FIG. 12, the variation of the drain current Ids is plus or minus 2.6%. The brightness of the organic light emitting element 34 also varies due to the variation in the drain current Ids. This variation causes uneven brightness.

As described with reference to FIG. 12, the display device 10 of the present embodiment does not have the parasitic capacitance forming portion F. Therefore, it is possible to reduce the luminance unevenness caused by the influence of the parasitic capacitance Cp as compared with the display device of the comparative example.

[Effect of suppressing uneven brightness due to disturbance]
The emission brightness of the organic light emitting element 34 may fluctuate in the middle of the emission period. As a result, uneven brightness occurs.

13 and 14 are explanatory views illustrating the effect of reducing the bound parasitic capacitance of the active layer 62. FIG. 13 shows a part of the pixel circuit 33 when the organic light emitting element 34 of the present embodiment is in a light emitting state. The transistor shown by the broken line means a transistor in a cutoff state. As described above, the first transistor 51 and the third transistor 53 are in the cutoff state.

The source and drain of the second transistor 52 are in the state of floating nodes that are not connected to the outside such as other transistors. The portion surrounded by the alternate long and short dash line in FIG. 13 schematically shows the space between the source and the drain of the second transistor 52. The potential of the floating node is susceptible to disturbance. The disturbance includes, for example, fluctuations in the potential of adjacent wiring, incident of electromagnetic noise from the outside of the display device 10, and the like. When the coupled parasitic capacitance generated between the wiring and the like is large, the influence of the disturbance becomes large.

As described above, when the potential of the gate of the drive transistor 56 fluctuates, the brightness of the organic light emitting element 34 also fluctuates. Luminance unevenness occurs due to fluctuations in the brightness of the organic light emitting element 34 during the light emission period.

FIG. 14 is an explanatory view in which a portion unnecessary for the explanation of the floating node is deleted from the schematic plan view shown in FIG. The portion surrounded by the alternate long and short dash line in FIG. 14 (see reference numeral W14) shows the wiring between the second transistor 52 and the third transistor 53 (hereinafter, referred to as wiring W14). The wiring W14 is connected to the gate of the drive transistor 56 as shown in FIG.

FIG. 15 is an explanatory diagram illustrating a comparative example of the effect of reducing the bound parasitic capacitance of the active layer 62. FIG. 15 is an explanatory view showing a portion corresponding to FIG. 14 in the schematic plan view shown in FIG. The portion surrounded by the alternate long and short dash line in FIG. 15 (see reference numeral W15) shows the wiring between the first transistor 51 and the third transistor 53 (hereinafter, referred to as wiring W15). As shown in FIG. 8, the wiring W15 is connected to the gate of the drive transistor 56. As described above, the wirings W14 and W15 are in a floating state during the light emitting period. That is, the wirings W14 and W15 include a node that becomes a floating node during the light emitting period. The wirings W14 and W15 are examples of parts sensitive to the characteristics of the pixel circuit 33 described with reference to FIGS. 2 and 3.

The wiring portion formed of the active layer 62 between the first transistor 51 and the second transistor 52 is covered with a gate 64 (see FIGS. 5, 6, and 14). The gate 64 that covers the wiring portion can block disturbances to the wiring portion. Therefore, it is not necessary to consider the influence of disturbance for this wiring portion.

The longer the wiring, including the floating nodes, the more susceptible it is to disturbances. When susceptible to disturbance, the potential of the gate of the drive transistor 56 fluctuates more. Therefore, if the length of the wiring including the floating node is shortened, it is less likely to be affected by the disturbance. As a result, the fluctuation of the brightness of the organic light emitting element 34 due to the fluctuation of the potential of the gate is reduced, and the uneven brightness can be suppressed.

FIG. 14 and FIG. 15 will be compared and described. As shown in the figure, the length of the wiring W14 of this embodiment is shorter than the length of the wiring W15 of the comparative example. Therefore, in the present embodiment, the coupling parasitic capacitance of the wiring W14 is smaller than that of the comparative example, and the wiring is less susceptible to disturbance. Therefore, according to the present embodiment, it is possible to realize the display device 10 in which the brightness unevenness due to the disturbance is suppressed.

The reason why the length of the wiring W14 of the present embodiment is shorter than the length of the wiring W15 of the comparative example will be described. In the present embodiment, the third wiring 43 is arranged between the first wiring 41 and the second wiring 42. The gate of the first transistor 51 is connected to the first wiring 41. The gate of the second transistor 52 is connected to the second wiring 42. The gate of the third transistor 53 is connected to the second wiring 42.

Therefore, the first transistor 51, the second transistor 52, and the third transistor 53 connected in series can be arranged in the vicinity of the first wiring 41, the third wiring 43, and the second wiring 42. .. As a result, it is possible to realize an arrangement in which the wiring including the floating node is short.

As described above, the wiring portion formed of the active layer 62 between the first transistor 51 and the second transistor 52 is covered with the gate 64. Therefore, it is not necessary to consider the influence of disturbance for this wiring portion.

On the other hand, in the comparative example, both the gate of the first transistor 51 and the gate of the third transistor 53 are connected to the Scan line 40. On the other hand, the gate of the second transistor 52, which is connected in series between the first transistor 51 and the third transistor 53, is connected to the third wiring 943.

Therefore, it is necessary to arrange the first transistor 51 and the third transistor 53 located at both ends of the three transistors connected in series in a U shape so as to be close to each other. As a result, as shown in FIG. 15, a long wiring W15 that bends in a U shape is generated.

[Effect of reducing the number of contact holes]
The contact hole is a conductive portion that connects the upper conductor layer and the lower conductor layer of the insulating layer. The first conductive portion 71 and the second conductive portion 72 described with reference to FIGS. 6 and 7 are examples of contact holes.

FIG. 16 is an explanatory diagram illustrating the effect of reducing the number of contact holes. FIG. 16 is an explanatory view in which a portion unnecessary for explaining the effect of reducing the number of contact holes is deleted from the schematic plan view shown in FIG. The following description describes the sub-pixel 32 in the range shown in FIG.

The sub-pixel 32 of the present embodiment has four first conductive portions 71, that is, four contact holes. Two first conductive portions 71 are located along the lower side of the sub-pixel 32, one in the central portion, and one in the vicinity of the drive transistor 56.

FIG. 17 is an explanatory diagram illustrating a comparative example of the effect of reducing the number of contact holes. FIG. 17 is an explanatory view showing a portion corresponding to FIG. 16 in the schematic plan view shown in FIG. The following description describes the sub-pixel 932 in the range shown in FIG.

The sub-pixel 932 of the comparative example has six first conductive portions 971, that is, six contact holes. The first conductive portion 971 is located at the lower left of the sub-pixel 932, at the diagonally upper right of the sub-pixel 932, at the center portion thereof, two above the first conductive portion 971, and one near the drive transistor 56.

16 and 17 will be compared and described. The number of contact holes of the present embodiment is two less than that of the contact holes of the comparative example. The number of contact holes in this embodiment is two-thirds of that in the comparative example.

Contact holes may cause problems such as poor continuity. According to the present embodiment, by reducing the number of contact holes, defects are reduced, and it is possible to provide a display device 10 having a high manufacturing yield.

[Effect of miniaturizing the sub-pixel 32]
FIG. 18 is an explanatory diagram illustrating the effect of reducing the size of the sub-pixel 32. FIG. 18A is a schematic plan view of the sub-pixel 932 of the comparative example shown in FIG. FIG. 18B is a schematic plan view of the sub-pixel 32 of the present embodiment shown in FIG.

The conditions of FIGS. 18A and 18B are the same in that they are not directly related to the difference in the essential configurations of FIGS. 18A and 18B. Specifically, the area of the holding capacity 47, the channel length of the drive transistor 56, the thickness and spacing of each pattern, and the aspect ratio of the sub-pixel 32 and the sub-pixel 932 of the comparative example are the same. The vertical and horizontal dimensions of the sub-pixel 32 in FIG. 18B are 13% shorter than the vertical and horizontal dimensions of the sub-pixel 932 in the comparative example of FIG. 18A.

According to this embodiment, the pixel circuit 33 having the same function can be arranged in a small area. Therefore, it is possible to provide a high-definition display device 10 in which the pixels 31 are small.

[Effect of simplifying the Scan drive circuit 21]
FIG. 19 is an explanatory diagram illustrating the effect of simplifying the Scan drive circuit 21. FIG. 19 is a schematic plan view of the display device 10. FIG. 19 shows a display area 15 in which the sub-pixels 32 are arranged, a Scan drive circuit 21, an Em drive circuit 23, a branch source wiring 44, a first wiring 41, a second wiring 42, and a third wiring 43.

The left-right direction in FIG. 19 is the above-mentioned first direction, that is, the scanning line direction. Further, the vertical direction in FIG. 19 is the above-mentioned second direction, that is, the scanning direction. A case where three pixels 31 (see FIG. 2) are arranged in the second direction will be described as an example.

The Scan drive circuit 21 has a plurality of unit drive circuits 211. One unit drive circuit 211 generates a first signal to be supplied to the sub-pixels 32 arranged in one line. The unit drive circuit 211 operates according to the control by the driver IC 13 (see FIG. 1).

The branch source wiring 44 extends to the right from the unit drive circuit 211. The unit drive circuit 211 outputs a first signal for controlling the pixel circuit 33 to the branch source wiring 44. One branch source wiring 44 is branched into two wires, a first wiring 41 and a second wiring 42, between the Scan drive circuit 21 and the first sub-pixel 32 (the leftmost sub-pixel 32). ..

A third wiring 43 extends to the left from the Em drive circuit 23. The Em drive circuit 23 outputs a second signal for controlling the pixel circuit 33 to the third wiring 43. The third wiring 43 does not intersect the first wiring 41, the second wiring 42, and the branch source wiring 44. The third wiring 43 is located between the first wiring 41 and the second wiring 42 that supply the first signal to the same sub-pixel 32.

FIG. 20 is an explanatory diagram illustrating a comparative example of the effect of simplifying the Scan drive circuit 21. In the comparative example of FIG. 20, the same sub-pixel 32 and Em drive circuit 23 as in the present embodiment described with reference to FIG. 5 and the like are used. Therefore, the sub-pixel 32 and the Em drive circuit 23 will be described using the same reference numerals in the present embodiment and the comparative example.

FIG. 20 is a schematic plan view of the display device 910 of the comparative example. FIG. 20 shows a display area in which the sub-pixels 32 are arranged, a Scan drive circuit 921, an Em drive circuit 23, a first wiring 941, a second wiring 942, and a third wiring 943.

The Scan drive circuit 921 of the comparative example includes the right side Scan drive circuit 26 and the left side Scan drive circuit 27. The right side Scan drive circuit 26 and the left side Scan drive circuit 27 have a plurality of unit drive circuits 211. The unit drive circuit 211 in the right side Scan drive circuit 26 and the left side Scan drive circuit 27 is the same circuit as the unit drive circuit 211 in FIG.

From the unit drive circuit 211 in the left Scan drive circuit 27, the first wiring 941 extends to the right, bypassing the unit drive circuit 211 in the right Scan drive circuit 26. One unit drive circuit 211 generates a first signal to be supplied to the first wiring 941 connected to the sub-pixels 32 arranged on one scanning line. The unit drive circuit 211 operates according to the control by the driver IC of the comparative example (not shown).

A second wiring 942 extends to the right from the unit drive circuit 211 in the right Scan drive circuit 26. One unit drive circuit 211 generates a first signal to be supplied to the second wiring 942 connected to the sub-pixel 932 arranged on one scanning line. The unit drive circuit 211 operates according to the control by the driver IC 13 of the comparative example (not shown).

FIG. 19 and FIG. 20 will be compared and described. The display device 10 of the present embodiment includes one Scan drive circuit 21 instead of the right Scan drive circuit 26 and the left Scan drive circuit 27. The display device 10 of the present embodiment includes a first wiring 41 and a second wiring 42 branched from the branch source wiring 44.

According to this embodiment, the scale of the Scan drive circuit 21 can be reduced to half that of the Scan drive circuit 921 of the comparative example. Further, since it is not necessary to control both the right side drive circuit 26 and the left side drive circuit 27, the load on the driver IC 13 can be reduced. That is, it is possible to provide a display device 10 in which the configuration of the Scan drive circuit 21 is simplified.

As described above, in the present embodiment, prevention of brightness unevenness due to wiring intersection, prevention of brightness unevenness due to disturbance, yield improvement by reducing the number of contact holes, high definition by downsizing of the sub-pixel 32, Scan. The effects such as simplification of the configuration of the drive circuit 21 are realized.

The technical significance of this embodiment will be described.

The pixel circuit 33 described with reference to FIG. 4 and the pixel circuit 933 of the comparative example described with reference to FIG. 8 include six transistors and one holding capacity 47. In the following description, this pixel circuit 33 will be referred to as a 6T1C circuit. The 6T1C circuit is a pixel circuit capable of preventing an image retention phenomenon and a leakage light emission phenomenon. The operation of the 6T1C circuit will be described later.

The image retention phenomenon is a phenomenon in which when a white display signal is input to a pixel 31 that has been displayed in black for a while, it takes several frames for the pixel 31 to actually emit light with the brightness of the white display. The cause of the image retention phenomenon is the hysteresis characteristic of the drive transistor 56.

The leakage light emission phenomenon is a phenomenon in which the organic light emitting element 34 during the non-light emitting period emits light due to the current flowing from the adjacent sub-pixel 32 or the like.

When the image retention phenomenon and the leakage light emission phenomenon occur, the image quality of the display device 10 deteriorates. By adopting the 6T1C circuit for the pixel circuit 33, it is possible to provide a display device 10 having high image quality.

By the way, a design using one signal bus line (input line) for one signal is common in layout design. The layout of the sub-pixel 32 shown in FIG. 9 is a layout created based on a design in which one input line is used for one signal.

The present inventor has a first wiring 41, a second wiring 42, and a second wiring 42 that supply a first signal to the pixel circuit 33 in order to realize a high-quality display device 10 using the 6T1C circuit. The third wiring 43 that supplies the signal of the above to the pixel circuit 33 is arranged in the sub-pixel 32 as shown in FIGS. 2 and 3. With this configuration, it is possible to prevent the first wiring 41 to the third wiring 43 from being complicatedly routed in the sub-pixel 32. By this suppression, as described with reference to FIGS. 14 and 15, the wiring including the floating node in the pixel circuit 33 can be shortened.

Further, one of the development trends of the display device 10 is high definition. In order to increase the definition of the display device 10, it is necessary to make the pixels 31 and the sub-pixels 32 smaller. In order to make the sub-pixel 32 smaller, it is necessary to efficiently arrange the pixel circuit 33 in a small area.

As a general rule, when designing a layout, the area of the circuit increases as the number of parts to be arranged increases. Therefore, it is desirable to arrange only one wiring material that transmits one signal. When two wiring materials for transmitting one signal are arranged, the sub-pixel 32 tends to be large, and it tends to be difficult to realize high definition.

However, by daringly arranging two wirings for transmitting the first signal, the present inventor has realized a layout in which the active layer 62 and the connection wiring are short and do not branch. Therefore, the occupied area of the active layer 62 and the connecting wiring in the sub-pixel 32 is reduced. The number of contact holes has also decreased. Therefore, as described with reference to FIG. 18, the vertical and horizontal lengths of the sub-pixel 32 can be shortened by 13%.

Further, effects such as reduction of parasitic capacitance Cp, prevention of variation in parasitic capacitance Cp, and reduction of combined parasitic capacitance can be obtained.

By the way, a circuit may be designed so that one signal output line is output from one signal output circuit. That is, the first wiring 41 and the second wiring 42 may be connected to different Scan drive circuits.

FIG. 20 is a diagram showing a state in which the first wiring 41 and the second wiring 42 are connected to different Scan drive circuits. As shown in FIG. 1, the Scan drive circuit 21 of the present embodiment is arranged along the left side of the display area 15.

The Scan drive circuit 921 of the comparative example shown in FIG. 20 includes a unit drive circuit 211 having twice the number of the Scan drive circuit 21 of the present embodiment shown in FIG. When the Scan drive circuit 921 of the comparative example is arranged along the left side of the display area 915 as in the Scan drive circuit 21 of FIG. 1, the width of the Scan drive circuit 21 in the left-right direction is doubled. Therefore, the so-called frame area around the display area 915 becomes thick.

In order to prevent the frame area from becoming thick, the inventor of the present invention has one branch source wiring 44 between the Scan drive circuit 21 and the display area 15 as a first wiring 41 and a second wiring 42. We proposed a configuration that branches into two.

FIG. 21 is a hardware configuration diagram of the display device 10. The display device 10 includes an FPC 14, a driver IC 13, a TFT substrate 16, and a power supply device 24. The TFT substrate 16 has a drive circuit 20 and a display area 15. The drive circuit 20 includes, for example, a Scan drive circuit 21, a data drive circuit 22, and an Em drive circuit 23.

The driver IC 13 processes the image signal acquired via the FPC 14 and outputs it to the drive circuit 20 of the TFT substrate 16. The drive circuit 20 controls the sub-pixels 32 arranged in the display area 15.

FIG. 22 is a configuration diagram of the driver IC 13. The function of the driver IC 13 will be described with reference to FIG. The driver IC 13 includes an adjusting unit 81, a receiving unit 86, a high voltage logic unit 85, an analog control unit 88, an analog output unit 89, and a DC / DC converter 80.

The adjusting unit 81 is a low-voltage logic circuit that can operate at high speed. The adjusting unit 81 includes a brightness adjusting unit 82, a color tone adjusting unit 83, and a gamma adjusting unit 84. The brightness adjustment unit 82, the color tone adjustment unit 83, and the gamma adjustment unit 84 are realized by a brightness adjustment circuit, a color tone adjustment circuit, and a gamma adjustment circuit, respectively.

The adjusting unit 81 may be a processor mounted in the driver IC 13. In this case, the adjusting unit 81 expands and executes, for example, a control program read from a non-volatile storage device (not shown) contained in the driver IC 13 on a DRAM (not shown) mounted in the driver IC 13. .. As described above, the brightness adjustment unit 82, the color tone adjustment unit 83, and the gamma adjustment unit 84 can be realized.

A control signal and an image signal are input to the driver IC 13 via the FPC 14. Further, the driver IC 13 receives an input power supply via the FPC 14. The image signal is, for example, a signal conforming to a standard defined by the MIPI (Mobile Industry Processor Interface) Alliance.

The receiving unit 86 receives the image signal and outputs it to the adjusting unit 81. The brightness adjusting unit 82, the color tone adjusting unit 83, and the gamma adjusting unit 84 sequentially process the image signal based on the control signal, and adjust the signal so as to match the characteristics of the display device 10.

The high voltage logic unit 85 generates a display panel control signal based on the image signal processed by the adjustment unit 81. The display panel control signal is a high voltage digital signal. The high voltage logic unit 85 outputs a display panel control signal to the Scan drive circuit 21 and the Em drive circuit 23 in the drive circuit 20 via the wiring on the TFT substrate 16.

As described above, the Scan drive circuit 21 outputs the first signal to the branch source wiring 44 (see FIG. 3) based on the display panel control signal. The Em drive circuit 23 outputs a second signal to the third wiring 43 (see FIG. 3) based on the display panel control signal.

The analog control unit 88 and the analog output unit 89 process the image signal processed by the adjustment unit 81 and output the output terminal signal. The output terminal signal is an analog signal. The analog output unit 89 outputs an output terminal signal to the data drive circuit 22. The data drive circuit 22 outputs an analog signal indicating the brightness of the sub-pixel 32 to the data line 455 (see FIG. 4).

The DC / DC converter 80 generates a display panel drive power supply based on the image signal and the input power supply processed by the adjusting unit 81 and supplies the power supply to each circuit on the TFT substrate 16. Each circuit is operated by a display panel drive power supply supplied by the DC / DC converter 80.

Based on the power supply supplied by the DC / DC converter 80, each power supply is supplied from the high power supply line 451 to the reference power supply line 454 (see FIG. 4). Here, the input power supply in the driver IC 13 is supplied from the power supply device 24 located outside the TFT substrate 16 via the FPC 14.

The Scan control circuit 21, the data drive circuit 22, and the Em drive circuit 23 control the brightness of the organic light emitting element 34 (see FIG. 4) of each sub-pixel 32 (see FIG. 2) via the pixel circuit 33 (see FIG. 4). .. The display area 15 (see FIG. 1) displays an image by this control.

FIG. 23 is a time chart showing a control signal of the pixel circuit 33. 24 to 26 are explanatory views illustrating the operation of the pixel circuit 33. The operation of the 6T1C circuit shown in FIG. 4 will be described with reference to FIGS. 23 to 26. In the description of the following figure, the state in which the transistor is not conducting is schematically indicated by a cross.

The outline of the time chart will be described with reference to FIG. 23. The horizontal axis of FIG. 23 is time. Scan indicates the state of the first signal. When the Scan is H, the first wiring 41 and the second wiring 42 supply a high potential. When the Scan is L, the first wiring 41 and the second wiring 42 supply the Low potential.

Em indicates the state of the second signal. When Em is H, the third wire 43 supplies the High potential. When Em is L, the third wire 43 supplies the Low potential.

Vdata indicates a signal to be input to the data line 455. Vref means a state in which the same reference voltage Vref as the reference power supply line 454 is input to the data line 455. Black and White mean a voltage indicating the brightness that causes the organic light emitting element 34 to emit light. In the following description, the voltage input from the data line 455 will be referred to as the data voltage Vdata.

The description will be continued with reference to FIGS. 23 and 24. The time on the time chart will be described by dividing it into a first period t1, a second period t2, and a third period t3. The first period t1 is a period for initializing the pixel circuit 33. In the second period t2, the pixel circuit 33 detects the threshold value of the drive transistor 56 and stores (also called holding or writing) a voltage (charge) corresponding to the emission brightness of the organic light emitting element 34 in the holding capacitance 47. It is a period to do.

The electric charge corresponding to the emission brightness of the organic light emitting element 34 is a voltage corresponding to the image. The third period t3 is a period during which the organic light emitting element 34 emits light. From the start of the first period t1 to the start of the third period t3, the organic light emitting element 34 does not emit light, which is a non-light emitting period t4.

The first transistor 51 to the fifth transistor 55 are in a conductive state when a Low potential is supplied to the gate, and are in a cutoff state when a High potential is supplied to the gate.

The power supply voltage supplied from the high power supply line 451 to the data line 455 to the pixel circuit 33 will be described. The power supply voltage is set so as to satisfy both of the following equations.
VDD> Vref
VDD> VSS ≧ Vrst
VDD is a high power supply voltage.
VSS is a low power supply voltage.
Vref is a reference voltage.
Vrst is the reset voltage.

The first period t1 will be described. Since Scan and Em are Low, the first transistor 51 to the fifth transistor 55 are in a conductive state.

The gate of the data line 455 and the drive transistor 56 is conducted through the third transistor 53. In the first period t1, the data voltage Vdata is equal to the reference voltage Vref. Therefore, the drive transistor 56 also becomes conductive, and a current i1 flows between the source and the drain. The current i1 initializes the hysteresis characteristic of the drive transistor 56. Initializing the hysteresis characteristic of the drive transistor 56 prevents the above-mentioned image retention phenomenon from occurring.

As shown by the broken line in FIG. 24, the current i1 flows to the reset power line 453 via the fifth transistor 55. The current i1 does not flow into the organic light emitting element 34. Therefore, the leakage light emission phenomenon of the organic light emitting element 34 does not occur.

A reference voltage Vref and a high power supply voltage VDD are applied to the left and right terminals of the holding capacity 47. The holding capacity 47 accumulates electric charges corresponding to the potential difference between the left and right terminals (in other words, between the first and second terminals).

As described above, the pixel circuit 33 at the end of the first period t1 is in a state in which initialization is completed.

The second period t2 will be described with reference to FIGS. 23 and 25. Since the Scan is Low, the first transistor 51, the third transistor 53, and the fifth transistor 55 are in a conductive state. Since Em is High, the fourth transistor 54 and the second transistor 52 are in the cutoff state.

The data voltage Vdata is input from the data line 455 to the gate of the drive transistor 56 via the third transistor 53. In the second period t2, the data voltage Vdata is a voltage indicating the emission brightness of the organic light emitting element 34. The drive transistor 56 also becomes conductive, and a current i2 flows between the source and the drain. The electric charge accumulated in the holding capacity 47 during the first period t1 is reduced by the flow of the current i2. Along with this, the potential difference between the electrodes having the holding capacity 47 also decreases.

As shown by the broken line in FIG. 25, the current i2 flows to the reset power line 453 via the fifth transistor 55. The current i2 does not flow into the organic light emitting element 34. Therefore, the leakage light emission phenomenon of the organic light emitting element 34 does not occur.

With the gate potential of the drive transistor 56 fixed to Vdata and the potential of the first terminal of the holding capacitance 47 fixed to Vref, the current i2 becomes sufficiently small. That is, the drive transistor 56 is cut off. Then, the potential difference between the gate and the source of the drive transistor 56 becomes equal to the threshold voltage Vth of the drive transistor 56. Since the gate-source voltage Vgs and Vth are equal, the potential of the source of the drive transistor 56, that is, the second terminal of the holding capacitance 47 becomes (Vdata-Vth). Therefore, the holding capacity 47 holds the electric charge corresponding to the voltage obtained by subtracting the threshold voltage Vth and the reference voltage Vref from the data voltage Vdata- (data voltage Vdata- (threshold voltage Vth + reference voltage Vref)).

The effect of compensating for the threshold voltage Vth variation of the drive transistor 56 by the pixel circuit 33 will be described. In the following description, the gate of the drive transistor 56 will be referred to as node A, the source of the drive transistor 56 will be referred to as node B, and the first terminal of the holding capacity 47 will be referred to as node C.

The potential VA of the node A, the potential VB of the node B, and the potential VC of the node C are as follows, and the voltage including the threshold voltage Vth of the drive transistor 56 and the data voltage Vdata is held in the holding capacity 47. As described above, in the present embodiment, the source follower type threshold voltage detecting means is used.
VA = Vdata
VB = VDD → Vdata-Vth
VC = Vref

In the third period t3 shown in FIG. 26, the third transistor 53, the first transistor 51, and the fifth transistor 55 are turned off, and the second transistor 52 and the fourth transistor 54 are turned on. A reference voltage Vref is supplied from the data line 455.

As a result, a potential difference Vdata-Vth-Vref between both terminals of the holding capacitance 47 is applied between the gate and the source of the drive transistor 56, and the corresponding current Ids flows to the organic light emitting element 34, and the organic light emitting element 34 Lights up.

At this time, the potential VB of the node B becomes a high power supply voltage VDD via the fourth transistor 54. On the other hand, the potential VA of the node A is a value obtained by subtracting the potential difference between both terminals of the holding capacity 47 from the high power supply voltage VDD. Therefore, the current Ids flowing through the drive transistor 56 is given by the following equation.
VA = VC = VDD- (Vdata-Vth-Vref)
VB = VDD
Therefore,
Ids = (1 / 2β) ((VA-VB) -Vth) ²
= (1 / 2β) (( VDD- (Vdata-Vth-Vref))- VDD) -Vth) ²
= (1 / 2β) (( VDD- (Vdata-Vth-Vref))- VDD) -Vth) ²
= (1 / 2β) (Vref-Vdata) ²

Note that β in the above equation is a constant determined by the structure and material of the drive transistor 56. That is, for the drive transistor 56, assuming that the capacitance of the gate insulating film is Cox, the channel width is W, and the channel length is L, β is given by the following equation.
β = Cox (W / L)

As can be seen from the above equation, since the current Ids does not include the term of the threshold voltage Vth, it is not affected by the variation and fluctuation of the threshold voltage Vth. This is the threshold voltage Vth variation compensation effect of the pixel circuit 33.

As described above, the pixel circuit 33 at the end of the second period t2 completes the detection of the threshold voltage Vth of the drive transistor 56 and the storage of the data voltage Vdata corresponding to the emission brightness of the organic light emitting element 34.

Since Scan and Em are High in the period from the end of the second period t2 to the start of the third period t3, the first transistor 51 to the fifth transistor 55 are in a cutoff state. No current flows through the pixel circuit 33.

The third period t3 will be described with reference to FIGS. 23 and 26. Since the Scan is High, the first transistor 51, the third transistor 53, and the fifth transistor 55 are in the cutoff state. Since Em is Low, the fourth transistor 54 and the second transistor 52 are in a conductive state.

The first terminal of the holding capacity 47, that is, the gate potential of the drive transistor 56 is in the state of the floating node described with reference to FIG. Therefore, the potential difference between the terminals of the holding capacity 47 remains unchanged at the potential difference Vc at the end of the second period t2. Therefore, the potential difference between the gate and the source of the drive transistor 56 is also maintained unchanged at the potential difference Vc at the end of the second period t2.

A drain current Ids corresponding to the potential difference Vc between the gate and the source flows through the drive transistor 56. As shown by the broken line in FIG. 26, the current Ids flows to the low power supply line 452 via the organic light emitting element 34. The organic light emitting element 34 emits light with a brightness corresponding to Ids. Therefore, the third period t3 is a period during which the organic light emitting element 34 emits light.

It is desirable that the potential difference between the high power supply voltage VDD and the reset voltage Vrst is larger than the potential difference between the high power supply voltage VDD and the low power supply voltage VSS. That is, it is desirable that the relationship between the high power supply voltage VDD, the low power supply voltage VSS, and the reset voltage Vrst satisfies the following equation.

By setting in this way, in the first period t1 and the second period t2, the current from the source to the drain of the drive transistor 56 can be surely flowed to the reset power supply line 453. Therefore, the leakage light emission of the organic light emitting element 34 can be reliably prevented.

Further, the potential difference between the high power supply voltage VDD and the reset voltage Vrst may be larger than the value obtained by subtracting the light emission threshold voltage Vf of the organic light emitting element 34 from the potential difference between the high power supply voltage VDD and the low power supply voltage VSS. desirable. That is, it is desirable that the relationship between the high power supply voltage VDD, the low power supply voltage VSS, the reset voltage Vrst, and the emission threshold voltage Vf satisfies the following equation.

The emission threshold voltage Vf will be described. The light emission threshold voltage Vf is a voltage that is a boundary between the case where the organic light emitting element 34 emits light and the case where it does not emit light. When the voltage of the anode electrode of the organic light emitting element 34 is equal to or greater than the sum of the voltage of the cathode electrode of the organic light emitting element 34 and the light emission threshold voltage Vf, the organic light emitting element 34 emits light. When the voltage of the anode electrode of the organic light emitting element 34 is less than the sum of the voltage of the cathode electrode of the organic light emitting element 34 and the light emission threshold voltage Vf, the organic light emitting element 34 does not emit light.

When the reset voltage Vrst has a potential equal to or lower than the low power supply voltage VSS, no current flows into the organic light emitting element 34 during the non-light emitting period t4. Therefore, leakage light emission can be prevented.

Further, the drain of the drive transistor 56 has the same voltage as the reset voltage Vrst. Since the source follower operation of the drive transistor 56 base insulating layer 61 is stable, it is possible to prevent variations in the potential difference Vc at the end of the second period t2.

27 to 33 are explanatory views for explaining the manufacturing process of the display panel. An outline of a method for manufacturing a display panel used for the display device 10 of the present embodiment will be described with reference to FIGS. 27 to 33.

The manufacturing equipment such as the vapor deposition equipment, the sputtering equipment, the spin coating equipment, the exposure equipment, the developing equipment, the etching equipment, the sealing equipment, the cutting equipment, and the transporting equipment connecting these equipments used for manufacturing the display panel is not shown. .. These devices operate according to a predetermined program.

FIG. 27 is an explanatory view showing the position of a cross section for explaining the manufacturing process. In the following description, a schematic cross-sectional view taken along the line XXVIII-XXVIII in FIG. 27 will be used.

This will be described with reference to FIG. 28. FIG. 28 shows a cross section of the first substrate 11 used for manufacturing the sub-pixel 32. The first substrate 11 is a flat plate. The description will be continued with reference to FIG. As shown in FIG. 29, the manufacturing apparatus forms a base insulating layer 61 having a uniform thickness by a CVD method or the like. The manufacturing apparatus forms an active layer 62 having a predetermined shape by a sputtering method, a photolithography method, or the like.

The description will be continued with reference to FIG. As shown in FIG. 30, the manufacturing apparatus forms a gate insulating layer 63 that covers the active layer 62 and the underlying insulating layer 61 by a CVD method or the like. The manufacturing apparatus forms a gate 64 having a predetermined shape by a sputtering method, a photolithography method, or the like.

The description will be continued with reference to FIG. As shown in FIG. 31, the manufacturing apparatus forms an interlayer insulating layer 65 that covers the gate 64 and the gate insulating layer 63 by a CVD method or the like. The manufacturing apparatus forms a hole extending from the surface of the interlayer insulating layer 65 to the active layer 62 by a dry etching method or the like.

The manufacturing apparatus forms a drain 66 having a predetermined shape by a sputtering method, a photolithography method, or the like. As described above, the material of the drain 66 is a conductor. The conductor, which is the material of the drain 66, also covers the inner surface of the hole and forms the first conductive portion 71 that connects the drain 66 and the active layer 62.

The description will be continued with reference to FIG. As shown in FIG. 32, the manufacturing apparatus forms a flattening layer 67 covering the drain 66 and the interlayer insulating layer 65 by a spin coating method or the like. The manufacturing apparatus forms a hole extending from the surface of the flattening layer 67 to the drain 66 by a dry etching method or the like.

The manufacturing apparatus forms an anode electrode 18 having a predetermined shape by a sputtering method, a photolithography method, or the like. As described above, the material of the anode electrode 18 is a conductor. The conductor, which is the material of the anode electrode 18, also covers the inner surface of the hole and forms the second conductive portion 72 connecting the anode electrode 18 and the drain 66.

The description will be continued with reference to FIG. 33. As shown in FIG. 33, the manufacturing apparatus forms a first insulating portion 69 having a predetermined shape by a CVD method, a dry etching method, or the like. The first insulating portion 69 is provided with an opening 691 (see FIG. 6) that does not cover the anode electrode 18.

In the manufacturing apparatus, an organic light emitting layer (not shown), a cathode electrode 19 (see FIG. 1), and a second substrate 12 (see FIG. 1) are sequentially laminated. The display panel is completed by the above.

As described above, in the manufacturing apparatus, the first wiring 41 and the second wiring 42 for supplying the first signal and the third wiring 42 for supplying the second signal are supplied to one surface of the first substrate 11. The first wiring 41, the third wiring 43, and the second wiring 43 are connected to the wiring 43 along the first direction in the region where the pixel circuit 33 controlled by the first signal and the second signal is arranged. It is formed together with the pixel circuit 33 so as to be arranged in the order of the wirings 42. The manufacturing apparatus arranges an organic light emitting element 34 controlled by a current supplied by the pixel circuit 33 above the pixel circuit 33, the first wiring 41, the second wiring 42, and the third wiring 43.

By using such a manufacturing method, as a result, it is possible to manufacture a high-quality display device 10 having less uneven brightness. Further, it is also possible to provide a high-definition display device 10.

The shapes of the active layer 62, the gate 64, the drain 66, and the like described in the present embodiment are all examples, and are simplified schematic views for the sake of explanation. Moreover, the manufacturing process and the manufacturing apparatus used in each process are also examples.

In the present embodiment, a case where a P-type transistor is used for the pixel circuit 33 has been described as an example. An N-type transistor may be used for the pixel circuit 33. In this case, the source and drain of the pixel circuit 33 are inverted.

[Embodiment 2]
The present embodiment relates to a display device 10 that shares a high power supply line 451 and a reference power supply line 454 between sub-pixels 32 adjacent to each other in the first direction.

FIG. 34 is a schematic plan view of the sub-pixel 32 of the second embodiment. FIG. 34 is an enlarged view of the two sub-pixels 32 and their periphery as seen from the front side of the display device 10. The display device 10 of the present embodiment will be described with reference to FIG. 34. The description of the parts common to the first embodiment will be omitted.

The sub-pixel 32 shown on the left side of FIG. 34 will be described as an example. The drain 66 includes a high power line 451 and a reference power line 454 and a data line 455. The high power supply line 451 and the reference power supply line 454 and the data line 455 have a strip shape extending in the vertical direction.

The high power line 451 is located on the right side of the sub-pixel 32 on the left side. The reference power line 454 is located on the left side of the sub-pixel 32 on the left side. The data line 455 is located on the left side of the sub-pixel 32 on the left side.

The first portion of the active layer 62 extends along the lower side of the sub-pixel 32, bends upward at a position about three-quarters from the left of the lower side, and extends upward through a U-shaped portion having an open right side. It bends three times, rightward, upward, and rightward, and extends beyond the right edge of the area of the sub-pixel 32 to the adjacent sub-pixel 32. The first portion extends to the adjacent sub-pixel 32 at the bottom of the left side of the sub-pixel 32. Further, the central portion of the lower side of the sub-pixel 32 also extends to the adjacent sub-pixel 32.

The second portion of the active layer 62 has a starting end portion diagonally to the upper right of the lower left corner of the sub-pixel 32, extends along the lower half of the left side of the sub-pixel 32, and passes through the central portion of the sub-pixel 32. It passes through the L-shaped region, extends beyond the upper side of the sub-pixel 32, and extends further upward.

That is, the active layer 62 is continuous in the two sub-pixels 32 adjacent in the vertical direction. Further, the active layer 62 is continuous even in the two sub-pixels 32 adjacent to each other in the left-right direction.

The gate 64 includes a first wiring 41, a second wiring 42, a third wiring 43, an L-shaped region, and a rectangular region.

The first wiring 41, the second wiring 42, and the third wiring 43 have a strip shape extending in the left-right direction. The first wiring 41, the second wiring 42, and the third wiring 43 extend beyond the right and left boundaries of the sub-pixel 32 to the adjacent sub-pixel 32. The first wiring 41 and the third wiring 43 are linear. The second wiring 42 is a shallow U-shape bent toward the lower side of the sub-pixel 32 near the boundary between the left and right sub-pixels 32.

The arrangement of the transistors in the sub-pixel 32 will be described using the sub-pixel 32 on the left side of FIG. 34. The portion of the active layer 62 that overlaps with the first wiring 41 forms a channel region of the first transistor 51. The active layer 62 overlaps with the third wiring 43 at two points. The active layer 62 on the left side of the active layer 62 forms a channel region of the second transistor 52. The active layer 62 on the right side forms the channel region of the fourth transistor 54.

The active layer 62 overlaps with the second wiring 42 at two points. The active layer 62 on the left side of the active layer 62 forms a channel region of the third transistor 53. The active layer 62 on the right side forms the channel region of the fifth transistor 55. The U-shaped portion of the active layer 62 forms a channel region of the drive transistor 56.

The shapes of the active layer 62, the gate 64, and the drain 66 of the left and right sub-pixels 32 are line-symmetrical with the long side of the sub-pixel 32 as the axis of symmetry. Therefore, the sub-pixel 32 on the left side shares the high power supply line 451 with the sub-pixel 32 on the right side. Similarly, the sub-pixel 32 on the left side shares the reference power line 454 with the sub-pixel 32 on the left side. Further, the sub-pixel 32 on the right side shares the reference power supply line 454 with the sub-pixel 32 on the right side.

The configuration of the sub-pixel 32 will be described with a focus on the high power supply line 451. The shapes of the active layer 62, the gate 64, and the drain 66 of the left and right sub-pixels 32 are line-symmetrical with the high power supply line 451 as the axis of symmetry. The configuration of the sub-pixel 32 will be described with a focus on the reference power supply line 454. The shapes of the active layer 62, the gate 64, and the drain 66 of the left and right sub-pixels 32 are line-symmetrical with the reference power supply line 454 as the axis of symmetry.

The high power line 451 is thicker than the reference power line 454 and the data line 455.

The fourth transistor 54 of the sub-pixel 32 on the right side and the fourth transistor 54 of the sub-pixel 32 on the left side are connected to the high power supply line 451 via the first conductive portion 71 located on the boundary line of the sub-pixel 32. doing.

As described with reference to FIG. 2, one pixel 31 includes three sub-pixels 32. The two pixels 31 adjacent to each other in the first direction include six sub-pixels 32. The two adjacent pixels 31 are the same as the state in which the two sub-pixels 32 shown in FIG. 34 are arranged in three sets in the first direction.

As described above, the display device 10 has a plurality of pixels 31. The plurality of pixels 31 are arranged in a matrix of M (M is an integer of 2 or more) rows and N (N is an integer of 2 or more) columns. The first direction is the row direction. The pixel circuits 33 of the two pixels 31 adjacent to each other in the row direction are arranged line-symmetrically with respect to the high power supply line 451. Each of the fourth transistors 54 included in the two pixels 31 adjacent in the row direction are commonly connected to the reference high power supply line 451.

According to the present embodiment, since the adjacent sub-pixels 32 share the high power supply line 451, the number of high power supply lines 451 included in the display device 10 is halved. Therefore, the sub-pixel 32 can be miniaturized. Therefore, it is possible to provide a high-definition display device 10.

According to the present embodiment, since the adjacent sub-pixels 32 share the reference power supply line 454, the number of the reference power supply lines 454 provided in the display device 10 is halved. Therefore, the sub-pixel 32 can be miniaturized. Therefore, it is possible to provide a high-definition display device 10.

According to the present embodiment, since the high power supply line 451 is thicker than the reference power supply line 454 and the data line 455, the high power supply voltage VDD can be stably applied to the pixel circuit 33 and the organic light emitting element 34.

The sub-pixel 32 may share only one of the high power supply line 451 and the reference power supply line 454 with the adjacent sub-pixel 32. The shapes of the active layer 62, the gate 64, and the drain 66 of the adjacent sub-pixels 32 may be shapes other than line symmetry.

[Embodiment 3]
The present embodiment relates to a display device 10 that does not share the reset power supply line 453 and the reference power supply line 454.

FIG. 35 is a schematic plan view of the sub-pixel 32 of the third embodiment. FIG. 36 is a schematic cross-sectional view of the sub-pixel 32 of the third embodiment. FIG. 35 is an enlarged view of one sub-pixel 32 and its periphery as seen from the front side of the illustrated device 10. The display device 10 of the present embodiment will be described with reference to FIGS. 35 and 36. The description of the parts common to the second embodiment will be omitted.

The two sub-pixels 32 adjacent to the first direction of the present embodiment are line-symmetrical like the two sub-pixels 32 adjacent to the first direction of the second embodiment. The sub-pixel 32 shown in FIG. 35 corresponds to the sub-pixel 32 shown on the left side of FIG. 34.

First, the main differences from the second embodiment will be described. As shown in FIG. 35, the common electrode portion 74 is located on the right side of the sub-pixel 32 and extends to the sub-pixel 32 adjacent to the top and bottom. The common electrode portion 74 is branched into two in the vicinity of the first conductive portion 71 located on the right side of the sub-pixel 32. The common electrode portion 74 has a branch connected to the third conductive portion 73.

As shown in FIG. 35, the interlayer insulating layer 65 includes a first interlayer insulating layer 651 and a second interlayer insulating layer 652. The common electrode portion 74 is located between the first interlayer insulating layer 651 and the second interlayer insulating layer 652.

The material of the common electrode portion 74 is a conductor. The common electrode portion 74 is connected to the drain 66 via the third conductive portion 73. The common electrode portion 74 supplies the reset voltage Vrst to the pixel circuit 33. Therefore, an arbitrary reset voltage Vrst can be set without increasing the area of the sub-pixel 32.

According to this embodiment, it is possible to provide a display device 10 in which the reset voltage Vrst is different from the reference voltage Vref.

The differences from the second embodiment other than the provision of the common insulating portion 74 will be briefly described.

The first portion of the active layer 62 has a starting end at the lower left of the sub-pixel 32, bends to the right at a position extending along the lower half of the left side of the sub-pixel 32, and passes through the central portion of the sub-pixel 32. , It extends to the left through the L-shaped region, and branches into two at a position intersecting the left side of the sub-pixel 32. One of the branches extends upward along the left side of the sub-pixel 32 and has an end on the upper boundary with the adjacent sub-pixel 32. The other end of the branch extends into the sub-pixel 32 adjacent to the left side.

The second portion of the active layer 62 extends upward from the starting end located near the central portion of the lower side of the sub-pixel 32, extends upward through a sideways Z-shaped portion, and faces right, upward, and right. It bends to the right at the bent position and extends beyond the right edge of the area of the sub-pixel 32 to the adjacent sub-pixel 32. The second part is not continuous with the first part.

The gate 64 includes a first wiring 41, a second wiring 42, a third wiring 43, an L-shaped region, and a rectangular region.

The first wiring 41, the second wiring 42, and the third wiring 43 have a strip shape extending in the left-right direction. The first wiring 41, the second wiring 42, and the third wiring 43 extend beyond the right and left boundaries of the sub-pixel 32 to the adjacent sub-pixel 32. The second wiring 42 and the third wiring 43 are linear. The first wiring 41 is a U-shape bent downward near the boundary with the sub-pixel 32 on the left side.

The type of signal is not limited to the Em signal and the Scan signal. In other words, it includes all signals with different signal waveforms. Further, the number of signal lines crossing the arrangement area of the sub-pixels is not limited to three.

The verification result of the effect of preventing display (luminance) unevenness due to the feedthrough phenomenon will be described using the organic light emitting type display device described in the first embodiment. FIG. 37 shows an equivalent circuit diagram of a 6T1C source follower type (6T1C_S) pixel circuit for verification. The description of the parts common to the pixel circuit 933 of the comparative example of the first embodiment described with reference to FIG. 8 will be omitted.

[Explanation of verification circuit]
Instead of the organic light emitting element, a load Z35 having a sheet resistance of about 1 kΩ / □ is used. The load Z35 is a polysilicon film (active layer) having a low resistance by injecting P-type impurities at a high concentration. A DC ammeter 36 is inserted between the load Z35 and the negative power supply Vss, and the current flowing through the load Z35 is measured. Each fixed voltage is high power supply Vdd = + 4.6V, Vss = -4.9V, reset power supply Vrst = -4.9V, reference power supply Vref = -3V.

The capacity Cst of the holding capacity 47 is 124 fF. A parasitic capacitance Cp is formed between the third wiring 943 and the node C which is the first terminal of the holding capacitance 47. Here, five types of 6T1C_S pixel circuits in which Cp / (Cp + Cst) are different from 0% to 2% in 0.5% steps are manufactured.

The Scan line 40 is connected to the gate of the first transistor 51, the gate of the third transistor 53, and the gate of the fifth transistor 55. The third wiring 943 is connected to the gate of the second transistor 52 and the gate of the fourth transistor 54.

FIG. 38 is a time chart showing a control signal of the pixel circuit 33. The outline of the time chart will be described with reference to FIG. 38. The horizontal axis of FIG. 38 is time. Scan represents a first signal to be input to the Scan line 40. Em indicates a signal to be input to the third wiring 943. Vdata indicates a signal to be input to the data line 9455. Vref means a state in which the same reference voltage Vref as the reference power supply line 9454 is input to the data line 9455. Data means a voltage indicating the brightness that causes the organic light emitting element 34 to emit light.

As shown in FIG. 38, in this embodiment, the detection period (also referred to as data storage period or threshold detection period) is 16 μs, and the delay time is 1 μs. The Low potential Vgl of the Scan signal and the Em signal is −9 V, and the High potential Vgh is + 6 V. The voltage of the signal Vdata input to the data line 9455 changes from Vref to data during the data storage period.

FIG. 39 is an explanatory diagram illustrating a state of a 6T1C_S pixel circuit for verification after inputting the signal pattern shown in FIG. 38. The first transistor 51, the third transistor 53, and the fifth transistor 55 are in a cutoff state. The fourth transistor 54 and the second transistor 52 are in a conductive state. The data voltage Vdata varies from −5V to + 2V. The DC ammeter 36 measures the value of the current flowing from Vdd to Vss.

[Experimental result]
FIG. 40 is a graph showing the data voltage dependence of the drain current Ids of the drive transistor 56. The horizontal axis of FIG. 40 indicates the data voltage Vdata input from the data line 9455, and the unit is volt. The vertical axis of FIG. 40 shows the value of the current flowing from Vdd to Vss, that is, the drain current Ids of the drive transistor 56. The unit of the vertical axis in FIG. 40 is ampere. The vertical axis of FIG. 40 is the current value measured by the DC ammeter 36.

The diamond-shaped plot shows the relationship between the data voltage Vdata and the drain current Ids when Cp / (Cp + Cst) = 0%. The rectangular plot shows the relationship between the data voltage Vdata and the drain current Ids when Cp / (Cp + Cst) = 0.5%. The triangular plot shows the relationship between the data voltage Vdata and the drain current Ids when Cp / (Cp + Cst) = 1%. The plots marked with a cross show the relationship between the data voltage Vdata and the drain current Ids when Cp / (Cp + Cst) = 1.5%. The plot marked with * shows the relationship between the data voltage Vdata and the drain current Ids when Cp / (Cp + Cst) = 2%.

When Cp / (Cp + Cst) = 0%, the drain current Ids of the drive transistor 56 ^{changes from 3 × 10 -10} A to 2 × 10 ^-5 A in the range of the data voltage Vdata from -5V to + 1V. This is a current capable of changing the organic light emitting element from a dark state to a bright state. Further, as Cp / (Cp + Cst) increases, the drain current Ids of the drive transistor 56 tends to increase.

FIG. 41 is a graph showing the Cp / (Cp + Cst) dependence of the drain current Ids of the drive transistor 56. The vertical axis of FIG. 41 indicates Cp / (Cp + Cst), and the unit is a percentage. The vertical axis of FIG. 41 shows the value of the current flowing from Vdd to Vss, that is, the drain current Ids of the drive transistor 56. The unit of the vertical axis in FIG. 40 is ampere. The vertical axis of FIG. 40 is the current value measured by the DC ammeter 36.

The diamond-shaped plot shows the measured value of the relationship between Cp / (Cp + Cst) and the drain current Ids when the data voltage Vdata is −4.5 V. The solid line shows a graph of an approximate expression that approximates the measured value with a polynomial.

[Derivation of approximate expression]
The method of deriving the approximate expression will be described below. As described above, the drain current Ids of the drive transistor 56 is represented by the equation (5).

The gate voltage Vg of the drive transistor 56 is represented by the above equation (2). Here, it is assumed that the source voltage Vs = Vdd of the drive transistor 56 and the gate-source voltage Vgs = Vg−Vs of the drive transistor 56. By eliminating the gate voltage Vg from the equations (5) and (2), the equation (6) showing the relationship between the drain current Ids and k of the drive transistor 56 can be obtained. As described above, k = Cp / (Cp + Cst).

Since the Ids on the left side of the equation (6) are represented by a quadratic function of k, the approximate equation shown in the equation (7) can be obtained by calculating each coefficient of the quadratic polynomial using the least squares method. Obtainable.

[Relationship between Cp / (Cp + Cst) variation and display unevenness]
The relationship between the variation of Cp / (Cp + Cst) and the display unevenness will be described based on the approximate expression of the equation (7). When the size of the portion where the wiring of the parasitic capacitance Cp intersects is 4 μm × 2.5 μm and the capacitance per unit area is 0.075 (fF / μm ² ), Cp = 0.75 fF. When the capacity Cst = 124fF of the holding capacity 47, k = Cp / (Cp + Cst) is calculated to be 0.0060.

Due to manufacturing variations, the width of each wiring is expected to vary by a few percent within and between substrates. This variation is the cause of the variation in the parasitic capacitance at the intersection of the wirings.

According to the equation (7), when k varies by ± 5% around 0.0060, the variation of the drain current Ids is ± 3.3%. The brightness of the organic light emitting element also varies due to the variation in the drain current Ids. When the drain current varies by 2%, the variation in the brightness of the organic light emitting element becomes easily visible. Therefore, display unevenness occurs.

[Comparison with Embodiment 1]
In the first embodiment, instead of the Scan wire 40, a first wiring 41 and a second wiring 42 are intentionally arranged at the upper end and the lower end of the sub-pixel 32, for a total of two wires, and between them. The third wiring 43 is arranged. Since it is possible to avoid the intersection of the wirings, the parasitic capacitance Cp = 0 due to the intersection of the wirings. Therefore, even if each wiring fluctuates due to manufacturing variation, the parasitic capacitance Cp does not change from 0. That is, the drain current Ids of the drive transistor 56 does not change, and the problem of display unevenness caused by feedthrough due to the intersection of wiring can be solved.

The technical contents (constituent requirements) described in the respective embodiments and examples can be combined with each other, and by combining them, a new technical content can be formed.
The embodiments and examples disclosed this time should be considered as exemplary in all respects and not restrictive. The scope of the present invention is indicated by the scope of claims, not the above-mentioned meaning, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

10 Display device 11 1st board 12 2nd board 13 Driver IC
14 FPC
15 Display area 16 TFT substrate 18 Anopole electrode 19 Cathode electrode 20 Drive circuit 21 Scan drive circuit 211 Unit drive circuit 22 Data drive circuit 23 Em drive circuit 24 Power supply device 25 Encapsulant 26 Right side Scan drive circuit 27 Left side Scan drive circuit 31 pixels 32 Sub-pixel 33 Pixel circuit 34 Organic light emitting element 35 Load 36 DC current meter 40 Scan line 41 First wiring (first scanning signal line)
42 Second wiring (second scanning signal line)
43 Third wiring (light emission control line)
44 Branch source wiring 45 Power line 451 High power line (first power line)
452 Low power line (second power line)
453 Reset power line (third power line)
454 Reference power line (fourth power line)
455 data line (fifth power line)
47 Retention capacity 51 First transistor 52 Second transistor 53 Third transistor 54 Fourth transistor 55 Fifth transistor 56 Drive transistor 61 Underlayer insulation layer 62 Active layer 63 Gate insulation layer 64 Gate 65 Interlayer insulation layer 651 First 1 interlayer insulating layer 652 2nd interlayer insulating layer 66 drain 67 flattening layer 69 1st insulating part 691 opening 692 non-opening 71 1st conductive part 72 2nd conductive part 73 3rd conductive part 74 common electrode part 80 DC / DC converter 81 Adjustment unit 82 Brightness adjustment unit 83 Color adjustment unit 84 Gamma adjustment unit 85 High voltage logic unit 86 Receiver unit 88 Analog control unit 89 Analog output unit 910 Display device of comparative example 915 Display area of comparative example (display area)
921 Scan drive circuit of comparative example (Scan drive circuit)
932 Sub-pixel of comparative example (sub-pixel)
933 Pixel circuit of comparative example (pixel circuit)
934 Organic light emitting element of comparative example (organic light emitting element)
941 First wiring of the comparative example (first wiring)
942 Second wiring of the comparative example (second wiring)
943 Third wiring of the comparative example (third wiring)
9451 High power line of comparative example (high power line)
9452 Low power line of comparative example (low power line)
9453 Reset power line of comparative example (reset power line)
9454 Reference power line of comparative example (reference power line)
9455 Data line of comparative example (data line)
962 Active layer of Comparative Example (Active layer)
9621 1st part 9622 2nd part 9623 3rd part 964 Gate of Comparative Example
966 Drain of Comparative Example (Drain)
966a Connection drain layer 971 First conductive part (first conductive part) of Comparative Example

Claims (13)

A pixel having an organic light emitting element and a pixel circuit for controlling a current supplied to the organic light emitting element, and
The first wiring and the second wiring that supply the first signal for controlling the pixel circuit to the pixel circuit,
It has a third wiring that supplies a second signal for controlling the pixel circuit to the pixel circuit.
The first wiring to the third wiring are arranged in the region where the pixel circuit is arranged and along the first direction.
The third wiring is arranged between the first wiring and the second wiring .
The plurality of pixels are arranged in a matrix of M (M is an integer of 2 or more) rows and N (N is an integer of 2 or more) columns.
The first direction is the row direction.
The first wiring and the second wiring supply the first signal to each pixel circuit of a plurality of pixels arranged in one row in the M row.
The third wiring supplies the second signal to each pixel circuit of the plurality of pixels arranged in the one row.
Further, it has a drive circuit that is arranged outside the display area in which the plurality of pixels are arranged and drives each pixel circuit of the plurality of pixels based on the first signal and the second signal.
The drive circuit is a display device that supplies the same first signal to the first wiring and the second wiring, and supplies the second signal to the third wiring. In claim 1,
The pixel circuit is
A drive transistor that controls the current supplied to the organic light emitting element, and
It has first, second, and third transistors connected in series.
The first, second, and third transistors are connected in series in this order,
The connection point between the second transistor and the third transistor is connected to the gate of the drive transistor.
A display device in which the first, third, and second wirings are connected to the gates of the first to third transistors in this order, respectively. In claim 2 ,
A first connection wiring connecting the channel region of the first transistor and the channel region of the second transistor,
It has a second connection wiring that connects the channel region of the second transistor and the channel region of the third transistor.
A display device in which the first connection wiring and the second connection wiring are arranged in a second direction intersecting the first direction. In claim 3 ,
A display device in which the first direction and the second direction are orthogonal to each other. In claim 2 ,
The pixel circuit further has fourth and fifth transistors and a capacitance.
The fourth transistor is connected between the first power supply line and the drive transistor, and is connected to the drive transistor.
The organic light emitting element is connected between the drive transistor and a second power supply line having a potential lower than that of the first power supply line.
The fifth transistor is connected between the connection point between the drive transistor and the organic light emitting element and the third power supply line having a potential lower than that of the first power supply line.
The capacitance is connected between the connection point between the first transistor and the second transistor and the connection point between the fourth transistor and the drive transistor.
The first transistor is directly connected between the fourth power line and the second transistor.
The third transistor is connected between a fifth power line that supplies a voltage applied to the gate of the drive transistor and the second transistor.
The second wire is further connected to the gate of the fifth transistor.
The third wiring is a display device further connected to the gate of the fourth transistor. In claim 5 ,
The capacitance is located in the area between the first wire and the third wire.
A display device in which the first power supply line, the fourth power supply line, and the fifth power supply line are arranged in a second direction. In claim 6 ,
The plurality of pixels are arranged in a matrix of M (M is an integer of 2 or more) rows and N (N is an integer of 2 or more) columns.
The first direction is the row direction.
The pixel circuits of the two pixels adjacent to each other in the row direction are arranged line-symmetrically with respect to the first power supply line.
A display device in which each of the fourth transistors included in the two pixels is commonly connected to the first power line as a reference. In claim 1 ,
The drive circuit is connected to a branch source wiring that branches into the first wiring and the second wiring, and supplies the first signal to the branch source wiring.
A display device that branches from the branch source wiring into the first wiring and the second wiring in the region between the display region and the arrangement region of the drive circuit. In claim 8 .
It has M branch source wires and M third wires.
The first wiring and the second wiring of the branch source wiring of the i-th (i is an integer of 1 to M) are the first wirings in the pixel circuits of the plurality of pixels arranged in the i-th row. Supply the signal,
The third wiring of the third is a display device that supplies the second signal to the pixel circuits of the plurality of pixels arranged in the i-th row. In claim 3 ,
The first connection wiring and the second connection wiring are display devices composed of an active layer of a semiconductor. In claim 1 ,
The first wiring is arranged on the first side side of the pixel.
The second wiring is arranged on the second side of the pixel facing the one side.
The third wiring is a display device arranged near the center between the first wiring and the second wiring. In claim 1,
A display device in which the first wiring and the second wiring are insulated from each other in the pixel circuit. A pixel whose first wiring and second wiring for supplying a first signal and a third wiring for supplying a second signal to a substrate are controlled by the first signal and the second signal. Formed together with the pixel circuit so as to be arranged in the order of the first wiring, the third wiring, and the second wiring along the first direction in the region where the circuit is arranged.
An organic light emitting element controlled by a current supplied by the pixel circuit is arranged above the pixel circuit, the first wiring, the second wiring, and the third wiring .
The pixel circuit is
A drive transistor that controls the current supplied to the organic light emitting element, and
It has first, second, and third transistors connected in series.
The first, second, and third transistors are connected in series in this order.
The connection point between the second transistor and the third transistor is connected to the gate of the drive transistor.
A method for manufacturing a display device in which the first, third, and second wirings are connected to the gates of the first to third transistors in this order, respectively.

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