JP6851140B2 - Manufacturing method of photoelectric conversion device, photoelectric conversion module and photoelectric conversion device - Google Patents

Description

The present invention relates to a photoelectric conversion device, a photoelectric conversion module, and a method for manufacturing the photoelectric conversion device.

Conventionally, intrinsic (i-type) amorphous silicon is interposed between an n-type crystalline silicon substrate and a p-type amorphous silicon layer to reduce defects at the interface and to reduce defects at the interface and to have characteristics at the heterojunction interface. There is known a photoelectric conversion device that has improved the above. This photoelectric conversion device is called a heterojunction solar cell.

The heterojunction solar cell described in Patent Document 1 includes a silicon substrate, a true amorphous semiconductor layer, an n-type amorphous semiconductor layer, a p-type amorphous semiconductor layer, an n electrode, and p. It is equipped with an electrode.

The intrinsic amorphous semiconductor layer, the n-type amorphous semiconductor layer, and the n-electrode are sequentially laminated on a part of the silicon substrate. Further, the intrinsic amorphous semiconductor layer, the p-type amorphous semiconductor layer, and the p electrode are sequentially laminated on a region different from a part of the silicon substrate.

In a heterojunction solar cell, electrons, which are a large number of carriers generated in a silicon substrate, diffuse into an n-type amorphous semiconductor layer and are collected by an n electrode. In addition, holes, which are minority carriers, diffuse into the p-type amorphous semiconductor layer and are collected by the p electrode.

International Publication No. 2013/133005 Pamphlet

In the heterojunction solar cell described in Patent Document 1, since the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer have a constant film thickness in the length direction, stress is applied to the semiconductor substrate. However, there is a problem that warpage or bending occurs in the semiconductor substrate.

Therefore, according to the embodiment of the present invention, there is provided a photoelectric conversion device capable of suppressing warpage and bending of a semiconductor substrate and having good characteristics.

Further, according to the embodiment of the present invention, there is provided a photoelectric conversion module including a photoelectric conversion device having good characteristics.

Further, according to the embodiment of the present invention, there is provided a method for manufacturing a photoelectric conversion device which can suppress warpage and bending of a semiconductor substrate and has good characteristics.

In the method for manufacturing a photoelectric conversion device according to an embodiment of the present invention, a plurality of first openings arranged in a row at predetermined intervals and two adjacent first openings are arranged and the first. A first amorphous having a first conductive mold on one surface of a semiconductor substrate using a first mask comprising at least one first convex portion having a thickness smaller than the depth of one opening. A first step of forming a quality semiconductor layer by a vapor phase growth method, a plurality of second openings arranged in a row at predetermined intervals, and two adjacent second openings are arranged. A first in-plane direction of the semiconductor substrate is applied to one surface of the semiconductor substrate using a second mask including at least one second convex portion having a thickness smaller than the depth of the second opening. A second step of forming a second amorphous semiconductor layer alternately arranged with the amorphous semiconductor layer of the above and having a second conductive type different from the first conductive type by a vapor phase growth method is provided. ..

In the method for manufacturing a photoelectric conversion device according to the embodiment of the present invention, the first amorphous semiconductor layer formed by using the first mask is an amorphous semiconductor at a position corresponding to the first convex portion. It has a film thickness reduction region so as to traverse the layer in the width direction. Further, the second amorphous semiconductor layer formed by using the second mask has a film thickness reduction region so as to cross the amorphous semiconductor layer in the width direction at a position corresponding to the second convex portion. Have.

As a result, the stress applied to the semiconductor substrate is less than the stress applied to the semiconductor substrate as compared with the case where the amorphous semiconductor layer having a constant film thickness is formed, and the warpage and bending of the semiconductor substrate can be suppressed. .. Further, even in the film thickness reduction region, since it is covered with the first amorphous semiconductor layer and the second amorphous semiconductor layer, carrier collection and electric field passivation effect can be obtained, and good characteristics can be obtained. Obtainable. Further, since the mask portion has a convex portion, the strength of the mask can be maintained, so that the first amorphous semiconductor layer and the second amorphous semiconductor layer can be satisfactorily formed.

Preferably, the method of manufacturing the photoelectric conversion device further includes a third step of forming a passivation film between the semiconductor substrate and the first and second amorphous semiconductor layers.

As a result, carrier recombination at the interface between the passivation film and the semiconductor substrate is suppressed.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

Preferably, in the third step, the intrinsic hydrogenated amorphous silicon is formed as a passivation film.

As a result, the hydrogen in the passivation film can compensate for the defects existing on the surface of the semiconductor substrate, and the life of the carrier is extended.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

Preferably, the method for manufacturing the photoelectric conversion device has a length corresponding to the length of the first and second amorphous semiconductor layers, and the first and second non-first and second non-semiconductors are formed in the in-plane direction of the semiconductor substrate. A plurality of third openings arranged in the arrangement direction of the crystalline semiconductor layer, and at least one provided in the plurality of third openings and having a thickness smaller than the depth of the third opening. A predetermined distance in the length direction of the first and second amorphous semiconductor layers between the two convex portions and the two third openings adjacent to each other in the arrangement direction of the first and second amorphous semiconductor layers. A region between adjacent first and second amorphous semiconductor layers using a third mask that is arranged in and has at least one recess having a thickness less than the depth of the third opening. And the protective film in the film thickness reduction region of the first amorphous semiconductor layer formed in the first step and the film thickness reduction region of the second amorphous semiconductor layer formed in the second step. Is further provided with a fourth step of forming the above by the vapor phase growth method.

By the fourth step, a protective film is formed between the first and second amorphous semiconductor layers and the film thickness reduction region.

As a result, the passivation film or the semiconductor substrate existing under the protective film can be protected, and the life of the carrier is extended.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

Preferably, in the method for manufacturing a photoelectric conversion device, the first amorphous semiconductor layer is formed on one surface of the semiconductor substrate, and the second amorphous semiconductor layer is the first non-in-plane direction of the semiconductor substrate. It is arranged alternately with the crystalline semiconductor layer and formed on one surface of the semiconductor substrate, has a length corresponding to the length of the first and second amorphous semiconductor layers, and is in-plane of the semiconductor substrate. A plurality of third openings arranged in the arrangement direction of the first and second amorphous semiconductor layers in the direction, and the depths of the third openings provided in the plurality of third openings. A fourth mask in which a protective film is formed by a vapor phase growth method in a region between adjacent first and second amorphous semiconductor layers using a third mask having at least one convex portion having a thickness smaller than that of the semiconductor. Further prepare for the process of.

A protective film is formed between the adjacent first and second amorphous semiconductor layers. The formed protective film has at least one film thickness reduction region in which the film thickness is reduced.

Therefore, the mechanical strength of the third mask for disregarding the protective film is increased, and the protective film can be accurately formed in the region between the adjacent first and second amorphous semiconductor layers.

Preferably, in the fourth step, the silicon nitride film is formed as a protective film.

The vapor deposition method can be used to form a protective film in a single process. In addition, the electric field passivation effect can be obtained by the positive fixed charge of the silicon nitride film. Since the protective film can be formed in one process, the thermal history can be reduced, and the deterioration of the characteristics due to the thermal deterioration of the passivation effect can be reduced.

Further, according to the embodiment of the present invention, the photoelectric conversion device includes a semiconductor substrate, a first amorphous semiconductor layer, and a second amorphous semiconductor layer. The semiconductor substrate has a first conductive type. The first amorphous semiconductor layer is formed on one surface of a semiconductor substrate and has a first conductive type. The second amorphous semiconductor layer is formed on one surface of the semiconductor substrate alternately arranged with the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate, and is different from the first conductive type. Has a conductive type. Then, at least one of the first and second amorphous semiconductor layers has at least one film thickness reduction region in which the film thickness decreases so as to cross the amorphous semiconductor layer in the width direction.

In the photoelectric conversion device according to the embodiment of the present invention, at least one of the first and second amorphous semiconductor layers has a film thickness reducing region so as to cross the amorphous semiconductor layer in the width direction. Therefore, the stress applied to the semiconductor substrate is reduced as compared with the case where the amorphous semiconductor layer having a constant film thickness is formed.

Therefore, warpage and bending of the semiconductor substrate can be suppressed. Further, even in the film thickness reduction region, since it is covered with at least one of the first amorphous semiconductor layer and the second amorphous semiconductor layer, carrier collection and electric field passivation effect can be obtained. Good characteristics can be obtained.

Preferably, the photoelectric conversion device further includes a passivation film disposed between the semiconductor substrate and the first and second amorphous semiconductor layers.

As a result, carrier recombination at the interface between the passivation film and the semiconductor substrate is suppressed.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

Preferably, the passivation membrane comprises intrinsically hydrogenated amorphous silicone.

As a result, the hydrogen in the passivation film can compensate for the defects existing on the surface of the semiconductor substrate, and the life of the carrier is extended.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

Preferably, the photoelectric conversion device further includes a protective film formed on the film thickness reduction region in the first and second amorphous semiconductor layers.

Since the protective film is formed between the first and second amorphous semiconductor layers and the film thickness reduction region, the passivation film or the semiconductor substrate existing under the protective film can be protected, and the life of the carrier is extended.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

The photoelectric conversion device according to the embodiment of the present invention includes a semiconductor substrate, a first amorphous semiconductor layer, a second amorphous semiconductor layer, and a protective film. The semiconductor substrate has a first conductive type. The first amorphous semiconductor layer is formed on one surface of a semiconductor substrate and has a first conductive type. The second amorphous semiconductor layer is formed on one surface of the semiconductor substrate by being alternately arranged with the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate, and is different from the first conductive type. Has a conductive type. The protective film is formed on one surface of the semiconductor substrate in the region between the adjacent first and second amorphous semiconductor layers. Then, the protective film has at least one film thickness reduction region that crosses the protective film in the width direction and reduces the film thickness.

A protective film is arranged between the adjacent first and second amorphous semiconductor layers, and the protective film is connected in the length direction of the first and second amorphous semiconductor layers.

Therefore, it is possible to suppress the invasion of moisture such as moisture from the region not covered by the first and second amorphous semiconductor layers.

Preferably, the protective film comprises at least a silicon nitride film.

The electric field passivation effect can be obtained by the positive fixed charge of the silicon nitride film.

Further, according to an embodiment of the present invention, the photoelectric conversion module includes a conductive portion and a plurality of photoelectric conversion devices. The conductive part is from the wiring sheet or wire grid. The plurality of photoelectric conversion devices are arranged on the conductive portion. Each of the plurality of photoelectric conversion devices comprises the photoelectric conversion device according to any one of configurations 6 to 10.

Since the above-mentioned photoelectric conversion device can improve the conversion efficiency, the photoelectric conversion module provided with the photoelectric conversion device can also improve the conversion efficiency.

Warpage and bending of the semiconductor substrate can be suppressed, and the conversion efficiency of the photoelectric conversion device can be improved.

It is a top view which shows the structure of the photoelectric conversion apparatus by Embodiment 1 of this invention. It is sectional drawing of the photoelectric conversion apparatus in line II-II shown in FIG. It is a top view of the metal mask for forming a p-type amorphous semiconductor layer. It is a top view of the metal mask for forming an n-type amorphous semiconductor layer. It is a top view of the metal mask for forming an electrode. It is a 1st process drawing which shows the manufacturing method of the photoelectric conversion apparatus shown in FIG. It is a 2nd process diagram which shows the manufacturing method of the photoelectric conversion apparatus shown in FIG. It is a 3rd process drawing which shows the manufacturing method of the photoelectric conversion apparatus shown in FIG. It is a 4th process diagram which shows the manufacturing method of the photoelectric conversion apparatus shown in FIG. It is a schematic diagram which shows the film thickness distribution of the film thickness decrease region. It is a top view which shows the example of the arrangement pattern of the n-type amorphous semiconductor layer and p-type amorphous semiconductor layer. It is a top view which shows the example of the arrangement pattern of an n-type amorphous semiconductor layer, a p-type amorphous semiconductor layer and an electrode. It is a top view which shows the example of another arrangement pattern of the n-type amorphous semiconductor layer and p-type amorphous semiconductor layer. It is a top view which shows the example of another arrangement pattern of an n-type amorphous semiconductor layer, a p-type amorphous semiconductor layer, and an electrode. It is a top view which shows the example of still another arrangement pattern of the n-type amorphous semiconductor layer and p-type amorphous semiconductor layer. It is a top view which shows the example of still another arrangement pattern of an n-type amorphous semiconductor layer, a p-type amorphous semiconductor layer, and an electrode. It is a top view which shows the example of still another arrangement pattern of the n-type amorphous semiconductor layer and p-type amorphous semiconductor layer. It is a top view which shows the example of still another arrangement pattern of an n-type amorphous semiconductor layer, a p-type amorphous semiconductor layer, and an electrode. It is a top view which shows the example of still another arrangement pattern of the n-type amorphous semiconductor layer and p-type amorphous semiconductor layer. It is a top view which shows the example of still another arrangement pattern of an n-type amorphous semiconductor layer, a p-type amorphous semiconductor layer, and an electrode. It is a top view which shows the example of still another arrangement pattern of the n-type amorphous semiconductor layer and p-type amorphous semiconductor layer. It is a top view which shows the example of still another arrangement pattern of an n-type amorphous semiconductor layer, a p-type amorphous semiconductor layer, and an electrode. It is a schematic diagram which enlarged a part of the wiring sheet in embodiment of this invention. It is a schematic diagram which shows the cross section of the photoelectric conversion device (including a conductive part). It is a schematic diagram which shows the cross section in the other direction of a photoelectric conversion device (including a conductive part). It is a schematic diagram which shows the cross section of the photoelectric conversion device (including a conductive part) using a wire grid. It is a top view which shows the structure of the photoelectric conversion apparatus by Embodiment 2. FIG. It is sectional drawing of the photoelectric conversion apparatus in line XXVIII-XXVIII shown in FIG. 27. It is sectional drawing of the photoelectric conversion apparatus in line XXIX-XXIX shown in FIG. 27. It is sectional drawing of the photoelectric conversion apparatus in line XXX-XXX shown in FIG. 27. It is a top view of the metal mask for forming a protective film. It is a top view of another metal mask for forming a protective film. It is the schematic which shows the structure of the photoelectric conversion module which comprises the photoelectric conversion apparatus by this embodiment.

Embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts in the drawings are designated by the same reference numerals, and the description thereof will not be repeated.

In this specification, the amorphous semiconductor layer may include a microcrystalline phase. The microcrystalline phase includes crystals having an average particle size of 1 to 50 nm. Further, in this specification, in order to make the explanation easy to understand, in the drawings referred to below, the configuration is shown in a simplified or schematic manner, or some constituent members are omitted. The dimensional ratio between the constituent members shown in each figure does not necessarily indicate the actual dimensional ratio.

[Embodiment 1]
FIG. 1 is a plan view showing a configuration of a photoelectric conversion device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the photoelectric conversion device in line II-II shown in FIG.

With reference to FIGS. 1 and 2, the photoelectric conversion device 10 according to the first embodiment of the present invention includes a semiconductor substrate 1, an antireflection film 2, a passivation film 3, an n-type amorphous semiconductor layer 4, and the like. A p-type amorphous semiconductor layer 5 and electrodes 6 and 7 are provided.

The semiconductor substrate 1 is made of, for example, an n-type single crystal silicon substrate. The semiconductor substrate 1 has a thickness of, for example, 100 to 150 μm. The semiconductor substrate 1 has a texture structure formed on one surface thereof. The surface on which the texture structure is formed is called the "light receiving surface".

The antireflection film 2 is arranged in contact with one surface (light receiving surface) of the semiconductor substrate 1.

The passivation film 3 is arranged in contact with the front surface (back surface) of the semiconductor substrate 1 opposite to the light receiving surface.

The n-type amorphous semiconductor layer 4 is arranged in contact with the passivation film 3.

The p-type amorphous semiconductor layer 5 is arranged alternately with the n-type amorphous semiconductor layer 4 in the in-plane direction (Y-axis direction) of the semiconductor substrate 1. More specifically, the p-type amorphous semiconductor layer 5 is arranged at a desired distance from the n-type amorphous semiconductor layer 4 in the in-plane direction (Y-axis direction) of the semiconductor substrate 1.

The n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are alternately arranged in the in-plane direction (Y-axis direction) of the semiconductor substrate 1.

The n-type amorphous semiconductor layer 4 has film thickness reduction regions 41 at desired intervals in the longitudinal direction (X-axis direction) of the n-type amorphous semiconductor layer 4. The film thickness reduction region 41 is a region of the n-type amorphous semiconductor layer 4 having a thinner film thickness than the portion other than the film thickness reduction region 41. Then, the film thickness reduction region 41 crosses the n-type amorphous semiconductor layer 4 in the width direction (Y-axis direction) of the n-type amorphous semiconductor layer 4. The n-type amorphous semiconductor layer 4 may include at least one film thickness reduction region 41.

The p-type amorphous semiconductor layer 5 has film thickness reduction regions 51 at desired intervals in the longitudinal direction (X-axis direction) of the p-type amorphous semiconductor layer 5 (see FIG. 2). The film thickness reduction region 51 is a region of the p-type amorphous semiconductor layer 5 whose film thickness is thinner than the portion other than the film thickness reduction region 51. Then, the film thickness reduction region 51 crosses the p-type amorphous semiconductor layer 5 in the width direction (Y-axis direction) of the p-type amorphous semiconductor layer 5. The p-type amorphous semiconductor layer 5 may include at least one film thickness reduction region 51.

The electrode 6 is arranged on the n-type amorphous semiconductor layer 4 in contact with the n-type amorphous semiconductor layer 4.

The electrode 7 is arranged on the p-type amorphous semiconductor layer 5 in contact with the p-type amorphous semiconductor layer 5.

It is preferable that the electrode 6 is arranged so as not to protrude from the n-type amorphous semiconductor layer 4, and the electrode 7 is arranged so as not to protrude from the p-type amorphous semiconductor layer 5.

When the electrode 6 (or the electrode 7) is formed in the gap region between the adjacent n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, the electrode 6 (or the electrode 7) is formed in these regions via the passivation film 3. This is because the leakage current of the pn junction increases.

Therefore, the adjacent electrodes 6 and 7 are arranged so as to be separated by a distance L in the Y-axis direction. The distance L is, for example, 100 to 300 μm.

The film thickness T1 of the film thickness reduction regions 41 and 51 is a film thickness in the range of 10% to 80% of the film thickness T2 of the region where the film thickness reduction regions 41 and 51 are not formed.

As described above, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have film thickness reduction regions 41 and 51 at desired intervals in the longitudinal direction (X-axis direction), respectively, but the film thickness is reduced. The regions 41 and 51 have a film thickness T1 of 10 to 80% with respect to the film thickness T2 in the regions other than the film thickness reduction regions 41 and 51. As a result, the stress applied to the semiconductor substrate is reduced as compared with the case where the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer having a constant film thickness in the length direction are formed on the semiconductor substrate. , It is possible to suppress the occurrence of warpage and bending of the semiconductor substrate.

Further, since the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are connected in the longitudinal direction (X-axis direction), the n-type amorphous semiconductor layer 4 and the p-type non-amorphous semiconductor layer 4 are connected. A passivation effect can be obtained as compared with the case where the crystalline semiconductor layer 5 is not connected in the longitudinal direction.

Further, the film thickness reduction regions 41 and 51 include a dopant showing a p-type or an n-type. For example, according to the analysis result by SIMS (Secondary Ion Mass Spectroscopy), the film thickness reduction regions 41 and 51 contain a dopant (boron or phosphorus) of ^{1 × 10 20} cm ^{-3 or more.}

The film thickness reduction regions 41 and 51 are preferably good conductive layers containing a dopant. This is because if the film thickness reduction regions 41 and 51 are good conductive layers, the carrier life is not shortened due to the electric field passivation effect of the conductive semiconductor layer, and the carriers can be effectively collected on the electrodes.

The dopant may be detected by a method other than SIMS such as EDX (Energy Dispersive X-ray Analysis).

Below the film thickness reduction regions 41 and 51, in addition to the chemical passivation effect of the passivation film 3, the electric field passivation effect of the conductive semiconductor layers of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 causes. , Carriers are effectively collected on the electrodes without reducing their lifespan.

Therefore, the curve factor is improved and good characteristics are obtained as compared with the case where the n-type amorphous semiconductor layer and the p-type amorphous semiconductor layer are separated from each other without providing the film thickness reduction regions 41 and 51. can get.

The film thickness reduction regions 41 and 51 preferably have a film thickness of 1 nm or more so that a good electric field passivation effect can be obtained. Since the film thickness reduction regions 41 and 51 are thinner than the portions other than the film thickness reduction regions 41 and 51, they do not become thicker than the film thickness of the portions other than the film thickness reduction regions 41 and 51.

In the photoelectric conversion device 10, the position of the film thickness reduction region 41 in the X-axis direction is different from the position of the film thickness reduction region 51 in the X-axis direction. The length of the film thickness reduction regions 41 and 51 in the X-axis direction is, for example, 2 mm or less, which is shorter than the diffusion length (for example, about 2 mm) of carriers (electrons and holes) generated in the semiconductor substrate 1. .. Therefore, the recombination of carriers in the regions below the film thickness reduction regions 41 and 51 is suppressed, and the carrier collection efficiency can be improved.

Further, when the electrode is not arranged on the film thickness reduction region, the position of the film thickness reduction region 41 in the X-axis direction and the position of the film thickness reduction region 51 in the X-axis direction are different, so that the film thickness is reduced in the X-axis direction. The carrier collection efficiency can be improved as compared with the case where the position of the region 41 and the position of the film thickness reduction region 51 in the X-axis direction are the same.

When the position of the film thickness reduction region 41 in the X-axis direction and the position of the film thickness reduction region 51 in the X-axis direction are different, the holes photoexcited immediately below the film thickness reduction region 41 are adjacent p-type amorphous. It diffuses toward the semiconductor layer 5 and reaches directly under the p-type amorphous semiconductor layer 5 having no film thickness reduction region 51, and is collected by the electrode 7.

On the other hand, when the position of the film thickness reduction region 41 in the X-axis direction and the position of the film thickness reduction region 51 in the X-axis direction are the same, the holes photoexcited immediately below the film thickness reduction region 41 are adjacent p. When diffused toward the type amorphous semiconductor layer 5, the film thickness reduction region 51 exists there, so that it becomes difficult to collect the film on the electrode 7.

The same applies to the holes photoexcited immediately below the film thickness reduction region 51.

Therefore, if the position of the film thickness reduction region 41 in the X-axis direction and the position of the film thickness reduction region 51 in the X-axis direction are different, the carrier collection efficiency can be improved.

The antireflection film 2 is composed of, for example, a silicon oxide film and a silicon nitride film. Then, the silicon oxide film is arranged in contact with the semiconductor substrate 1, and the silicon nitride film is arranged in contact with the silicon oxide film. The silicon oxide film has a film thickness of, for example, 20 nm, and the silicon nitride film has a film thickness of, for example, 60 nm.

The passivation film 3 is made of, for example, any of amorphous silicon, an oxide of amorphous silicon, a nitride of amorphous silicon, an oxynitride of amorphous silicon, and polycrystalline silicon.

When the passivation film 3 is made of an oxide of amorphous silicon, the passivation film 3 may be made of a thermal oxide film of silicon, or is formed by a vapor deposition method such as a plasma CVD (Chemical Vapor Deposition) method. It may consist of an oxide of silicon.

The passivation film 3 has, for example, a film thickness of 1 to 20 nm, preferably a film thickness of 1 to 3 nm. When the passivation film 3 is made of a silicon insulating film, the passivation film 3 has a film thickness that allows carriers (electrons and holes) to tunnel. In the first embodiment, the passivation film 3 is made of i-type amorphous silicon.

The n-type amorphous semiconductor layer 4 is an amorphous semiconductor layer having an n-type conductive type and containing hydrogen. The n-type amorphous semiconductor layer 4 includes, for example, n-type amorphous silicon, n-type amorphous silicon germanium, n-type amorphous germanium, n-type amorphous silicon carbide, and n-type amorphous silicon nitride. , N-type amorphous silicon oxide, n-type amorphous silicon oxynitride, n-type amorphous silicon carbon oxide and the like.

The n-type amorphous semiconductor layer 4 contains phosphorus (P) as an n-type dopant, for example.

The film thickness of the n-type amorphous semiconductor layer 4 is, for example, 5 to 20 nm.

The p-type amorphous semiconductor layer 5 is an amorphous semiconductor layer having a p-type conductive type and containing hydrogen. The p-type amorphous semiconductor layer 5 includes, for example, p-type amorphous silicon, p-type amorphous silicon germanium, p-type amorphous germanium, p-type amorphous silicon carbide, and p-type amorphous silicon nitride. , P-type amorphous silicon oxide, p-type amorphous silicon oxynitride, p-type amorphous silicon carbon oxide, and the like.

The p-type amorphous semiconductor layer 5 contains boron (B) as a p-type dopant, for example.

The film thickness of the p-type amorphous semiconductor layer 5 is, for example, 5 to 20 nm.

The electrodes 6 and 7 are metals such as Ag (silver), Ni (nickel), Al (aluminum), Cu (copper), Sn (tin), Pt (platinum), Au (gold), Ti (titanium) and the like. , ITO and other oxide conductor films, alloys of these metals, or laminated films of these metals. The electrodes 6 and 7 are preferably made of a metal having high conductivity. The thickness of the electrodes 6 and 7 is, for example, about 50 nm to 1 μm.

FIG. 3 is a plan view of a metal mask for forming the p-type amorphous semiconductor layer 5.

FIG. 3B is a cross-sectional view of the metal mask at line IIIB-IIIB shown in FIG. 3A.

With reference to FIG. 3, the metal mask 200 has a plurality of opening regions 201 for forming the p-type amorphous semiconductor layer 5.

The plurality of opening regions 201 are arranged at regular intervals in the Y-axis direction (see (a) in FIG. 3). The distance GA between the opening regions 201 and the opening regions 201 adjacent to each other in the Y-axis direction is about 2 mm or less.

The opening region 201 has an opening 201A for forming the p-type amorphous semiconductor layer 5 other than the film thickness reduction region 51, and a convex portion 201B for forming the film thickness reduction region 51.

The convex portion 201B is half-etched so that the thickness (length in the Z-axis direction) is in the range of 10% to 70% of the length of the opening 201A in the Z-axis direction. The thickness (length in the Z-axis direction) of the convex portion 201B may be smaller than the length of the opening 201A in the Z-axis direction. Further, at least one convex portion 201B may be provided.

Therefore, the metal mask 200 is arranged between a plurality of openings 201A arranged in a row at predetermined intervals and two adjacent openings 201A, and has a thickness smaller than the depth of the openings 201A at least. Includes one convex portion 201B.

By providing the convex portion 201B in this way, the opening region 201 is divided, and the ratio (aspect ratio) of the lengths of the long side and the short side of the opening 201A can be reduced. The aspect ratio of the opening 201A is preferably 300 or less. As a result, the mechanical strength of the metal mask 200 is increased, and the deformation of the metal mask 200 can be suppressed even when the metal mask is washed or heated.

Further, by forming the p-type amorphous semiconductor layer 5 by using the plasma CVD method, the reaction gas wraps around under the half-etched convex portion 201B, and the p-type non-film is formed in the opening 201A. The p-type amorphous semiconductor layer 5 in the film thickness reduction region 51, which is thinner than the crystalline semiconductor layer 5, is formed on the lower side of the convex portion 201B. Although it depends on the size of the convex portion 201B, the film thickness of the p-type amorphous semiconductor layer 5 formed on the lower side of the convex portion 201B is the p-type amorphous formed on the opening 201A. It is about 10% to 80% of the semiconductor layer 5.

The metal mask 200 may be made of a metal such as stainless steel, an alloy containing copper, nickel and nickel (for example, SUS430, 42 alloy, or Invar material), molybdenum and the like. Instead of the metal mask 200, a mask made of glass, ceramic (alumina, zirconia, etc.), an organic film, or the like may be used. Further, a mask obtained by etching a semiconductor substrate may be used. The thickness of the metal mask 200 is preferably, for example, about 50 μm to 300 μm. In this case, the metal mask 200 is unlikely to bend or float due to the magnetic force.

Considering the coefficient of thermal expansion of the semiconductor substrate 1 and the raw material cost, the metal mask 200 is more preferably 42 alloys. Considering the manufacturing cost with respect to the thickness of the metal mask 200, it is a problem to dispose of the metal mask 200 at one time. Since the running cost of production can be suppressed by using the metal mask 200 many times, it is preferable to regenerate the metal mask 200 and use it many times. In this case, as one of the regeneration methods, the film film adhering to the metal mask 200 may be removed by using fluoroacid or NaOH.

FIG. 4 is a plan view of a metal mask for forming the n-type amorphous semiconductor layer 4. FIG. 4B is a cross-sectional view of the metal mask 300 in line IVB-IVB shown in FIG. 4A.

With reference to FIG. 4, the metal mask 300 has a plurality of opening regions 301 for forming the n-type amorphous semiconductor layer 4n.

The detailed description of the metal mask 300 is the same as the detailed description of the metal mask 200 shown in FIG. 3, and the opening region 201, the opening 201A, and the convex portion 201B are referred to as the opening region 301, the opening 301A, and the convex portion 301B, respectively. The p-type amorphous semiconductor layer 5 may be read as the n-type amorphous semiconductor layer 4, and the film thickness reduction region 51 may be read as the film thickness reduction region 41.

In the metal mask 300, the spacing GA of the openings 301A adjacent to each other in the Y-axis direction is about 500 to 1500 μm.

As a result, the metal mask 300 is arranged between the plurality of openings 301A arranged in a row at predetermined intervals and two adjacent openings 301A, and has a thickness smaller than the depth of the openings 301B. Includes at least one convex portion 301B.

FIG. 5 is a plan view of a metal mask for forming the electrodes 6 and 7. With reference to FIG. 5, the metal mask 400 has a plurality of openings 401n for forming the electrode 6 and a plurality of openings 401p for forming the electrode 7. The aspect ratio of the openings 401p and 401n is preferably 300 or less.

As the metal mask 400, materials such as metal, ceramics, glass, and organic substances are used as in the above-mentioned metal masks 200 and 300. Depending on the material and processing method used for the metal mask 400, the ends of the electrodes 6 and 7 formed by using the metal mask 400 may not easily form an angular shape like the openings 401p and 401n of the metal mask 400. is there.

6 to 9 are first to fourth process diagrams showing the manufacturing method of the photoelectric conversion device 10 shown in FIG. 1, respectively.

With reference to FIG. 6, when the production of the photoelectric conversion device 10 is started, a wafer having a thickness of 100 to 300 μm is cut out from bulk silicon by a wire saw. Then, etching for removing the damaged layer on the surface of the wafer and etching for adjusting the thickness are performed to prepare the semiconductor substrate 1'(see step (a) in FIG. 6).

Then, the protective film 20 is formed on one surface of the semiconductor substrate 1'(see step (b) in FIG. 6). The protective film 20 is made of, for example, a silicon oxide film and a silicon nitride film.

Then, the semiconductor substrate 1'with the protective film 20 formed is etched with an alkaline solution such as NaOH and KOH (for example, an aqueous solution of KOH: 1 to 5 wt% and isopropyl alcohol: 1 to 10 wt%). As a result, the surface of the semiconductor substrate 1'on which the protective film 20 is formed is anisotropically etched, and a pyramid-shaped texture structure is formed. Then, the semiconductor substrate 1 is obtained by removing the protective film 20 (see step (c) of FIG. 6).

After that, i-type amorphous silicon is deposited on the back surface of the semiconductor substrate 1 by the plasma CVD method to form the passivation film 3, and the silicon oxide film and silicon nitride are formed on the light receiving surface of the semiconductor substrate 1 by the sputtering method or the like. The films are sequentially laminated to form the antireflection film 2 (see step (d) of FIG. 6).

The i-type amorphous silicon is formed as follows. The temperature of the semiconductor substrate 1 is set to 130 to 180 ° C., hydrogen (H ₂ ) gas of 0 to 100 sccm and silane (SiH ₄ ) gas of 40 sccm are passed through the reaction chamber, and the pressure in the reaction chamber is set to 40 to 120 Pa. .. Then, high frequency power (13.56 MHz) having an RF power density of 5 to 15 mW / cm ^{2 is applied to the parallel plate electrodes.} As a result, i-type amorphous silicon is formed on the light receiving surface of the semiconductor substrate 1.

After the step (d) of FIG. 6, the semiconductor substrate 1 is placed in the reaction chamber of the plasma apparatus, and the metal mask 200 described above is placed on the passivation film 3 of the semiconductor substrate 1 (see step (e) of FIG. 7).

Then, the temperature of the semiconductor substrate 1 was set to 150 to 210 ° C., and 0 to 100 sccm of H ₂ gas, 40 sccm of SiH ₄ gas, and 40 sccm of diborane (B ₂ H ₆ ) gas were flowed into the reaction chamber, and the reaction chamber was charged. Set the pressure to 40-120 Pa. Then, high frequency power (13.56 MHz) having an RF power density of 5 to 15 mW / cm ^{2 is applied to the parallel plate electrodes.} The B ₂ H ₆ gas is diluted with hydrogen, and _{the concentration of the B 2} H ₆ gas is, for example, 2%.

As a result, p-type amorphous silicon is deposited in the region of the passivation film 3 not covered by the metal mask 200 and the region of the passivation film 3 facing the convex portion 201B of the metal mask 200, and the p-type amorphous semiconductor is deposited. The layer p is formed on the passivation film 3 (see step (f) in FIG. 7). In this case, the n-type amorphous silicon 31 is also deposited on the metal mask 200.

After the step (f) of FIG. 7, a metal mask 300 is placed on the passivation film 3 and the p-type amorphous semiconductor layer 5 instead of the metal mask 200 (see step (g) of FIG. 7).

In the step (g) of FIG. 13, the metal mask 300 is shown so as to be separated from the passivation film 3, but the thickness of the p-type amorphous semiconductor layer 5 is 5 as described above. Since it is very thin at ~ 20 nm, the metal mask 300 is actually arranged close to the passivation film 3.

Then, the temperature of the semiconductor substrate 1 is set to about 170 ° C., H ₂ gas of 0 to 100 sccm, SiH ₄ gas of 40 sccm, and phosphine (PH ₃ ) gas of 40 sccm are passed through the reaction chamber, and the pressure in the reaction chamber is set to 40. Set to ~ 200 Pa. Then, high frequency power (13.56 MHz) having an RF power density of about 8.33 mW / cm ^{2 is applied to the parallel plate electrodes.} The PH ₃ gas is diluted with hydrogen, and _{the concentration of the PH 3} gas is, for example, 1%.

As a result, n-type amorphous silicon is deposited in the region of the passivation film 3 not covered by the metal mask 300 and the region of the passivation film 3 facing the convex portion 301B of the metal mask 300, and the n-type amorphous semiconductor is deposited. The layer 4 is formed on the passivation film 3 (see step (h) of FIG. 8). In this case, the n-type amorphous silicon 32 is also deposited on the metal mask 300.

When the metal mask 300 is removed after the n-type amorphous semiconductor layer 4 is deposited, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 alternately arranged in the in-plane direction of the semiconductor substrate 1 are removed. Is formed on the passivation film 3 (see step (i) of FIG. 8).

After the step (i) of FIG. 8, the metal mask 400 is arranged so that the openings 401n and 401p are located on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively (FIG. 8). (See step (j)).

Then, electrodes 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 via the metal mask 400 by a vapor deposition method or the like (see step (k) of FIG. 9). .. The film thickness of the electrodes 6 and 7 is preferably 50 nm to 1 μm, more preferably 50 nm to 500 nm. This is because when the electrodes 6 and 7 become thicker, the stress applied to the semiconductor substrate 1 becomes stronger, which causes the semiconductor substrate 1 to warp.

By forming the electrodes 6 and 7, the photoelectric conversion device 10 is completed (see step (l) in FIG. 9).

FIG. 10 is a schematic view showing the film thickness distribution of the film thickness reduction regions 41 and 51. FIG. 10A shows the film thickness distribution of the film thickness reduction region 41 of the n-type amorphous semiconductor layer 4, and FIG. 10B shows the film thickness reduction region of the p-type amorphous semiconductor layer 5. The film thickness distribution of 51 is shown.

On the paper surface of FIG. 10, the left-right direction is the length direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. The region Area I shows the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 formed corresponding to the openings 201A and 301A of the metal masks 200 and 300.

Further, the regions AreaII to AreaIV indicate the film thickness reduction regions 41 and 51 formed corresponding to the convex portions 201B and 301B of the metal masks 200 and 300.

The film thickness of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 is such that the region AreaI is the thickest and the region AreaII is the second thickest, and is approximately 50% or more of the film thickness of the region AreaI. The region Area III is the third thickest region, which is approximately 20% to 50% of the film thickness of the region Area I, and the region Area IV is the thinnest region, which is approximately 20% or less of the film thickness of the region Area I. .. It can be confirmed by SIMS (Secondary Ion Mass Spectroscopy) or the like that each region is a conductive semiconductor layer containing a dopant.

Therefore, in the film thickness reduction regions 41 and 51, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have a film thickness distribution as shown in FIG. 10 in both the width direction and the length direction. Have.

FIG. 11 is a plan view showing an example of the arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

On the paper surface of FIG. 11, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, and the vertical direction indicates the n-type amorphous semiconductor layer 4 and the p-type non-type. The width direction of the crystalline semiconductor layer 5 is shown.

With reference to FIG. 11, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are arranged alternately in the width direction. The n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have the same width.

The film thickness reduction regions 41 and 51 are arranged at the same positions in the length direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

In FIG. 11, one n-type amorphous semiconductor layer 4 or p-type amorphous semiconductor layer 5 is arranged in the longitudinal direction, but a plurality of n-type amorphous semiconductor layers 4 or a plurality of p-types are arranged. The amorphous semiconductor layer 5 may be arranged.

The n-type amorphous semiconductor layer 4 has a film thickness reduction region 41, and the p-type amorphous semiconductor layer 5 has a film thickness reduction region 51.

Therefore, one n-type amorphous semiconductor layer 4 and one p-type amorphous semiconductor layer 5 are connected in the length direction via the film thickness reduction regions 41 and 51, respectively.

FIG. 12 is a plan view showing an example of another arrangement pattern of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7.

On the paper surface of FIG. 12, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7, and the vertical direction indicates the n-type amorphous semiconductor layer. 4. The width direction of the p-type amorphous semiconductor layer 5 and the electrodes 6 and 7 is shown.

FIG. 12 shows electrodes 6 and 7 added to the arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 shown in FIG.

With reference to FIG. 12, the electrode 6 is arranged on the n-type amorphous semiconductor layer 4 excluding the film thickness reduction region 41, and the electrode 7 is the p-type amorphous semiconductor layer 5 excluding the film thickness reduction region 51. Placed on top.

Therefore, the electrodes 6 and 7 are not arranged in the film thickness reduction regions 41 and 51.

When the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have the planar shape shown in FIG. 12, electrodes 6 and 7 are also formed in the film thickness reduction regions 41 and 51, respectively, to lengthen the length. It may be connected in one direction. In this case, it is desirable that the widths of the electrodes 6 and 7 arranged in the film thickness reduction regions 41 and 51 are narrower than the widths corresponding to the regions Area II and the regions Area III in FIG.

FIG. 13 is a plan view showing an example of another arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

On the paper surface of FIG. 13, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, and the vertical direction indicates the n-type amorphous semiconductor layer 4 and the p-type non-type. The width direction of the crystalline semiconductor layer 5 is shown.

In FIG. 13, one n-type amorphous semiconductor layer 4 or p-type amorphous semiconductor layer 5 is arranged in the longitudinal direction, but a plurality of n-type amorphous semiconductor layers 4 or a plurality of p-types are arranged. The amorphous semiconductor layer 5 may be arranged.

With reference to FIG. 13, the film thickness reduction region 41 is arranged at a position different from the film thickness reduction region 51 in the length direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

In the embodiment of the present invention, the film thickness reduction region 41 and the film thickness reduction region 51 may be formed at arbitrary positions as long as they are at different positions.

Therefore, one n-type amorphous semiconductor layer 4 and one p-type amorphous semiconductor layer 5 are connected in the length direction via the film thickness reduction region 41 and the film thickness reduction region 51, respectively. ..

Other explanations with respect to FIG. 13 are the same as those with reference to FIG.

FIG. 14 is a plan view showing an example of another arrangement pattern of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7.

On the paper surface of FIG. 14, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7, and the vertical direction indicates the n-type amorphous semiconductor layer. 4. The width direction of the p-type amorphous semiconductor layer 5 and the electrodes 6 and 7 is shown.

FIG. 14 shows electrodes 6 and 7 added to the arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 shown in FIG.

With reference to FIG. 14, the electrode 6 is arranged on the n-type amorphous semiconductor layer 4 excluding the film thickness reduction region 41, and the electrode 7 is the p-type amorphous semiconductor layer 5 excluding the film thickness reduction region 51. Placed on top.

Therefore, the electrodes 6 and 7 are not arranged in the film thickness reduction regions 41 and 51.

When the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have the planar shape shown in FIG. 14, the electrodes 6 and 7 are also formed in the film thickness reduction regions 41 and 51, respectively, to lengthen the length. It may be connected in one direction. In this case, it is desirable that the widths of the electrodes 6 and 7 arranged in the film thickness reduction regions 41 and 51 are narrower than the widths corresponding to the regions Area II and the regions Area III in FIG.

FIG. 15 is a plan view showing an example of still another arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

On the paper surface of FIG. 15, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, and the vertical direction indicates the n-type amorphous semiconductor layer 4 and the p-type non-type. The width direction of the crystalline semiconductor layer 5 is shown.

In FIG. 15, one n-type amorphous semiconductor layer 4 or p-type amorphous semiconductor layer 5 is arranged in the longitudinal direction, but a plurality of n-type amorphous semiconductor layers 4 or a plurality of p-types are arranged. The amorphous semiconductor layer 5 may be arranged.

With reference to FIG. 15, the width of the n-type amorphous semiconductor layer 4 is wider than the width of the p-type amorphous semiconductor layer 5.

In the embodiment of the present invention, the width of the p-type amorphous semiconductor layer 5 may be wider than the width of the n-type amorphous semiconductor layer 4.

Other explanations with respect to FIG. 15 are the same as those with reference to FIG.

FIG. 16 is a plan view showing an example of still another arrangement pattern of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7.

On the paper surface of FIG. 16, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7, and the vertical direction indicates the n-type amorphous semiconductor layer. 4. The width direction of the p-type amorphous semiconductor layer 5 and the electrodes 6 and 7 is shown.

FIG. 16 shows electrodes 6 and 7 added to the arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 shown in FIG.

With reference to FIG. 16, the electrode 6 is arranged on the n-type amorphous semiconductor layer 4 excluding the film thickness reduction region 41, and the electrode 7 is the p-type amorphous semiconductor layer 5 excluding the film thickness reduction region 51. Placed on top.

Therefore, the electrodes 6 and 7 are not arranged in the film thickness reduction regions 41 and 51.

When the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have the planar shape shown in FIG. 16, electrodes 6 and 7 are also formed in the film thickness reduction regions 41 and 51, respectively, to lengthen the length. It may be connected in one direction. In this case, it is desirable that the widths of the electrodes 6 and 7 arranged in the film thickness reduction regions 41 and 51 are narrower than the widths corresponding to the regions Area II and the regions Area III in FIG.

FIG. 17 is a plan view showing an example of still another arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

On the paper surface of FIG. 17, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, and the vertical direction indicates the n-type amorphous semiconductor layer 4 and the p-type non-type. The width direction of the crystalline semiconductor layer 5 is shown.

In FIG. 17, one n-type amorphous semiconductor layer 4 or p-type amorphous semiconductor layer 5 is arranged in the longitudinal direction, but a plurality of n-type amorphous semiconductor layers 4 or a plurality of p-types are arranged. The amorphous semiconductor layer 5 may be arranged.

With reference to FIG. 17, the length of the film thickness reduction region 41 in the length direction of the n-type amorphous semiconductor layer 4 is shorter than the length of the film thickness reduction region 51. As a result, the area of the film thickness reduction region 41 facing the semiconductor substrate 1 becomes smaller than the area of the film thickness reduction region 51 facing the semiconductor substrate 1, and in the region of the semiconductor substrate 1 directly below the film thickness reduction region 41, The rate of carrier recombination can be reduced.

In the embodiment of the present invention, the length of the film thickness reduction region 51 in the length direction of the p-type amorphous semiconductor layer 5 may be shorter than the length of the film thickness reduction region 41.

Other explanations with respect to FIG. 17 are the same as those with reference to FIG.

FIG. 18 is a plan view showing an example of still another arrangement pattern of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7.

On the paper surface of FIG. 18, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7, and the vertical direction indicates the n-type amorphous semiconductor layer. 4. The width direction of the p-type amorphous semiconductor layer 5 and the electrodes 6 and 7 is shown.

FIG. 18 shows electrodes 6 and 7 added to the arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 shown in FIG.

With reference to FIG. 18, the electrode 6 is arranged on the n-type amorphous semiconductor layer 4 excluding the film thickness reduction region 41, and the electrode 7 is the p-type amorphous semiconductor layer 5 excluding the film thickness reduction region 51. Placed on top.

Therefore, the electrodes 6 and 7 are not arranged in the film thickness reduction regions 41 and 51.

When the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have the planar shape shown in FIG. 18, electrodes 6 and 7 are also formed in the film thickness reduction regions 41 and 51, respectively, to lengthen the length. It may be connected in one direction. In this case, it is desirable that the widths of the electrodes 6 and 7 arranged in the film thickness reduction regions 41 and 51 are narrower than the widths corresponding to the regions Area II and the regions Area III in FIG.

FIG. 19 is a plan view showing an example of still another arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

On the paper surface of FIG. 19, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, and the vertical direction indicates the n-type amorphous semiconductor layer 4 and the p-type non-type. The width direction of the crystalline semiconductor layer 5 is shown.

In FIG. 19, one n-type amorphous semiconductor layer 4 or p-type amorphous semiconductor layer 5 is arranged in the longitudinal direction, but a plurality of n-type amorphous semiconductor layers 4 or a plurality of p-types are arranged. The amorphous semiconductor layer 5 may be arranged.

FIG. 19 shows a form in which the number of the film thickness reduction region 41 and the number of the film thickness reduction region 51 are different.

In the embodiment of the present invention, the film thickness reduction region 51 is arranged at the same position as the film thickness reduction region 41 in the length direction of the p-type amorphous semiconductor layer 5, and the n-type amorphous semiconductor layer is arranged. It may be arranged in the central portion between the film thickness reduction regions 41 of 4.

Further, the film thickness reduction region 51 is arranged at the same position as the film thickness reduction region 41 in the length direction of the p-type amorphous semiconductor layer 5, and the film thickness reduction region 41 of the n-type amorphous semiconductor layer 4 is arranged. It may be placed at any position between them.

Further, in a configuration different from the configuration shown in FIG. 19, the film thickness reduction region 41 is arranged at the same position as the film thickness reduction region 51 in the length direction of the n-type amorphous semiconductor layer 4, and at an arbitrary different position. It may be configured to be arranged in.

Further, in a configuration different from the configuration shown in FIG. 19, the film thickness reduction region 41 and the film thickness reduction region 51 are formed by the lengths of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively. It may be arranged at different positions in the direction, and the number may be arbitrary.

Other descriptions of FIG. 19 are the same as those of FIG.

FIG. 20 is a plan view showing an example of still another arrangement pattern of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7.

On the paper surface of FIG. 20, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7, and the vertical direction indicates the n-type amorphous semiconductor layer. 4. The width direction of the p-type amorphous semiconductor layer 5 and the electrodes 6 and 7 is shown.

FIG. 20 shows the arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 shown in FIG. 19 with electrodes 6 and 7 added. With reference to FIG. 20, the electrode 6 is The electrode 7 is arranged on the n-type amorphous semiconductor layer 4 excluding the film thickness reduction region 41, and the electrode 7 is arranged on the p-type amorphous semiconductor layer 5 excluding the film thickness reduction region 51.

Therefore, the electrodes 6 and 7 are not arranged in the film thickness reduction regions 41 and 51.

When the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have the planar shape shown in FIG. 20, electrodes 6 and 7 are also formed in the film thickness reduction regions 41 and 51, respectively, to lengthen the length. It may be connected in one direction. In this case, it is desirable that the widths of the electrodes 6 and 7 arranged in the film thickness reduction regions 41 and 51 are narrower than the widths corresponding to the regions Area II and the regions Area III shown in FIG.
FIG. 21 is a plan view showing an example of still another arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

On the paper surface of FIG. 21, the left-right direction indicates the length direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, and the vertical direction indicates the n-type amorphous semiconductor layer 4 and the p-type non-type. The width direction of the crystalline semiconductor layer 5 is shown.

With reference to FIG. 21, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are arranged alternately in the width direction. The n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have the same width.

FIG. 11 shows a configuration in which a plurality of n-type amorphous semiconductor layers 4 or a plurality of p-type amorphous semiconductor layers 5 are arranged, and the film thickness reduction region 41 or the film thickness reduction region 51 is formed. The structure is formed at the end of the n-type amorphous semiconductor layer 4 or the p-type amorphous semiconductor layer 5.

Between the two adjacent n-type amorphous semiconductor layers 4, the respective film thickness reduction regions 41 provided at the ends of the n-type amorphous semiconductor layer 4 are not connected. Further, between the two adjacent p-type amorphous semiconductor layers 5, the respective film thickness reduction regions 51 provided at the ends of the n-type amorphous semiconductor layer 5 are not connected.

FIG. 22 is a plan view showing an example of still another arrangement pattern of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7.

On the paper surface of FIG. 22, the left-right direction shows the length direction of the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7, and the vertical direction shows the n-type amorphous semiconductor layer. 4. The width direction of the p-type amorphous semiconductor layer 5 and the electrodes 6 and 7 is shown.

FIG. 22 shows electrodes 6 and 7 added to the arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 shown in FIG.

With reference to FIG. 22, the electrode 6 is arranged on the n-type amorphous semiconductor layer 4 excluding the film thickness reduction region 41, and the electrode 7 is the p-type amorphous semiconductor layer 5 excluding the film thickness reduction region 51. Placed on top.

Therefore, the electrodes 6 and 7 are not arranged in the film thickness reduction regions 41 and 51.

When the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have the planar shape shown in FIG. 21, electrodes 6 and 7 may be formed in the film thickness reduction regions 41 and 51, respectively. .. In this case, the electrodes 6 and 7 arranged in the film thickness reduction regions 41 and 51 are preferably provided in the regions corresponding to the regions Area I, the region Area II, and the region Area III shown in FIG.

In order to form the arrangement pattern of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 shown in FIGS. 11, 13, 15, 17, 19, and 21, the openings of the metal masks 200 and 300 described above are formed. The n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor shown in FIGS. 11, 13, 15, 17, 19, and 21 show the length and / or width of the portions 201A and 301A and the positions of the convex portions 201B and 301B. It may be determined so as to correspond to the arrangement pattern of the layer 5.

As described above, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have various planar shapes. The film thickness reduction regions 41 and 51 have various planar shapes along with the planar shapes of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

Further, one n-type amorphous semiconductor layer 4 and one p-type amorphous semiconductor layer 5 are connected to each other in the length direction via the film thickness reduction region 41 and the film thickness reduction region 51.

When the electrodes 6 and 7 are also arranged in the film thickness reduction regions 41 and 51, respectively, the electrodes 6 and 7 are a metal having one opening in which the openings 401n and 401p are extended in the X-axis direction in the metal mask 400. The mask forms the n-type amorphous semiconductor layer 4 and the film thickness reduction region 41, and the p-type amorphous semiconductor layer 5 and the film thickness reduction region 51, respectively.

When the width of the n-type amorphous semiconductor layer 4 is wider than the width of the p-type amorphous semiconductor layer 5, the electrode is used in the metal mask 400 using a metal mask in which the width of the opening 401n is wider than the width of 401p. 6 and 7 are formed on the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, respectively.

FIG. 23 is an enlarged schematic view of a part of the wiring sheet according to the embodiment of the present invention. FIG. 24 is a schematic view showing a cross section of a photoelectric conversion device (including a conductive portion). Further, FIG. 25 is a schematic view showing a cross section of the photoelectric conversion device (including the conductive portion) in the other direction. FIG. 26 is a schematic view showing a cross section of a photoelectric conversion device (including a conductive portion) using a wire grid.

When forming the conductive portion of the photoelectric conversion device 10, the photoelectric conversion device 10 is electrically connected to the wiring circuit. As the external wiring circuit, for example, the wiring sheet shown in FIG. 23 can be used. Alternatively, as another method, a connection using a wire grid can be used.

With reference to FIG. 23, the wiring sheet 30 includes an insulating substrate 31, an n-type wiring material 32n, and a p-type wiring material 32p. The n-type wiring material 32n and the p-type wiring material 32p are formed on the insulating substrate 31.

The insulating substrate 31 may be any insulating material, and for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyvinyl fluoride (PVF), polyimide, or the like may be used. .. The film thickness of the insulating substrate 31 is not particularly limited, but is preferably about 25 μm or more and 150 μm or less. Further, the insulating substrate 31 may have a one-layer structure or a multi-layer structure having two or more layers.

The n-type wiring material 32n and the p-type wiring material 32p have a comb-teeth shape and are alternately arranged at predetermined intervals. The electrodes 6 and 7 formed on the back surface of the photoelectric conversion device 10 are joined to the n-type wiring material 32n and the p-type wiring material 32p, respectively (see FIGS. 24 and 25).

Wiring for connection (not shown) is formed on the surface of the insulating substrate 31. The n-type wiring material 32n and the p-type wiring material 32p of the adjacent photoelectric conversion devices 10 are electrically connected by the connection wiring, and the adjacent photoelectric conversion devices 10 on the wiring sheet 30 are electrically connected to each other. It is connected. As a result, the current generated by the light incident on the light receiving surface of the photoelectric conversion device 10 can be taken out to the outside through the p-type wiring material 32p and the n-type wiring material 32n.

The n-type wiring material 32n and the p-type wiring material 32p may be made of a conductive material, and may be, for example, any metal such as Cu, Al, Ag, or any of these. It may be an alloy containing the above metal as a main component.

The film thicknesses of the n-type wiring material 32n and the p-type wiring material 32p are not particularly limited, but are preferably 10 μm or more and 100 μm or less, for example. If the film thickness of the n-type wiring material 32n and the p-type wiring material 32p is thinner than 10 μm, the wiring resistance may increase. Further, if it is thicker than 100 μm, it is necessary to apply heat when bonding the n-type wiring material 32n and the p-type wiring material 32p and the photoelectric conversion device 10. As a result, when it becomes thicker than 100 μm, the warp of the wiring sheet 30 becomes large due to the difference in the coefficient of thermal expansion between the n-type wiring material 32n and the p-type wiring material 32p and the semiconductor substrate 1 of the photoelectric conversion device 10. Therefore, the thickness of the n-type wiring material 32n and the p-type wiring material 32p is more preferably 100 μm or less.

Further, a conductive material such as nickel, gold, platinum, palladium, silver, tin, indium, or ITO may be formed on a part of the surface of the n-type wiring material 32n and the p-type wiring material 32p. .. With this configuration, the electrical connection between the n-type wiring material 32n and the electrode 6 of the photoelectric conversion device 10 and the electrical connection between the p-type wiring material 32p and the electrode 7 of the photoelectric conversion device 10 are good. Therefore, the weather resistance of the n-type wiring material 32n and the p-type wiring material 32p is improved. The n-type wiring material 32n and the p-type wiring material 32p may have a one-layer structure or a multi-layer structure having two or more layers.

In this way, the plurality of photoelectric conversion devices 10 are arranged on the wiring sheet 30 to form a photoelectric conversion module.

In the above, it has been described that both the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have the film thickness reduction regions 41 and 51, respectively, but in the embodiment of the present invention, this Not limited to this, at least one of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 may have a film thickness reduction region. If at least one of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 has a film thickness reduction region, the stress applied to the semiconductor substrate 1 is an amorphous film having a constant film thickness. This is because it is reduced as compared with the case where the quality semiconductor layer is formed, and warpage and bending of the semiconductor substrate can be suppressed.

[Embodiment 2]
FIG. 27 is a plan view showing the configuration of the photoelectric conversion device according to the second embodiment. FIG. 28 is a cross-sectional view of the photoelectric conversion device in line XXVIII-XXVIII shown in FIG. 27. FIG. 29 is a cross-sectional view of the photoelectric conversion device in the line XXIX-XXIX shown in FIG. 27. FIG. 30 is a cross-sectional view of the photoelectric conversion device on the line XXX-XXX shown in FIG. 27.

With reference to FIG. 27, the photoelectric conversion device 10A according to the second embodiment is the same as the photoelectric conversion device 10 except that the protective film 8 is added to the photoelectric conversion device 10 shown in FIGS. 1 and 2. is there.

The protective film 8 is arranged on the region excluding a part of the electrodes 6 and 7. That is, the protective film 8 is arranged in the film thickness reduction regions 41 and 51, and in the region between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5.

The protective film 8 includes a portion 81 arranged between the adjacent n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, a portion 82 arranged on the film thickness reduction region 41, and a film. The portion 83 arranged on the thickness reduction region 51 and the portion 83 arranged adjacent to the n-type amorphous semiconductor layer 4 or the p-type amorphous semiconductor layer 5 in the in-plane direction (Y-axis direction) of the semiconductor substrate 1. It has a portion 84 and.

The protective film portion 81 has the thickest film thickness d1, and the protective film 8 portions 82, 83, 84 have a film thickness in the range of 10% to 90% of the film thickness d1.

The protective film 8 is made of, for example, a silicon nitride film (SiN).

By arranging the protective film 8 in the film thickness reduction regions 41 and 51 in this way, the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are protected, and the n-type amorphous semiconductor layer 4 is protected. And the electric passivation effect by the p-type amorphous semiconductor layer 5 can be obtained.

Further, the passivation layer 3 (i-type amorphous silicon) is protected by arranging the protective film 8 between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, and the passivation layer 3 (passivation layer 3 (i-type amorphous silicon)) is protected. The chemical passivation effect of i-type amorphous silicon) can be obtained.

When a plurality of n-type amorphous semiconductor layers 4 and a plurality of p-type amorphous semiconductor layers 5 are arranged in the longitudinal direction, there are a plurality of n-type amorphous semiconductor layers 4 or a plurality of p-types. The protective layer 8 can be formed between the amorphous semiconductor layers 5.

With reference to FIG. 28, the portion 82 of the protective film 8 is arranged in the film thickness reduction region 41 and is in contact with the n-type amorphous semiconductor layer 4 and the electrode 6. The portion 82 of the protective film 8 is also arranged on a part of the electrodes 6 and 6 that are separated from each other in the length direction (X-axis direction) of the n-type amorphous semiconductor layer 4.

The film thickness of the portion 82 of the protective film 8 has a film thickness in the range of 10% to 90% of the film thickness d1 of the portion 81 of the protective film 8.

The portion 83 of the protective film 8 is arranged in the film thickness reduction region 51 in the same manner as the portion 82 of the protective film 8 is arranged in the film thickness reduction region 41.

With reference to FIG. 29, the protective film 8 is an n-type region between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 in the in-plane direction (Y-axis direction) of the semiconductor substrate 1. It is arranged in a region on the amorphous semiconductor layer 4 and a region on the p-type amorphous semiconductor layer 5.

The portion 81 of the protective film 8 arranged in the region between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 has a film thickness d1 and is an n-type amorphous semiconductor layer. The film thickness of the protective film 8 arranged on the region on 4 and the region on the p-type amorphous semiconductor layer 5 is thinner than the film thickness d1.

With reference to FIG. 30, in the region where the film thickness reduction regions 41 and 51 are not arranged, the protective film 8 is a passion film between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5. 3 (i-type amorphous silicon), n-type amorphous semiconductor layer 4, p-type amorphous semiconductor layer 5 and electrodes 6 and 7 are arranged in contact with each other.

Therefore, the protective film 8 protects the passivation film 3 (i-type amorphous silicon), the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the electrodes 6 and 7. As a result, the chemical passivation effect of the passivation film 3 (i-type amorphous silicon) can be obtained.

Further, it is possible to prevent moisture or the like from entering between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 and the electrodes 6 and 7 from the outside.

FIG. 31 is a plan view of a metal mask for forming the protective film 8.

With reference to FIG. 31, the metal mask 500 has a plurality of openings 501A, a plurality of convex portions 501B, and a plurality of concave portions 501C.

The openings 501A have a rectangular shape whose long sides are parallel to the X-axis, and are arranged at predetermined intervals along the Y-axis direction.

The convex portion 501B is provided in the opening 501A. The convex portion 501B is half-etched so that the thickness (length in the Z-axis direction) is 10% to 70% of the length of the opening 501A in the Z-axis direction.

The thickness (length in the Z-axis direction) of the convex portion 501B may be smaller than the length of the opening 501A in the Z-axis direction.

The recesses 501C are provided between adjacent openings 501A in the Y-axis direction at predetermined intervals in the X-axis direction.

The recess 501C is half-etched so that the depth (length in the Z-axis direction) is 10% to 70% of the thickness of the metal mask 500.

The convex portion 501B is provided to increase the strength of the metal mask 500. That is, when the convex portion 501B is not provided, the opening 501A has a rectangular shape that is long in the X-axis direction, so that the strength of the metal mask 500 is weakened. Therefore, the convex portion 501B is provided in the opening 501A to increase the strength of the metal mask 500.

The portion 81 of the protective film 8 shown in FIG. 27 is formed corresponding to the region of the opening 501A excluding the convex portion 501B. Further, the portions 82 and 83 of the protective film 8 shown in FIG. 27 are formed corresponding to the recess 501C. Further, the portion 84 of the protective film 8 shown in FIG. 27 is formed corresponding to the convex portion 501B.

When the protective film 8 is formed by a vapor phase growth method such as a plasma CVD method, the material gas that reaches the semiconductor substrate 1 from the opening 501A wraps around from the opening 501A to the regions of the convex portion 501B and the concave portion 501C. , The protective film 8 is formed in the region corresponding to the convex portion 501B and the concave portion 501C.

Therefore, the film thickness of the protective film 8 portions 82 to 84 is thinner than that of the protective film 8 portion 81.

FIG. 32 is a plan view of another metal mask for forming the protective film. With reference to FIG. 32, in the metal mask 500 shown in FIG. 31, the convex 501B is added so that the convex 501B are arranged on both sides of the concave 501C in the X-axis direction.

As a result, the number of convex portions 501B provided in one opening 501A increases, and the mechanical strength of the metal mask 600 can be made stronger than that of the metal mask 500.

Other descriptions of the metal mask 600 are the same as those of the metal mask 500.

In the metal masks 500 and 600, since the recess 501C forms the protective film 8 on the film thickness reduction regions 41 and 51, the position of the recess 501C cannot be freely changed.

On the other hand, since the convex portion 501B is provided to increase the mechanical strength of the metal masks 500 and 600, the number and arrangement positions of the convex portions 501B are determined in consideration of the mechanical strength of the metal masks 500 and 600. You can change it freely.

Therefore, in the metal mask 600, the number of convex portions 501B is increased as compared with the metal mask 500 to increase the mechanical strength.

The metal mask for forming the protective film 8 is not limited to the metal masks 500 and 600, and a metal mask in which an arbitrary number of convex portions 501B are arranged at an arbitrary position in consideration of the mechanical strength of the metal mask. May be.

As described above, at least one film thickness reduction region 41, 51 is sufficient, and if at least one convex portion 501B is provided, the strength of the metal masks 500, 600 can be increased, so that the metal masks 500, 600 can be strengthened. Has the following configurations.

That is, the metal masks 500 and 600 have a length corresponding to the lengths of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5, and are n-type in the in-plane direction of the semiconductor substrate 1. A plurality of openings 501A arranged in the arrangement direction of the amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 and a thickness provided in the plurality of openings 501A and smaller than the depth of the openings 501A. The n-type amorphous semiconductor layer 4 and the n-type amorphous semiconductor layer 4 and the n-type amorphous semiconductor layer 4 and the two openings 501A adjacent to each other in the arrangement direction of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 It has at least one recess 501C arranged at predetermined intervals in the length direction of the p-type amorphous semiconductor layer 5 and having a thickness smaller than the depth of the opening 501A.

The protective film 8 is formed using the metal masks 500 and 600 as follows. After the electrodes 6 and 7 are formed, the metal mask 500 is placed on the back surface side of the semiconductor substrate 1 and a silicon nitride film (SiN) is formed by using a vapor phase growth method such as a plasma CVD method. As a result, SiN is deposited in the region corresponding to the opening 501A, and the protective film 8 is formed. Further, the reaction gas wraps around the region corresponding to the half-etched convex portion 501B and the concave portion 501C, and the protective film 8 is also formed on the lower side of the convex portion 501B and the concave portion 501C.

Although it depends on the size of the convex portion 501B and the concave portion 501C, the film thickness of the protective film 8 formed on the lower side of the convex portion 501B and the concave portion 501C is the film thickness of the protective film 8 formed on the opening 501A. It may be about 10% to 90%.

By forming a SiN film using the metal masks 500 and 600 in this way, a protective film 8 is formed on the back surface side of the semiconductor substrate 1 except for a part of the electrodes 6 and 7.

As a result, the region of the passion film 3 not covered by any of the electrodes 6 and 7, the n-type amorphous semiconductor layer 4, and the p-type amorphous semiconductor layer 5, and the film of the n-type amorphous semiconductor layer 4. The thickness reduction region 41, the film thickness reduction region 51 of the p-type amorphous semiconductor layer 5, and the space between the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 are covered with the protective film 8.

In the above example, it is preferable to use SiN as the material of the protective film 8, but for example, SiO, SiON, AlO, TiO and the like may be used as the material of the protective film 8.

The photoelectric conversion device 10A is manufactured according to a step of adding a step of forming a protective film 8 using a metal mask 500 (or a metal mask 600) to the steps (a) to (l) shown in FIGS. 6 to 9. To.

In the photoelectric conversion device 10A, in addition to the effects of the photoelectric conversion device 10, the passivation film 3, the n-type amorphous semiconductor layer 4, the p-type amorphous semiconductor layer 5, and the film thickness reduction regions 41, 51 are provided by the protective film 8. Is protected. As a result, the chemical passivation effect of the passivation film 3 can be obtained, and the electric field passivation effect of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 can also be obtained, which is a characteristic of the photoelectric conversion device 10A. Can be improved. When the protective film 8 is made of a silicon nitride film (SiN), the silicon nitride film (SiN) has a positive fixed charge, so that the electric field passivation effect due to the positive fixed charge can be further obtained.

In the above, it has been described that both the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 have the film thickness reduction regions 41 and 51, respectively, but in the embodiment of the present invention, this is described. Not limited to this, in the photoelectric conversion device 10A, both the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 do not have a film thickness reduction region, and only the protective film 8 has a film thickness reduction region. You may be doing it.

Further, in the photoelectric conversion device 10A, at least one of the n-type amorphous semiconductor layer 4 and the p-type amorphous semiconductor layer 5 has a film thickness reduction region, and the protective film has a film thickness reduction region. May be.

The other description in the second embodiment is the same as the description in the first embodiment.

In the above, it has been described that the semiconductor substrate 1 has an n-type conductive type, but in the embodiment of the present invention, the present invention is not limited to this, and the semiconductor substrate 1 has a p-type conductive type. May be good.

[Embodiment 3]
FIG. 33 is a schematic view showing the configuration of a photoelectric conversion module including a photoelectric conversion device according to this embodiment. With reference to FIG. 33, the photoelectric conversion module 1000 includes a plurality of photoelectric conversion devices 1001, a cover 1002, and output terminals 1003 and 1004.

The plurality of photoelectric conversion devices 1001 are arranged in an array and connected in series. The plurality of photoelectric conversion devices 1001 may be connected in parallel instead of being connected in series, or may be connected in combination of series and parallel.

Each of the plurality of photoelectric conversion devices 1001 is composed of any of the photoelectric conversion devices 10 and 10A.

The cover 1002 comprises a weather resistant cover and covers a plurality of photoelectric conversion devices 1001. The cover 1002 is, for example, a transparent base material (for example, glass) provided on the light receiving surface side of the photoelectric conversion device 1001 and a back surface base material (for example, glass or the like) provided on the back surface side opposite to the light receiving surface side of the photoelectric conversion device 1001. For example, glass, resin sheet, etc.) and a sealing material (for example, EVA, etc.) that fills the gap between the transparent base material and the back surface base material.

The output terminal 1003 is connected to a photoelectric conversion device 1001 arranged at one end of a plurality of photoelectric conversion devices 1001 connected in series.

The output terminal 1004 is connected to a photoelectric conversion device 1001 arranged at the other end of a plurality of photoelectric conversion devices 1001 connected in series.

As described above, the photoelectric conversion devices 10 and 10A are excellent in conversion efficiency and moisture resistance.

Therefore, the conversion efficiency and moisture resistance of the photoelectric conversion module 1000 can be improved.

The number of photoelectric conversion devices 1001 included in the photoelectric conversion module 1000 is an arbitrary integer of 2 or more.

Further, the photoelectric conversion module according to the third embodiment is not limited to the configuration shown in FIG. 33, and may have any configuration as long as any of the photoelectric conversion devices 10 and 10A is used.

According to the above-described first to third embodiments, the photoelectric conversion device, the photoelectric conversion module, and the method for manufacturing the photoelectric conversion device according to the embodiment of the present invention have the following configurations.

(Structure 1)
In the method for manufacturing a photoelectric conversion device according to an embodiment of the present invention, a plurality of first openings arranged in a row at predetermined intervals and two adjacent first openings are arranged and the first. A first amorphous having a first conductive mold on one surface of a semiconductor substrate using a first mask comprising at least one first convex portion having a thickness smaller than the depth of one opening. A first step of forming a quality semiconductor layer by a vapor phase growth method, a plurality of second openings arranged in a row at predetermined intervals, and two adjacent second openings are arranged. A first in-plane direction of the semiconductor substrate is applied to one surface of the semiconductor substrate using a second mask including at least one second convex portion having a thickness smaller than the depth of the second opening. A second step of forming a second amorphous semiconductor layer alternately arranged with the amorphous semiconductor layer of the above and having a second conductive type different from the first conductive type by a vapor phase growth method is provided. ..

According to the configuration 1, the first amorphous semiconductor layer formed by using the first mask has a film thickness reduction region at a position corresponding to the first convex portion. Further, the second amorphous semiconductor layer formed by using the second mask has a film thickness reduction region at a position corresponding to the second convex portion.

As a result, the stress applied to the semiconductor substrate is less than the stress applied to the semiconductor substrate as compared with the case where the amorphous semiconductor layer having a constant film thickness is formed, and the warpage and bending of the semiconductor substrate can be suppressed. ..

(Structure 2)
In configuration 1, the method for manufacturing a photoelectric conversion device further includes a third step of forming a passivation film between the semiconductor substrate and the first and second amorphous semiconductor layers.

According to the configuration 2, carrier recombination at the interface between the passivation film and the semiconductor substrate is suppressed.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

(Structure 3)
In configuration 2, in the third step, intrinsically hydrogenated amorphous silicon is formed as a passivation film.

According to the configuration 3, the hydrogen in the passivation film can compensate for the defects existing on the surface of the semiconductor substrate, and the life of the carrier is extended.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

(Structure 4)
In any one of the configurations 1 to 3, the method for manufacturing the photoelectric conversion device has a length corresponding to the lengths of the first and second amorphous semiconductor layers, and in the in-plane direction of the semiconductor substrate. A plurality of third openings arranged in the arrangement direction of the first and second amorphous semiconductor layers, a plurality of third openings, and more than the depth of the third opening. Between at least one convex portion having a small thickness and two third openings adjacent to each other in the arrangement direction of the first and second amorphous semiconductor layers, the first and second amorphous semiconductor layers Adjacent first and second masks with at least one recess arranged in the longitudinal direction at predetermined intervals and having a thickness smaller than the depth of the third opening. The region between the amorphous semiconductor layers, the film thickness reduction region of the first amorphous semiconductor layer formed in the first step, and the film of the second amorphous semiconductor layer formed in the second step. A fourth step of forming a protective film on the thickness reduction region by the vapor phase growth method is further provided.

According to the configuration 4, a protective film is formed between the first and second amorphous semiconductor layers and the film thickness reduction region.

As a result, the passivation film or the semiconductor substrate existing under the protective film can be protected, and the life of the carrier is extended.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

(Structure 5)
In any one of configurations 1 to 3, in the method for manufacturing a photoelectric conversion device, a first amorphous semiconductor layer is formed on one surface of a semiconductor substrate, and a second amorphous semiconductor layer is a surface of the semiconductor substrate. It is arranged alternately with the first amorphous semiconductor layer in the inward direction and formed on one surface of the semiconductor substrate, and has a length corresponding to the length of the first and second amorphous semiconductor layers. In addition, a plurality of third openings arranged in the arrangement direction of the first and second amorphous semiconductor layers in the in-plane direction of the semiconductor substrate, and a plurality of third openings provided in the plurality of third openings, and A protective film is vaporized in the region between the adjacent first and second amorphous semiconductor layers using a third mask having at least one convex portion having a thickness smaller than the depth of the third opening. It further comprises a fourth step of forming by the growth method.

According to the configuration 5, a protective film is formed between the adjacent first and second amorphous semiconductor layers. The formed protective film has at least one film thickness reduction region in which the film thickness is reduced.

Therefore, the mechanical strength of the third mask for disregarding the protective film is increased, and the protective film can be accurately formed in the region between the adjacent first and second amorphous semiconductor layers.

(Structure 6)
In the fourth step of the configuration 4 or 5, the silicon nitride film is formed as a protective film.

According to Configuration 6, a protective film can be formed in a single process using the vapor deposition method. In addition, the electric field passivation effect can be obtained by the positive fixed charge of the silicon nitride film.

(Structure 7)
The photoelectric conversion device according to the embodiment of the present invention includes a semiconductor substrate, a first amorphous semiconductor layer, and a second amorphous semiconductor layer. The semiconductor substrate has a first conductive type. The first amorphous semiconductor layer is formed on one surface of a semiconductor substrate and has a first conductive type. The second amorphous semiconductor layer is formed on one surface of the semiconductor substrate by being alternately arranged with the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate, and is different from the first conductive type. Has a conductive type. Then, at least one of the first and second amorphous semiconductor layers has at least one film thickness reduction region that traverses the amorphous semiconductor layer in the width direction and reduces the film thickness.

According to the configuration 6, at least one of the first and second amorphous semiconductor layers has a film thickness reduction region, so that the stress applied to the semiconductor substrate is an amorphous semiconductor having a constant film thickness. It is less than if a layer is formed.

Therefore, warpage and bending of the semiconductor substrate can be suppressed.

(Structure 8)
In configuration 7, the photoelectric conversion device further includes a passivation film arranged between the semiconductor substrate and the first and second amorphous semiconductor layers.

According to the configuration 7, carrier recombination at the interface between the passivation film and the semiconductor substrate is suppressed.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

(Structure 9)
In configuration 8, the passivation membrane comprises intrinsically hydrogenated amorphous silicon.

According to the configuration 9, the hydrogen in the passivation film can compensate for the defects existing on the surface of the semiconductor substrate, and the life of the carrier is extended.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

(Structure 10)
In any of configurations 7 to 9, the photoelectric conversion device further includes a protective film formed on the film thickness reduction region in the first and second amorphous semiconductor layers.

According to the configuration 10, a protective film is formed between the first and second amorphous semiconductor layers and the film thickness reduction region.

As a result, the passivation film or the semiconductor substrate existing under the protective film can be protected, and the life of the carrier is extended.

Therefore, the conversion efficiency of the photoelectric conversion device can be improved.

(Structure 11)
The photoelectric conversion device according to the embodiment of the present invention includes a semiconductor substrate, a first amorphous semiconductor layer, a second amorphous semiconductor layer, and a protective film. The semiconductor substrate has a first conductive type. The first amorphous semiconductor layer is formed on one surface of a semiconductor substrate and has a first conductive type. The second amorphous semiconductor layer is formed on one surface of the semiconductor substrate by being alternately arranged with the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate, and is different from the first conductive type. Has a conductive type. The protective film is formed on one surface of the semiconductor substrate in the region between the adjacent first and second amorphous semiconductor layers. Then, the protective film has at least one film thickness reduction region that crosses the protective film in the width direction and reduces the film thickness.

According to the configuration 11, the protective film is arranged between the adjacent first and second amorphous semiconductor layers, and the protective film is connected in the length direction of the first and second amorphous semiconductor layers. ing.

Therefore, it is possible to suppress the invasion of moisture such as moisture from the region not covered by the first and second amorphous semiconductor layers.

(Structure 12)
In configuration 10 or 11, the protective film comprises at least a silicon nitride film.

According to the configuration 12, the electric field passivation effect can be obtained by the positive fixed charge of the silicon nitride film.

(Structure 13)
The photoelectric conversion module according to the embodiment of the present invention includes a conductive portion and a plurality of photoelectric conversion devices. The conductive part is from the wiring sheet or wire grid. The plurality of photoelectric conversion devices are arranged on the conductive portion. Each of the plurality of photoelectric conversion devices comprises the photoelectric conversion device according to any one of configurations 7 to 12.

According to the configuration 13, the photoelectric conversion device according to any one of the configurations 7 to 12 can improve the conversion efficiency, so that the photoelectric conversion module provided with the photoelectric conversion device can also improve the conversion efficiency.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims rather than the description of the embodiment described above, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

The present invention applies to photoelectric conversion devices, photoelectric conversion modules, and methods for manufacturing photoelectric conversion devices.

1 Semiconductor substrate, 2 Antireflection film, 3 Passivation film, 4 n-type amorphous semiconductor layer, 5 p-type amorphous semiconductor layer, 6, 7 electrodes, 8 protective film, 10, 10A photoelectric conversion device, 30 Wiring sheet , 31 Insulating substrate, 32n n type wiring material, 32pp type wiring material, 41,51 film thickness reduction area, 200, 300, 400, 500 metal mask, 201, 301, 501 opening area, 201A, 301A, 401n, 401p, 501A, 501C openings, 201B, 301B convex parts, 501B concave parts, 1003, 1004 output terminals.

Claims (15)

It is arranged between a plurality of first openings arranged in a row at predetermined intervals and two adjacent first openings, and has a thickness smaller than the depth of the first openings. A first amorphous semiconductor layer having a first conductive type on one surface of a semiconductor substrate is formed by a vapor phase growth method using a first mask including at least one first convex portion. Process and
It is arranged between a plurality of second openings arranged in a row at predetermined intervals and two adjacent second openings, and has a thickness smaller than the depth of the second openings. Using a second mask including at least one second convex portion, the first amorphous semiconductor layer is alternately arranged on one surface of the semiconductor substrate in the in-plane direction of the semiconductor substrate, and A second step of forming a second amorphous semiconductor layer having a second conductive type different from the first conductive type by a vapor phase growth method is provided.
The plurality of first openings are arranged in a row in the length direction of the first amorphous semiconductor layer.
The plurality of second openings are arranged in a row in the length direction of the second amorphous semiconductor layer.
The first amorphous semiconductor layer crosses the first amorphous semiconductor layer in the width direction at a position corresponding to the first convex portion, and the film thickness is reduced. Have,
The second amorphous semiconductor layer crosses the second amorphous semiconductor layer in the width direction at a position corresponding to the second convex portion, and the film thickness is reduced. A method for manufacturing a photoelectric conversion device. The method for manufacturing a photoelectric conversion device according to claim 1, further comprising a third step of forming a passivation film between the semiconductor substrate and the first and second amorphous semiconductor layers. The method for manufacturing a photoelectric conversion device according to claim 2, wherein in the third step, intrinsically hydrogenated amorphous silicon is formed as the passivation film. It has a length corresponding to the length of the first and second amorphous semiconductor layers, and in the in-plane direction of the semiconductor substrate, in the arrangement direction of the first and second amorphous semiconductor layers. A plurality of arranged third openings, at least one convex portion provided in the plurality of third openings and having a thickness smaller than the depth of the third opening, and the said. The first and second amorphous semiconductor layers are arranged at predetermined intervals in the length direction of the first and second amorphous semiconductor layers between the two adjacent third openings in the arrangement direction of the first and second amorphous semiconductor layers. And, using a third mask having at least one recess having a thickness smaller than the depth of the third opening, with the region between the adjacent first and second amorphous semiconductor layers. The film thickness reduction region of the first amorphous semiconductor layer formed in the first step and the film thickness reduction region of the second amorphous semiconductor layer formed in the second step. The method for manufacturing a photoelectric conversion device according to any one of claims 1 to 3, further comprising a fourth step of forming a protective film by a vapor phase growth method. The first amorphous semiconductor layer is formed on one surface of the semiconductor substrate, and the second amorphous semiconductor layer alternates with the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate. Is formed on one surface of the semiconductor substrate, has a length corresponding to the length of the first and second amorphous semiconductor layers, and is the first in the in-plane direction of the semiconductor substrate. From the depth of the plurality of third openings arranged in the arrangement direction of the first and second amorphous semiconductor layers, the plurality of third openings, and the depth of the third openings. A fourth mask in which a protective film is formed by a vapor phase growth method in a region between adjacent first and second amorphous semiconductor layers using a third mask having at least one convex portion having a small thickness. The method for manufacturing a photoelectric conversion device according to any one of claims 1 to 3, further comprising the above step. The method for manufacturing a photoelectric conversion device according to claim 4 or 5, wherein in the fourth step, a silicon nitride film is formed as the protective film. A semiconductor substrate having a first conductive type and
A first amorphous semiconductor layer formed on one surface of the semiconductor substrate and having the first conductive type,
A second conductive type that is alternately arranged with the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate and is formed on one surface of the semiconductor substrate and has a second conductive type different from the first conductive type. and the amorphous semiconductor layer of 2,
With the first electrode arranged on the first amorphous semiconductor layer,
With the second electrode arranged on the second amorphous semiconductor layer,
On one surface of the semiconductor substrate, a first protective film formed in a region between the adjacent first and second electrodes is provided.
At least one of the first and second amorphous semiconductor layers is a photoelectric conversion device that traverses the amorphous semiconductor layer in the width direction and has at least one film thickness reduction region in which the film thickness decreases. .. The photoelectric conversion device according to claim 7, further comprising a passivation film arranged between the semiconductor substrate and the first and second amorphous semiconductor layers. The photoelectric conversion device according to claim 8, wherein the passivation film contains intrinsically hydrogenated amorphous silicon. The photoelectric conversion device according to any one of claims 7 to 9, further comprising a second protective film formed on the film thickness reduction region in the first and second amorphous semiconductor layers. .. A semiconductor substrate having a first conductive type and
A first amorphous semiconductor layer formed on one surface of the semiconductor substrate and having the first conductive type,
A second conductive type that is alternately arranged with the first amorphous semiconductor layer in the in-plane direction of the semiconductor substrate and is formed on one surface of the semiconductor substrate and has a second conductive type different from the first conductive type. 2 amorphous semiconductor layers and
On one surface of the semiconductor substrate, a third protective film formed in a region between the adjacent first and second amorphous semiconductor layers is provided.
The third protective film is a photoelectric conversion device that crosses the third protective film in the width direction and has at least one film thickness reduction region in which the film thickness is reduced. The photoelectric conversion device according to any one of claims 7 to 10, wherein the first protective film includes at least a silicon nitride film. The photoelectric conversion device according to claim 10 , wherein the second protective film contains at least a silicon nitride film. The photoelectric conversion device according to claim 11 , wherein the third protective film includes at least a silicon nitride film. Conductive parts consisting of wiring sheets or wire grids,
A plurality of photoelectric conversion devices arranged on the conductive portion are provided.
Each of the plurality of photoelectric conversion devices is a photoelectric conversion module comprising the photoelectric conversion device according to any one of claims 7 to 14.

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