JP6845688B2 - Switch device and switch circuit - Google Patents

Description

The present invention relates to switch devices and switch circuits.

In wireless communication, a technique called antenna diversity is used in order to realize highly accurate communication by providing redundancy in signal transmission / reception. In antenna diversity, in order to receive a signal without fading effect, a plurality of antennas are installed to receive the signal. At that time, a switch circuit for selecting an antenna suitable for communication from a plurality of antennas is used. As such a switch circuit, for example, a DPDT (Dual Port Dual Throw) type switch circuit having two inputs and two outputs composed of a plurality of switch elements (for example, MOS transistors) is used.

In a switch circuit using a plurality of MOS transistors as switch elements, a switch circuit adopting a triple-well structure is known in order to control the substrate potential of the NMOS transistor. For example, as a switch circuit using such a triple-well structure, in order to suppress the generation of off-leakage current, two circuits in which a MOSFET transistor and an NMOS transistor are connected in series are connected in parallel, and a clock signal is supplied to the gate of the NMOS transistor. However, a switch circuit for supplying a signal obtained by inverting the clock signal to the gate of the MOSFET transistor has been proposed (for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2005-191657

A bulk (board) type CMOS device generally requires a substrate potential, and in the case of a P-type substrate, the substrate potential is fixed to a GND (ground) potential. Therefore, the range of input / output signal voltages is limited between the power supply voltage VDD level and the GND level. This also applies to high-frequency switches for radio, and switches using NMOS transistors are used with a DC bias. Therefore, for example, by setting the DC bias voltage to VDD / 2, the input / output signal voltage is dynamic. It is necessary to secure a range. At this time, since the substrate voltage of the MOSFET transistor is usually GND, there is a problem that the threshold voltage Vth rises due to the back bias effect and the loss characteristic of the switch deteriorates. In order to improve the loss characteristics of the switch, a method of raising the gate voltage by using a booster circuit can be considered, but in that case, there are problems such as the influence of noise due to the clock, the current consumption and the increase in the circuit scale.

Further, in a DPDT type switch circuit used for antenna diversity for high frequency, it is particularly required that each of a plurality of switches constituting the circuit has a small loss characteristic over a wide band regardless of transmission / reception power. Therefore, it is difficult to configure such a high-frequency switch circuit as a switch circuit built in a bulk CMOS device as in the above-mentioned conventional technology, and it is often realized as a system using a high-performance dedicated IC separately. .. Therefore, there is a problem that external parts are required and the scale and cost of the entire system are increased.

The switch device according to the present invention includes a first well made of a first conductive substrate and a second well of a second conductive type opposite to the first conductive type provided in the first well. , The first conductive type third well provided in the second well and the third well provided in the third well, turned on or off according to the control signal applied to the gate, and between the source and the drain. It is composed of a switching transistor that transmits or cuts a signal, a power supply terminal that receives a power supply voltage, and a resistance portion connected between the power supply terminal and the second well, and the resistance portion and the second well. A voltage applying means for applying the power supply voltage to the back gate of the switching transistor via the contact region of the third well, and a voltage applying means provided in the third well, which is turned on or off according to the control signal. A first substrate potential control transistor for connecting or disconnecting the back gate of the switching transistor and the source or drain of the switching transistor is provided.

Further, the switch circuit according to the present invention has a first well made of a first conductive type substrate and a second conductive type second well which is opposite to the first conductive type and is provided in the first well. It is formed on the surface of the third well in the region of the triple well structure having the well and the first conductive type third well provided in the second well, and responds to a control signal applied to the gate. It is formed in a contact region between a switching transistor that turns on or off and transmits or cuts a signal between a source and a drain, a power supply terminal that receives a power supply voltage, and the second well and the third well. A parasitic diode whose anode is connected to the back gate of the switching transistor, a resistance portion connected between the power supply terminal and the cathode of the parasitic diode, and a source and drain of the back gate and source or drain of the switching transistor. A first substrate potential control transistor, which is connected between the two and receives the control signal applied to the gate, is provided.

According to the present invention, it is possible to provide a switch device and a switch circuit having good loss characteristics and a reduced device scale.

It is a block diagram which shows the structure of a high frequency switch 100. It is a figure which shows the structure of the switch circuit 10 of Example 1. FIG. It is a figure which shows the device structure of a switch circuit 10. It is a figure which shows the structure of the node part 11 of a switch circuit 10. It is a figure which shows the frequency characteristic of Gain by comparing the case where a resistor is inserted between a power source and a pseudo diode, and the case where a resistor is not inserted. It is a figure which shows the frequency characteristic of a Gain when a resistor is inserted between a power source and a pseudo diode. It is a figure which shows the structure of the switch circuit 20 of Example 2. It is a figure which shows the device structure of the switch circuit 20. It is a figure which shows the structure of the node part 21 of a switch circuit 20. It is a figure which shows the frequency characteristic of a Gain when a transistor is inserted between a power source and a pseudo diode.

Hereinafter, examples of the present invention will be described with reference to the drawings. In the description and the accompanying drawings in each of the following examples, substantially the same or equivalent parts are designated by the same reference numerals.

FIG. 1 is a block diagram showing a configuration of a high frequency switch 100 including the switch circuit of the present invention. In the high frequency switch 100, high frequency signals are input and output from ports PT1 to PT4 by turning on or off the switches SW1 to SW4. The switch circuit of the present invention corresponds to, for example, the switch SW1.

FIG. 2 is a circuit diagram showing the configuration of the switch circuit 10 according to the first embodiment of the present invention. The switch circuit 10 is built in a bulk (board) type CMOS device and has properties as a switch device. The switch circuit 10 includes transistors NM1, NM2, and NM3, which are N-channel type MOS transistors (NMOS transistors).

The transistor NM1 is a switching transistor that functions as a main switch for turning on or off (transmission or cutoff) the input / output of an RF (Radio Frequency) signal. The source of the transistor NM1 is connected to the port PT1 which is an input port for RF signals. Similarly, the drain of the transistor NM1 is connected to port PT2, which is an input port for RF signals. The gate of the transistor NM1 is connected to the gate of the transistor NM2 and is also connected to the node n2 to which the first control voltage Vcont is applied. The first control voltage Vcont is a control voltage that controls the on or off of the transistors NM1 and NM2, and has a high level (hereinafter, H level) or a low level (hereinafter, L level) voltage level. For example, the H level corresponds to the voltage level of the VDD power supply (power supply voltage VDD), and the L level corresponds to the voltage level of the ground potential GND.

The transistor NM2 is a transistor having a function as a back bias control switch for controlling the voltage of the back gate of the transistor NM1. The source and backgate of transistor NM2 are connected to the backgate of transistor NM1 and the drain of transistor NM3. The drain of the transistor NM2 is connected to the port PT1 and the gate is connected to the node n2.

The transistor NM3 is a transistor having a function as a switch for fixing the back gates of the transistors NM1 and NM2 to GND (ground potential). The source of the transistor NM3 is connected to the GND, and the gate is connected to the node n3 to which the second control voltage Vcont_b is applied. The second control voltage Vcont_b is a voltage obtained by inverting the first control voltage Vcont, and is a control voltage that controls turning on or off of the transistor NM3.

FIG. 3 is a schematic view showing a cross section of a device structure (that is, a switch device) of the switch circuit 10 including each transistor. The switch circuit 10 is a P-type substrate PS, which is the first well of the P-type (first conductive type), and an N-type (second conductive type opposite to the first conductive type) provided in the first well. It has a triple-well structure including an N-type well NW which is the second well of the above and a P-type well PW which is a P-type (first conductive type) third well provided in the second well.

The transistors NM1 and NM2 are formed in a P-type well PW which is a third well of a triple well structure. The transistor NM3 is formed on the outer P-type substrate PS of the triple well structure.

A parasitic diode is formed in the contact region between the N-type well NW which is the second well and the P-type well PW which is the third well. Hereinafter, the parasitic diode formed in the contact region between the N-type well NW and the P-type well PW will be referred to as a pseudo diode D1. When a voltage is applied to the pseudo diode D1 in the direction from the N-type well NW to the P-type well PW (that is, in the opposite direction), a depletion layer is formed in the contact region and has a junction capacitance (pseudo-capacitor). State).

Referring again to FIG. 2, the first bias voltage source VB1 is a bias supply source that supplies the bias voltage to the transistor NM1 and is connected to the source of the transistor NM1 and the port PT1 via the resistor R3. Further, the first bias voltage source VB1 is connected to the drain of the transistor NM1 and the port PT2 via the resistor R2.

The anode of the pseudo-diode D1 is connected to the back gate of transistor NM1, the source and back gate of transistor NM2, and the drain of transistor NM3.

The resistor R1 is a resistance element having one end connected to the cathode of the pseudo diode D1 and the other end connected to a VDD power supply (power supply voltage VDD). That is, in the switch circuit 10 of this embodiment, the resistor R1 is inserted between the VDD power supply and the pseudo diode D1.

Next, the operation of the switch circuit 10 of this embodiment will be described.

First, when the L-level first control voltage Vcont is applied to the node n2 and the H-level second control voltage Vcont_b is applied to the node n3, the transistors NM1 and NM2 are turned off and the transistors NM3 are turned on. .. At this time, since the node n1 is fixed to the GND by the transistor NM3, the switch circuit 10 is in the off state as a whole, and the ports PT1 and PT2 are in the isolation state.

Next, when the H-level first control voltage Vcont is applied to the node n2 and the L-level second control voltage Vcont_b is applied to the node n3, the transistors NM1 and NM2 are turned on and the transistors NM3 are turned off. Become. At this time, the node n1 is fixed to the source potential of the transistor NM1 by the transistor NM2. Therefore, since the transistor NM1 is not affected by the back bias effect, the threshold voltage Vth of the transistor NM1 does not increase, and the loss between the ports PT1 and PT2 does not deteriorate in the low frequency region.

On the other hand, when a reverse voltage is applied to the pseudo diode D1, a pseudo capacitor is added to the node n1. This pseudo capacitor can be a factor that deteriorates the loss characteristics. That is, unlike the switch circuit 10 of this embodiment, if the resistor R1 is not provided between the VDD power supply and the pseudo diode D1, the frequency characteristics of the node n1 deteriorate and the source node or drain of the transistor NM1 is deteriorated. The back gates of the transistors NM1 and NM2 cannot follow the high frequency signal of the node.

However, in the switch circuit 10 of this embodiment, since the resistor R1 is inserted between the VDD power supply and the pseudo diode D1, it is possible to suppress the deterioration of the loss characteristics even in the high frequency region for the following reasons. ..

FIG. 4 is a simplified diagram showing a portion surrounded by a broken line in FIG. 1 (a portion along the node n1, hereinafter referred to as a node portion 11). The resistor R_m2on indicates the on-resistance when the transistor NM2 is in the on-state. Further, the pseudo-capacitor C1 shows the parasitic capacitance of the pseudo-diode D1 when a VDD voltage is applied.

In the node portion 11 of FIG. 4, when the resistor R1 is not inserted and the pseudo capacitor C1 is directly connected to the VDD power supply, the frequency characteristic of the node n1 is expressed by the following equation (1). Here, fc is the cutoff frequency.
fc = 1 / (2 * π * R_m2on * C1) ・ ・ ・ (1)

FIG. 5 is a graph schematically showing a comparison of the frequency characteristics of the gain (Gain) when the resistor R1 is inserted and when it is not inserted. When the resistor R1 is not inserted, the gain decreases with a slope of -20 dB / dec on the higher frequency side than the cutoff frequency fc.

On the other hand, as shown in FIG. 4, when the resistor R1 is inserted between the pseudo capacitor C1 and the VDD power supply, the frequency characteristics of the node n1 are shown by the following equations (2) to (4).
f1 = 1 / (2 * π * (R1 + R_m2on) * C1) ・ ・ ・ (2)
f2 = 1 / (2 * π * R1 * C1) ・ ・ ・ (3)
G2 = R_m2on / (R1 + R_m2on) ・ ・ ・ (4)

FIG. 6 is a graph schematically showing the frequency characteristics of Gain when the resistor R1 is inserted. Here, f1 is a high-frequency cutoff frequency. In the high frequency region, Gain decreases, but the amount of attenuation is limited at a predetermined frequency f2. G2 indicates Gain after the amount of attenuation is limited.

As shown in FIG. 5, when the resistor R1 is not inserted, the Gain continues to attenuate with a slope of −20 dB / dec after the cutoff frequency fc, but when the resistor R1 is inserted, it is predetermined. With the frequency f2 as the boundary, Gain remains in G2 of the equation (4) (that is, R_m2on / (R1 + R_m2on)). As a result, when the switch circuit 10 of this embodiment is used in the high frequency region, the decrease in Gain in the used band BW is suppressed.

That is, in the switch circuit 10 of this embodiment, the resistor R1 inserted between the VDD power supply and the pseudo diode D1 hinders the function of the pseudo diode D1 as a capacitor, and the potential of the node n1 is the level of the input / output signal. It becomes a variable (responsive) state according to. As a result, the high frequency characteristic of the node n1 does not deteriorate, and the potential of the node n1 can follow the high frequency signal of the source node or the drain node of the transistor NM1. Therefore, it is possible to suppress an increase in the threshold voltage Vth of the transistor NM1 due to the back bias effect, improve the deterioration of the loss characteristic between the ports PT1 and PT2 in the high frequency region, and obtain a good loss characteristic.

As described above, in the switch circuit 10 of the present embodiment, in addition to controlling the back bias of the transistor NM1, the power supply voltage VDD is supplied to the back gates of the transistors NM1 and NM2, that is, the N-type well NW in the triple well structure. The power supply voltage is supplied to the power supply through the resistor R1. This makes it possible to improve the characteristics of the node n1 in the high frequency region and to follow the operation of the source node or the drain node of the transistor NM1. As a result, it is possible to suppress an increase in the threshold voltage Vth of the transistor NM1 due to the back bias effect, improve the deterioration of the loss characteristics between the ports PT1 and PT2 in the high frequency region, and obtain good loss characteristics.

Further, since the switch circuit 10 of this embodiment is built in the bulk type CMOS device, the scale of the device can be reduced as compared with the case of configuring as a system using a dedicated IC separately or the case of using a booster circuit. It will be possible.

FIG. 7 is a circuit diagram showing the configuration of the switch circuit 20 according to the second embodiment of the present invention. In the switch circuit 20, a transistor PM4 is inserted instead of the resistor R1 between the pseudo diode D1 and the VDD power supply, and a second bias voltage source VB2 that applies a bias voltage to the gate of the transistor PM4 is connected. It is different from the switch circuit 10 of the first embodiment.

The transistor PM4 is a P-channel type MOS transistor (MOSFET transistor), and its source is connected to a VDD power supply. The gate of the transistor PM4 is connected to the positive electrode terminal of the second bias voltage source VB2, which is a voltage source having a variable voltage value. The negative electrode terminal of the second bias voltage source VB2 is connected to the GND. The transistor PM4 is turned on by applying a bias voltage to the gate, and functions as a resistor connected between the VDD power supply and the pseudo diode D1 by its on resistance.

FIG. 8 is a schematic view showing a cross section of a device structure (that is, a switch device) of the switch circuit 20 including each transistor. Similar to the switch circuit 10 of the first embodiment, the switch circuit 20 is provided in the P-type substrate PS which is the first well, the N-type well NW which is the second well provided in the first well, and the second well. It has a triple-well structure composed of a P-type well PW which is a third well.

The transistors NM1 and NM2 are formed in a P-type well PW which is a third well of a triple well structure. The transistor NM3 is formed on the outer P-type substrate PS of the triple well structure.

The transistor PM4 is formed in an N-type well NW2 which is a fourth well provided at a position separated from the second well and the third well in the first well.

Similar to the first embodiment, a parasitic diode is formed in the contact region between the N-type well NW which is the second well and the P-type well PW which is the third well, and the contact region functions as a pseudo diode D1. That is, when a voltage is applied in the direction (reverse direction) from the N-type well NW to the P-type well PW, a depletion layer is formed, resulting in a pseudo-capacitor state having a junction capacitance.

Referring again to FIG. 7, the drain of the transistor PM4 is connected to the cathode of the pseudodiode D1.

Next, the operation of the switch circuit 20 of this embodiment will be described.

First, when the L-level first control voltage Vcont is applied to the node n2 and the H-level second control voltage Vcont_b is applied to the node n3, the transistors NM1 and NM2 are turned off and the transistors NM3 are turned on. .. At this time, since the node n1 is fixed to the GND by the transistor NM3, the switch circuit 20 is in the off state as a whole, and the ports PT1 and PT2 are in the isolation state.

Next, when the H-level first control voltage Vcont is applied to the node n2 and the L-level second control voltage Vcont_b is applied to the node n3, the transistors NM1 and NM2 are turned on and the transistors NM3 are turned off. Become. At this time, the node n1 is fixed to the source potential of the transistor NM1 by the transistor NM2. Therefore, since the transistor NM1 is not affected by the back bias effect, the threshold voltage Vth of the transistor NM1 does not increase, and the loss between the ports PT1 and PT2 does not deteriorate in the low frequency region.

On the other hand, when a reverse voltage is applied to the pseudo diode D1, a pseudo capacitor is added to the node n1. This pseudo capacitor can be a factor that deteriorates the loss characteristics. That is, unlike the switch circuit 20 of this embodiment, if the transistor PM4 is not provided between the VDD power supply and the pseudo diode D1, the frequency characteristics of the node n1 deteriorate and the source node or drain of the transistor NM1 is deteriorated. The back gates of the transistors NM1 and NM2 cannot follow the high frequency signal of the node.

However, in the switch circuit 20 of this embodiment, since the transistor PM4 is inserted between the VDD power supply and the pseudo diode D1, it is possible to suppress the deterioration of the loss characteristics even in the high frequency region for the following reasons. ..

FIG. 9 is a simplified diagram showing a portion surrounded by a broken line in FIG. 7 (a portion along the node n1, hereinafter referred to as a node portion 21). The resistor R_m2on indicates the on-resistance when the transistor NM2 is in the on-state. Further, the pseudo-capacitor C1 shows the parasitic capacitance of the pseudo-diode D1 when a VDD voltage is applied.

In the node section 21 of FIG. 9, when the transistor PM4 is not inserted and the pseudo capacitor C1 is directly connected to the VDD power supply, the frequency characteristic of the node n1 is shown by the following equation (5). Here, fc is the cutoff frequency.
fc = 1 / (2 * π * R_m2on * C1) ・ ・ ・ (5)

When the transistor PM4 is not inserted, the gain decreases with a slope of −20 dB / dec on the higher frequency side than the cutoff frequency fc.

On the other hand, as shown in FIG. 9, when the transistor PM4 is inserted between the pseudo capacitor C1 and the VDD power supply, if the on resistance of the transistor PM4 in the on state is the resistor R_m4on, the frequency characteristic of the node n1 is determined. It is expressed as the following equations (6) to (8).
f1 = 1 / (2 * π * (R_m4on + R_m2on) * C1) ・ ・ ・ (6)
f2 = 1 / (2 * π * R_m4on * C1) ・ ・ ・ (7)
G2 = R_m2on / (R_m4on + R_m2on) ・ ・ ・ (8)

FIG. 10 is a graph schematically showing the frequency characteristics of Gain when the transistor PM4 is inserted. Here, f1 is a high-frequency cutoff frequency. In the high frequency region, Gain decreases, but the amount of attenuation is limited at a predetermined frequency f2. G2 indicates Gain after the amount of attenuation is limited.

When the transistor PM4 is not inserted, the Gain continues to be attenuated with a gradient of -20 dB / dec after the cutoff frequency fc, but when the transistor PM4 is inserted, it is determined by the on-resistance of the transistor PM4. With the frequency f2 as the boundary, Gain remains in G2 of the equation (8) (that is, R_m2on / (R_m4on + R_m2on)).

That is, in the switch circuit 20 of this embodiment, the on-resistance of the transistor PM4 inserted between the VDD power supply and the pseudo diode D1 hinders the function of the pseudo diode D1 as a capacitor, and the potential of the node n1 is input and output. It becomes a variable (responsive) state according to the signal level. As a result, the high frequency characteristic of the node n1 does not deteriorate, and the potential of the node n1 can follow the high frequency signal of the source node or the drain node of the transistor NM1. Therefore, it is possible to suppress an increase in the threshold voltage Vth of the transistor NM1 due to the back bias effect, improve the deterioration of the loss characteristic between the ports PT1 and PT2 in the high frequency region, and obtain a good loss characteristic.

Further, since the second bias voltage source VB2 is a voltage source having a variable voltage value, it is possible to change the on-resistance of the transistor PM4 by changing the gate voltage of the transistor PM4. Therefore, the high cutoff frequency in the equation (6) can be adjusted to an appropriate value.

As described above, in the switch circuit 20 of the present embodiment, in addition to controlling the back bias of the transistor NM1, the power supply voltage VDD is supplied to the back gates of the transistors NM1 and NM2, that is, the N-type well NW in the triple well structure. The power supply voltage is supplied to the power supply through the transistor PM4. This makes it possible to improve the characteristics of the node n1 in the high frequency region and to follow the operation of the source node or the drain node of the transistor NM1.

Further, in the switch circuit 20 of the present embodiment, the on-resistance of the transistor PM4 can be changed by changing the gate voltage of the transistor PM4, and the high-frequency cutoff frequency can be adjusted to an appropriate value. Therefore, by adjusting the cutoff frequency corresponding to the frequency of each input signal, the increase in the threshold voltage Vth of the transistor NM1 due to the back bias effect is suppressed, and the loss characteristic between the ports PT1 and PT2 in the high frequency region deteriorates. Can be improved to obtain good loss characteristics.

Further, since the switch circuit 20 of this embodiment is built in the bulk type CMOS device, the scale of the device can be reduced as compared with the case of configuring as a system using a dedicated IC separately or the case of using a booster circuit. It will be possible.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the example in which the NMOS transistor is used as the transistor of the main switch has been described, but the MOSFET transistor may be used as the transistor of the main switch. It is also possible to use a transfer gate of an NMOS transistor and a MOSFET transistor.

Further, in the above embodiment, the configuration in which the first bias voltage source VB1 is connected to the source and drain of the transistor NM1 and the port PT1 and the port PT2 via the resistors R2 and R3 has been described. An inductor may be used.

Further, in the first embodiment, the configuration in which the resistor R1 is inserted between the N-type well NW and the VDD power supply has been described, but unlike this, for example, a filter or resonance targeting only the frequency band of the input / output signal is used. It is also possible to insert a circuit.

Further, in the above embodiment, an example in which the source of the transistor NM1 is connected to the port PT1 and the drain is connected to the port PT2 has been described. However, on the contrary, the drain of the transistor NM1 may be connected to the port PT1 and the source may be connected to the port PT2.

10,20 Switch circuit 11,21 Node part D1 Pseudo diode NM1, PM4 Transistor R1 to R3 Resistor VB1, VB2 Bias voltage source PT1 to 4 Port SW1 to 4 Switch

Claims (10)

The first well made of the first conductive type substrate and
The second well of the second conductive type, which is the opposite conductive type to the first conductive type, provided in the first well,
With the first conductive type third well provided in the second well,
A switching transistor provided in the third well, which is turned on or off according to a control signal applied to the gate, and transmits or cuts a signal between the source and the drain.
It is composed of a power supply terminal to which a power supply voltage is applied, a resistance portion connected between the power supply terminal and the second well, and via a contact region between the resistance portion and the second well and the third well. A voltage applying means for applying the power supply voltage to the back gate of the switching transistor, and
A first substrate potential control transistor provided in the third well, which is turned on or off according to the control signal to connect or cut off the back gate of the switching transistor and the source or drain of the switching transistor. When,
A switch device characterized by being equipped with. The first well made of the first conductive type substrate and
The second well of the second conductive type, which is the opposite conductive type to the first conductive type, provided in the first well,
With the first conductive type third well provided in the second well,
A switching transistor provided in the third well, which is turned on or off according to a control signal applied to the gate, and transmits or cuts a signal between the source and the drain.
It is composed of a power supply terminal to which a power supply voltage is applied, a resistance portion connected between the power supply terminal and the second well, and via a contact region between the resistance portion and the second well and the third well. A voltage applying means for applying the power supply voltage to the back gate of the switching transistor, and
A second well provided in the first well, which is turned on or off by receiving an inverting signal obtained by inverting the control signal to the gate, and connects or cuts off between the back gate of the switching transistor and the ground potential. Substrate potential control transistor and
The switch device according to claim 1, wherein the switch device comprises. The switch device according to claim 1 or 2, wherein the resistance portion includes a resistance element having one end connected to the power supply terminal and the other end connected to the second well. The first well made of the first conductive type substrate and
The second well of the second conductive type, which is the opposite conductive type to the first conductive type, provided in the first well,
With the first conductive type third well provided in the second well,
A switching transistor provided in the third well, which is turned on or off according to a control signal applied to the gate, and transmits or cuts a signal between the source and the drain.
It is composed of a power supply terminal to which a power supply voltage is applied, a resistance portion connected between the power supply terminal and the second well, and via a contact region between the resistance portion and the second well and the third well. A voltage applying means for applying the power supply voltage to the back gate of the switching transistor, and
The second well in the first well and the second conductive type fourth well provided at a position separated from the third well.
With
The resistance portion is provided in the fourth well and is turned on or off according to the bias voltage applied to the gate, and is a connection between the power supply terminal and the contact regions of the second well and the third well. or wherein the to Luz switch device that a resistor transistor for blocking. A bias voltage supply unit for applying the bias voltage to the gate of the resistance transistor is provided.
The switch device according to claim 4 , wherein the bias voltage supply unit is configured so that the voltage value of the bias voltage can be changed. A first well made of a first conductive type substrate, a second well of a second conductive type opposite to the first conductive type provided in the first well, and a second well of a second conductive type provided in the second well. It is formed on the surface of the third well in the region of the triple well structure having the first conductive type third well, and is turned on or off depending on the control signal applied to the gate, and is between the source and the drain. A switching transistor that transmits or cuts off the signal of
The power supply terminal that receives the power supply voltage and
A parasitic diode formed in the contact region between the second well and the third well and having an anode connected to the back gate of the switching transistor.
A resistor connected between the power supply terminal and the cathode of the parasitic diode,
A first substrate potential control transistor in which the source and drain are connected between the back gate of the switching transistor and the source or drain and the control signal is applied to the gate.
A switch circuit characterized by being provided with. A first well made of a first conductive type substrate, a second well of a second conductive type opposite to the first conductive type provided in the first well, and a second well of a second conductive type provided in the second well. It is formed on the surface of the third well in the region of the triple well structure having the first conductive type third well, and is turned on or off depending on the control signal applied to the gate, and is between the source and the drain. A switching transistor that transmits or cuts off the signal of
The power supply terminal that receives the power supply voltage and
A parasitic diode formed in the contact region between the second well and the third well and having an anode connected to the back gate of the switching transistor.
A resistor connected between the power supply terminal and the cathode of the parasitic diode,
A second substrate potential control transistor in which a source and a drain are connected between the back gate and the ground potential of the switching transistor and receive an inverting signal obtained by inverting the control signal at the gate.
A switch circuit characterized by being provided with. The switch circuit according to claim 6 or 7, wherein the resistance portion includes a resistance element having one end connected to the power supply terminal and the other end connected to the cathode of the parasitic diode. The resistance portion according to claim 6 or 7 , wherein the source and drain are connected between the power supply terminal and the cathode of the parasitic diode, and the resistance portion comprises a resistance transistor to which a bias voltage is applied to the gate. Switch circuit. A bias voltage supply unit for applying the bias voltage to the gate of the resistance transistor is provided.
The switch circuit according to claim 9 , wherein the bias voltage supply unit is configured so that the voltage value of the bias voltage can be changed.

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