JP6841202B2 - Semiconductor wafer evaluation method and semiconductor wafer manufacturing method - Google Patents

Description

The present invention relates to a method for evaluating a semiconductor wafer and a method for manufacturing a semiconductor wafer.

In recent years, with respect to a semiconductor wafer, the cross-sectional shape of the wafer including the outer peripheral edge of the wafer has been evaluated (see, for example, Patent Document 1).

Special Table 2017-503164

In Patent Document 1, the coordinate sequence of the surface contour is obtained from the cross-sectional image of the wafer, and this is expressed as a curve in a mathematical coordinate system, so that the curve is mathematically processed and the shape analysis data regarding the shape of the wafer is numerically obtained. It has been proposed to express it in a modified manner (see paragraph 0032 of Patent Document 1).

By the way, a semiconductor wafer is generally manufactured by subjecting a wafer cut out from an ingot to various processes. Since the outer peripheral edge of the wafer cut out from the ingot has corners as it is, cracks and chips are likely to occur. Therefore, it is usual practice to chamfer the outer peripheral edge of the wafer to form a chamfered surface.

By acquiring a cross-sectional image of a semiconductor wafer on which a chamfered surface is formed, in the cross-sectional image, the surface (front surface) that becomes the device forming surface of the semiconductor wafer or the surface opposite to the front surface (back surface). ) And the chamfered surface can be observed. In the following, the "front surface" of a semiconductor wafer means either or both of the front surface and the back surface, unless otherwise specified. The shape of the boundary between the wafer surface and the chamfered surface can be used as an index for predicting the susceptibility to chipping and scratches in the manufacturing process of the semiconductor device. For example, in the manufacturing process of a semiconductor device, by appropriately setting the shape of the boundary portion between the wafer surface (for example, the back surface) and the chamfered surface according to the shape of the wafer support that supports the wafer during heat treatment, the boundary portion due to contact is formed. Since chipping and scratches are less likely to occur, it is possible to reduce the occurrence rate of dislocations (slip) and dust generation caused by chipping and scratches. However, in the method described in Patent Document 1, since the process for quantifying the shape of the wafer is complicated, it is desirable that the shape of the boundary portion between the wafer surface and the chamfered surface can be evaluated by a simpler evaluation method.

Therefore, an object of the present invention is to provide a new method for easily evaluating the shape of the boundary portion between the wafer surface and the chamfered surface of the semiconductor wafer.

One aspect of the present invention is
This is an evaluation method for semiconductor wafers.
Obtaining a cross-sectional image of the semiconductor wafer to be evaluated,
The cross-sectional image includes a chamfered surface of the outer peripheral edge of the wafer and a boundary portion between the chamfered surface and an adjacent wafer surface.
Creating an enlarged image of the obtained cross-sectional image enlarged only in the wafer thickness direction,
To evaluate the shape of the boundary in the created magnified image,
Evaluation method of semiconductor wafer including (hereinafter, also referred to as "evaluation method"),
Regarding.

In one aspect, the cross-sectional image can be a cross-sectional image taken on a cleavage plane where the semiconductor wafer to be evaluated is cleaved and exposed.

In one aspect, the enlarged image can be an enlarged image created by enlarging the acquired cross-sectional image only in the wafer thickness direction at a magnification of 4 times or more.

In one aspect, the magnification can be 4 times or more and 15 times or less.

In one aspect, the magnified image used for the evaluation can be an image that has been binarized after the magnifying.

In one aspect, the evaluation can be performed using the size of the circle created by fitting the circle to the shape of the boundary portion in the enlarged image as an index.

In one aspect, the evaluation of the boundary portion of the semiconductor wafer to be evaluated can be performed by comparing the created magnified image with the magnified image to be compared. This magnified image of the comparison target acquires a cross-sectional image including the chamfered surface of the outer peripheral edge of the wafer of the semiconductor wafer to be compared and the boundary portion between the chamfered surface and the adjacent wafer surface, and obtains the acquired cross-sectional image of the wafer. It is possible to obtain a magnified image created by enlarging at the same magnifying magnification as the magnified image of the semiconductor wafer to be evaluated only in the thickness direction.

A further aspect of the present invention is
Manufacture semiconductor wafer lots containing multiple semiconductor wafers,
Extracting at least one semiconductor wafer from the semiconductor wafer lot,
Evaluating the extracted semiconductor wafer by the above evaluation method, and preparing to ship a semiconductor wafer of the same semiconductor wafer lot as the semiconductor wafer judged as a non-defective product as a product semiconductor wafer as a result of the above evaluation.
(Hereinafter, also referred to as "first manufacturing method"), a method for manufacturing a semiconductor wafer including
Regarding.

A further aspect of the present invention is
Manufacture of evaluation semiconductor wafers under test manufacturing conditions,
To evaluate the manufactured evaluation semiconductor wafer by the above evaluation method,
Based on the result of the above evaluation, the manufacturing condition obtained by modifying the test manufacturing condition is determined as the actual manufacturing condition, or the test manufacturing condition is determined as the actual manufacturing condition.
Manufacturing semiconductor wafers under the above-determined actual manufacturing conditions,
(Hereinafter, also referred to as "second manufacturing method"), a method for manufacturing a semiconductor wafer including
Regarding.

In one aspect, the manufacturing conditions to which the above modifications are made can be at least one of a semiconductor wafer surface polishing condition and a chamfering condition.

According to one aspect of the present invention, it is possible to provide an evaluation method capable of easily evaluating the shape of the boundary portion between the chamfered surface of the semiconductor wafer and the wafer surface.

It is a cross-sectional image (without binarization processing) including a boundary portion between a wafer surface and a chamfered surface of two semiconductor wafers. It is a binarized image obtained by binarizing the cross-sectional image shown in FIG. 1. This is an enlarged image (binarized) obtained by doubling the cross-sectional image shown in FIG. 1 only in the wafer thickness direction. This is an enlarged image (binarized) obtained by enlarging the cross-sectional image shown in FIG. 1 three times only in the wafer thickness direction. This is a magnified image (binarized) obtained by enlarging the cross-sectional image shown in FIG. 1 four times only in the wafer thickness direction. This is an enlarged image (binarized) obtained by magnifying the cross-sectional image shown in FIG. 1 by 5 times only in the wafer thickness direction. This is an enlarged image (binarized) obtained by enlarging the cross-sectional image shown in FIG. 1 by 10 times only in the wafer thickness direction. This is an enlarged image (binarized) obtained by magnifying the cross-sectional image shown in FIG. 1 by 15 times only in the wafer thickness direction. This is an enlarged image (binarized) obtained by enlarging the cross-sectional image shown in FIG. 1 by 20 times only in the wafer thickness direction. This is an enlarged image (binarized) obtained by enlarging the cross-sectional image shown in FIG. 1 30 times only in the wafer thickness direction. 2 is a graph showing the relationship between the ratio value shown on the far right of FIGS. 2 to 10 and the magnification in the wafer thickness direction.

[Evaluation method for semiconductor wafers]
One aspect of the present invention is a method for evaluating a semiconductor wafer, in which a cross-sectional image of a semiconductor wafer to be evaluated is acquired, and the cross-sectional image is a chamfered surface of an outer peripheral edge of the wafer and a wafer adjacent to the chamfered surface. A semiconductor including a boundary portion with a surface, creating an enlarged image obtained by enlarging the acquired cross-sectional image only in the wafer thickness direction, and evaluating the shape of the boundary portion in the created enlarged image. Regarding the evaluation method of the wafer.

In the above evaluation method, the shape of the boundary portion is evaluated by using an enlarged image obtained by enlarging the cross-sectional image including the boundary portion between the chamfered surface and the wafer surface of the semiconductor wafer only in the wafer thickness direction. By enlarging the cross-sectional image only in the wafer thickness direction, it is possible to emphasize the difference in the shape of the boundary portion of the semiconductor wafer with respect to the wafer surface (so-called horizontal plane) in the contour of the cross-sectional shape, so that the boundary portion is gentle. / It is possible to evaluate steepness with high accuracy. Therefore, for example, when comparing the cross-sectional shapes of a plurality of semiconductor wafers with the cross-sectional images acquired at the same magnification in the vertical and horizontal directions, even if there is almost no difference in the boundary portion, the difference in the shape of the boundary portion of the plurality of semiconductor wafers is observed. Can be emphasized, so that even a slight difference in the shape of the boundary portion can be discriminated. Further, according to the above evaluation method, the shape of the boundary portion between the chamfered surface and the wafer surface of the semiconductor wafer is evaluated by a simple image processing in which the cross-sectional image is enlarged only in the wafer thickness direction without going through a complicated process. can do.
Hereinafter, the above evaluation method will be described in more detail.

<Semiconductor wafer to be evaluated>
The semiconductor wafer to be evaluated by the above evaluation method may be a semiconductor wafer in which the outer peripheral edge of the wafer is chamfered to form a chamfered surface. The semiconductor wafer to be evaluated can be various semiconductor wafers generally used as a semiconductor substrate. For example, various silicon wafers can be mentioned as specific examples of semiconductor wafers. The silicon wafer can be, for example, a silicon single crystal wafer that has been cut out from a silicon single crystal ingot and then subjected to various processing such as chamfering. Specific examples of such a silicon single crystal wafer include a polished wafer that has been polished and has a polished surface on its surface. Further, the silicon wafer can be various silicon wafers such as an epitaxial wafer having an epitaxial layer on the silicon single crystal wafer and an annealed wafer in which a modified layer is formed on the silicon single crystal wafer by an annealing treatment.

<Acquisition of cross-sectional image>
In the above evaluation method, a cross-sectional image of the semiconductor wafer to be evaluated is acquired. This cross-sectional image may be acquired so as to include a boundary portion between the chamfered surface and the wafer surface (front surface or back surface) adjacent to the chamfered surface. The outer peripheral edge of the chamfered semiconductor wafer usually has a chamfered surface adjacent to the front surface of the wafer and a chamfered surface adjacent to the back surface of the wafer. The cross-sectional image may include one or both of a boundary between the front surface and the chamfered surface of the wafer and a boundary between the back surface and the chamfered surface of the wafer.

In one aspect, the cross-sectional image can be obtained as a projection image without exposing the cross-section of the semiconductor wafer to be evaluated. The projected image can be obtained by a known projection method. In another aspect, the cross-sectional image can be obtained by exposing the cross-section of the semiconductor wafer to be evaluated and imaging the exposed cross-section. For example, the cross section can be exposed by cleaving the semiconductor wafer to be evaluated or cutting it by a known cutting means. From the viewpoint of ease of cross-section exposure, it is preferable that the cross-section is a cleavage surface in which the semiconductor wafer to be evaluated is cleaved perpendicular to the surface to be exposed. For example, in the case of a silicon single crystal wafer whose surface is the (100) plane, the cleavage plane perpendicular to the surface can be exposed by cleaving at the (110) plane. Various known microscopes such as an optical microscope, a scanning electron microscope (SEM), and a laser microscope can be used for imaging the exposed cross section. As the optical microscope, an optical metallurgical microscope (called an epi-illumination type microscope or the like) can be preferably used. Further, it is more preferable to use a differential interference microscope further provided with a differential interference contrast observation function because the depth of focus becomes shallow and a slight difference in shape appears in the cross-sectional image.

The cross-sectional image may be acquired with the imaging magnification set to 1x (that is, in the actual size), or may be acquired with the imaging magnification set to more than 1x. When magnifying, the imaging magnification can be, for example, 50 to 1000 times, preferably 50 to 500 times. However, the enlargement here is performed at the same magnification in all directions, as is performed by the enlargement function provided in the known microscope. Then, in the above evaluation method, the cross-sectional image thus obtained is enlarged only in the wafer thickness direction (so-called vertical direction) and is not enlarged in the wafer radial direction (so-called horizontal direction) to create an enlarged image. By using the enlarged image enlarged only in the wafer thickness direction in this way, the shape of the boundary portion between the wafer surface and the chamfered surface can be evaluated with high accuracy.

<Creating a magnified image>
The enlarged image obtained by enlarging the cross-sectional image only in the wafer thickness direction can be created by using a known image processing software capable of enlarging the image. The magnification in the wafer thickness direction is more than 1 time, and can be, for example, 2 times or more or 3 times or more. From the viewpoint of more accurately evaluating the shape of the wafer surface and the chamfered surface, the magnification in the wafer thickness direction is preferably 4 times or more, more preferably 5 times or more, and 6 times or more. More preferably, it is more preferably 7 times or more, and even more preferably 8 times or more. Further, the magnification in the wafer thickness direction can be, for example, 30 times or less, 25 times or less or 20 times or less, and 19 times or less, 18 times or less, 17 times or less or 16 times or less. From the viewpoint of more accurately evaluating the shape of the boundary between the wafer surface and the chamfered surface, the value is preferably 15 times or less, more preferably 14 times or less, still more preferably 13 times or less. It is more preferably 12 times or less.

From the viewpoint of more accurately evaluating the shape of the boundary between the wafer surface and the chamfered surface, it is possible to binarize the obtained image before or after enlarging the cross-sectional image only in the wafer thickness direction. It is preferable that the cross-sectional image is enlarged only in the wafer thickness direction, and then the obtained image is binarized. By the binarization process, the outline of the cross-sectional shape can be displayed more clearly, so that the shape of the boundary portion between the wafer surface and the chamfered surface can be evaluated more accurately. As is known, the binarization process is a process of converting an image with shading into two gradations of white and black, and is performed by setting a certain threshold value. When the binarized cross-sectional image is used for evaluation in the above evaluation method, the threshold value in the binarization process may be appropriately set so that the outline of the cross-sectional shape is clearly displayed.

<Evaluation of the shape of the boundary>
In the above evaluation method, the shape of the boundary portion between the wafer surface and the chamfered surface adjacent to the wafer surface is evaluated in the enlarged image enlarged only in the wafer thickness direction as described above. The evaluation of this shape can be performed as a relative evaluation by visually comparing the magnified images obtained for a plurality of different semiconductor wafers, for example. For example, in the created magnified image, it is visually and relatively evaluated whether the shape of the boundary portion is gentler or steeper, and the boundary between the wafer surface and the chamfered surface of the semiconductor wafer to be evaluated is evaluated. The shape of the part can be evaluated. Further, for example, the boundary between the wafer surface and the chamfered surface of the semiconductor wafer to be evaluated is visually compared with the enlarged image of the standard sample having the desired boundary shape and the enlarged image created for the semiconductor wafer to be evaluated. It is also possible to evaluate the shape of the part. In the above evaluation, it is preferable that the plurality of magnified images to be compared are magnified images magnified at the same magnification only in the wafer thickness direction from the viewpoint of evaluation accuracy. That is, it is preferable to evaluate the boundary portion of the semiconductor wafer to be evaluated by comparing the enlarged image created for the wafer to be evaluated with one or more enlarged images to be compared. For this magnified image of the comparison target, a cross-sectional image including the chamfered surface of the outer peripheral edge of the wafer of the semiconductor wafer to be compared and the boundary portion between the chamfered surface and the adjacent wafer surface is acquired, and the acquired cross-sectional image is used as the wafer. It is preferable that the enlarged image is created by enlarging the enlarged image of the semiconductor wafer to be evaluated at the same magnification as the enlarged image only in the thickness direction.

Further, in the enlarged image enlarged only in the wafer thickness direction, the shape of the boundary portion between the wafer surface and the chamfered surface is usually curved in the contour of the wafer cross-sectional shape. Therefore, the shape of the boundary portion can be evaluated based on the circle of curvature of this curve. Specifically, on the contour of the wafer cross-sectional shape of the enlarged image enlarged only in the wafer thickness direction, a circle having an arc shape similar to the shape of this curve is fitted to the shape of the curve at the boundary between the wafer surface and the chamfered surface. Or, the shape of the curve at the boundary between the wafer surface and the chamfer is fitted with a circle having an arc shape that matches the shape of this curve. The fitting of this circle does not necessarily have to be an accurate circle fitting using a fitting formula. For example, in a magnified image magnified only in the wafer thickness direction, an arc having a shape that matches or approximates the shape of the curve at the boundary on the contour of the wafer cross-sectional shape using known software that can manually draw a circle. A circle with can be set. Alternatively, the circle may be fitted using a known fitting formula using image processing software. It can be determined that the larger the size of the circle (curvature circle) thus obtained, for example, the diameter or radius, the smoother the shape of the boundary between the wafer surface and the chamfered surface, and the smaller the size of the circle, the more the wafer. It can be judged that the shape of the boundary portion between the surface and the chamfered surface is steep. Evaluating the shape of the boundary portion using the size of the circle in this way is preferable from the viewpoint of reliability of evaluation because the evaluation can be objectively performed based on numerical values.

As described above, according to the evaluation method according to one aspect of the present invention, the shape of the boundary portion between the wafer surface (front surface or back surface) of the semiconductor wafer and the chamfered surface adjacent to the front surface is formed into a complicated process. It can be easily evaluated without going through. Further, according to the evaluation method according to one aspect of the present invention, it is possible to emphasize the difference in the shape of the boundary portion with respect to the wafer surface in the contour of the cross-sectional shape of the semiconductor wafer to be evaluated, so that the boundary portion is gentle. It is possible to evaluate the sharpness / steepness with high accuracy.

<Manufacturing method of semiconductor wafer>
The method for manufacturing a semiconductor wafer (first manufacturing method) according to one aspect of the present invention is as follows.
Manufacture semiconductor wafer lots containing multiple semiconductor wafers,
Extracting at least one semiconductor wafer from the semiconductor wafer lot,
Evaluating the extracted semiconductor wafer by the above evaluation method, and preparing to ship a semiconductor wafer of the same semiconductor wafer lot as the semiconductor wafer judged as a non-defective product as a product semiconductor wafer as a result of the above evaluation.
Manufacturing method of semiconductor wafer including
Is.

The method for manufacturing a semiconductor wafer (second manufacturing method) according to another aspect of the present invention is as follows.
Manufacture of evaluation semiconductor wafers under test manufacturing conditions,
To evaluate the manufactured evaluation semiconductor wafer by the above evaluation method,
Based on the result of the above evaluation, the manufacturing condition obtained by modifying the test manufacturing condition is determined as the actual manufacturing condition, or the test manufacturing condition is determined as the actual manufacturing condition.
Manufacturing semiconductor wafers under the above-determined actual manufacturing conditions,
Manufacturing method of semiconductor wafer including
Is.

In the first manufacturing method, a semiconductor wafer of the same lot as a semiconductor wafer determined to be a non-defective product as a result of so-called sampling inspection is prepared for shipment as a product semiconductor wafer. On the other hand, in the second manufacturing method, the semiconductor wafer manufactured under the test manufacturing conditions is evaluated, and the actual manufacturing conditions are determined based on the evaluation result. In both the first manufacturing method and the second manufacturing method, the evaluation of the semiconductor wafer is performed by the evaluation method according to one aspect of the present invention described above. Therefore, the evaluation of the semiconductor wafer can be easily performed, and further, it can be performed with high accuracy.

(First manufacturing method)
The semiconductor wafer lot can be manufactured in the first manufacturing method in the same manner as the general semiconductor wafer manufacturing method. For example, a polished wafer, which is one aspect of a silicon wafer, is obtained by cutting (slicing), chamfering, and rough polishing (for example, wrapping) a silicon wafer from a silicon single crystal ingot grown by the Czochralski method (CZ method) or the like. It can be manufactured by a manufacturing process including etching, mirror polishing (finish polishing), and cleaning performed during or after the processing steps. Further, the annealed wafer can be manufactured by subjecting the polished wafer manufactured as described above to an annealing treatment. The epitaxial wafer can be manufactured by vapor-phase growing (epitaxial growth) an epitaxial layer on the surface of the polished wafer manufactured as described above. The total number of semiconductor wafers included in the semiconductor wafer lot is not particularly limited. The number of semiconductor wafers extracted from the manufactured semiconductor wafer lot and subjected to so-called sampling inspection is at least one, and may be two or more, and the number is not particularly limited.

In the semiconductor wafer extracted from the semiconductor wafer lot, the shape of the boundary portion between the wafer surface and the chamfered surface adjacent to the wafer surface is evaluated by the evaluation method according to one aspect of the present invention. The details of the evaluation method are as described above. Then, as a result of the evaluation, a semiconductor wafer having the same semiconductor wafer lot as the semiconductor wafer judged to be a non-defective product is prepared for shipment as a product semiconductor wafer. The criteria for determining a non-defective product may be determined according to the quality required for the product semiconductor wafer. For example, in one aspect, the size of a circle created by fitting a circle to the shape of the boundary between the wafer surface and the chamfered surface as described above is equal to or greater than a certain value (that is, equal to or greater than a threshold value). It can be used as a criterion for judgment. Alternatively, the shape and evaluation of the boundary portion of the standard sample are evaluated by visually comparing the enlarged image of the standard sample having the desired boundary portion shape with the enlarged image created for the semiconductor wafer to be evaluated extracted from the semiconductor wafer lot. It is also possible to visually determine that the shape of the boundary portion of the target semiconductor wafer is similar to that of the target semiconductor wafer, and determine that the product is non-defective. Next, one or more semiconductor wafers in the same lot as the semiconductor wafer determined to be non-defective are prepared for shipment as product semiconductor wafers. Examples of this preparation include packing and the like. In this way, according to the first manufacturing method, it is possible to stably mass-produce a semiconductor wafer in which the shape of the boundary portion between the wafer surface and the chamfered surface is the shape desired for the product semiconductor wafer.

(Second manufacturing method)
Regarding the second manufacturing method, as test manufacturing conditions and actual manufacturing conditions, various conditions in various processes for manufacturing semiconductor wafers can be mentioned. The various steps for manufacturing the semiconductor wafer are as described above for the first manufacturing method. The "actual manufacturing conditions" shall mean the manufacturing conditions of the product semiconductor wafer.

In the second manufacturing method, test manufacturing conditions are set as a preliminary step for determining the actual manufacturing conditions, and the evaluation semiconductor wafer is manufactured under these test manufacturing conditions. In the manufactured semiconductor wafer, the shape of the boundary portion between the wafer surface and the chamfered surface adjacent to the surface is evaluated by the evaluation method according to one aspect of the present invention. The details of the evaluation method are as described above. The number of evaluation semiconductor wafers is at least one, and may be two or more, and the number thereof is not particularly limited. As a result of the evaluation, if the shape of the boundary between the wafer surface and the chamfered surface of the evaluation semiconductor wafer is the shape desired for the product semiconductor wafer, the product semiconductor wafer is manufactured and shipped using this test manufacturing condition as the actual manufacturing condition. By doing so, it is possible to stably mass-produce product semiconductor wafers in which the shape of the wafer surface and the chamfered surface is a desired shape. On the other hand, as a result of the evaluation, if the shape of the boundary between the wafer surface and the chamfered surface of the evaluation semiconductor wafer is different from the shape desired for the product semiconductor wafer, the manufacturing conditions obtained by changing the test manufacturing conditions are actually realized. Determined as manufacturing conditions. The manufacturing conditions to be changed are preferably manufacturing conditions that are considered to affect the shape of the boundary portion between the wafer surface and the chamfered surface. As an example of such manufacturing conditions, polishing conditions for the front surface (front surface and / or back surface) of the semiconductor wafer can be mentioned. Specific examples of such polishing conditions include rough polishing conditions and mirror polishing conditions. More specifically, the type of polishing liquid, the abrasive grain concentration of the polishing liquid, the type of polishing pad (for example, hardness, etc.) and the like can be described. Can be mentioned. Further, as an example of the manufacturing conditions, chamfering conditions can be mentioned, and more specifically, machining conditions such as grinding and polishing in chamfering can be mentioned. More specifically, the type of polishing tape used for chamfering. And so on. By determining the manufacturing conditions obtained by changing the test manufacturing conditions as the actual manufacturing conditions and manufacturing and shipping the product semiconductor wafer under these actual manufacturing conditions, the shape of the wafer surface and the chamfered surface is a desired shape. Product semiconductor wafers can be mass-produced in a stable manner. It should be noted that the evaluation semiconductor wafer is manufactured again under the manufacturing conditions obtained by changing the test manufacturing conditions, the evaluation semiconductor wafer is evaluated by the evaluation method according to one aspect of the present invention, and the manufacturing conditions are referred to as the actual manufacturing conditions. Determining whether to do or make further changes may be repeated once or more than once.
In the above second manufacturing method, regarding the method for determining whether or not the shape of the boundary portion between the wafer surface and the chamfered surface of the evaluation semiconductor wafer is the shape desired for the product semiconductor wafer, the first manufacturing method is performed first. You can refer to the description regarding the judgment of non-defective products in the method.

For other details of the first manufacturing method and the second manufacturing method, known techniques for manufacturing semiconductor wafers can be applied.

Hereinafter, the present invention will be further described based on examples. However, the present invention is not limited to the embodiments shown in the examples.

1. 1. Preparation of semiconductor wafers for evaluation Two types of semiconductor wafers (polished wafers with a diameter of 300 mm and a surface of (100)) with different polishing conditions and chamfering conditions on the wafer surface were prepared. In the following, one semiconductor wafer will be referred to as “sample 1” and the other semiconductor wafer will be referred to as “sample 2”.

2. 2. Preparation of sample for cross-section observation Samples 1 and 2 were cleaved on the (110) plane to prepare a sample for cross-section observation.

3. 3. Acquisition of cross-sectional image 2. Using a differential interference microscope, adjust the brightness and contrast of the cross-sectional observation sample prepared in the above section to include a cross-sectional image including the boundary between the wafer surface (front surface) and the adjacent chamfered surface (imaging magnification: 500 times) was acquired. The acquired cross-sectional image is shown in FIG.

4. Creation of a magnified image 3. The cross-sectional image obtained in 1) was taken into image processing software (software name Photoshop CS5 manufactured by Adobe), enlarged 2 to 30 times only in the wafer thickness direction, and then binarized. The enlarged image after the binarization process is shown in FIGS. 3 to 10. In FIG. 2, the above 3. The cross-sectional image obtained in the above is shown as a binarized image obtained by performing only the binarization treatment in the same manner as above without enlarging.

5. Circle fitting Above 4. Each image created in step 1 is imported into software (PowerPoint manufactured by Microsoft), and using the drawing tool of the software, the shape of the curve and the shape of the arc at the boundary between the wafer surface and the chamfered surface are displayed on the contour of the cross-sectional shape. I drew a circle that almost matched. It was visually judged that the shape of the curve and the shape of the arc were almost the same. 2 to 10 also show a circle or a part of the circle thus drawn. The numbers in the circles in each figure are the diameters of the circles.
Further, in FIGS. 2 to 10, the magnification shown on the far left is an enlargement magnification enlarged only in the wafer thickness direction. For example, since FIG. 3 shows a magnified image magnified at a magnification of 2 times only in the wafer thickness direction, “x2” is shown on the far left of FIG. In FIG. 2, the above 3. Since the binarized image of the cross-sectional image (without enlargement) obtained in FIG. 1 is shown, "x1" is written on the leftmost side of FIG.
On the other hand, in FIGS. 2 to 10, the numerical value shown on the far right is the ratio of the diameter of the circle drawn for sample 2 to the diameter of the circle drawn for sample 1 (of the circle drawn for sample 2). Diameter / diameter of the circle drawn for sample 1).

Even when the cross-sectional image of the sample 1 and the cross-sectional image of the sample 2 shown in FIG. 2 are compared, it is difficult to visually confirm the difference in the shape of the boundary portion between the wafer surface and the chamfered surface. Further, as can be seen from the fact that the ratio value shown on the far right of FIG. 2 is slightly more than 1, the diameter of the circle drawn for sample 1 and the diameter of the circle drawn for sample 2 The difference is also slight.
On the other hand, by comparing the binarized image without enlargement shown in FIG. 2 with the enlarged image shown in FIGS. 3 to 10, the cross-sectional image is enlarged only in the wafer thickness direction. , The difference in the shape of the boundary between the wafer surface and the chamfered surface of the sample 1 and the sample 2 can be emphasized with respect to the wafer surface, and the difference in the shape of the boundary can be easily confirmed visually. Understand.
Further, by enlarging the cross-sectional image only in the wafer thickness direction from the comparison between the ratio value shown on the far right of FIG. 2 and the ratio value shown on the far right of FIGS. 3 to 10. , The difference in the size (diameter) of the circle fitted to the curved shape of the boundary between the wafer surface and the chamfered surface becomes large, and even if the difference in the shape of the boundary is slight, the difference is indexed by the size of the circle. It can be confirmed that it becomes easy to determine as.

Regarding the magnification, if the magnification in the wafer thickness direction is 4 times or more from the comparison of FIGS. 2 to 10, the difference in the shape of the boundary between the wafer surface and the chamfered surface of the wafer 1 and the wafer 2 can be easily visually recognized. You can see that it can be confirmed.
On the other hand, FIG. 11 is a graph showing the relationship between the ratio value shown on the far right of FIGS. 2 to 10 and the magnification in the wafer thickness direction. From the graph of FIG. 11, it can be confirmed that the ratio value monotonously increases when the magnification becomes 4 times or more. Further, from the graph of FIG. 11, it can be confirmed that the degree of increase in the ratio value becomes smaller when the magnification exceeds 15 times. Further, in the enlarged image in which the magnification in the wafer thickness direction is 20 times (FIG. 9) or 30 times (FIG. 10), the unevenness on the wafer surface side is larger than that in the other enlarged images (the wafer surface side of the image is other). Blurred compared to the magnified image). From these facts, from the viewpoint of more accurately obtaining the shape information in the wafer thickness direction, it is considered that the magnification in the wafer thickness direction is preferably 15 times or less.
From the above results, it can be determined that the magnification in the wafer thickness direction is preferably 4 times or more and 15 times or less.

As described above, by using an enlarged image obtained by enlarging the cross-sectional image of the semiconductor wafer to be evaluated only in the wafer thickness direction, the shape of the boundary portion between the wafer surface and the chamfered surface can be easily evaluated, and the shape is slight. It was confirmed that the difference can be evaluated accurately.
The results of such evaluation can be used for sampling inspection from lots as described above, and can also be used for determining the actual manufacturing conditions of semiconductor wafers.

The present invention is useful in the field of manufacturing various semiconductor wafers such as silicon wafers.

Claims (10)

This is an evaluation method for semiconductor wafers.
Obtaining a cross-sectional image of the semiconductor wafer to be evaluated,
The cross-sectional image includes a boundary between a chamfered surface of the outer peripheral edge of the wafer and a wafer surface adjacent to the chamfered surface.
To create an enlarged image obtained by enlarging the acquired cross-sectional image only in the wafer thickness direction.
To evaluate the shape of the boundary portion in the created magnified image.
Evaluation method of semiconductor wafer including. The method for evaluating a semiconductor wafer according to claim 1, wherein the cross-sectional image is a cross-sectional image taken on a cleavage plane exposed by cleaving the semiconductor wafer to be evaluated. The method for evaluating a semiconductor wafer according to claim 1 or 2, wherein the enlarged image is a magnified image created by enlarging the acquired cross-sectional image only in the wafer thickness direction at a magnification of 4 times or more. The method for evaluating a semiconductor wafer according to claim 3, wherein the magnification is 4 times or more and 15 times or less. The method for evaluating a semiconductor wafer according to any one of claims 1 to 4, wherein the enlarged image used for the evaluation is an image that has been binarized after the enlargement. The method for evaluating a semiconductor wafer according to any one of claims 1 to 5, wherein the evaluation is performed using the size of a circle created by fitting a circle to the shape of the boundary portion in the enlarged image as an index. The boundary portion of the semiconductor wafer to be evaluated is evaluated by comparing the created magnified image with the magnified image to be compared.
The magnified image of the comparison target acquires a cross-sectional image including a chamfered surface of the outer peripheral edge of the wafer of the semiconductor wafer to be compared and a boundary portion between the chamfered surface and the surface of the adjacent wafer, and obtains the acquired cross-sectional image of the wafer. The method for evaluating a semiconductor wafer according to any one of claims 1 to 6, which is an enlarged image created by enlarging the enlarged image of the semiconductor wafer to be evaluated at the same magnification as the enlarged image of the semiconductor wafer to be evaluated only in the thickness direction. Manufacture semiconductor wafer lots containing multiple semiconductor wafers,
Extracting at least one semiconductor wafer from the semiconductor wafer lot,
The extracted semiconductor wafer is evaluated by the evaluation method according to any one of claims 1 to 7, and a semiconductor wafer having the same semiconductor wafer lot as the semiconductor wafer determined to be non-defective as a result of the evaluation is produced. To prepare for shipping as a semiconductor wafer,
A method for manufacturing a semiconductor wafer including. Manufacture of evaluation semiconductor wafers under test manufacturing conditions,
To evaluate the manufactured semiconductor wafer for evaluation by the evaluation method according to any one of claims 1 to 7.
Based on the result of the evaluation, the manufacturing conditions obtained by modifying the test manufacturing conditions are determined as the actual manufacturing conditions, or the test manufacturing conditions are determined as the actual manufacturing conditions.
Manufacturing semiconductor wafers under the determined actual manufacturing conditions,
A method for manufacturing a semiconductor wafer including. The method for manufacturing a semiconductor wafer according to claim 9, wherein the manufacturing condition to which the modification is applied is at least one of a polishing treatment condition and a chamfering processing condition for the surface of the semiconductor wafer.