JP6840994B2 - Circuit equipment, electro-optic equipment, electronic devices, mobile objects and error detection methods - Google Patents

Description

The present invention relates to a circuit device, an electro-optical device, an electronic device, a mobile body, an error detection method, and the like.

In display control in a display device (for example, a liquid crystal display device), a processing device such as a CPU transmits image data and a control signal to the display controller, and the display controller performs image processing and timing signal generation, and the image processed image. The display driver operates according to the data and timing signal. For example, the LVDS (Low Voltage Differential Signal) method or the RGB serial method is used for transmitting the image data from the processing device to the display controller, but in any case, an error may occur in the image data due to a communication error or the like. .. For example, Patent Documents 1 to 3 disclose a technique for detecting an error of image data received by a display controller from a processing device by CRC (Cyclic Redundancy Check).

Japanese Unexamined Patent Publication No. 2012-35677 Japanese Unexamined Patent Publication No. 2007-101691 Japanese Unexamined Patent Publication No. 2007-72394

In such error detection, the processing device obtains the expected value information of error detection (for example, the expected value of CRC) from the image data transmitted to the display controller, and the display controller detects the error from the image data received from the processing device. A calculated value (for example, CRC value) is obtained, and the expected value information is compared with the calculated value to detect an error. Therefore, the processing device has a processing load for obtaining the expected value information for error detection. For example, when all the image data of the image of one frame is detected as an error, the amount of data used for calculating the expected value information becomes enormous, and the processing load becomes large. In order to reduce this load, a method of reducing the area where error detection is performed (error detection is performed only in a part of the image) is conceivable, but errors cannot be detected in images other than that area.

According to some aspects of the present invention, it is possible to provide a circuit device, an electro-optical device, an electronic device, a moving body, an error detection method, and the like that can reduce the processing load of the processing device in error detection of image data.

One aspect of the present invention includes an interface unit for receiving image data and an error detection unit for performing error detection, and the interface unit includes error detection including at least display image data and position information of an error detection area. The image data including the data for display is received, and the error detection unit detects the error of the display image data based on the display image data of the error detection area specified by the position information. It is related to the circuit equipment to be performed.

In one aspect of the present invention, both the display image data and the error detection data are received by the interface unit that receives the image data. Further, the error detection data includes the position information of the error detection area. In this way, the error detection data can be received by the same interface as the interface for receiving the display image data. Therefore, the error detection area can be flexibly set for each frame, and the processing load of error detection can be reduced.

Further, in one aspect of the present invention, the error detection data further includes expected value information used in the error detection, and the error detection unit may perform the error detection based on the expected value information. ..

In this way, error detection can be appropriately performed by using the error detection information including the expected value information.

Further, in one aspect of the present invention, the image data includes the second to nth error detection data (n is an integer of 2 or more), and the second to nth error detection data i (i). the error detection data integer) satisfying 2 ≦ i ≦ n may include the position information corresponding to the error detection region of the i.

In this way, it is possible to flexibly set a plurality of error detection areas for one image (one frame image).

Further, in one aspect of the present invention, the error detection unit may perform the error detection based on the error detection data of the i in the error detection region of the i.

In this way, error detection can be performed for each of the plurality of set error detection areas.

Further, in one aspect of the present invention, the error detection unit may perform the error detection of the display image data based on the error detection data added to the front side of the display image data.

By doing so, it becomes possible to include the display image data and the error detection data used for error detection of the display image data in the image data of the same frame, and efficient data communication and error detection can be performed. It will be possible.

Further, in one aspect of the present invention, an error determination information output unit is further included, and the error detection unit calculates an error detection code in a plurality of error detection areas of the image data to perform the error detection, and the error determination is performed. The information output unit may output error determination information in the plurality of error detection areas based on the error detection codes in the plurality of frames.

In this way, since the error determination is performed based on the time-series error detection code, it is possible to perform the error determination flexibly according to the situation.

Further, another aspect of the present invention relates to an electro-optical device including the circuit device according to any one of the above and an electro-optical panel.

Further, another aspect of the present invention relates to an electronic device including the circuit device according to any one of the above.

Further, another aspect of the present invention relates to a mobile body including the circuit device according to any one of the above.

In another aspect of the present invention, the image data including the display image data and the error detection data including at least the position information of the error detection area is received, and the error detection area specified by the position information is received. It relates to an error detection method for detecting an error in the display image data based on the display image data.

Configuration example of a circuit device. Other configuration examples of circuit devices. Other configuration examples of circuit devices. Error detection area setting example. The schematic diagram explaining the image area. Data structure example when error detection data is included in the image data. Detailed configuration example of the error detection unit and error judgment information output unit. Configuration example of the first determination unit. Configuration example of the second determination unit. Configuration example of the third determination unit. Other configuration examples of error detection section and register section. Timing chart of error detection processing. Error detection area setting example. Error detection area setting example. Error detection area setting example. Other configuration examples of the register section. Configuration example of an electro-optical device. Configuration example of electronic equipment. Configuration example of a moving body.

Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as a means for solving the present invention. Not necessarily.

1. 1. Circuit device FIG. 1 shows a configuration example of the circuit device 100 (display controller 400) of the present embodiment. The circuit device 100 includes a control unit 110 (control circuit), an image processing unit 120 (image processing circuit), an error detection unit 130 (error detection circuit), an error judgment information output unit 140 (error judgment information output circuit), and a register unit 150. (Register), interface units 160, 170 (interface circuit) are included. The circuit device 100 is realized by, for example, an integrated circuit device (IC).

The interface unit 160 communicates between the processing device 200 and the circuit device 100. For example, the interface unit 160 receives image data transmitted from the processing device 200 to the image processing unit 120, and a timing control signal (for example, a clock signal, a vertical synchronization signal, a horizontal synchronization) transmitted from the processing device 200 to the control unit 110. Receive signals, data enable signals, etc.). Further, as will be described later with reference to FIG. 11 and the like, writing may be performed from the processing device 200 to the register unit 150. In that case, the interface unit 160 receives the register value written from the processing device 200 to the register unit 150. Alternatively, the interface unit 160 transmits the error determination information (error signal, error detection signal) output by the error determination information output unit 140 to the processing device 200, or transmits the register value read from the register unit 150 by the processing device 200. To do.

As a communication method for image data and timing control signals, for example, an LVDS (Low Voltage Differential Signal) method, an RGB serial method, a display port standard transmission method, or the like can be adopted. Further, as the communication method of the error signal and the register value, an I2C method, a 3-wire or 4-wire serial transmission method or the like can be adopted. The interface unit 160 is composed of an input / output buffer circuit and a control circuit (for example, a PLL circuit in the LVDS system) that realizes these communication methods.

When the circuit device 100 is mounted on, for example, an automobile, the processing device 200 is an ECU (Electronic Control Unit). Alternatively, when the circuit device 100 is mounted on an electronic device such as an information communication terminal, the processing device 200 is a processor such as a CPU (Central Processing Unit) or a microprocessor.

The processing device 200 supplies error detection data including the position information of the error detection area and the expected CRC value (expected value information of error detection) in the error detection area to the circuit device 100 (display controller 400). Send. Specifically, as will be described later with reference to FIGS. 5 and 6, display image data actually used for display and error detection data are transmitted as image data. In other words, the processing device 200 transmits the error detection data via the image data transmission interface (LVDS method, RGB serial method, etc. described above) in the interface unit 160. Alternatively, as will be described later with reference to FIG. 11 and the like, the processing device 200 may write error detection data to the register unit 150 via an interface for register values (I2C method or the like).

The control unit 110 controls each unit of the circuit device 100. In particular, the control unit 110 may perform timing control, controls each part of the circuit device 100 based on the timing control signal from the processing device 200, and a timing control signal (for example, a clock signal, vertical) transmitted to the display driver 300. (Synchronization signal, horizontal synchronization signal, data enable signal, etc.) is generated.

The image processing unit 120 generates transmission data suitable for various image processing (for example, gradation correction) and data shaping processing (data receiving method of the display driver 300) for the image data (display data) from the processing device 200. Process).

The error detection unit 130 performs error detection processing on the image data from the processing device 200. In the following, an example will be described in which the error detection unit 130 performs error detection processing by CRC (Cyclic Redundancy Check). The error detection method is not limited to CRC, and a method such as a checksum can be adopted. A detailed configuration example of the error detection unit 130 will be described later.

The error determination information output unit 140 outputs error determination information based on the output of the error detection unit 130 (CRC value or comparison result signal of CRC value and expected value). The output of the error determination information may be, for example, the output of the error determination information (error signal) to the processing device 200, or the writing of the error determination information to the register unit 150. The error signal here is, for example, an interrupt request signal (IRQ: Interrupt ReQuest). Alternatively, the error signal may be a signal that simply informs that an error has been determined (becomes active when an error is determined).

As will be described later in FIG. 4, in this embodiment, a plurality of error detection areas are set for the image. The error detection unit 130 performs error detection of image data for each error detection area, and outputs a CRC value and a comparison result signal for each error detection area. Then, the error determination information output unit 140 performs error determination for each error detection area based on the CRC value and the comparison result signal in each error detection area, and outputs the error determination information. A detailed configuration example of the error determination information output unit 140 will be described later.

The interface unit 170 communicates between the circuit device 100 and the display driver 300. For example, the interface unit 170 transmits the image data output by the image processing unit 120 to the display driver 300, or transmits the timing control signal output by the control unit 110 to the display driver 300. Further, the interface unit 170 may transmit a setting signal (for example, a mode setting signal) for controlling the operation of the display driver 300 to the display driver 300. As the communication method, the same method as that of the interface unit 160 can be adopted.

The display driver 300 is a circuit device that drives a display panel (electro-optical panel, for example, a liquid crystal display panel, an electrophoresis display panel, etc.). The display driver 300 supplies a power supply voltage and a reference voltage to, for example, a data driver that drives a data line of a display panel, a scanning driver that drives a scanning line of a display panel, a control circuit that controls them, and each part of the display driver 300. It consists of a power supply circuit and the like.

The control unit 110, the image processing unit 120, the error detection unit 130, the error determination information output unit 140, and the register unit 150 are logic circuits (for example, gate circuits such as AND circuits, or circuits, inverter circuits, flip-flop circuits, and the like. It is composed of a gate array) in which the functional circuits of are arranged. Each of these parts represents a functional block, and may be configured as an integrated logic circuit as hardware, or may be configured as an individual logic circuit.

Alternatively, each of the above parts may be realized by software. That is, the circuit device 100 and the like of the present embodiment may realize a part or most of the processing by a program. In this case, the circuit device 100 or the like of the present embodiment is realized by executing the program by a processor such as a CPU. Specifically, a program stored in a non-temporary information storage medium is read, and a processor such as a CPU executes the read program. Here, the information storage medium (medium that can be read by a computer) stores programs, data, and the like, and its function is an optical disk (DVD, CD, etc.), an HDD (hard disk drive), or a memory (card type). It can be realized by memory, ROM, etc.). Then, a processor such as a CPU performs various processes of the present embodiment based on a program (data) stored in the information storage medium. That is, the information storage medium is a program for operating a computer (a device including an operation unit, a processing unit, a storage unit, and an output unit) as each part of the present embodiment (a program for causing the computer to execute the processing of each part). Is memorized.

In the above, an example in which the circuit device 100 according to the present embodiment is realized by the display controller 400 (included in the display controller 400) has been described, but the present invention is not limited to this. For example, as shown in FIG. 2, the circuit device 100 of this embodiment may be realized by the display driver 300.

The display driver 300 includes an interface unit 161, an error detection unit 131, an error determination information output unit 141, a register unit 151, a control unit (control circuit) 181 and a drive unit (drive circuit) 191. The interface unit 161, the error detection unit 131, the error judgment information output unit 141, and the register unit 151 have the same configurations as the interface unit 160, the error detection unit 130, the error judgment information output unit 140, and the register unit 150 shown in FIG. 1, respectively. Can be realized by. Further, the drive unit 191 corresponds to the above-mentioned data driver and scanning driver.

As shown in FIGS. 1 and 2, image data is also communicated between the display controller 400 (in a narrow sense, the interface unit 170) and the display driver 300 (in a narrow sense, the interface unit 161). Therefore, by realizing the circuit device 100 by the display driver 300, it is possible to determine a communication error between the display controller 400 and the display driver 300.

Further, FIGS. 1 and 2 show an example in which the display controller 400 and the display driver 300 are mounted as different ICs. On the other hand, as shown in FIG. 3, the display controller 400 and the display driver 300 may be mounted as one chip. As shown in FIG. 3, the circuit device 100 in this case includes a control unit 112, an image processing unit 122, an error detection unit 132, an error determination information output unit 142, a register unit 152, an interface unit 162, a control unit 182, and a drive unit. Includes part 192. Each part of the circuit device 100 has the same configuration as that of FIG. 1 or 2. Although the control unit 112 for the display controller 400 and the control unit 182 for the display driver 300 are described separately in FIG. 3, these may be used as one control unit.

In the example of FIG. 3, since communication between the display controller 400 and the display driver 300 is unnecessary, a communication error between the processing device 200 and the circuit device 100 may be determined.

In the following, an example in which the circuit device 100 is realized as the display controller 400 as shown in FIG. 1 will be described, but in the following description, the circuit device 100 is realized as another device as shown in FIGS. 2 and 3. It is possible to expand and think in some cases.

2. 2. Example of setting the error detection area FIG. 4 shows an example of setting the error detection area. In FIG. 4, the first to fourth error detection regions AR1 to AR4 are set for the image IMG of a given frame. The size (width, height) of each error detection area is smaller than the size of the image IMG. That is, error detection is performed not for the entire image IMG but for a part of the error detection areas AR1 to AR4.

The error detection areas AR1 to AR4 are designated by the start points SP1 to SP4 and the end points EP1 to EP4. Specifically, the error detection areas AR1 to AR4 are designated by acquiring the coordinates of the start points SP1 to SP4 and the coordinates of the end points EP1 to EP4 as position information. For example, the coordinates x in the horizontal scanning direction and the coordinates y in the vertical scanning direction are defined with the coordinates of the upper left pixel of the image IMG as the origin. The pixel with the smallest coordinates x and y is the start point, and the pixel with the largest coordinates x and y is the end point.

In FIG. 4, the processing device 200 calculates the CRC value in each of the error detection areas AR1 to AR4, and transmits the CRC value as an expected value to the circuit device 100. Then, the error detection unit 130 calculates the CRC value in each of the error detection areas AR1 to AR4, and compares the calculated value with the expected value.

The number of error detection areas is not limited to four, and two or more arbitrary error detection areas can be set. Further, in FIG. 4, the error detection areas AR1 to AR4 are not overlapped with each other, but the region is not limited to this, and a part of the error detection areas may be overlapped with each other. Further, the position information for designating the error detection area is not limited to the start point and the end point, and may be any information that can determine the area. For example, the coordinates of the start point of the error detection region, the horizontal width (the number of pixels in the horizontal scanning direction), and the vertical width (the number of pixels in the vertical scanning direction) may be used.

In this way, error detection is performed not for the entire image but for a part of the error detection area. As a result, the amount of data for which the processing device 200 calculates the CRC value can be reduced, and the processing load of the processing device 200 can be reduced. Further, by setting a plurality of error detection areas, error detection in a wider area of the image becomes possible, and detection omission can be reduced. If an error detection area is set in a particularly important area, efficient error detection becomes possible.

Further, although FIG. 4 shows an error detection area in a given frame, the setting of the error detection area can be changed for each frame. That is, in the present embodiment, the number, position, size, and shape of the error detection area can be variably set in each frame. In other words, in the i-th frame image, error detection is performed in the error detection area for the i-frame, and in the j-th frame image, error detection is performed in the error detection area for the j-th frame. The position of the error detection area for the jth frame is different. Note that n is an integer of 2 or more, i and j are integers of 1 or more and n or less, and i ≠ j. As a result, error detection can be performed in error detection areas at different positions in each frame, and error detection in a wide range of the image becomes possible. Further, since the error detection is performed in a region smaller than the entire image in one frame, the processing load of the processing apparatus 200 can be reduced.

Here, the error detection is to check whether or not the image data that the processing device 200 tries to transmit to the circuit device 100 and the image data actually received by the circuit device 100 match (communication error). Detection). The frame image is an image displayed (or an image to be displayed) in one frame. For example, when the display of the display panel is updated at 30 fps (frames per second), 1/30 second is one frame, and the image drawn in the one frame is the frame image. The frame image here is an image at the stage when the processing device 200 transmits the image to the circuit device 100. That is, the frame image that is finally displayed and the frame image that is the target of error detection may not be exactly the same image because image processing may be performed between them.

3. 3. Example of Data Receiving Method Next, a method of receiving display image data and error detection data from the processing device 200 will be described. As will be described later with reference to FIG. 11 and the like, the method of receiving the display image data and the error detection data can be modified differently.

As shown in FIG. 1, the circuit device 100 according to the present embodiment includes an interface unit 160 for receiving image data and an error detection unit 130 for performing error detection. As described above, the interface unit 160 includes an interface for image data (RGB method, etc.) and an interface for error signals and register values (I2C method, 3-wire or 4-wire serial transmission method, etc.). The interface unit 160 here is, in a narrow sense, an interface for image data.

Then, the interface unit 160 receives the image data including the display image data and the error detection data including at least the position information of the error detection area, and the error detection unit 130 receives the error detection area specified by the position information. Error detection of display image data is performed based on the display image data of.

In this way, it becomes possible to include error detection data in the image data. In other words, the circuit device 100 of the present embodiment can receive the error detection data by using the interface for receiving the display image data.

FIG. 5 is a schematic view of an image area (including a display area and a non-display area) corresponding to the image data of the present embodiment. In FIG. 5, th1 represents the number of pixels (size) in the horizontal direction of the effective image area (display area), and tv1 represents the number of pixels in the vertical direction of the effective image area (display area). In the example of FIG. 5, the area of the effective image area (total number of pixels), that is, the size of the displayed image is th1 × tv1.

For example, in the case of allocating 8 bits to each of R, G, and B for each pixel, 24 bits of data may be used for each pixel. In the present embodiment, the image data actually used for display is referred to as display image data. The display image data is the data of the effective image area, and in the above example, it is the data of th1 × tv1 × 24 bits.

Further, when displaying the image data, a horizontal blanking interval, which is a period from the display of one line in the horizontal direction to the start of the display of the next one line, is provided. A1 of FIG. 5 shows a region corresponding to the horizontal blanking interval for convenience, and th2 represents the number of pixels in the region. Further, in the display of the image data, a vertical blanking interval, which is a period from the display of the image for one frame to the start of the display of the image of the next frame, is provided. A2 of FIG. 5 shows a region corresponding to the vertical blanking interval for convenience, and tv2 represents the number of pixels in the region. The area A3 determined from A1 and A2 is a non-display area that is not used for displaying an image.

As described above, since the data in the effective image area is the image data for display, it is not preferable to include the error detection data in the effective image area. This is because the image cannot be displayed in the effective image area in which the error detection data is written.

On the other hand, error detection data may be added to the above non-display area. Since the non-display area corresponds to the blanking interval, adding data to the non-display area does not hinder the transmission and reception of display image data. However, depending on the communication standard, it may be difficult to add error detection data to the non-display area.

Therefore, in the present embodiment, as shown as LINE0 in FIG. 5, the interface unit 160 receives the image data in which the error detection data is added to the front side of the display image data. By doing so, it becomes possible to appropriately receive the error detection data without hindering the reception of the display image data.

In the example of FIG. 5, LINE0 can include data for one horizontal line, for example, th1 × 24 bit data.

FIG. 6 is an example of the LINE 0 data format. The error detection data includes expected value information used in error detection. Specifically, the interface unit 160 receives image data including error detection data including position information of an error detection area and expected value information used in error detection. In FIG. 6, since an example of setting four error detection areas is assumed, the error detection information includes four position information and expected value information, respectively.

As described with reference to FIG. 4, the position information is, for example, the coordinates of the start points SP1 to SP4 (coordinates of the pixels corresponding to the start point) and the coordinates of the end points EP1 to EP4 (coordinates of the pixels corresponding to the end point). In this case, the error detection unit 130 uses a quadrangular region whose diagonal line connecting the start point and the end point is the error detection region. When the coordinates of the start point are (hs, vs) and the coordinates of the end point are (he, ve), each value of hs, vs, he, ve is information that can identify any pixel in the effective image area. All you need is. For example, if the effective image area has a size of 1920 × 1080, 11-bit data may be used for each value of the position information. However, various modifications can be made to the number of bits.

Further, the expected value information is obtained by the processing device 200 on the transmitting side. For example, the expected value information of the error detection area for the i-frame is obtained by the processing device 200 of the image data for displaying the i-frame image. Of these, it is obtained from the display image data of the error detection area for the i-frame. The expected value information includes, for example, an expected value crcr based on the R data value of each pixel in the error detection region, an expected value crcg based on the G data value, and an expected value crcb based on the B data. Here, each of crcr, crcg, and crcb is set to 16 bits, but various modifications can be performed for this as well. The expected value information in the present embodiment may be the expected value itself, but is not limited to this, and may be any information that can calculate the expected value (or information corresponding to the expected value).

In the example of FIG. 6, the region of the i-pixel to i + 6-pixel of LINE0 corresponds to the position information and the expected value information of the first error detection region. Specifically, 11 bits of the 16 bits in the R region of i and i + 1 pixels are used to store the vertical coordinate value vs0 of the start point. Similarly, the horizontal coordinate value hs0 of the start point is stored using the 11 bits of the G region of i and i + 1 pixels, the vertical coordinate value ve0 of the end point is stored using the 11 bits of the R region of i + 2 and i + 3 pixels, and i + 2 And the horizontal coordinate value he0 of the end point is stored using 11 bits of the G region of i + 3 pixels. In the example of FIG. 6, the B region of i to i + 3 pixels is not used.

Further, the expected value crcr0 based on the R data is stored by using 16 bits which are R regions of i + 4 and i + 5 pixels. Similarly, the expected value crcg0 based on the G data is stored using the 16 bits that are the G region of the i + 4 and i + 5 pixels, and the expected value crcb0 based on the B data is stored using the 16 bits that are the B region of the i + 4 and i + 5 pixels. Remember.

The same applies to the other error detection areas, where the i + 6 to i + 11 pixels correspond to the second error detection area, the i + 12 to i + 17 pixels correspond to the third error detection area, and the i + 18 to i + 23 pixels correspond to the third error detection area. Corresponds to the error detection area of 4.

However, the error detection data may be in a format in which the position information and the expected value information of each error detection region can be specified in the circuit device 100 on the receiving side, and the data format is not limited to FIG. For example, the arrangement of the position information and the expected value information of each error detection area is not limited to the order shown in FIG.

As shown in FIG. 6, the image data includes the second to second error detection data (n is an integer of 2 or more), and the second to nth error detection data i (i is 2). error detection data of ≦ i integer satisfying ≦ n) includes position information corresponding to the error detection region of the i. For example, the interface unit 160 corresponds to the first to nth error detection areas (n is an integer of 2 or more), and each error detection data includes the position information of each error detection area. Receives error detection data. In the example of FIG. 6, n = 4, and as described above, the error detection data includes four position information.

In this way, it is possible to appropriately set a plurality of error detection areas in each frame. It is not necessary to set a plurality of error detection areas in each frame, and there may be a frame in which one error detection area is set. Further, by not setting the error detection area, it is not prevented that there is a frame for skipping error detection (and error determination). In any case, in the method of FIGS. 5 and 6, since the circuit device 100 can receive the error detection data for each frame using the image data, the error detection area can be flexibly set.

4. Details of the Error Detection Unit and the Error Judgment Information Output Unit FIG. 7 shows a detailed configuration example of the error detection unit 130 and the error judgment information output unit 140. The error detection unit 130 includes calculation units 11 to 14 (calculation circuit) and comparison units 21 to 24 (comparison circuit). The error determination information output unit 140 includes a first determination unit 81-1 to 81-4, a second determination unit 82-1 to 82-4, and a third determination unit 83-1-83-4. Although the case where there are four calculation units and the like will be described here as an example, the number of calculation units and the like may be any number of two or more (for example, the same number as the maximum number of error detection areas that can be set). Hereinafter, each unit of the error detection unit 130 and the error determination information output unit 140 will be described in detail.

4.1 Error detection unit The position information of the first error detection area and the display image data of the error detection data are input to the calculation unit 11. The calculation unit 11 calculates the CRC value (calculated value) based on the display image data in the first error detection area specified by the position information among the display image data. In a broad sense, the calculation unit 11 calculates an error detection code for image data. Various methods are widely known for the format of the error detection code and the calculation, and they can be widely applied in the present embodiment. The calculation unit 11 outputs the calculated CRC value to the comparison unit 21 and the first determination unit 81-1.

The expected value information of the first error detection region of the error detection data and the CRC value calculated by the calculation unit 11 are input to the comparison unit 21. The expected value of CRC transmitted from the processing device 200 and the CRC value calculated by the calculation units 11 to 14 have the same number of bits and are calculated by the same calculation formula. The comparison unit 21 performs a comparison process of whether or not the calculated CRC value and the expected value match. That is, the error detection unit 130 performs error detection based on the expected value information. The comparison unit 21 outputs a signal representing the comparison result (comparison result signal) to the second determination unit 82-1 and the third determination unit 83-1.

The same applies to the calculation units 12 to 14 and the comparison units 22 to 24, in which the CRC value of the corresponding error detection area is calculated and the comparison processing is performed, and the CRC value and the comparison result signal are corresponded to by the error judgment information output unit 140. Output to the judgment unit.

As shown in FIG. 7, when the interface unit 160 receives the first to nth error detection data corresponding to the first to nth error detection regions, the error detection unit 130 detects each error. In the area, error detection is performed based on each error detection data. Specifically, the error detection unit 130 performs error detection in the i-th error detection region based on the i-th error detection data. In the example of FIG. 7, n = 4, and by providing four calculation units and four comparison units, error detection is executed in each error detection region.

In this way, even when a plurality of error detection areas are set in one frame, it is possible to appropriately execute error detection for each error detection area.

As shown in FIG. 7, error detection by the error detection unit 130 requires error detection data (position information, expected value information) and display image data. At this time, as for the display image data, it is not necessary to acquire the display image data for the entire image, and it is sufficient to acquire the display image data of the error detection area specified by the position information. That is, when the display image data to be processed is received, it is preferable to start the calculation of the CRC value by the calculation unit 11 sequentially (by pipeline processing). In this way, efficient error detection becomes possible.

At that time, which display image data is to be processed cannot be specified without the position information. That is, it is necessary to receive the error detection data at a timing before the display image data.

Therefore, the error detection unit 130 may perform error detection of the display image data based on the error detection data added to the front side of the display image data. Here, the “front side” means that the interface unit 160 receives the signal at an earlier timing. Assuming a two-dimensional image as shown in FIG. 5, and when scanning is performed from the upper left to the lower right, the "front side" means the upper side in the image and the left side in the same line. ..

In this way, when receiving the image data for one frame, the error detection data is first received, and then the display image data is received. Therefore, the error detection data for performing the error detection of the display image data can be included in the image data of the same frame.

However, it is not prevented that the error detection data is added to the rear side of the display image data. In this case, the error detection data included in the image data of a given frame will be used for error detection of the display image data of the next frame. That is, the paired display image data and the error detection data are included in the image data of different frames.

The interface unit 160 receives display data used for display on the electro-optical panel from the processing device 200 as image data, and the error detection unit 130 detects a transfer error of the image data. The error detection code used for error detection is a cyclic redundancy check (CRC).

That is, the error detection performed by the circuit device 100 according to the present embodiment specifically checks the identity of the received display image data with the transmitting side when the display image data is received. It is a process.

4.2 Error determination information output unit The error detection unit 130 performs comparison processing between the CRC value and the expected value. That is, if the comparison results do not match, it means that a communication error has occurred in the display image data. Therefore, the error determination information output unit 140 may output an error signal (interrupt request signal) to the processing device 200 when the comparison result signal indicates a mismatch.

However, the frequency of error occurrence due to communication is determined to some extent by the standard, and for example, a standard that requires the ^{bit error to be 10-9 or less can be considered.} Since this is the probability that a data error will occur in 1-bit data transfer, if the image size of 1 frame is th1 × tv1 and the data size of 1 pixel is 24 bits, the error occurrence probability per frame is It becomes th1 × tv × 24 × ^10-9. The specific value depends on the image size, but for example, in the case of an image of 1920 × 1080 pixels, an error may occur once every 20 frames. In this case, if the frame rate is 30 fps, the interrupt request signal is output 1.5 times per second, and if the frame rate is 60 fps, the interrupt request signal is output three times per second. This is excessively high as the frequency of occurrence of interrupt processing, and may hinder the smooth operation of the processing device 200. In the present embodiment, the output frequency of the interrupt request signal (frequency of occurrence of interrupt processing) can be reduced by setting an area narrower than the entire image as an error detection area, but this is not sufficient.

Therefore, in the present embodiment, further error determination may be performed based on the output from the error detection unit 130. Specifically, the circuit device 100 has an interface unit 160 that receives image data, an error detection unit 130 that calculates an error detection code of the image data to perform error detection, and an error detection code in a plurality of frames. Includes an error determination information output unit 140 that outputs based error determination information.

In this way, error determination information based on the error detection code in a plurality of frames can be output. A specific example will be described later, but an error having a higher importance than a single error occurrence, such as a large number of error detections based on an error detection code or continuous errors, is determined. Will be possible. Therefore, it is possible to prevent interrupts from occurring frequently as described above.

Further, the error detection unit 130 calculates an error detection code in a plurality of error detection areas of the image data to perform error detection, and the error judgment information output unit 140 outputs error judgment information in the plurality of error detection areas. To do. That is, it is possible to output the error determination information for each error detection area. Therefore, it is possible to adjust the content of the error determination according to the error detection area. For example, it is possible to prevent an error from being overlooked by making it easier to determine an error in an important area. Alternatively, it is possible to prevent the interrupt request signal from being excessively output by making it difficult to determine an error in a region of low importance.

As shown in FIG. 7, the error determination information output unit 140 includes a first determination unit 81 (81-1 to 81-4), a second determination unit 82 (82-1 to 82-4), and a third determination unit 83. (831-183-4) may be included. Hereinafter, a detailed description will be given. However, the configuration of each determination unit is not limited to that described below, and various modifications can be performed.

FIG. 8 is a configuration example of the first determination unit 81-1. Although description will be omitted below, the same configuration may be used for the first determination units 81-2 to 81-4 in FIG. The first determination unit 81-1 includes delay circuits DA1-1 and DA1-2, a comparison unit CP1, and a frame counter FC1.

The CRC value from the calculation unit 11 is input to the delay circuit DA1-1, and the CRC value is delayed by one frame. The output from the delay circuit DA1-1 is input to the delay circuit DA1-2, and the output of the delay circuit DA1-1 is further delayed by one frame. The delay circuits DA1-1 and DA1-2 can be realized by, for example, a D flip-flop. The comparison unit CP1 compares the output of the delay circuit DA1-1 with the output of the delay circuit DA1-2. In other words, the comparison unit CP1 determines whether or not the CRC value of the frame i and the CRC value of the frame i + 1 one frame later match. The frame counter FC1 is a counter that counts up or resets based on the output of the comparison unit CP1.

The matched signal in FIG. 8 is a signal that becomes “1” (high level, active) when the CRC values of frames i and i + 1 match, and becomes “0” (low level, inactive) when they do not match. Uncatched is a signal that becomes active when the CRC values of frames i and i + 1 do not match, and becomes inactive when they match. The frame counter FC1 is counted up (counter value increment) when the signal input to UP is active, and reset (for example, counter value = 0) when the signal input to CLEAR is active. ..

According to the first determination unit 81-1 shown in FIG. 8, the error determination information output unit 140 is based on the comparison result between the error detection code in the i-th frame and the error detection code in the i + 1 frame. The first error determination information is output as the error determination information.

In the display image data, there may be a region in which the display content (pixel value) does not change in many cases. For example, when the circuit device 100 is provided in a vehicle, a warning light for notifying an abnormality of the vehicle may be displayed on a part of a display panel. The warning light is displayed in the first color pattern (for example, a pattern in which the entire warning light display area is green) when no abnormality has occurred, and is displayed in the second color pattern (for example, the entire surface in red) when an abnormality has occurred. Will be done. By doing so, it is possible to clearly notify the user of the presence or absence of an abnormality.

In many cases, the warning light will be displayed in the first color pattern because the warning light is displayed in the second color pattern when there is a serious abnormality that poses a danger to the user. It will be displayed. As a result, when a part or all of the display area of the warning light is set as the error detection area, the CRC value in the error detection area becomes constant in many cases. In addition to the warning light, it is conceivable that the same display will continue in an area, and if this area is used as an error detection area, the CRC value is expected to remain unchanged for a long period of time.

That is, when the error detection area where the CRC value is assumed to be invariant is targeted, if the CRC value is invariant (matches with one frame before), no communication error has occurred and the CRC value has changed. If this is the case, it can be determined that the occurrence of a communication error is suspected.

For example, the first determination unit 81-1 checks the value of the frame counter FC1 at predetermined time intervals. If no communication error has occurred, the count value of the frame counter FC1 is a value determined by the elapsed time (number of elapsed frames). On the other hand, if a communication error has occurred, the reset is applied at the timing corresponding to the frame in which the error has occurred, so that the count value is smaller than when the error does not occur. The first determination unit 81-1 determines a communication error based on the magnitude of the count value of the counter, and outputs the determination result as the first error determination information.

FIG. 9 is a configuration example of the second determination unit 82-1. Although description will be omitted below, the same configuration may be used for the second determination units 82-2 to 82-4 in FIG. 7. The second determination unit 82-1 can be realized by the integration counter AC1.

The integration counter AC1 is a counter in which the comparison result signal from the comparison unit 21 of the error detection unit 130 is input to the UP, and the count-up is performed based on the comparison result signal. In FIG. 9, the comparison result signal is a signal that becomes “1” (active) when the CRC value and the expected value do not match, and becomes “0” (inactive) when they match. However, the comparison result signal may be a signal that becomes active when the CRC value and the expected value match, and becomes inactive when the CRC value and the expected value do not match. In that case, the second determination unit 82-1 may include an inverting circuit (not circuit) (not shown), invert the comparison result signal, and then input it to the UP of the integration counter AC1.

The integration counter AC1 counts up when the comparison result signal is active, that is, when the CRC value and the expected value do not match. As a result, the integration counter AC1 can integrate the number of times the CRC value and the expected value do not match (the number of times a CRC error has occurred). Then, the integration counter AC1 sets a predetermined threshold value, and when the number of CRC error occurrences exceeds the threshold value, it is determined as an error. If the number of CRC errors occurs, the severity of the error is considered to be high. That is, by using the integration counter AC1, it is possible to determine the occurrence of a serious communication error.

According to the second determination unit 82-1 shown in FIG. 9, the error determination information output unit 140 uses the error determination information output unit 140 as the error determination information when the integrated value of the number of error detections based on the error detection code reaches a given number of times. Outputs the error judgment information of 2. The given number of times here can be set in various ways, and in the example of FIG. 9, any one of four candidates of 31, 63, 127, and 255 times can be selected. For example, a relatively small value may be set for an important error detection area, and a relatively large value may be set for a less important error detection area. In this way, flexible error determination according to the importance becomes possible.

FIG. 10 is a configuration example of the third determination unit 83-1. Although description will be omitted below, the same configuration may be used for the third determination units 83-2 to 83-4 in FIG. 7. The third determination unit 83-1 includes the first to fourth delay circuits (D flip-flops) DB1-1 to DB1-4 and the AND circuit AN1.

A comparison result signal from the comparison unit 21 of the error detection unit 130 is input to the first delay circuit DB1-1. Here, as in the above-mentioned example, an example is shown in which the comparison result signal is a signal that becomes active when the CRC value and the expected value do not match and becomes inactive when they match, but various modifications can be performed. is there. The output bit1 of the first delay circuit DB1-1 is input to the second delay circuit DB1-2. The output bit2 of the second delay circuit DB1-2 is input to the third delay circuit DB1-3. The output bit3 of the third delay circuit DB1-3 is input to the fourth delay circuit DB1-4. The bit1 to bit3 and the output bit4 of the fourth delay circuit DB1-4 are input to the AND circuit AN1.

In the delay circuits DB1-1 to DB1-4, a signal corresponding to the frame timing of the image data is input as a clock signal. That is, the delay circuits DB1-1 to DB1-4 are circuits that delay the comparison result signal one frame at a time, and bit1 to bit4 represent comparison result signals of four different frames (in a narrow sense, four consecutive frames). ..

Since the AND circuit AN1 outputs the logical product of bits 1 to bit 4, the output of the AND circuit AN1 is when all of the bits 1 to bit 4 are active, that is, when the CRC value and the expected value do not match for 4 consecutive frames. Becomes active. As mentioned above, the CRC error itself can occur several times per second, but it is usually unlikely that it will continue in multiple frames. Therefore, when the CRC error continues for a plurality of frames, it can be determined that a serious communication error has occurred.

According to the third determination unit 83-1 shown in FIG. 10, the error determination information output unit 140 uses the error determination information output unit 140 as the error determination information when the error detection based on the error detection code occurs continuously for a given set number of frames. Outputs the error judgment information of 3. Note that FIG. 10 shows an example in which a given number of set frames is 4, but the present invention is not limited to this. For example, other AND circuits (not shown) may be added to FIG. Specifically, a 2-input AND circuit in which bit1 and bit2 are input and a 3-input AND circuit in which bit1 to bit3 are input may be added.

Then, the output of the third determination unit 83-1 is set to be selectable from any of bit1 itself, the logical product of bit1 and bit2, the logical product of bit1 to bit3, and the logical product of bit1 to bit4. In this way, the given number of set frames can be selected from 1 to 4, and flexible error determination according to the importance can be performed. Further, the number of set frames may be set to 5 or more. As with the second determination unit 82-1 described above, the number of set frames may be reduced as the error detection region becomes more important.

Note that FIG. 7 shows an example in which the first to third determination units are provided for all of the plurality of error detection regions, but the present invention is not limited to this. For example, for a given error detection region, it is possible to carry out modification such that the first determination unit 81 is not provided, or is provided as a configuration but is not operated (deactivated).

The output of the error determination information in this embodiment can be realized by various methods. For example, as described above, the output of the error determination information may be the output of the interrupt request signal to the processing device 200. Alternatively, the output of the error determination information may be written to the register unit 150. In this case, the processing device 200 periodically reads the corresponding area of the register 150 to check the error occurrence status (polling).

As an example, the error determination information output unit 140 outputs the first error determination information from the first determination unit 81 described above by writing to the register unit 150, and the second determination unit 82 outputs the first error determination information. The error determination information and the third error determination information of the third determination unit 83 are output by the output of the interrupt request signal. In this example, the error determination information output unit 140 requests an interrupt based on the results of eight determinations by the second determination unit 82-1 to 82-4 and the third determination unit 83-1-83-4. It will output a signal. For example, when any one of the second determination unit 82-1 to 82-4 and the third determination unit 83-1 to 83-4 determines an error, an interrupt request signal may be output.

Various operations can be assumed when the processing device 200 receives the interrupt request signal. For example, the processing device 200 may stop transmitting image data to the circuit device 100, or the processing device 200 may control a specific display (for example, display black (make the entire screen black) or display a predetermined pattern). May be instructed to the circuit device 100. Alternatively, the processing device 200 may stop the operation of the circuit device 100 or reset the circuit device 100.

At this time, the operation in the processing device 200 may be changed according to the determination of an error in any of the error detection areas of the plurality of error detection areas. Alternatively, the operation of the processing device 200 may be changed depending on which of the plurality of error determination information (first to third error determination information in the above example) is output. As described above, in the present embodiment, the error detection area can be flexibly set, and the importance may differ for each area. Further, since the content of the determination process is different from each other for the error determination information, the error occurrence status differs depending on which determination is determined as an error. Therefore, by specifying the content of the error detection area and the error determination information, the processing device 200 can take an appropriate response according to the area and the content of the determination.

Further, in the above, an example in which the processing device 200 takes measures when an error is determined is shown, but the present invention is not limited to this. The circuit device 100 of the present embodiment further includes a control unit 110 that controls the operation of the circuit device, and the error determination information output unit 140 determines a plurality of error determination information having different determination processes for the error detection code. Output as information. Then, the control unit 110 of the circuit device 100 indicates information indicating in which error detection area of the plurality of error detection areas the error was determined, and which error determination information of the plurality of error determination information was output. Operation control is performed based on at least one of the information.

That is, when it is determined that an error occurs, the circuit device 100 may execute the operation control for the error. The operation control here can be considered in various ways as in the example of the processing device 200, and even if the output of image data to the outside (for example, the output from the display controller 400 which is the circuit device 100 to the display driver 300) is stopped. Alternatively, a black display, a specific pattern, or a specific display control such as displaying an image stored inside the circuit device 100 may be performed.

Further, in the method of the present embodiment, the interface unit 160 for receiving the image data and the first error detection unit for performing error detection by calculating the error detection code of the image data in the first error detection area of the image data. And, in the second error detection region of the image data, it can be applied to the circuit device 100 including the second error detection unit that calculates the error detection code of the image data and performs the error detection.

Here, the first error detection unit corresponds to, for example, the calculation unit 11 and the comparison unit 21 of the error detection unit 130 of FIG. 7, and the second error detection unit is the calculation unit 12 and the comparison unit 22. Corresponds to.

Then, the circuit device 100 includes an error detection code of the image data of the first frame output from the first error detection unit, an error detection code of the image data of the second frame after the first frame, and an error detection code of the image data of the second frame after the first frame. The error detection code of the image data of the third frame output from the first error judgment information output unit that outputs the error judgment information based on the third frame and the second error detection unit, and the third frame after the third frame. It includes an error detection code of the image data of the frame 4 and a second error determination information output unit that outputs error determination information based on the error detection code.

Here, the first error determination information output unit is, for example, among the error determination information output units 140 of FIG. 7, the first determination unit 81-1, the second determination unit 82-1, and the third determination unit 83-. Corresponds to 1. The second error determination information output unit corresponds to the first determination unit 81-2, the second determination unit 82-2, and the third determination unit 83-2.

In this way, it is possible to set a plurality of error detection areas for the image, and to perform error detection processing and error determination information output processing for each error detection area. That is, in the method of the present embodiment, it is possible to independently perform error determination using a plurality of frames for each error detection area (output from the error detection unit 130 independently for each error detection area). For example, the area where the warning light is displayed may be the first error detection area, and the other areas may be the second error detection area. In this way, it is possible to perform processing for each area according to the characteristics (in a narrow sense, the degree of importance) of the error detection area.

5. Other Examples of Method for Receiving Error Detection Data In the above, an example in which the image data includes the error detection data and the interface unit 160 receives the error detection data using the image data interface has been described. By doing so, the error detection data can be easily received without hindering the reception of the display image data in each frame, and it is not necessary to write the error detection data to the register unit 150. ..

However, the method for receiving error detection data is not limited to this. For example, error detection data may be received using an interface different from the interface for image data. Further, error detection may be performed by writing the received error detection data to the register unit 150. Hereinafter, a detailed description will be given.

FIG. 11 shows a detailed configuration example of the error detection unit 130 and the register unit 150. The error detection unit 130 includes calculation units 11 to 14, comparison units 21 to 24, and error detection area setting unit 30 (error area setting circuit). The calculation units 11 to 14 and the comparison units 21 to 24 have the same configurations as those in FIG. 7.

The register unit 150 includes first to fourth position information registers 51 to 54 and first to fourth expected value registers 61 to 64. As in the example of FIG. 7, the number of calculation units and the like may be any number of 2 or more.

The position information of the first to fourth error detection areas is written from the processing device 200 to the position information registers 51 to 54. The expected value of CRC in the first to fourth error detection regions is written from the processing device 200 to the expected value registers 61 to 64.

For example, the position information and the expected value information are written to the register unit 150 by an interface different from the image data by I2C communication, 3-wire or 4-wire serial communication, or the like. Alternatively, the expected value information may be written to the register unit 150 via the image data interface.

The calculation units 11 to 14 read the position information from the position information registers 51 to 54, and calculate the CRC value of the first to fourth error detection regions from the image data (display image data).

The comparison units 21 to 24 include the expected value of the CRC of the first to fourth error detection regions from the expected value registers 61 to 64 and the CRC value of the first to fourth error detection regions from the calculation units 11 to 14. Compare with. The comparison units 21 to 24 output "0" (low level, inactive) as a comparison result signal when the expected value and the CRC value match, and when the expected value and the CRC value do not match, the comparison result signal. "1" (high level, active) is output as.

FIG. 12 shows a timing chart of the error detection process. A vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and a data enable signal DE are supplied from the processing device 200 to the control unit 110 (timing control unit) of the circuit device 100. The control unit 110 may generate these signals based on some synchronization signal supplied from the processing device 200, not limited to the case where these signals are directly supplied from the processing device 200.

The vertical synchronization signal VSYNC is a signal that defines a vertical scanning period (frame), and one vertical scanning period is from the fall of the vertical sync signal VSYNC to the next fall. In one vertical scanning period, the image data of one frame image is transmitted from the processing device 200 to the circuit device 100.

The horizontal synchronization signal HSYNC is a signal that defines the horizontal scanning period, and one horizontal scanning period is from the fall of the horizontal sync signal HSYNC to the next fall. In one horizontal scanning period, image data of one horizontal scanning line is transmitted from the processing device 200 to the circuit device 100.

The data enable signal DE becomes active (high level) in a part of the horizontal scanning period (data valid period), and the image data of the horizontal scanning line is transmitted from the processing device 200 to the circuit device 100 during that period. The period between the data validity period and the data validity period is called the horizontal blanking interval, and image data is not transmitted during this period. Further, a vertical blanking interval is provided for switching the vertical scanning period, and the data enable signal DE becomes inactive (low level) during the vertical blanking interval. No image data is transmitted during this period. In the example of FIG. 12, the vertical blanking interval corresponds to four horizontal blanking intervals, and the vertical sync signal VSYNC becomes a low level in two of the horizontal blanking intervals. The image data (display image data) of the frame image is transmitted between the end of the vertical blanking interval and the start of the next vertical blanking interval.

The error detection process is executed during the above vertical blanking interval. That is, in the first register access period TA1 after the vertical blanking interval is started, the processing device 200 writes the expected value of CRC in the expected value registers 61 to 64. This expected value is an expected value obtained from the image data transmitted in the frame immediately before the vertical blanking interval. In the error detection period TB1 after the first register access period TA1, the comparison units 21 to 24 compare the CRC value calculated by the calculation units 11 to 14 with the expected value. The calculation units 11 to 14 calculate the CRC value from the image data transmitted to the frame immediately before the vertical blanking interval. This calculation process is sequentially performed as the image data is input (that is, it is not always performed during the vertical blanking interval), and ends before the error detection period TB1. In the second register access period TA2 after the error detection period TB1, the processing device 200 writes the position information of the error detection area to the position information registers 51 to 54. This position information is the position information of the error detection area applied to the image data transmitted to the frame immediately after the vertical blanking interval.

The processing after the CRC value and the comparison result signal are obtained by the error detection unit 130 is the same as the above-described example using FIG. 7. Alternatively, the error detection unit 130 outputs the comparison result signal to the error judgment information output unit 140 (error signal output unit), and the error judgment information output unit 140 receives the comparison result signal (detection signal) from the error detection information unit 130. When active, an error signal may be output to the processor 200. That is, the configuration of the error determination information output unit 140 may be simplified as compared with FIGS. 7 to 10. In this case, the error detection unit 130 performs error detection of image data for each error detection area of the plurality of error detection areas, and outputs a detection signal for each error detection area (that is, outputs a plurality of detection signals). ). Then, the error signal output unit outputs an error signal when even one of the plurality of detection signals is active.

When writing the position information and the expected value information to the register unit 150, the error detection data for a plurality of frames are collectively written to the register unit 150, and the error detection area setting unit 30 determines which position information is to be used. It is also possible to set by.

The error detection area setting unit 30 sets (controls) in which of the first to fourth error detection areas the error detection is performed in each frame. Specifically, the error detection area setting unit 30 includes a frame counter 31 that counts the vertical synchronization signal VSYNC, and selects an error detection area to be detected according to the count value of the frame counter 31.

For example, as shown in FIG. 11, error detection information regarding the four error detection regions is obtained by using the first to fourth position information registers 51 to 54 and the first to fourth expected value registers 61 to 64. Consider the case where the data is stored in the register unit 150. In this case, as shown in FIG. 4, it is possible to continuously set four error detection areas AR1 to AR4 per frame (hereinafter, this is referred to as the first method). However, by using the information of the above four error detection areas, it is possible to carry out modifications of the following second to fourth methods and the like.

FIG. 13 shows an explanatory diagram of the second method of error detection. In the second method, error detection is performed in one error detection area for one frame image. As shown in FIG. 13, for example, an error is detected in the first error detection area AR1 for the frame image IMG1 of the first frame, and an error is detected in the second error detection area AR2 for the frame image IMG2 of the second frame. The detection is performed, an error is detected in the third error detection area AR3 for the frame image IMG3 of the third frame, and an error is detected in the fourth error detection area AR4 for the frame image IMG4 of the fourth frame. This is repeated in the same manner for the fifth and subsequent frames.

Taking the first frame as an example, the processing device 200 calculates a CRC value in the error detection area AR1 of the frame image IMG1 and writes the CRC value as an expected value in the register unit 150. Then, the error detection unit 130 calculates the CRC value in the error detection area AR1 of the frame image IMG1 and compares the calculated value with the expected value. The error signal output unit (error determination information output unit 140) outputs an interrupt request signal to the processing device 200 when the calculated value and the expected value do not match. In the second to fourth frames, the same error detection processing is performed for the second to fourth error detection areas AR2 to AR4. The position information of the error detection areas AR1 to AR4 is specified by the coordinates of the start point and the end point as in the first method.

The error detection area used in each frame is controlled as follows, for example. That is, the position information of the error detection areas AR1 to AR4 is collectively written to the register unit 150, and the position information of which error detection area is used in which frame is controlled based on the output of the frame counter. At this time, the processing device 200 writes a register value for specifying which error detection area is valid in each frame to the register unit 150, and the error detection unit 130 detects an error specified by the register value in each frame. Detects area errors. Alternatively, the error detection unit 130 performs error detection in all the error detection areas AR1 to AR4 in each frame, and the error signal output unit enables only the error detection result in the error detection area specified by the register value (its). The interrupt request signal may be output based only on the valid error detection result.

According to the second method, error detection is performed not for the entire image but for a part of the error detection area, and a different error detection area is set for each frame. As a result, the amount of data for which the processing device 200 calculates the CRC value can be reduced, and the processing load of the processing device 200 can be reduced. Further, by setting a different error detection area for each frame, error detection in a wider area of the image becomes possible, and detection omission can be reduced.

FIG. 14 shows an explanatory diagram of the third method of error detection. In the third method, error detection is performed in different numbers of error detection regions in the frame image of the first frame and the frame image of the second frame. As shown in FIG. 14, for example, error detection is performed in the first error detection area AR1 for the frame image IMG1 of the first frame, and the second to fourth error detection areas for the frame image IMG2 of the second frame. Error detection is performed by AR2 to AR4. This is repeated in the same manner for the third and subsequent frames. Alternatively, in the third frame, the errors of the first and second error detection areas AR1 and AR2 are detected, and in the fourth frame, the errors of the third and fourth error detection areas AR3 and AR4 are detected. The number of regions may be changed.

The position information of the error detection areas AR1 to AR4 is specified by the coordinates of the start point and the end point as in the first method. Further, the error detection area used in each frame is controlled by the same method as the second method.

According to the third method, the processing load of the processing device 200 can be reduced as in the second method, and error detection in a wider area of the image becomes possible.

FIG. 15 shows an explanatory diagram of the fourth method of error detection. In the fourth method, the image is divided into a plurality of areas, the divided areas are selected in order for each frame, and the selected divided areas are used as an error detection area for error detection. For example, in FIG. 15, a division area of 8 rows × (M / 2) columns is set, and M (M is an integer of 3 or more, M is an even number in the example of FIG. 15) in 2 rows. Is placed. The divided areas of the first and second lines are AR11 to AR1M (error detection area of the first group), and the divided areas of the third and fourth lines are AR21 to AR2M (error detection area of the second group). The divided areas of the 5th and 6th lines are AR31 to AR3M (error detection area of the 3rd group), and the divided areas of the 7th and 8th lines are AR41 to AR4M (error detection area of the 4th group). .. In the frame image IMG1 of the first frame, the divided areas AR11, AR21, AR31, and AR41 are error detection areas, and in the frame image IMG2 of the second frame, the divided areas AR12, AR22, AR32, and AR42 are error detection areas. This is repeated up to the Mth frame, and in the M + 1th frame, the same error detection area as in the first frame is obtained again.

The error detection area in each frame is controlled as follows, for example. That is, the processing device 200 writes the position information of the divided areas (error detection areas) AR11, AR21, AR31, and AR41 to the register unit 150 in the first frame, and the divided areas (error detection areas) AR12, AR22 in the second frame. The position information of AR32 and AR42 is written in the register unit 150. By repeating this up to the Mth frame, the error detection area in each frame is controlled. In this case, the position information is the coordinates of the start point and the end point of each division area.

Alternatively, the processing device 200 provides the position information (coordinates of the start point and the end point) of the first divided areas AR11, AR21, AR31, and AR41 in the error detection areas of the first to fourth groups, and the final divided areas AR1M, AR2M, and AR3M. , The position information (coordinates of the end point) of AR4M is written in the register unit 150. The error detection unit 130 obtains the coordinates of the start point and the end point of each division region from these position information. For example, when the width of the divided area AR11 is 100 pixels, the coordinates of the start point SP11 and the end point EP11 of the divided area AR11 shifted by 100 in the horizontal scanning direction become the coordinates of the start point and the end point of the divided area AR12. When the coordinates of the end point obtained in this way match the coordinates of the end point EP1M of the division area AR1M, that area is set as the final division area. The error detection unit 130 controls the error detection area in each frame by, for example, shifting the division area by one each time a vertical synchronization signal is input and updating the register unit 150 with the position information of the division area. To do.

In addition, error detection may be performed for all the groups of the error detection regions of the first to fourth groups, or error detection may be performed for a part (arbitrary one group, two groups, or three groups). For example, in the 1st to Mth frames, error detection is performed for all the error detection areas of the 1st to 4th groups, and in the next M + 1st to 2nd M frames, error detection is performed only in the error detection area of the 4th group. May be done. For example, the processing device 200 controls which group is enabled by writing a register value indicating which group is enabled in the register unit 150. For example, if the upper 3/4 of the image is black and only the lower 1/4 is displayed, the error detection area of the 4th group corresponding to the lower 1/4 is enabled. Since the processing device 200 knows what the image data looks like, such control is possible. Since the CRC reliability (error detection rate) is low in an image containing a large amount of continuous black image data, the processing load of the processing device 200 can be reduced by omitting the calculation of the CRC value in such an area. Can be reduced.

According to the fourth method, the processing load of the processing device 200 can be reduced as in the second and third methods. Further, by selecting the division area in order for each frame, an error is detected for the entire image, and it is possible to further reduce the detection omission.

When a communication error of image data is detected for the entire image, the processing device 200 calculates an expected value for error detection for the entire image, so that the amount of data to be calculated increases and the processing load increases. On the other hand, when the error detection area is set to a fixed area smaller than the entire image, the processing load of the processing device 200 is reduced, but the error can be detected only for a part of the image.

In this respect, in the present embodiment, the circuit device 100 includes an error detection unit 130 that detects an error in image data, and an error signal output unit that outputs an error signal based on the result of the error detection. Let n be an integer of 2 or more, i and j be an integer of 1 or more and n or less, and i ≠ j. An error detection area for the i-frame is set for the i-th frame image of the first to nth frame images, and the j-th frame image of the first to nth frame images is set. The error detection area for the jth frame is set at a position different from the error detection area for the i-frame. In this case, the error detection unit 130 performs error detection based on the image data of the error detection area for the i-th frame and the error detection area for the j-th frame. The error signal output unit outputs an error signal based on the result of error detection in the error detection area for the i-th frame and the error detection area for the j-th frame.

According to the present embodiment, in the i-th frame image, error detection is performed in the error detection area for the i-frame, and in the j-th frame image, error detection is performed in the error detection area for the j-th frame. The positions of the error detection areas for the i-th and j-th frames are different. As a result, error detection can be performed in error detection areas at different positions in each frame, and error detection in a wide range of the image becomes possible. Further, since the error detection is performed in a region smaller than the entire image in one frame, the processing load of the processing apparatus 200 can be reduced.

Here, the error detection is to check whether or not the image data that the processing device 200 tries to transmit to the circuit device 100 and the image data actually received by the circuit device 100 match (communication error). Detection). The error signal is a signal related to the result of error detection, for example, a signal indicating whether or not an error in image data has been detected, or a signal requesting the processing device 200 to perform some operation according to the result of error detection. is there. The frame image is an image displayed (or an image to be displayed) in one frame. For example, when the display of the display panel is updated at 30 fps (frames per second), 1/30 second is one frame, and the image drawn in the one frame is the frame image. The frame image here is an image at the stage when the processing device 200 transmits the image to the circuit device 100. That is, the frame image that is finally displayed and the frame image that is the target of error detection may not be exactly the same image because image processing may be performed between them.

For example, in the second method of FIG. 13, n = 4. Taking the case of i = 1 and j = 2, the error detection area for the i-th frame is AR1, and the error detection area for the j-frame is AR2. The positions of these error detection areas AR1 and AR2 are different. In the example of FIG. 13, the positions correspond to the start point and the end point of the region. However, the position of the region is not limited to this, and may be, for example, only the start point or the center point of the region (for example, a point where two diagonal lines intersect).

In the third method of FIG. 14, n = 2. Assuming that i = 1 and j = 2, the error detection area for the i-th frame is AR1, and the error detection area for the j-th frame is AR2 to AR4. As described above, the error detection area for the i-th and j-th frames may be composed of a plurality of areas. In this case, the position of the region is the position of each region of the plurality of regions (for example, the start point and the end point), and the position of any one of the plurality of regions may be different. For example, in the example of FIG. 14, each area of the error detection area AR2 to AR4 for the j-th frame has a different position from the error detection area AR1 for the i-th frame. For example, the error detection areas for the jth frame may be AR1 and AR2. In this case, the position of the area AR2 is different from that of the error detection area AR1 for the i-frame.

In the fourth method of FIG. 15, n = M. Assuming that i = 1 and j = 2, the error detection areas for the i-th frame are AR11 to AR41, and the error detection areas for the j-frame are AR12 to AR42.

Further, in the present embodiment, the circuit device 100 includes a register unit 150 that stores the position information of the error detection area for the i-th frame and the error detection area for the j-th frame. The error detection area for the i-th frame and the error detection area for the j-th frame are set based on the position information stored in the register unit 150.

As described with reference to FIG. 4 and the like, the position information is, for example, the coordinates of the start points SP1 to SP4 (coordinates of the pixels corresponding to the start point) and the coordinates of the end points EP1 to EP4 (coordinates of the pixels corresponding to the end point). In this case, the error detection unit 130 uses a quadrangular region whose diagonal line connecting the start point and the end point is the error detection region.

According to this embodiment, the error detection area to be the target of error detection can be set by writing the position information of the error detection area for the i-th and j-th frames to the register unit 150. Then, as the position information of the error detection areas for the i and jth frames, different position information is written to the register unit 150, so that the error detection areas for the i and jth frames having different positions can be set. ..

Further, in the present embodiment, the register unit 150 stores the expected value information of error detection together with the position information of the error detection area for the i-th frame and the error detection area for the j-th frame. The error detection unit 130 detects an error based on the expected value information.

The expected value information is obtained by the processing device 200 on the transmitting side. For example, the expected value information of the error detection area for the i-frame is the i-th of the display data of the i-frame image displayed by the processing device 200. It is obtained from the display data of the error detection area for the frame.

According to the present embodiment, the expected value information of error detection corresponding to the error detection area for the i and jth frames is written to the register unit 150, whereby the error detection area for the i and jth frames is described. Error detection is possible.

Further, in the present embodiment, the circuit device 100 includes an interface unit 160. The position information and the expected value information are set in the register unit 150 by the external processing device 200 via the interface unit 160.

For example, the position information and the expected value information are written to the register unit 150 by an interface different from the image data by I2C communication, 3-wire or 4-wire serial communication, or the like. Alternatively, the expected value information may be written to the register unit 150 via the image data interface. In this case, the expected value information is transmitted during the period when the image data is not transmitted (for example, the return line period described later). For example, when the image data of one pixel is 24 bits (8 bits each for RGB) and the expected value information is a 16-bit CRC value, the 16-bit CRC value is embedded in the 24-bit data in the same format as the image data and transmitted. To do. For example, the processing device 200 transmits 16 bits of RG out of 8 bits of each of RGB as CRC values, and the interface unit 160 takes out 16 bits of RG out of the received 24 bits and writes them in the register unit 150 as expected value information. It is possible to know at what timing the received image data is the expected value information by the timing control of the control unit 110 (timing control unit).

According to the present embodiment, the position information and the expected value information are set in the register unit 150 by the external processing device 200 via the interface unit 160, and the error detection area is set based on the position information. Error detection can be performed in the error detection area based on the expected value information.

Further, in the present embodiment, the expected value information and the position information received during the blanking interval of the image data are set in the register unit 150.

The blanking interval is a non-transmission period of image data, for example, a vertical blanking interval. As shown in FIG. 12, the vertical return period is the transmission period of the image data of the frame image (the period including the horizontal scanning period in which the data valid period exists) and the transmission period of the image data of the next frame image. The period between them (the period including the horizontal scanning period when there is no data validity period).

It is necessary that the frame image for which the processing device 200 has obtained the expected value information and the frame image for which the circuit device 100 performs error detection match. In this regard, according to the present embodiment, by receiving the expected value information during the return period of the image data, the expected value information is the expected value information of the frame image received before the return period. Is clearly associated. In addition, it is necessary to know the position information of the error detection area before performing error detection. In this regard, according to the present embodiment, by receiving the position information during the blanking interval of the image data, the position information is the position information of the error detection area in the frame image received after the blanking interval. There is a clear association.

Further, in the present embodiment, a plurality of error detection areas are set as each error detection area of the error detection area for the i-th frame and the error detection area for the j-th frame.

For example, in the third method of FIG. 14, three error detection areas AR2 to AR4 are set as error detection areas for the second frame. In the fourth method of FIG. 15, four divided areas (for example, AR11 to AR41) are set as error detection areas for each frame.

Further, in the present embodiment, the error detection area for the i-frame and the error detection area for the i-frame are arranged so that the number of error detection areas for the i-frame and the number of error detection areas for the j-frame are different (variable number). An error detection area for the jth frame may be set.

For example, in the third method of FIG. 14, one error detection area AR1 is set as the error detection area for the first frame, and three error detection areas AR2 to AR4 are set as the error detection area for the second frame. To.

According to this embodiment, a plurality of error detection areas are set as each error detection area, or a different number of error detection areas are set as each error detection area. This makes it possible to freely set the error detection area, such as setting an appropriate error detection area according to the content of the display image. For example, if one frame has only a part of the image displayed, that frame has only one error detection area set, and another frame has a wide area of the image displayed. , In that frame, multiple error detection areas can be set within that range.

Further, as described above in FIG. 11, the error detection unit 130 includes an error detection area setting unit 30. Based on the count value of the frame counter 31, the error detection area setting unit 30 selects the error detection area for the i-th frame and the error detection area for the j-th frame, which are the targets of error detection, from among the plurality of error detection areas. Set.

Specifically, the position information of a plurality of error detection areas is set in the register unit 150, and among the plurality of error detection areas, which error detection area is to be detected (or which error detection area is the detection result). Is output) by the error detection area setting unit 30 according to the count value. Such control corresponds to setting the error detection area based on the count value of the error detection area.

According to this embodiment, an error detection area to be an error detection target in each frame is set from a plurality of error detection areas. As a result, a plurality of error detection areas can be set as the error detection areas for the i and jth frames, and different numbers of error detection areas can be set as the error detection areas for the i and jth frames. Control is possible.

Further, in the present embodiment, the error detection area setting unit 30 sets the error detection area for the kth frame in the kth frame image of the first to nth frame images when k is an integer of 1 or more and n or less. And the error detection area for the k + 1 frame in the frame image of the k + 1 are set so as to be adjacent to each other.

For example, in the fourth method of FIG. 15, k = 1 and k + 1 = 2. In this case, the error detection areas for the kth frame are AR11 to AR41, and the error detection areas for the k + 1th frame are AR12 to AR42. The regions AR12, AR22, AR32, and AR42 are regions adjacent to the regions AR11, AR21, AR31, and AR41, respectively. Here, the fact that the regions are adjacent to each other means that one side of one region and one side of the other region are adjacent to each other (for example, there is no pixel between them).

According to this embodiment, the error detection area is sequentially shifted to the adjacent area for each frame. As a result, it is possible to detect an error in the entire image without gaps over a plurality of frames, and it is possible to improve the accuracy of error detection.

Hereinafter, the operation of each method described with reference to FIGS. 4 and 13 to 15 will be described in detail in association with the configuration example of FIG. It is assumed that the count value of the frame counter 31 is 0 to 15 (after 15 is returned to 0), and the count values 0 to 15 correspond to the first to 16th frames.

For example, in the first method of FIG. 4, all of the first to fourth error detection areas AR1 to AR4 are valid regardless of the count value of the frame counter 31, and the error detection area setting unit 30 is the calculation unit 11 to 11. Have all 14 calculate the CRC value.

In the second method of FIG. 13, when the count values of the frame counter 31 are 0, 4, 8, and 12, the first error detection area AR1 is valid, and the second to fourth error detection areas AR2 to AF4 are invalid. It becomes. That is, the error detection area setting unit 30 causes the calculation unit 11 to calculate the CRC value, and disables the operations of the calculation units 12 to 14. The comparison units 22 to 24 corresponding to the disabled calculation units 12 to 14 output "0" (inactive). In this case, the processing device 200 writes the register value only to the first position information register 51 and the first expected value register 61. Similarly, when the count values are 1, 5, 9, and 13, the second error detection area AR2 is valid, and when the count values are 2, 6, 10, and 14, the third error detection area AR3 is valid. Then, when the count values are 3, 7, 11, and 15, the fourth error detection area AR4 becomes effective.

The following modifications can be considered in the second method. That is, in any frame, the processing device 200 writes the register values to the first to fourth position information registers 51 to 54 and the first to fourth expected value registers 61 to 64. Further, regardless of the count value, the calculation units 11 to 14 calculate the CRC value, and the comparison units 21 to 24 compare the expected value and the CRC value. Taking the case where the count values are 0, 4, 8, and 12, the error detection area setting unit 30 causes the comparison unit 21 to perform weighting by multiplying the comparison result of the comparison unit 21 by 1, and the comparison unit 22. The comparison units 22 to 24 are weighted by multiplying the comparison results of ~ 24 by 0. As a result, the comparison unit 21 outputs the comparison result, and the comparison units 22 to 24 output “0”.

In the third method of FIG. 14, when the count value of the frame counter 31 is 0, 2, 4, 6, 8, 10, 12, 14, the first error detection area AR1 is valid, and the count value of the frame counter 31 is valid. When is 1, 3, 5, 7, 9, 11, 13, and 15, the second to fourth error detection regions AR2 to AR4 are valid. The error detection area setting unit 30 controls the calculation units 11 to 14 and the comparison units 21 to 24 in the same manner as in the second method. The same applies to the modified example.

In the fourth method of FIG. 15, in the first frame, the processing device 200 writes the position information of the error detection areas AR11 to AR41 to the first to fourth position information registers 51 to 54, and the first to fourth expected values. The expected value of CRC of the error detection areas AR11 to AR41 is written in the registers 61 to 64. In the second frame, the processing device 200 writes the position information of the error detection areas AR12 to AR42 in the first to fourth position information registers 51 to 54, and the error detection area 61 to 64 in the first to fourth expected value registers 61 to 64. Write the expected value of CRC of AR12 to AR42. In the subsequent frames, the area is shifted in the same manner. For example, when M = 16, the error detection areas AR1M to AR4M become effective in the 16th frame.

The error detection area setting unit 30 causes the calculation units 11 to 14 to calculate the CRC value and causes the comparison units 21 to 24 to output the comparison result regardless of the count value of the frame counter 31. Alternatively, the error detection area setting unit 30 may set any of the calculation units 11 to 14 to be enabled and the others to be disabled. For example, calculation units 11 to 13 are set to disabled, and calculation units 14 are set to enable. In this case, only the error detection areas AR41 to AR4M of the fourth group are the targets of error detection. It should be noted that the same operation may be realized by weighting in the comparison units 21 to 24 as in the modified example described in the second method. That is, the calculation units 11 to 14 may be made to calculate the CRC value, the comparison units 21 to 23 may be made to multiply the comparison result by 0, and the comparison unit 24 may be made to multiply the comparison result by 1.

The operation of the error detection area setting unit 30 as described above is realized by, for example, register setting. For example, the processing device 200 sets a register value in which the count value of the frame counter 31 and which of the calculation units 11 to 14 are enabled (or weighting in the comparison units 21 to 24) are associated with each count value. The register unit 150 is written, and the error detection area setting unit 30 refers to the register unit 150 for operation. Alternatively, the processing device 200 writes the mode setting value for switching the first to fourth methods as a register value to the register unit 150, and the error detection area setting unit 30 refers to the mode setting value and operates. In this case, the error detection area setting unit 30 voluntarily controls which of the calculation units 11 to 14 is enabled (or the weighting of the comparison units 21 to 24) in each count value.

Further, FIG. 16 is a second detailed configuration example of the register unit 150. In FIG. 16, the register unit 150 further includes the first to fourth calculated value registers 71 to 74.

The CRC values (CRC calculated values) calculated by the calculation units 11 to 14 are stored in the first to fourth calculated value registers 71 to 74. The processing device 200 can read the CRC value from the first to fourth calculated value registers 71 to 74 via the interface unit 160.

Since the error judgment information (interrupt request signal) from the error judgment information output unit 140 is only input to the processing device 200, it is possible to know the communication error of the image data, but an error has occurred in which error detection area. I can't know. In the present embodiment, the processing device 200 can know in which error detection region an error has occurred by referring to the calculated value registers 71 to 74.

When the processing device 200 receives the error signal (interrupt request signal), the processing device 200 reads the CRC value from the calculated value registers 71 to 74, compares it with the expected value, and determines in which error detection area an error has occurred. For example, the processing device 200 can perform processing according to the area where the error has occurred, such as retransmitting the image data of the area where the error has occurred to the circuit device 100 and redrawing the image data.

6. Electro-optic device, electronic device, mobile body The method of the present embodiment can be applied to various devices including the circuit device 100 described above. For example, the method of this embodiment can be applied to a circuit device 100 and an electro-optical device including an electro-optical panel (display panel). Further, the method of the present embodiment can be applied to an electronic device including a circuit device 100 and a mobile body.

FIG. 17 shows a configuration example of an electro-optical device (display device) including the circuit device 100 of the present embodiment. The electro-optical device includes a circuit device 100 (display controller), a display panel 360, and a display driver 300 that drives the display panel 360 under control by the circuit device 100.

The display panel 360 is composed of, for example, a glass substrate and a pixel array (liquid crystal cell array) formed on the glass substrate. The pixel array includes pixels, data lines, and scanning lines. The display driver 300 is mounted on a glass substrate, and the display driver 300 and the pixel array are connected by a wiring group formed of transparent electrodes (ITO: Indium Tin Oxide). The circuit device 100 is mounted on a circuit board different from the glass substrate, and the circuit board and the glass substrate are connected by a flexible substrate or the like. The electro-optical device is not limited to this configuration. For example, the display driver 300 and the circuit device 100 may be mounted on a circuit board, and the circuit board and the display panel 360 may be connected by a flexible board or the like.

FIG. 18 shows a configuration example of an electronic device including the circuit device 100 of the present embodiment. Examples of the electronic devices of the present embodiment include in-vehicle display devices (for example, instrument panels), displays, projectors, television devices, information processing devices (computers), portable information terminals, car navigation systems, portable game terminals, and DLPs. Various electronic devices equipped with a display device, such as a (Digital Light Processing) device, can be assumed.

The electronic devices include a CPU 310 (processing device), a circuit device 100 (display controller), a display driver 300, a display panel 360, a storage unit 320 (memory), an operation unit 330 (operation device), and a communication unit 340 (communication circuit, communication device). )including.

The operation unit 330 is a user interface that receives various operations from the user. For example, it is composed of a button, a mouse, a keyboard, a touch panel attached to the display panel 360, and the like. The communication unit 340 is a data interface that communicates (transmits, receives) image data and control data. For example, it is a wired communication interface such as USB, or a wireless communication interface such as a wireless LAN. The storage unit 320 stores the image data input from the communication unit 340. Alternatively, the storage unit 320 functions as a working memory of the CPU 310. The CPU 310 performs control processing and various data processing of each part of the electronic device. The circuit device 100 controls the display driver 300. For example, the circuit device 100 converts the image data transferred from the communication unit 340 or the storage unit 320 via the CPU 310 into a format that can be accepted by the display driver 300, and outputs the converted image data to the display driver 300. To do. The display driver 300 drives the display panel 360 based on the image data transferred from the circuit device 100.

FIG. 19 shows a configuration example of a mobile body including the circuit device 100 of the present embodiment. As the moving body of the present embodiment, for example, various moving bodies such as a car, an airplane, a motorcycle, a ship, or a robot (traveling robot, walking robot) can be assumed. The moving body is, for example, a device / device provided with a drive mechanism such as an engine or a motor, a steering mechanism such as a steering wheel or a rudder, and various electronic devices, and moves on the ground, in the sky, or on the sea.

FIG. 19 schematically shows an automobile 206 as a specific example of a moving body. The automobile 206 incorporates a display device 350 (electro-optical device) having a circuit device 100 and an ECU 510 that controls each part of the automobile 206. The ECU 510 generates an image (image data) that presents information such as vehicle speed, remaining fuel amount, mileage, and settings of various devices (for example, an air conditioner) to the user, and transmits the image to the display device 350 for display. It is displayed on the panel 360.

Although the present embodiment has been described in detail as described above, those skilled in the art will easily understand that many modifications that do not substantially deviate from the novel matters and effects of the present invention are possible. Therefore, all such modifications are included in the scope of the present invention. For example, a term described at least once in a specification or drawing with a different term in a broader or synonymous manner may be replaced by that different term anywhere in the specification or drawing. All combinations of the present embodiment and modifications are also included in the scope of the present invention. Further, the configuration / operation of the circuit device, the processing device, the display driver, the electro-optical device, the electronic device, the moving body, and the like are not limited to those described in the present embodiment, and various modifications can be performed.

AC1 ... Integration counter, AN1 ... And circuit, AR1-AR4 ... Error detection area,
CP1 ... Comparison part, DA1-1, DA1-2, DB1-1-1 to DB1-4 ... Delay circuit,
FC1 ... Frame counter, 11-14 ... Calculation unit, 21-24 ... Comparison unit,
30 ... Error detection area setting unit, 31 ... Frame counter,
51-54 ... Position information register, 61-64 ... Expected value register,
71-74 ... Calculated value register, 81 (81-1 to 81-4) ... First determination unit,
82 (82-1 to 82-4) ... 2nd judgment unit, 83 (83-1 to 83-4) ... 3rd judgment unit,
100 ... Circuit device, 110, 112 ... Control unit, 120, 122 ... Image processing unit,
130, 131, 132 ... Error detector,
140, 141, 142 ... Error judgment information output unit,
150, 151, 152 ... Register section,
160,161,162,170 ... Interface unit, 181,182 ... Control unit,
191 ... 192 ... drive unit, 200 ... processing device, 206 ... automobile,
300 ... Display driver, 320 ... Storage unit, 330 ... Operation unit, 340 ... Communication unit,
350 ... Display device, 360 ... Display panel, 400 ... Display controller

Claims (12)

The interface part that receives image data and
An error detection unit that detects errors and
Including
The interface unit
The image data including the display image data and the error detection data including at least the position information of the error detection area is received, and the image data is received.
The error detection unit
Based on the display image data of the error detection region specified by the position information, the error detection of the display image data is performed.
The image corresponding to the display image data is a region set to the first position specified by the position information and the position does not change with time, and a second region specified by the position information. Includes a second area that is set to a position and whose position does not change over time.
Of the images corresponding to the display image data, the frequency with which the first region is included in the error detection region and the second region of the images corresponding to the display image data are included in the error detection region. A circuit device characterized in that the frequency of inclusion is different. In claim 1,
The error detection area is periodically set with a plurality of frames as one cycle.
A circuit device characterized in that, among the images corresponding to the display image data, a region not included in the error detection region exists in the one cycle. In claim 1 or 2,
The error detection data further includes expected value information used in the error detection.
The error detection unit
A circuit device characterized in that the error detection is performed based on the expected value information. In any one of claims 1 to 3,
The image data is
Contains the second to second error detection data (n is an integer of 2 or more)
Error detection data of the second to i data for error detection of the n (i is an integer satisfying 2 ≦ i ≦ n) is
A circuit device including the position information corresponding to the third error detection region. In claim 4,
The error detection unit
A circuit device characterized in that the error detection is performed based on the error detection data of the i-th in the error detection region of the i-th. In any of claims 1 to 5,
The error detection unit
A circuit device characterized in that the error detection of the display image data is performed based on the error detection data received at a timing earlier than the display image data. In any of claims 1 to 6,
Including the error judgment information output section
The error detection unit
In the plurality of error detection areas of the image data, the error detection code is calculated to perform the error detection.
The error determination information output unit
A circuit device characterized by outputting error determination information in the plurality of error detection regions based on the error detection codes in a plurality of frames. The circuit device according to any one of claims 1 to 7.
Electro-optic panel and
An electro-optic device comprising. An electronic device comprising the circuit device according to any one of claims 1 to 7. A mobile body including the circuit device according to any one of claims 1 to 7. The image data including the display image data and the error detection data including at least the position information of the error detection area is received, and the image data is received.
Based on the display image data in the error detection area specified by the position information, error detection of the display image data is performed.
The image corresponding to the display image data is a region set to the first position specified by the position information and the position does not change with time, and a second region specified by the position information. Includes a second area that is set to a position and whose position does not change over time.
Of the images corresponding to the display image data, the frequency with which the first region is included in the error detection region and the second region of the images corresponding to the display image data are included in the error detection region. An error detection method characterized in that the frequency of inclusion is different. 11.
The error detection area is periodically set with a plurality of frames as one cycle.
An error detection method, characterized in that, among the images corresponding to the display image data, a region not included in the error detection region exists in the one cycle.