JP6720517B2 - Circuit devices, electro-optical devices, electronic devices, moving objects - Google Patents

Description

The present invention relates to a circuit device, an electro-optical device, an electronic device, a moving body and the like.

In display control of a display device (for example, a liquid crystal display device), a processing device such as a CPU transmits image data and control signals to a display controller, the display controller performs image processing and timing signal generation, and the image-processed image The display driver operates according to the data and timing signals. For example, an LVDS (Low Voltage Differential Signal) system or an RGB serial system is used to transmit the image data from the processing device to the display controller, but in any case, an error may occur in the image data due to a communication error or the like. .. For example, Patent Documents 1 to 3 disclose techniques in which a display controller detects an error in image data received from a processing device by CRC (Cyclic Redundancy Check).

JP, 2012-35677, A JP, 2007-101691, A JP, 2007-72394, A

In such error detection, the processing device obtains expected value information for error detection (for example, expected value of CRC) from image data transmitted to the display controller, and the display controller detects error detection from image data received from the processing device. A calculated value (for example, a CRC value) is obtained, and the expected value information and the calculated value are compared to detect an error. Therefore, a processing load is imposed on the processing device to obtain expected value information for error detection. For example, when all the image data of the image of one frame is error-detected, the amount of data used to calculate the expected value information becomes enormous and the processing load increases. In order to reduce this load, a method of reducing the area in which error detection is performed (error detection is performed only in a partial area of the image) can be considered, but an error cannot be detected in images other than that area.

According to some aspects of the present invention, it is possible to provide a circuit device, an electro-optical device, an electronic device, a moving body, and the like that can reduce the processing load of the processing device in error detection of image data.

One aspect of the present invention includes an error detection unit that detects an error in image data, and an error signal output unit that outputs an error signal based on a result of the error detection, wherein the error detection unit sets n to 2 When the integers i and j are 1 or more and n or less, and i≠j, an error for the i-th frame with respect to the i-th frame image of the first to n-th frame images A detection area is set, and an error detection area for the jth frame is set at a position different from the error detection area for the ith frame with respect to the jth frame image of the first to nth frame images. In this case, the error detection is performed based on the image data of the error detection area for the i-th frame and the error detection area for the j-th frame, and the error signal output unit outputs the error for the i-th frame. The present invention relates to a circuit device that outputs the error signal based on a result of the error detection in the detection region and the error detection region for the j-th frame.

According to one aspect of the present invention, error detection is performed in the error detection area for the i-th frame in the i-th frame image, and error detection is performed in the error detection area for the j-th frame in the j-th frame image. The positions of the error detection areas for the i-th and j-th frames are different. That is, error detection is performed in error detection regions at different positions in each frame, and error detection is performed in a region smaller than the entire image in one frame. As a result, the processing load on the processing device in error detection of image data can be reduced, and error detection can be performed in a wide range of an image.

In one aspect of the present invention, the circuit device includes a register unit that stores position information of the error detection area for the i-th frame and the error detection area for the j-th frame, and the error detection for the i-th frame is performed. The area and the error detection area for the j-th frame may be set based on the position information stored in the register unit.

According to one aspect of the present invention, by writing the position information of the error detection areas for the i-th frame and the j-th frame in the register section, it is possible to set the error detection area to be the target of error detection. Then, as the position information of the error detection areas for the i-th and j-th frames, different position information is written in the register unit, whereby error detection areas for the i-th and j-th frames having different positions can be set.

In one aspect of the present invention, the register unit stores expected value information for error detection together with the position information of the error detection area for the i-th frame and the error detection area for the j-th frame, The unit may detect an error based on the expected value information.

According to one aspect of the present invention, expected value information for error detection corresponding to the error detection areas for the i-th and j-th frames is written in the register unit, so that the error detection areas for the i-th and j-th frames are Error detection of.

Further, according to an aspect of the present invention, the circuit device may include an interface unit, and the position information and the expected value information may be set in the register unit by an external processing device via the interface unit.

According to one aspect of the present invention, the position information and the expected value information are set in the register unit by the external processing device via the interface unit, and the error detection area is set based on the position information and the expected value is set. Error detection in the error detection area can be performed based on the value information.

Further, according to an aspect of the present invention, the expected value information and the position information received during a blanking period of image data may be set in the register unit.

The frame image for which the processing device has obtained the expected value information and the frame image for which the circuit device performs error detection need to match. In this respect, according to the aspect of the present invention, by receiving the expected value information during the blanking period of the image data, the expected value information is the expected value information of the frame image received before the blanking period. There is a clear correspondence. The position information of the error detection area needs to be known before the error detection. In this regard, according to one aspect of the present invention, by receiving the position information in the blanking period of the image data, the position information is the position of the error detection area in the frame image received next to the blanking period. Information is clearly associated.

Further, in an aspect of the present invention, a plurality of error detection areas may be set as each of the error detection areas of the i-th frame error detection area and the j-th frame error detection area.

In one aspect of the present invention, the error detection area for the i-th frame and the error detection area for the i-th frame are set so that the number of error detection areas for the i-th frame is different from the number of error detection areas for the j-th frame. The error detection area for the j-th frame may be set.

According to these aspects of the present invention, a plurality of error detection areas are set as the error detection areas for each frame, or a different number of error detection areas are set as the error detection areas for each frame. As a result, it is possible to freely set the error detection area, such as setting an appropriate error detection area according to the content of the display image.

Further, in one aspect of the present invention, the error detection unit, based on a count value of a frame counter, the error detection area for the i-th frame and the j-th frame, which are targets of error detection, among a plurality of error detection areas. An error detection area setting unit that sets an error detection area for a frame may be included.

According to one aspect of the present invention, an error detection area to be an error detection target in each frame is set from a plurality of error detection areas. As a result, a plurality of error detection areas can be set as the error detection areas for the i-th and j-th frames, and a different number of error detection areas can be set as the error detection areas for the i-th and j-th frames. It becomes possible to control.

Further, in one aspect of the present invention, the error detection area setting unit is for the kth frame in the kth frame image of the first to nth frame images when k is an integer of 1 or more and n or less. The error detection area may be set such that the error detection area and the error detection area for the (k+1)th frame in the (k+1)th frame image are adjacent to each other.

According to this embodiment, the error detection area is sequentially shifted to the adjacent area for each frame. This makes it possible to detect an error in the entire image over a plurality of frames without any gap, and improve the accuracy of error detection.

Another aspect of the present invention is an electro-optical device including the circuit device according to any one of the above, a display driver that drives a display panel based on information from the circuit device, and the display panel. Involved.

Still another aspect of the present invention relates to an electronic device including the circuit device described in any of the above.

Yet another aspect of the present invention relates to a moving body including the circuit device described in any of the above.

Configuration example of circuit device. Explanatory drawing of the 1st method of error detection. Explanatory drawing of the 2nd method of error detection. Explanatory drawing of the 3rd method of error detection. Explanatory drawing of the 4th method of error detection. A detailed configuration example of the error detection unit, the error signal output unit, and the register unit. The 2nd detailed structural example of a register part. The timing chart of error detection processing. FIG. 9A is a configuration example of an electro-optical device. FIG. 9B is a configuration example of an electronic device. FIG. 9C is a configuration example of a moving body.

Hereinafter, preferred embodiments of the present invention will be described in detail. Note that the present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all the configurations described in the present embodiment are essential as a solution means of the present invention. Not necessarily.

1. Circuit Device FIG. 1 shows a configuration example of the circuit device 100 (display controller) of the present embodiment. The circuit device 100 includes a timing control unit 110 (timing control circuit), an image processing unit 120 (image processing circuit), an error detection unit 130 (error detection circuit), an error signal output unit 140 (error signal output circuit), and a register unit 150. (Register), and interface units 160 and 170 (interface circuit). The circuit device 100 is realized by, for example, an integrated circuit device (IC).

The interface unit 160 communicates between the processing device 200 and the circuit device 100. For example, the interface unit 160 receives the image data transmitted from the processing device 200 to the image processing unit 120 and the timing control signal (for example, a clock signal, a vertical synchronization signal, a horizontal signal) transmitted from the processing device 200 to the timing control unit 110. (Synchronization signal, data enable signal, etc.) and the register value written in the register unit 150 from the processing device 200. Alternatively, the interface unit 160 transmits an error signal (error detection signal) output by the error signal output unit 140 to the processing device 200, or transmits a register value read from the register unit 150 by the processing device 200.

As a communication system for image data and a timing control signal, for example, a LVDS (Low Voltage Differential Signal) system, an RGB serial system, a display port standard transmission system, or the like can be adopted. As an error signal or register value communication method, an I2C method, a 3-wire or 4-wire serial transmission method, or the like can be adopted. The interface section 160 is composed of an input/output buffer circuit and a control circuit (for example, a PLL circuit or the like in the LVDS method) that realizes these communication methods.

When the circuit device 100 is mounted on, for example, an automobile, the processing device 200 is an ECU (Electronic Control Unit). Alternatively, when the circuit device 100 is mounted on an electronic device such as an information communication terminal, the processing device 200 is a processor such as a CPU (Central Processing Unit) or a microprocessor.

The timing control unit 110 controls the respective units of the circuit device 100 based on the timing control signal from the processing device 200 and a timing control signal (for example, a clock signal, a vertical synchronization signal, a horizontal synchronization signal, or a data) transmitted to the display driver 300. Enable signal).

The image processing unit 120 generates various image processing (for example, gradation correction and the like) and data shaping processing (image data (display data) from the processing device 200) and transmission data suitable for the data receiving method of the display driver 300. Process).

The interface unit 170 performs communication between the circuit device 100 and the display driver 300. For example, the interface unit 170 transmits the image data output by the image processing unit 120 to the display driver 300 and the timing control signal output by the timing control unit 110 to the display driver 300. The interface unit 170 may also transmit a setting signal (for example, a mode setting signal) that controls the operation of the display driver 300 to the display driver 300. As the communication method, the same method as the interface unit 160 can be adopted.

The display driver 300 is a circuit device that drives a display panel (for example, a liquid crystal display panel, an electrophoretic display panel, etc.). The display driver 300 supplies, for example, a data driver that drives the data lines of the display panel, a scan driver that drives the scan lines of the display panel, a control circuit that controls them, and a power supply voltage and a reference voltage to each unit of the display driver 300. It is composed of a power circuit.

The error detection unit 130 performs error detection processing on the image data from the processing device 200. Hereinafter, a case where the error detection unit 130 performs an error detection process by a CRC (Cyclic Redundancy Check) will be described as an example. The error detection method is not limited to CRC, and a checksum method or the like can be used.

The processing device 200 writes the position information of the error detection area and the expected value of CRC (expected value information of error detection) in the error detection area in the register unit 150. The error detection unit 130 refers to the position information of the error detection area stored in the register unit 150, and calculates the CRC value (calculated value) in the error detection area from the image data. Then, the error detection unit 130 compares the calculated CRC value with the expected value stored in the register unit 150, outputs an inactive detection signal when they match, and when they do not match. Outputs an active detection signal.

The error signal output unit 140 outputs the error signal to the processing device 200 when the detection signal from the error detection unit 130 is active. The error signal is, for example, an interrupt request signal (IRQ: Interrupt ReQuest). Alternatively, the error signal may be a signal that simply signals that an error has been detected (becomes active when an error is detected).

As will be described later with reference to FIGS. 2 to 5, a plurality of error detection areas are set for the image in this embodiment. The error detection unit 130 performs error detection on the image data in each error detection area and outputs a detection signal for each error detection area (that is, outputs a plurality of detection signals). Then, the error signal output unit 140 outputs an error signal when at least one of the plurality of detection signals is active.

The timing control unit 110, the image processing unit 120, the error detection unit 130, the error signal output unit 140, and the register unit 150 are logic circuits (for example, AND circuits, OR circuits, gate circuits such as inverter circuits, and flip-flop circuits). The gate array in which the functional circuits are arranged). Each of these units represents a functional block, and may be configured as an integrated logic circuit as hardware or may be configured as an individual logic circuit.

2. Error Detection Method The error detection method of this embodiment will be described in detail below.

FIG. 2 shows an explanatory diagram of the first method of error detection. In the first method, first to fourth error detection areas AR1 to AR4 are set. The size (width, height) of each error detection area is smaller than the size of the image IMG. That is, error detection is performed not on the entire image IMG but on some error detection areas AR1 to AR4.

The error detection areas AR1 to AR4 are designated by start points SP1 to SP4 and end points EP1 to EP4. Specifically, the error detection areas AR1 to AR4 are specified by setting the coordinates of the start points SP1 to SP4 and the coordinates of the end points EP1 to EP4 as position information in the register unit 150. For example, coordinates x in the horizontal scanning direction and coordinates y in the vertical scanning direction are defined with the coordinates of the upper left pixel of the image IMG as the origin. The pixel with the smallest coordinates x and y is the start point, and the pixel with the largest coordinates x and y is the end point.

In the first method, error detection for the error detection areas AR1 to AR4 is performed in each frame. Specifically, the following series of processing is performed on each frame image. That is, the processing device 200 calculates the CRC value in each of the error detection areas AR1 to AR4 and writes the CRC value in the register unit 150 as an expected value. Then, the error detection unit 130 calculates the CRC value in each of the error detection areas AR1 to AR4 and compares the calculated value with the expected value. The error signal output unit 140 outputs an interrupt request signal (error signal in a broad sense) to the processing device 200 when there is one or more error detection areas where the calculated value and the expected value do not match.

Various operations can be assumed when the processing device 200 receives the interrupt request signal. For example, the processing device 200 may stop the transmission of the image data to the circuit device 100, or the processing device 200 may perform a specific display control (for example, black display (the entire screen is black) or a predetermined pattern display). May be instructed to the circuit device 100. Alternatively, the processing device 200 may stop the operation of the circuit device 100 or reset the circuit device 100.

The number of error detection areas is not limited to four, and two or more arbitrary error detection areas can be set. In FIG. 2, the error detection areas AR1 to AR4 are areas that do not overlap each other, but the invention is not limited to this and may be areas that partially overlap. The position information that specifies the error detection area is not limited to the start point and the end point, and may be any information that can determine the area. For example, the coordinates of the start point of the error detection area, the horizontal width (the number of pixels in the horizontal scanning direction), and the vertical width (the number of pixels in the vertical scanning direction) may be used.

According to the first method, error detection is performed not on the entire image but on a part of the error detection area. As a result, the amount of data for the processing device 200 to calculate the CRC value is reduced, and the processing load on the processing device 200 can be reduced. Also, by setting a plurality of error detection areas, it is possible to detect errors in a wider area of the image, and it is possible to reduce detection omissions. If an error detection area is set in a particularly important area, efficient error detection can be performed.

FIG. 3 shows an explanatory diagram of the second method of error detection. In the second method, error detection is performed on one frame image in one error detection area. As shown in FIG. 3, for example, error detection is performed in the first error detection area AR1 for the frame image IMG1 of the first frame, and error is detected in the second error detection area AR2 for the frame image IMG2 of the second frame. The detection is performed on the frame image IMG3 of the third frame in the third error detection area AR3, and the error detection is performed on the frame image IMG4 of the fourth frame in the fourth error detection area AR4. This is similarly repeated after the fifth frame.

For example, taking the first frame as an example, the processing device 200 calculates a CRC value in the error detection area AR1 of the frame image IMG1 and writes the calculated CRC value in the register unit 150 as an expected value. Then, the error detection unit 130 calculates the CRC value in the error detection area AR1 of the frame image IMG1 and compares the calculated value with the expected value. The error signal output unit 140 outputs an interrupt request signal to the processing device 200 when the calculated value and the expected value do not match. In the second to fourth frames, similar error detection processing is performed on the second to fourth error detection areas AR2 to AR4. The position information of the error detection areas AR1 to AR4 is designated by the coordinates of the start point and the end point as in the first method.

The error detection area used in each frame is controlled as follows, for example. That is, the position information of the error detection areas AR1 to AR4 is collectively written in the register unit 150, and which frame is used for which error detection area is controlled based on the output of the frame counter. At this time, the processing device 200 writes a register value that specifies which error detection area is valid in each frame into the register unit 150, and the error detection unit 130 detects the error detection specified by the register value in each frame. Area error detection is performed. Alternatively, the error detection unit 130 performs error detection on all the error detection areas AR1 to AR4 in each frame, and the error signal output unit 140 validates only the error detection result of the error detection area designated by the register value ( Such weighting may be performed) and the interrupt request signal may be output only based on the valid error detection result.

According to the second method, error detection is performed not for the entire image but for a part of the error detection area, and a different error detection area is set for each frame. As a result, the amount of data for the processing device 200 to calculate the CRC value is reduced, and the processing load on the processing device 200 can be reduced. Also, by setting different error detection areas in each frame, it is possible to detect errors in a wider area of the image, and it is possible to reduce detection omissions.

FIG. 4 shows an explanatory diagram of the third method of error detection. In the third method, error detection is performed in different numbers of error detection areas in the frame image of the first frame and the frame image of the second frame. As shown in FIG. 4, for example, error detection is performed in the first error detection area AR1 in the frame image IMG1 of the first frame, and second to fourth error detection areas in the frame image IMG2 of the second frame. Error detection is performed in AR2 to AR4. This is similarly repeated for the third and subsequent frames. Alternatively, further error detection is performed, such as performing error detection in the first and second error detection areas AR1 and AR2 in the third frame and performing error detection in the third and fourth error detection areas AR3 and AR4 in the fourth frame. The number of areas may be changed.

The position information of the error detection areas AR1 to AR4 is designated by the coordinates of the start point and the end point as in the first method. The error detection area used in each frame is controlled by the same method as the second method.

According to the third method, it is possible to reduce the processing load on the processing device 200 and detect an error in a wider area of the image, as in the second method.

FIG. 5 shows an explanatory diagram of the fourth method of error detection. In the fourth method, the image is divided into a plurality of areas, the divided areas are sequentially selected for each frame, and error detection is performed using the selected divided area as an error detection area. For example, in FIG. 5, 8 rows×(M/2) columns of divided areas are set, and 2 rows have M divided areas (M is an integer of 3 or more, and in the example of FIG. 5, M is an even number) divided areas. Are arranged. The divided areas on the first and second rows are AR11 to AR1M (error detection areas of the first group), and the divided areas on the third and fourth rows are AR21 to AR2M (error detection areas of the second group), The divided areas on the fifth and sixth rows are AR31 to AR3M (error detection areas of the third group), and the divided areas on the seventh and eighth rows are AR41 to AR4M (error detection areas of the fourth group). .. In the frame image IMG1 of the first frame, the divided areas AR11, AR21, AR31, AR41 are error detection areas, and in the frame image IMG2 of the second frame, the divided areas AR12, AR22, AR32, AR42 are error detection areas. This is repeated up to the Mth frame, and the M+1th frame becomes an error detection area similar to the first frame.

The error detection area in each frame is controlled as follows, for example. That is, the processing device 200 writes the position information of the divided areas (error detection areas) AR11, AR21, AR31, AR41 in the register unit 150 in the first frame, and the divided areas (error detection areas) AR12, AR22 in the second frame. The position information of AR32 and AR42 is written in the register unit 150. By repeating this up to the Mth frame, the error detection area in each frame is controlled. In this case, the position information is the coordinates of the start point and the end point of each divided area.

Alternatively, the processing device 200 uses the position information (coordinates of the start point and the end point) of the first divided areas AR11, AR21, AR31, AR41 in the error detection areas of the first to fourth groups and the final divided areas AR1M, AR2M, AR3M. , AR4M position information (coordinates of the end point) are written in the register unit 150. The error detection unit 130 obtains the coordinates of the start point and the end point of each divided area from the position information. For example, when the width of the divided area AR11 is 100 pixels, the coordinates obtained by shifting the coordinates of the start point SP11 and the end point EP11 of the divided area AR11 by 100 in the horizontal scanning direction become the coordinates of the start point and the end point of the divided area AR12. When the coordinates of the end point thus obtained match the coordinates of the end point EP1M of the divided area AR1M, that area is set as the final divided area. The error detection unit 130 controls the error detection region in each frame by shifting the divided region one by one each time a vertical synchronization signal is input and updating the register unit 150 with the position information of the divided region. To do.

In addition, the error detection may be performed on all the groups of the error detection areas of the first to fourth groups, or may be performed on a part thereof (arbitrary 1 group, 2 groups or 3 groups). For example, in the first to Mth frames, error detection is performed for all the groups of the first to fourth error detection areas, and in the next M+1 to 2Mth frames, error detection is performed only in the fourth group of error detection areas. You may go. For example, the processing device 200 controls which group is enabled by writing a register value instructing which group is enabled in the register unit 150. For example, when the upper 3/4 of the image is black and only the lower ¼ is displayed, the error detection area of the fourth group corresponding to the lower ¼ is validated. Since the processing device 200 knows what the image data looks like, such control is possible. Since the reliability of the CRC (error detection rate) becomes low in an image containing a lot of continuous black image data, the processing load of the processing device 200 can be reduced by omitting the calculation of the CRC value in such an area. Can be reduced.

According to the fourth method, the processing load of the processing device 200 can be reduced similarly to the second and third methods. In addition, by sequentially selecting the divided areas for each frame, an error is detected for the entire image, and it is possible to further reduce the omission of detection.

When detecting a communication error of image data for the entire image, the processing device 200 calculates an expected value for error detection for the entire image, which increases the amount of data to be calculated and increases the processing load. On the other hand, when the error detection area is a fixed area smaller than the entire image, the processing load on the processing device 200 is reduced, but the error detection can be performed only on a part of the image.

In this regard, in the present embodiment, the circuit device 100 includes an error detection unit 130 that detects an error in the image data, and an error signal output unit 140 that outputs an error signal based on the result of the error detection. It is assumed that n is an integer of 2 or more, i and j are integers of 1 or more and n or less, and i≠j. An error detection area for the i-th frame is set for the i-th frame image of the first-nth frame images, and for the j-th frame image of the first-nth frame images, The error detection area for the j-th frame is set at a position different from the error detection area for the i-th frame. In this case, the error detection unit 130 performs error detection based on the image data of the error detection area for the i-th frame and the error detection area for the j-th frame. The error signal output unit 140 outputs an error signal based on the result of error detection in the error detection area for the i-th frame and the error detection area for the j-th frame.

According to this embodiment, in the i-th frame image, error detection is performed in the error detection area for the i-th frame, and in the j-th frame image, error detection is performed in the error detection area for the j-th frame. The error detection areas for the i-th and j-th frames are different in position. As a result, it is possible to perform error detection in error detection areas at different positions in each frame, and it is possible to detect errors in a wide range of an image. Further, in one frame, error detection is performed in an area smaller than the entire image, so that the processing load of the processing device 200 can be reduced.

Here, the error detection is to check whether or not the image data which the processing device 200 tries to send to the circuit device 100 and the image data which the circuit device 100 actually receives match (communication error). Detection). The error signal is a signal relating to the result of error detection, and is, for example, a signal indicating whether or not an error in image data has been detected, or a signal requesting the processing device 200 to perform some operation according to the result of error detection. is there. The frame image is an image displayed in one frame (or an image to be displayed). For example, when the display on the display panel is updated at 30 fps (frames per second), 1/30 second is one frame, and an image drawn in the one frame is a frame image. The frame image here is an image at the stage when the processing device 200 has transmitted to the circuit device 100. That is, the frame image that is finally displayed and the frame image that is the target of error detection are not necessarily the same image because image processing may be performed during that time.

For example, in the second method of FIG. 3, n=4. Taking the case of i=1 and j=2 as an example, the error detection area for the i-th frame is AR1, and the error detection area for the j-th frame is AR2. The positions of these error detection areas AR1 and AR2 are different. In the example of FIG. 3, the positions correspond to the start point and end point of the area. However, the position of the area is not limited to this, and for example, only the start point or the center point of the area (for example, the point where two diagonal lines intersect) may be the position.

In the third method of FIG. 4, n=2. When i=1 and j=2, the error detection area for the i-th frame is AR1, and the error detection areas for the j-th frame are AR2 to AR4. As described above, the error detection area for the i-th frame and the j-th frame may be composed of a plurality of areas. In this case, the position of the area is the position of each area of the plurality of areas (for example, the start point and the end point), and any one of the plurality of areas may have different positions. For example, in the example of FIG. 4, each of the error detection areas AR2 to AR4 for the j-th frame is different in position from the error detection area AR1 for the i-th frame. For example, the error detection area for the j-th frame may be AR1 and AR2. In this case, the area AR2 is different in position from the error detection area AR1 for the i-th frame.

In the fourth method of FIG. 5, n=M. If i=1 and j=2, the error detection areas for the i-th frame are AR11 to AR41, and the error detection areas for the j-th frame are AR12 to AR42.

Further, in the present embodiment, the circuit device 100 includes the register unit 150 that stores the position information of the error detection area for the i-th frame and the error detection area for the j-th frame. The error detection area for the i-th frame and the error detection area for the j-th frame are set based on the position information stored in the register unit 150.

As described with reference to FIG. 2 and the like, the position information is, for example, the coordinates of the start points SP1 to SP4 (the coordinates of the pixels corresponding to the start points) and the coordinates of the end points EP1 to EP4 (the coordinates of the pixels corresponding to the end points). In this case, the error detection unit 130 sets a square area having a diagonal line connecting the start point and the end point as an error detection area.

According to the present embodiment, the position information of the error detection areas for the i-th and j-th frames is written in the register unit 150, so that the error detection area to be the target of error detection can be set. Then, as position information of the error detection areas for the i-th and j-th frames, different position information is written in the register unit 150, so that error detection areas for the i-th and j-th frames having different positions can be set. ..

Further, in this embodiment, the register unit 150 stores expected value information for error detection together with position information of the error detection area for the i-th frame and the error detection area for the j-th frame. The error detection unit 130 detects an error based on the expected value information.

The expected value information is obtained by the processing device 200 on the transmission side. For example, the expected value information of the error detection area for the i-th frame is calculated by the processing device 200 from the i-th frame image display data. It is obtained from the display data of the error detection area for the frame.

According to the present embodiment, expected value information for error detection corresponding to the error detection areas for the i-th and j-th frames is written in the register unit 150, so that the error detection areas for the i-th and j-th frames are Error detection is possible.

Further, in the present embodiment, the circuit device 100 includes the interface unit 160. The position information and the expected value information are set in the register unit 150 by the external processing device 200 via the interface unit 160.

For example, the position information and the expected value information are written in the register unit 150 by an interface different from the image data by I2C communication, 3-line or 4-line serial communication, or the like. Alternatively, the expected value information may be written in the register unit 150 via the image data interface. In this case, expected value information is transmitted during a period in which image data is not transmitted (for example, a blanking period described later). For example, when the image data of one pixel is 24 bits (8 bits for each RGB) and the expected value information is a 16-bit CRC value, the 16-bit CRC value is embedded in the 24-bit data of the same format as the image data for transmission. To do. For example, 16 bits of RG of each 8 bits of RGB are transmitted as a CRC value by the processing device 200, and the interface section 160 extracts 16 bits of RG of the received 24 bits and writes them in the register section 150 as expected value information. The timing control of the timing control unit 110 can determine at which timing the image data received is the expected value information.

According to the present embodiment, the position information and the expected value information are set in the register unit 150 by the external processing device 200 via the interface unit 160, and the error detection area is set based on the position information. It is possible to detect an error in the error detection area based on the expected value information.

Further, in this embodiment, the expected value information and the position information received during the blanking period of the image data are set in the register unit 150.

The blanking period is a non-transmission period of image data, and is, for example, a vertical blanking period. As shown in FIG. 8 to be described later, the vertical blanking period is a transmission period of image data of a frame image (a period including a horizontal scanning period in which a data valid period exists) and a transmission period of image data of the next frame image. And (a period including a horizontal scanning period in which a data valid period does not exist).

The frame image in which the processing device 200 has obtained the expected value information and the frame image in which the circuit device 100 performs error detection need to match. In this regard, according to the present embodiment, the expected value information is received during the blanking period of the image data, and the expected value information is the expected value information of the frame image received before the blanking period. Are clearly associated. The position information of the error detection area needs to be known before the error detection. In this regard, according to the present embodiment, by receiving the position information in the blanking period of the image data, the position information is the position information of the error detection area in the frame image received next to the blanking period. There is a clear correspondence.

Further, in the present embodiment, a plurality of error detection areas are set as each error detection area of the i-th frame error detection area and the j-th frame error detection area.

For example, in the third method of FIG. 4, three error detection areas AR2 to AR4 are set as the error detection areas for the second frame. In the fourth method of FIG. 5, four divided areas (for example, AR11 to AR41) are set as the error detection area for each frame.

In the present embodiment, the number of error detection areas for the i-th frame and the number of error detection areas for the j-th frame are set to be different (variable number), and The error detection area for the j-th frame may be set.

For example, in the third method of FIG. 4, one error detection area AR1 is set as the error detection area for the first frame, and three error detection areas AR2 to AR4 are set as the error detection area for the second frame. It

According to this embodiment, a plurality of error detection areas are set as each error detection area, or a different number of error detection areas are set as each error detection area. As a result, it is possible to freely set the error detection area, such as setting an appropriate error detection area according to the content of the display image. For example, if a part of the image is displayed in a certain frame, one error detection area is set only in that part of the frame, and a wide range of the image is displayed in another frame. , In that frame, a plurality of error detection areas can be set within the range.

Further, as will be described later with reference to FIG. 6, the error detection unit 130 includes an error detection area setting unit 30. The error detection area setting unit 30 selects an error detection area for the i-th frame and an error detection area for the j-th frame, which are error detection targets, from the plurality of error detection areas based on the count value of the frame counter 31. Set.

Specifically, position information of a plurality of error detection areas is set in the register unit 150, and which error detection area among the plurality of error detection areas is to be subjected to error detection (or which error detection area is detected) Is output) is controlled by the error detection area setting unit 30 according to the count value. Such control corresponds to setting the error detection area based on the count value.

According to the present embodiment, the error detection area to be the error detection target in each frame is set from the plurality of error detection areas. As a result, a plurality of error detection areas can be set as the error detection areas for the i-th and j-th frames, and a different number of error detection areas can be set as the error detection areas for the i-th and j-th frames. It becomes possible to control.

Further, in the present embodiment, the error detection area setting unit 30 sets the error detection area for the kth frame in the kth frame image of the first to nth frame images when k is an integer of 1 or more and n or less. And the error detection area for the (k+1)th frame in the (k+1)th frame image are set to be adjacent to each other.

For example, in the fourth method of FIG. 5, k=1 and k+1=2. In this case, the error detection areas for the kth frame are AR11 to AR41, and the error detection areas for the k+1th frame are AR12 to AR42. The areas AR12, AR22, AR32, AR42 are areas adjacent to the areas AR11, AR21, AR31, AR41, respectively. Here, the regions being adjacent to each other means that one side of one region is adjacent to one side of the other region (for example, there is no pixel between them).

According to this embodiment, the error detection area is sequentially shifted to the adjacent area for each frame. This makes it possible to detect an error in the entire image over a plurality of frames without any gap, and improve the accuracy of error detection.

3. Detailed Configuration FIG. 6 shows a detailed configuration example of the error detection unit 130, the error signal output unit 140, and the register unit 150. The error detection unit 130 includes calculation units 11 to 14 (calculation circuit), comparison units 21 to 24 (comparison circuit), and an error detection area setting unit 30 (error area setting circuit). The register unit 150 includes first to fourth position information registers 51 to 54 and first to fourth expected value registers 61 to 64. It should be noted that although the case where there are four calculation units and the like is described here as an example, the number of calculation units and the like may be any number of 2 or more (for example, the same number as the maximum number of error detection areas that can be set).

The position information of the first to fourth error detection areas is written from the processing device 200 to the position information registers 51 to 54. The calculation units 11 to 14 read the position information from the position information registers 51 to 54, and calculate the CRC value (calculated value of CRC) of the first to fourth error detection areas from the image data PDT. As the CRC value (CRC data), one value (data) is calculated for the image data in the error detection area. For example, the CRC value is 16 bits, but is not limited to 16 bits.

The expected values of CRC of the first to fourth error detection areas are written from the processing device 200 to the expected value registers 61 to 64. The expected value of the CRC transmitted from the processing device 200 and the CRC value calculated by the calculation units 11 to 14 have the same number of bits and are calculated by the same arithmetic expression. The comparing units 21 to 24 calculate the expected CRC values of the first to fourth error detection areas from the expected value registers 61 to 64 and the CRC values of the first to fourth error detection areas from the calculating units 11 to 14. Compare with. The calculation units 11 to 14 output “0” (low level, inactive) as a detection signal when the expected value and the CRC value match, and output “0” (low level, inactive) as the detection signal when the expected value and the CRC value do not match. 1" (high level, active) is output.

The error signal output unit 140 adds the outputs of the comparison units 21 to 24, compares the added value with the reference value, and when the added value is equal to or greater than the reference value, outputs an error signal ERS (for example, an interrupt request signal to the CPU ) Is activated. For example, the reference value is "1". In that case, if at least one of the outputs of the comparison units 21 to 24 is “1”, the error signal ERS becomes active.

The error detection area setting unit 30 sets (controls) which of the first to fourth error detection areas is to be used for error detection in each frame. Specifically, the error detection area setting unit 30 includes a frame counter 31 that counts the vertical synchronization signal VSYNC, and selects an error detection area to be detected according to the count value of the frame counter 31.

The operation of the method described with reference to FIGS. 2 to 5 will be described below. The count value of the frame counter 31 is 0 to 15 (returns to 0 after 15), and the count values 0 to 15 correspond to the 1st to 16th frames.

For example, in the first method of FIG. 2, all of the first to fourth error detection areas AR1 to AR4 are valid regardless of the count value of the frame counter 31, and the error detection area setting unit 30 includes the calculation units 11 to 11. All 14 have their CRC values calculated.

In the second method of FIG. 3, when the count value of the frame counter 31 is 0, 4, 8, and 12, the first error detection area AR1 is valid and the second to fourth error detection areas AR2 to AF4 are invalid. Becomes That is, the error detection area setting unit 30 causes the calculation unit 11 to calculate the CRC value and disables the operations of the calculation units 12 to 14. The comparison units 22 to 24 corresponding to the disabled calculation units 12 to 14 output “0” (inactive). In this case, the processing device 200 writes the register value only to the first position information register 51 and the first expected value register 61. Similarly, the second error detection area AR2 is valid when the count values are 1, 5, 9, and 13, and the third error detection area AR3 is valid when the count values are 2, 6, 10, and 14. Therefore, when the count value is 3, 7, 11, or 15, the fourth error detection area AR4 becomes valid.

It should be noted that the following modified examples can be considered in the second method. That is, in any frame, the processing device 200 writes register values in the first to fourth position information registers 51 to 54 and the first to fourth expected value registers 61 to 64. Further, the calculation units 11 to 14 calculate the CRC value regardless of the count value, and the comparison units 21 to 24 compare the expected value and the CRC value. If the count values are 0, 4, 8, and 12, for example, the error detection area setting unit 30 causes the comparison unit 21 to perform weighting by multiplying the comparison result of the comparison unit 21 by 1. The comparison units 22 to 24 are weighted to multiply the comparison results of to 24 by 0. As a result, the comparison unit 21 outputs the comparison result, and the comparison units 22 to 24 output "0".

In the third method of FIG. 4, when the count value of the frame counter 31 is 0, 2, 4, 6, 8, 10, 12, and 14, the first error detection area AR1 is valid, and the count value of the frame counter 31 is Is 1, 3, 5, 7, 9, 11, 13, 15, the second to fourth error detection areas AR2 to AR4 are valid. The error detection area setting unit 30 controls the calculation units 11 to 14 and the comparison units 21 to 24 similarly to the second method. The same applies to the modified example.

In the fourth method of FIG. 5, in the first frame, the processing device 200 writes the position information of the error detection areas AR11 to AR41 in the first to fourth position information registers 51 to 54, and the first to fourth expected values. The expected value of the CRC of the error detection areas AR11 to AR41 is written in the registers 61 to 64. In the second frame, the processing device 200 writes the position information of the error detection areas AR12 to AR42 in the first to fourth position information registers 51 to 54, and the error detection areas in the first to fourth expected value registers 61 to 64. Write the expected CRC values of AR12 to AR42. In the subsequent frames, the area is similarly shifted. For example, when M=16, the error detection areas AR1M to AR4M become effective in the 16th frame.

The error detection area setting unit 30 causes the calculation units 11 to 14 to calculate the CRC value and outputs the comparison results to the comparison units 21 to 24 regardless of the count value of the frame counter 31. Alternatively, the error detection area setting unit 30 may set any one of the calculation units 11 to 14 to enable and set the other to disable. For example, the calculation units 11 to 13 are set to be disabled, and the calculation unit 14 is set to be enabled. In this case, only the error detection areas AR41 to AR4M of the fourth group are the targets of error detection. Note that similar operations may be realized by weighting in the comparison units 21 to 24 as in the modification described in the second method. That is, the calculation units 11 to 14 may calculate the CRC value, the comparison units 21 to 23 may multiply the comparison result by 0, and the comparison unit 24 may multiply the comparison result by 1.

The operation of the error detection area setting unit 30 as described above is realized by register setting, for example. For example, the processing device 200 stores a register value that associates the count value of the frame counter 31 with which of the calculation units 11 to 14 is enabled (or weighted by the comparison units 21 to 24) for each count value. It is written in the register unit 150, and the error detection area setting unit 30 refers to it to operate. Alternatively, the processing device 200 writes the mode setting value for switching the first to fourth methods as a register value in the register unit 150, and the error detection area setting unit 30 refers to it to operate. In this case, the error detection area setting unit 30 voluntarily controls which of the calculation units 11 to 14 is to be enabled (or the weighting of the comparison units 21 to 24) for each count value.

FIG. 7 shows a second detailed configuration example of the register section 150. In FIG. 7, the register unit 150 further includes first to fourth calculated value registers 71 to 74.

The CRC values (calculated values of CRC) calculated by the calculation units 11 to 14 are stored in the first to fourth calculated value registers 71 to 74. The processing device 200 can read the CRC value from the first to fourth calculated value registers 71 to 74 via the interface unit 160.

Since only the error signal ERS from the error signal output unit 140 is input to the processing device 200, it is possible to know the communication error of the image data, but it is not possible to know in which error detection area the error occurred. .. In the present embodiment, the processing device 200 can know in which error detection area an error has occurred by referring to the calculated value registers 71 to 74.

When the processing device 200 receives the active error signal ERS, the processing device 200 reads the CRC value from the calculated value registers 71 to 74 and compares it with the expected value to determine in which error detection area the error has occurred. For example, the processing device 200 can perform processing according to the region in which the error has occurred, such as retransmitting the image data in the region in which the error has occurred to the circuit device 100 to redraw the image data.

FIG. 8 shows a timing chart of the error detection process. The vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, and the data enable signal DE are supplied from the processing device 200 to the timing control unit 110 of the circuit device 100. Note that the timing control unit 110 may generate these signals based on some synchronization signal supplied from the processing device 200, without being limited to the case where these signals are directly supplied from the processing device 200.

The vertical synchronization signal VSYNC is a signal that defines a vertical scanning period (frame), and one vertical scanning period is from the fall of the vertical synchronization signal VSYNC to the next fall. Image data of one frame image is transmitted from the processing device 200 to the circuit device 100 in one vertical scanning period.

The horizontal synchronizing signal HSYNC is a signal that defines the horizontal scanning period, and one horizontal scanning period is from the falling edge of the horizontal synchronizing signal HSYNC to the next falling edge. The image data of one horizontal scanning line is transmitted from the processing device 200 to the circuit device 100 in one horizontal scanning period.

The data enable signal DE becomes active (high level) during a part of the horizontal scanning period (data valid period), and the image data of the horizontal scanning line is transmitted from the processing device 200 to the circuit device 100 during that period. The period between the data valid period and the data valid period is called a horizontal blanking period, and image data is not transmitted during this period. A vertical blanking period is provided for switching the vertical scanning period, and the data enable signal DE becomes inactive (low level) during the vertical blanking period. Image data is not transmitted during this period. In the example of FIG. 8, the vertical blanking period corresponds to four horizontal blanking periods, and the vertical synchronizing signal VSYNC becomes low level during two horizontal blanking periods. The image data of the frame image is transmitted until the vertical blanking period ends and the next vertical blanking period starts.

The error detection process is executed during the vertical blanking period. That is, in the first register access period TA1 after the vertical blanking period is started, the processing device 200 writes the expected CRC value in the expected value registers 61 to 64. This expected value is an expected value obtained from the image data transmitted in the frame immediately before the vertical blanking period. In the error detection period TB1 after the first register access period TA1, the comparison units 21 to 24 compare the CRC value calculated by the calculation units 11 to 14 with the expected value. Note that the calculation units 11 to 14 calculate the CRC value from the image data transmitted in the frame immediately before the vertical blanking period. This calculation process is sequentially performed as the image data is input (that is, it is not always performed in the vertical retrace line period), and ends before the error detection period TB1. In the second register access period TA2 after the error detection period TB1, the processing device 200 writes the position information of the error detection area in the position information registers 51 to 54. This position information is the position information of the error detection area applied to the image data transmitted in the frame immediately after the vertical blanking period.

4. Electro-Optical Device, Electronic Device, Moving Object FIG. 9A shows a configuration example of an electro-optical device (display device) including the circuit device 100 of the present embodiment. The electro-optical device includes a circuit device 100 (display controller), a display panel 360, and a display driver 300 that drives the display panel 360 under the control of the circuit device 100.

The display panel 360 includes, for example, a glass substrate and a pixel array (liquid crystal cell array) formed on the glass substrate. The pixel array includes pixels, data lines, and scan lines. The display driver 300 is mounted on a glass substrate, and the display driver 300 and the pixel array are connected by a wiring group formed of transparent electrodes (ITO: Indium Tin Oxide). The circuit device 100 is mounted on a circuit board different from the glass board, and the circuit board and the glass board are connected by a flexible board or the like. The electro-optical device is not limited to this configuration. For example, the display driver 300 and the circuit device 100 may be mounted on a circuit board, and the circuit board and the display panel 360 may be connected by a flexible board or the like.

FIG. 9B shows a configuration example of an electronic device including the circuit device 100 of this embodiment. As the electronic device of the present embodiment, for example, a vehicle-mounted display device (for example, a meter panel), a display, a projector, a television device, an information processing device (computer), a portable information terminal, a car navigation system, a portable game terminal, a DLP. Various electronic devices equipped with a display device such as a (Digital Light Processing) device can be assumed.

The electronic device includes a CPU 310 (processing device), a circuit device 100 (display controller), a display driver 300, a display panel 360, a storage unit 320 (memory), an operation unit 330 (operation device), a communication unit 340 (communication circuit, communication device). )including.

The operation unit 330 is a user interface that receives various operations from the user. For example, it is composed of a button, a mouse, a keyboard, a touch panel mounted on the display panel 360, and the like. The communication unit 340 is a data interface that performs communication (transmission, reception) of image data and control data. For example, it is a wired communication interface such as USB or a wireless communication interface such as a wireless LAN. The storage unit 320 stores the image data input from the communication unit 340. Alternatively, the storage unit 320 functions as a working memory of the CPU 310. The CPU 310 performs control processing of various parts of the electronic device and various data processing. The circuit device 100 performs control processing of the display driver 300. For example, the circuit device 100 converts the image data transferred from the communication unit 340 or the storage unit 320 via the CPU 310 into a format that the display driver 300 can accept, and outputs the converted image data to the display driver 300. To do. The display driver 300 drives the display panel 360 based on the image data transferred from the circuit device 100.

FIG. 9C shows a configuration example of a moving body including the circuit device 100 of this embodiment. As the moving body of this embodiment, various moving bodies such as a car, an airplane, a motorcycle, a ship, or a robot (a traveling robot or a walking robot) can be assumed. The moving body is a device/device that includes a drive mechanism such as an engine and a motor, a steering mechanism such as a steering wheel and a rudder, and various electronic devices, and moves on the ground, in the air, or on the sea.

FIG. 9C schematically shows an automobile 206 as a specific example of the moving body. A display device 350 (electro-optical device) having the circuit device 100 and an ECU 510 for controlling each unit of the car 206 are incorporated in the car 206. The ECU 510 generates an image (image data) that presents information such as vehicle speed, remaining fuel amount, mileage, setting of various devices (eg, air conditioner) to the user, and transmits the image to the display device 350 for display. It is displayed on the panel 360.

Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Therefore, all such modifications are included in the scope of the present invention. For example, in the specification or the drawings, a term described together with a different term having a broader meaning or the same meaning at least once can be replaced with the different term in any place in the specification or the drawing. Further, all combinations of the present embodiment and modifications are also included in the scope of the present invention. The configurations and operations of the circuit device, the processing device, the display driver, the electro-optical device, the electronic device, and the moving body are not limited to those described in the present embodiment, and various modifications can be made.

11 to 14... Calculation unit, 21 to 24... Comparison unit, 30... Error detection area setting unit,
31... Frame counter, 51-54... First to fourth position information registers,
61 to 64... First to fourth expected value registers, 71... First to fourth calculated value registers,
100... Circuit device, 110... Timing control section, 120... Image processing section,
130...Error detection unit, 140...Error signal output unit, 150...Register unit,
160... Interface unit, 170... Interface unit, 200... Processing device,
206... Automotive, 300... Display driver, 310... CPU, 320... Storage unit,
330... Operation unit, 340... Communication unit, 350... Display device, 360... Display panel,
510... ECU,
AR1 to AR4... error detection area, EP1 to EP4... end point, ERS... error signal,
IMG1 to IMG4... Frame image, PDT... Image data, SP1 to SP4... Starting point

Claims (11)

An error detection unit that detects errors in image data,
An error signal output unit that outputs an error signal based on the result of the error detection,
A register unit that stores the error detection area and the position information of the error detection area,
Including
The error detection unit,
When n is an integer of 2 or more, i and j are integers of 1 or more and n or less, and i≠j, the i-th frame of the i-th frame image of the first to n-th frame images Error detection area for the j-th frame is set at a position different from the error detection area for the i-th frame with respect to the j-th frame image of the first to n-th frame images. When an area is set, the error detection is performed based on the image data of the error detection area for the i-th frame and the error detection area for the j-th frame,
The error signal output unit,
Outputting the error signal based on a result of the error detection in the error detection area for the i-th frame and the error detection area for the j-th frame,
The circuit device , wherein the error detection area for the i-th frame and the error detection area for the j-th frame are set based on the position information stored in the register unit . In claim 1 ,
The register section is
Together with the position information of the error detection area for the i-th frame and error detection region of the j-th off for frame stores an expected value information error detection,
The error detection unit,
A circuit device for detecting an error based on the expected value information. In claim 2 ,
Including the interface part,
The circuit device, wherein the position information and the expected value information are set in the register unit by an external processing device via the interface unit. In claim 2 or 3 ,
A circuit device, wherein the expected value information and the position information received during a blanking period of image data are set in the register unit. In any one of Claim 1 thru|or 4 ,
A circuit device, wherein a plurality of error detection areas are set as each of the error detection areas of the i-th frame error detection area and the j-th frame error detection area. In any one of Claim 1 thru|or 5 ,
The error detection area for the i-th frame and the error detection area for the j-th frame are set such that the number of error detection areas for the i-th frame is different from the number of error detection areas for the j-th frame. A circuit device in which a region is set. In any one of Claim 1 thru|or 6 ,
The error detection unit,
An error detection area setting unit that sets an error detection area for the i-th frame and an error detection area for the j-th frame to be subjected to error detection from a plurality of error detection areas based on the count value of the frame counter. A circuit device comprising: In claim 7 ,
The error detection area setting unit,
When k is an integer of 1 or more and n or less, the error detection area for the kth frame in the kth frame image of the first to nth frame images and the k+1th frame in the k+1th frame image A circuit device, wherein the error detection area is set so as to be adjacent to the error detection area. A circuit device according to any one of claims 1 to 8 ,
A display driver that drives the display panel based on information from the circuit device;
The display panel,
An electro-optical device comprising: An electronic apparatus comprising the circuit apparatus according to any one of claims 1 to 8. A mobile body comprising the circuit device according to any one of claims 1 to 8 .

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