JP6840236B2 - パイプライン高スループット階層化ｌｄｐｃデコーダアーキテクチャ - Google Patents

パイプライン高スループット階層化ｌｄｐｃデコーダアーキテクチャ Download PDF

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JP6840236B2
JP6840236B2 JP2019519683A JP2019519683A JP6840236B2 JP 6840236 B2 JP6840236 B2 JP 6840236B2 JP 2019519683 A JP2019519683 A JP 2019519683A JP 2019519683 A JP2019519683 A JP 2019519683A JP 6840236 B2 JP6840236 B2 JP 6840236B2
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ヴィンセント・ロンケ
ギリシュ・ヴァラトカル
トーマス・ジョセフ・リチャードソン
イ・カオ
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/002—Error detection; Error correction; Monitoring protecting against parasitic influences, e.g. noise, temperatures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/004—Error avoidance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3006—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1443—Transmit or communication errors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Retry When Errors Occur (AREA)
JP2019519683A 2016-11-02 2017-09-23 パイプライン高スループット階層化ｌｄｐｃデコーダアーキテクチャ Active JP6840236B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662416584P 2016-11-02 2016-11-02
US62/416,584 2016-11-02
US15/712,845 US10778371B2 (en) 2016-11-02 2017-09-22 Deeply-pipelined high-throughput LDPC decoder architecture
US15/712,845 2017-09-22
PCT/US2017/053128 WO2018084956A1 (en) 2016-11-02 2017-09-23 Pipelined high-throughput layered ldpc decoder architecture

Publications (3)

Publication Number Publication Date
JP2019536316A JP2019536316A (ja) 2019-12-12
JP2019536316A5 JP2019536316A5 (https=) 2020-11-19
JP6840236B2 true JP6840236B2 (ja) 2021-03-10

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US (1) US10778371B2 (https=)
EP (1) EP3535849B1 (https=)
JP (1) JP6840236B2 (https=)
KR (1) KR102265247B1 (https=)
CN (1) CN109906559B (https=)
SG (1) SG11201902036YA (https=)
WO (1) WO2018084956A1 (https=)

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US11032061B2 (en) * 2018-04-27 2021-06-08 Microsoft Technology Licensing, Llc Enabling constant plaintext space in bootstrapping in fully homomorphic encryption
CN109921880B (zh) * 2019-01-25 2020-10-23 北京航空航天大学 基于询问的目标定位方法、装置与电子设备
CN112583419B (zh) * 2019-09-30 2024-06-18 华为技术有限公司 一种译码方法及装置
US20210152282A1 (en) * 2019-11-15 2021-05-20 Nvidia Corporation Scheduling method for ldpc decoding
US12199634B2 (en) 2021-11-26 2025-01-14 Samsung Electronics Co., Ltd. Decoding apparatus, decoding method, and electronic apparatus
US11799700B1 (en) * 2022-08-31 2023-10-24 Qualcomm Incorporated Decoding multi-level coded (MLC) systems

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US6633865B1 (en) 1999-12-23 2003-10-14 Pmc-Sierra Limited Multithreaded address resolution system
US6633856B2 (en) 2001-06-15 2003-10-14 Flarion Technologies, Inc. Methods and apparatus for decoding LDPC codes
US7673223B2 (en) * 2001-06-15 2010-03-02 Qualcomm Incorporated Node processors for use in parity check decoders
US6961888B2 (en) 2002-08-20 2005-11-01 Flarion Technologies, Inc. Methods and apparatus for encoding LDPC codes
US7174495B2 (en) * 2003-12-19 2007-02-06 Emmanuel Boutillon LDPC decoder, corresponding method, system and computer program
US20070089016A1 (en) * 2005-10-18 2007-04-19 Nokia Corporation Block serial pipelined layered decoding architecture for structured low-density parity-check (LDPC) codes
JP5231453B2 (ja) * 2007-01-24 2013-07-10 クゥアルコム・インコーポレイテッド 可変サイズのパケットのｌｄｐｃ符号化及び復号化
US8418023B2 (en) * 2007-05-01 2013-04-09 The Texas A&M University System Low density parity check decoder for irregular LDPC codes
US7958429B2 (en) * 2007-07-02 2011-06-07 Broadcom Corporation Distributed processing LDPC (low density parity check) decoder
US20090113256A1 (en) 2007-10-24 2009-04-30 Nokia Corporation Method, computer program product, apparatus and device providing scalable structured high throughput LDPC decoding
US8219876B2 (en) * 2007-10-24 2012-07-10 Core Wireless Licensing, S.a.r.l. Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix
US20090271686A1 (en) * 2008-04-28 2009-10-29 Qualcomm Incorporated Communication signal decoding with iterative cooperation between turbo and reed-solomon decoding
US8464121B2 (en) * 2009-01-07 2013-06-11 Intel Corporation LDPC codes with small amount of wiring
US8443255B2 (en) * 2010-08-26 2013-05-14 Qualcomm Incorporated Parity check matrix optimization and selection for iterative decoding
CN103155421B (zh) * 2011-01-14 2016-11-09 马维尔国际贸易有限公司 Ldpc多解码器架构
US9037938B2 (en) * 2012-10-30 2015-05-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Hardware architecture and implementation of low power layered multi-level LDPC decoder
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JP6511284B2 (ja) * 2015-02-13 2019-05-15 パナソニック株式会社 最小値選択回路、復号器及び最小値選択方法

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Publication number Publication date
EP3535849B1 (en) 2022-04-13
CN109906559A (zh) 2019-06-18
JP2019536316A (ja) 2019-12-12
WO2018084956A1 (en) 2018-05-11
CN109906559B (zh) 2023-07-04
KR20190071728A (ko) 2019-06-24
SG11201902036YA (en) 2019-05-30
US20180123734A1 (en) 2018-05-03
US10778371B2 (en) 2020-09-15
EP3535849A1 (en) 2019-09-11
KR102265247B1 (ko) 2021-06-14
BR112019008746A2 (pt) 2019-07-09

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