JP2019536316A5 - - Google Patents

Download PDF

Info

Publication number
JP2019536316A5
JP2019536316A5 JP2019519683A JP2019519683A JP2019536316A5 JP 2019536316 A5 JP2019536316 A5 JP 2019536316A5 JP 2019519683 A JP2019519683 A JP 2019519683A JP 2019519683 A JP2019519683 A JP 2019519683A JP 2019536316 A5 JP2019536316 A5 JP 2019536316A5
Authority
JP
Japan
Prior art keywords
llr
encoded bits
bits
encoded
post
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019519683A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019536316A (ja
JP6840236B2 (ja
Filing date
Publication date
Priority claimed from US15/712,845 external-priority patent/US10778371B2/en
Application filed filed Critical
Publication of JP2019536316A publication Critical patent/JP2019536316A/ja
Publication of JP2019536316A5 publication Critical patent/JP2019536316A5/ja
Application granted granted Critical
Publication of JP6840236B2 publication Critical patent/JP6840236B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2019519683A 2016-11-02 2017-09-23 パイプライン高スループット階層化ｌｄｐｃデコーダアーキテクチャ Active JP6840236B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662416584P 2016-11-02 2016-11-02
US62/416,584 2016-11-02
US15/712,845 US10778371B2 (en) 2016-11-02 2017-09-22 Deeply-pipelined high-throughput LDPC decoder architecture
US15/712,845 2017-09-22
PCT/US2017/053128 WO2018084956A1 (en) 2016-11-02 2017-09-23 Pipelined high-throughput layered ldpc decoder architecture

Publications (3)

Publication Number Publication Date
JP2019536316A JP2019536316A (ja) 2019-12-12
JP2019536316A5 true JP2019536316A5 (https=) 2020-11-19
JP6840236B2 JP6840236B2 (ja) 2021-03-10

Family

ID=62022740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019519683A Active JP6840236B2 (ja) 2016-11-02 2017-09-23 パイプライン高スループット階層化ｌｄｐｃデコーダアーキテクチャ

Country Status (7)

Country Link
US (1) US10778371B2 (https=)
EP (1) EP3535849B1 (https=)
JP (1) JP6840236B2 (https=)
KR (1) KR102265247B1 (https=)
CN (1) CN109906559B (https=)
SG (1) SG11201902036YA (https=)
WO (1) WO2018084956A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11032061B2 (en) * 2018-04-27 2021-06-08 Microsoft Technology Licensing, Llc Enabling constant plaintext space in bootstrapping in fully homomorphic encryption
CN109921880B (zh) * 2019-01-25 2020-10-23 北京航空航天大学 基于询问的目标定位方法、装置与电子设备
CN112583419B (zh) * 2019-09-30 2024-06-18 华为技术有限公司 一种译码方法及装置
US20210152282A1 (en) * 2019-11-15 2021-05-20 Nvidia Corporation Scheduling method for ldpc decoding
US12199634B2 (en) 2021-11-26 2025-01-14 Samsung Electronics Co., Ltd. Decoding apparatus, decoding method, and electronic apparatus
US11799700B1 (en) * 2022-08-31 2023-10-24 Qualcomm Incorporated Decoding multi-level coded (MLC) systems

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6633865B1 (en) 1999-12-23 2003-10-14 Pmc-Sierra Limited Multithreaded address resolution system
US6633856B2 (en) 2001-06-15 2003-10-14 Flarion Technologies, Inc. Methods and apparatus for decoding LDPC codes
US7673223B2 (en) * 2001-06-15 2010-03-02 Qualcomm Incorporated Node processors for use in parity check decoders
US6961888B2 (en) 2002-08-20 2005-11-01 Flarion Technologies, Inc. Methods and apparatus for encoding LDPC codes
US7174495B2 (en) * 2003-12-19 2007-02-06 Emmanuel Boutillon LDPC decoder, corresponding method, system and computer program
US20070089016A1 (en) * 2005-10-18 2007-04-19 Nokia Corporation Block serial pipelined layered decoding architecture for structured low-density parity-check (LDPC) codes
JP5231453B2 (ja) * 2007-01-24 2013-07-10 クゥアルコム・インコーポレイテッド 可変サイズのパケットのｌｄｐｃ符号化及び復号化
US8418023B2 (en) * 2007-05-01 2013-04-09 The Texas A&M University System Low density parity check decoder for irregular LDPC codes
US7958429B2 (en) * 2007-07-02 2011-06-07 Broadcom Corporation Distributed processing LDPC (low density parity check) decoder
US20090113256A1 (en) 2007-10-24 2009-04-30 Nokia Corporation Method, computer program product, apparatus and device providing scalable structured high throughput LDPC decoding
US8219876B2 (en) * 2007-10-24 2012-07-10 Core Wireless Licensing, S.a.r.l. Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix
US20090271686A1 (en) * 2008-04-28 2009-10-29 Qualcomm Incorporated Communication signal decoding with iterative cooperation between turbo and reed-solomon decoding
US8464121B2 (en) * 2009-01-07 2013-06-11 Intel Corporation LDPC codes with small amount of wiring
US8443255B2 (en) * 2010-08-26 2013-05-14 Qualcomm Incorporated Parity check matrix optimization and selection for iterative decoding
CN103155421B (zh) * 2011-01-14 2016-11-09 马维尔国际贸易有限公司 Ldpc多解码器架构
US9037938B2 (en) * 2012-10-30 2015-05-19 Avago Technologies General Ip (Singapore) Pte. Ltd. Hardware architecture and implementation of low power layered multi-level LDPC decoder
US9235467B2 (en) * 2013-03-15 2016-01-12 Pmc-Sierra Us, Inc. System and method with reference voltage partitioning for low density parity check decoding
KR102241416B1 (ko) * 2013-09-16 2021-04-16 삼성전자주식회사 디지털 비디오 방송 시스템에서 LDPC(Low Density Parity Check) 복호기 및 LDPC 복호기의 복호화 방법
US9276610B2 (en) * 2014-01-27 2016-03-01 Tensorcom, Inc. Method and apparatus of a fully-pipelined layered LDPC decoder
JP6511284B2 (ja) * 2015-02-13 2019-05-15 パナソニック株式会社 最小値選択回路、復号器及び最小値選択方法

Similar Documents

Publication Publication Date Title
JP2019536316A5 (https=)
US10951233B2 (en) System and method for decoding iterations and dynamic scaling
CN102543149B (zh) 使用混合解码器执行有效解码的系统和方法
US8812939B2 (en) Soft decoding systems and methods for flash based memory systems
US10666295B1 (en) Mitigation of error correction failure due to trapping sets
JP6730215B2 (ja) メモリコントローラ、メモリシステムおよび制御方法
US20130031440A1 (en) Checksum using sums of permutation sub-matrices
US8751895B2 (en) Semiconductor memory device and decoding method
US20130212451A1 (en) Reduced complexity non-binary ldpc decoding algorithm
CN111078662B (zh) 一种区块链数据存储方法与装置
US10574272B2 (en) Memory system
TW201335943A (zh) 決定同位元檢查陣列之方法以及快閃記憶體系統
TWI570736B (zh) 利用混碼器的編碼器旁路
KR101631128B1 (ko) 크기조정 상수를 사용하는 가변 노드 업데이터를 갖는 ldpc 디코더
US11418219B2 (en) Learning device
CN116318191A (zh) 基于列表的分阶统计译码方法、设备、装置及存储介质
CN120958728A (zh) 用于对非二进制极化码进行解码的专用硬件设备
US20180191375A1 (en) Tapered variable node memory
CN119105901B (zh) 校验矩阵的构造方法、存储介质、计算机程序产品和相关装置
CN106849959B (zh) 数据处理方法及译码器
JP2016187099A5 (ja) データ処理回路及びエラー訂正方法
CN109714062A (zh) 执行迭代解码的解码器和使用该解码器的存储设备
CN117176185B (zh) 一种基于极化码的数据编解码方法、装置和存储介质
CN103973316A (zh) 具有使用定标常数的可变节点更新器的ldpc解码器
US10530395B2 (en) Iterative message-passing decoding with global code embedded with local code in time-division manner for fault tolerance improvement