BR112019008746A2 - arquitetura de decodificador ldpc de alta capacidade de transmissão usando a tecnologia pipeline - Google Patents
arquitetura de decodificador ldpc de alta capacidade de transmissão usando a tecnologia pipelineInfo
- Publication number
- BR112019008746A2 BR112019008746A2 BR112019008746A BR112019008746A BR112019008746A2 BR 112019008746 A2 BR112019008746 A2 BR 112019008746A2 BR 112019008746 A BR112019008746 A BR 112019008746A BR 112019008746 A BR112019008746 A BR 112019008746A BR 112019008746 A2 BR112019008746 A2 BR 112019008746A2
- Authority
- BR
- Brazil
- Prior art keywords
- memory
- llr
- bitrates
- messages
- consistency
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/002—Error detection; Error correction; Monitoring protecting against parasitic influences, e.g. noise, temperatures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/004—Error avoidance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3006—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1443—Transmit or communication errors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
- Retry When Errors Occur (AREA)
- Mobile Radio Communication Systems (AREA)
Abstract
certos aspectos da presente revelação geralmente referem-se aos métodos e aparelhos para decodificar códigos de verificação de paridade de baixa densidade (ldpc) e, mais particularmente, a uma arquitetura de decodificador de ldpc em camadas profundamente divididas para altas capacidades de processamento de decodificação que resolve problemas de consistência e conflito. aspectos da presente revelação apresentam técnicas para mitigar atrasos de pipeline, por exemplo, relaxando a dependência entre atualizar llrs de bit e computar mensagens de nó de verificação, de modo que para uma linha específica, o processamento de nó de verificação pode usar a última llr de bit disponível (por exemplo, llrs de bits desatualizados) em vez de esperar que as atualizações mais recentes (por exemplo, llrs de bits atualizados) ocorram. os conflitos de consistência de memória são evitados armazenando as últimas llrs de bits disponíveis em uma memória llr e atualizando as llrs de bit com a diferença entre as mensagens de nó de verificação antigas e novas. além disso, dividir logicamente a memória llr em bancos duplos permite que o decodificador leia ou grave em ambos os bancos de memória ao mesmo tempo, aumentando assim a largura de banda de leitura/gravação. vantajosamente, escolher a ordem de cálculo da matriz de verificação de paridade (pcm), ordenar as mensagens do nó de verificação e as atualizações de llr de bit na memória e/ou escolher um banco de memória para armazenar as mensagens do nó de verificação e atualizações de llr de bit baseadas, por exemplo, em dependências entre linhas na pcm alivia conflitos de memória/erros de consistência e reduz atrasos de processamento de pipeline.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662416584P | 2016-11-02 | 2016-11-02 | |
US15/712,845 US10778371B2 (en) | 2016-11-02 | 2017-09-22 | Deeply-pipelined high-throughput LDPC decoder architecture |
PCT/US2017/053128 WO2018084956A1 (en) | 2016-11-02 | 2017-09-23 | Pipelined high-throughput layered ldpc decoder architecture |
Publications (1)
Publication Number | Publication Date |
---|---|
BR112019008746A2 true BR112019008746A2 (pt) | 2019-07-09 |
Family
ID=62022740
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112019008746A BR112019008746A2 (pt) | 2016-11-02 | 2017-09-23 | arquitetura de decodificador ldpc de alta capacidade de transmissão usando a tecnologia pipeline |
Country Status (8)
Country | Link |
---|---|
US (1) | US10778371B2 (pt) |
EP (1) | EP3535849B1 (pt) |
JP (1) | JP6840236B2 (pt) |
KR (1) | KR102265247B1 (pt) |
CN (1) | CN109906559B (pt) |
BR (1) | BR112019008746A2 (pt) |
SG (1) | SG11201902036YA (pt) |
WO (1) | WO2018084956A1 (pt) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11032061B2 (en) * | 2018-04-27 | 2021-06-08 | Microsoft Technology Licensing, Llc | Enabling constant plaintext space in bootstrapping in fully homomorphic encryption |
CN109921880B (zh) * | 2019-01-25 | 2020-10-23 | 北京航空航天大学 | 基于询问的目标定位方法、装置与电子设备 |
CN112583419B (zh) * | 2019-09-30 | 2024-06-18 | 华为技术有限公司 | 一种译码方法及装置 |
US20210152282A1 (en) * | 2019-11-15 | 2021-05-20 | Nvidia Corporation | Scheduling method for ldpc decoding |
US11799700B1 (en) * | 2022-08-31 | 2023-10-24 | Qualcomm Incorporated | Decoding multi-level coded (MLC) systems |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6633865B1 (en) | 1999-12-23 | 2003-10-14 | Pmc-Sierra Limited | Multithreaded address resolution system |
US6633856B2 (en) | 2001-06-15 | 2003-10-14 | Flarion Technologies, Inc. | Methods and apparatus for decoding LDPC codes |
US7673223B2 (en) * | 2001-06-15 | 2010-03-02 | Qualcomm Incorporated | Node processors for use in parity check decoders |
US6961888B2 (en) | 2002-08-20 | 2005-11-01 | Flarion Technologies, Inc. | Methods and apparatus for encoding LDPC codes |
US7174495B2 (en) * | 2003-12-19 | 2007-02-06 | Emmanuel Boutillon | LDPC decoder, corresponding method, system and computer program |
KR101339120B1 (ko) * | 2007-01-24 | 2013-12-09 | 퀄컴 인코포레이티드 | 가변 크기들의 패킷들의 ldpc 인코딩 및 디코딩 |
US8418023B2 (en) * | 2007-05-01 | 2013-04-09 | The Texas A&M University System | Low density parity check decoder for irregular LDPC codes |
US7958429B2 (en) * | 2007-07-02 | 2011-06-07 | Broadcom Corporation | Distributed processing LDPC (low density parity check) decoder |
US8219876B2 (en) * | 2007-10-24 | 2012-07-10 | Core Wireless Licensing, S.a.r.l. | Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix |
US20090113256A1 (en) | 2007-10-24 | 2009-04-30 | Nokia Corporation | Method, computer program product, apparatus and device providing scalable structured high throughput LDPC decoding |
US20090271686A1 (en) * | 2008-04-28 | 2009-10-29 | Qualcomm Incorporated | Communication signal decoding with iterative cooperation between turbo and reed-solomon decoding |
US8464121B2 (en) * | 2009-01-07 | 2013-06-11 | Intel Corporation | LDPC codes with small amount of wiring |
US8443255B2 (en) * | 2010-08-26 | 2013-05-14 | Qualcomm Incorporated | Parity check matrix optimization and selection for iterative decoding |
WO2012097046A1 (en) * | 2011-01-14 | 2012-07-19 | Marvell World Trade Ltd. | Ldpc multi-decoder architectures |
US9037938B2 (en) * | 2012-10-30 | 2015-05-19 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Hardware architecture and implementation of low power layered multi-level LDPC decoder |
US9235467B2 (en) * | 2013-03-15 | 2016-01-12 | Pmc-Sierra Us, Inc. | System and method with reference voltage partitioning for low density parity check decoding |
KR102241416B1 (ko) * | 2013-09-16 | 2021-04-16 | 삼성전자주식회사 | 디지털 비디오 방송 시스템에서 LDPC(Low Density Parity Check) 복호기 및 LDPC 복호기의 복호화 방법 |
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2017
- 2017-09-22 US US15/712,845 patent/US10778371B2/en active Active
- 2017-09-23 CN CN201780067344.6A patent/CN109906559B/zh active Active
- 2017-09-23 EP EP17778447.7A patent/EP3535849B1/en active Active
- 2017-09-23 BR BR112019008746A patent/BR112019008746A2/pt unknown
- 2017-09-23 SG SG11201902036YA patent/SG11201902036YA/en unknown
- 2017-09-23 KR KR1020197012298A patent/KR102265247B1/ko active IP Right Grant
- 2017-09-23 WO PCT/US2017/053128 patent/WO2018084956A1/en unknown
- 2017-09-23 JP JP2019519683A patent/JP6840236B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
KR102265247B1 (ko) | 2021-06-14 |
US10778371B2 (en) | 2020-09-15 |
JP6840236B2 (ja) | 2021-03-10 |
CN109906559B (zh) | 2023-07-04 |
CN109906559A (zh) | 2019-06-18 |
EP3535849B1 (en) | 2022-04-13 |
WO2018084956A1 (en) | 2018-05-11 |
JP2019536316A (ja) | 2019-12-12 |
US20180123734A1 (en) | 2018-05-03 |
EP3535849A1 (en) | 2019-09-11 |
KR20190071728A (ko) | 2019-06-24 |
SG11201902036YA (en) | 2019-05-30 |
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B350 | Update of information on the portal [chapter 15.35 patent gazette] | ||
B06W | Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette] | ||
B15K | Others concerning applications: alteration of classification |
Free format text: A CLASSIFICACAO ANTERIOR ERA: H03M 13/11 Ipc: H03M 13/11 (2006.01), G06F 11/14 (2006.01) |