JP6837640B2 - Imaging device - Google Patents

Description

The present invention relates to an imaging device, and more particularly to a radiation resistant imaging device.

In order to monitor the inside of the reactor building in the event of a severe accident at a nuclear-related facility, a radiation-resistant imaging device capable of acquiring images even under a high dose of gamma-ray radiation is required.

Conventionally, there are radiation-resistant imaging devices that can be used in a gamma-ray environment, but the image quality tends to deteriorate over time. Specifically, it is considered that the deterioration of image quality is mainly caused by noise generated on the entire screen. The generated noise increases with the passage of gamma ray irradiation time, and eventually exceeds the video signal level, making it impossible to observe the subject. This is because it is difficult for the CMOS image sensor to shield gamma rays among the parts of the image sensor, and it is considered that the image quality deteriorates as the absorbed dose of gamma rays by the CMOS image sensor exposed to gamma rays increases. Be done.

The deterioration of image quality is due to the increase in dark current, and the following is presumed as the reason. Hydrogen ions are generated in the oxide film on the upper part of the semiconductor layer in the CMOS image pickup device by gamma rays, diffuse in the oxide film and reach the semiconductor interface, and deprive the hydrogen atom that suppressed the dark current at the interface to hydrogen gas. It is thought that the semiconductor interface on which the photodiode is formed is activated to generate a large dark current.

It is considered that the increase in dark current is due to the generation of hydrogen ions in the thick oxide film existing on the upper surface of the photodiode as the absorbed dose of gamma rays increases and diffuses to the semiconductor interface on which the photodiode is formed. Based on these considerations, the photoelectric conversion unit is not a mere photodiode, but a gate electrode (transparent electrode) is formed through a thin oxide film, and by adjusting this gate voltage, the activation of the semiconductor interface is greatly enhanced. A PG (photogate) type COMS image sensor has been proposed so as to be able to reduce the voltage (Patent Document 1).

International Publication No. 2016/013227

However, when the video signal was actually acquired by an image pickup device using such a PG type CMOS image sensor, it became clear that there is still a region where the image is unclear simply by suppressing the dark current. As a result of investigating such a cause by the present inventors, when the dark current is suppressed by controlling the PG voltage of the PG type CMOS image sensor, the sensitivity and the saturated charge amount of the PG type CMOS image sensor also decrease. , It turned out that this is because the dynamic range is lowered. As a result of further examination of this problem, good image quality was obtained by a method of adjusting the dynamic range by correcting the brightness level while suppressing the dark current by controlling the PG voltage while balancing the decrease in the saturated charge amount. We have found that it can be maintained and came to the present invention. An object of the present invention is to provide an imaging device capable of capturing a good image even in a radiation environment.

In order to solve the above problems, the invention described in one embodiment has a plurality of pixels, and each pixel of the plurality of pixels is a solid state composed of a PG (photogate) type CMOS image sensor. When the dark current is detected by the image pickup unit, the dark current detecting means for detecting the dark current based on the voltage level obtained in the state where the PG type CMOS image sensor is shielded from light, and the dark current detecting means, the dark current is detected. When the PG voltage control means for suppressing the dark current by controlling the PG voltage of the PG type CMOS image sensor constituting the plurality of pixels of the solid-state imaging unit and the dark current detecting means do not detect the dark current. In addition, the correction coefficient determining means for determining the correction coefficient based on the voltage level obtained in a state where the PG-type CMOS image sensor of the solid-state image sensor is not shielded from light, and the PG-type CMOS image sensor of the solid-state image sensor, respectively. The PG voltage control means is provided with a brightness gradation control means for controlling the brightness gradation of the finally output video signal by correcting the voltage level output from the image sensor using the determined correction coefficient. Is an image sensor, characterized in that the PG voltage is set according to the level of the saturated charge amount that fluctuates when the PG voltage is changed by a predetermined value.

It is a figure which shows the schematic structure of the image pickup apparatus of this embodiment. It is a figure for demonstrating the pixel area of the solid-state image sensor of this embodiment. It is a top view which shows the structural example of the photoelectric conversion region of a PG type CMOS image sensor. It is sectional drawing which shows the structural example of the photoelectric conversion region of a PG type CMOS image sensor. It is a figure explaining the potential profile corresponding to the configuration shown in the cross-sectional view of FIG. 4 and the movement of the signal charge in this potential profile (when the reset voltage VRD = high). It is a figure which shows the logic circuit of the PG type CMOS image sensor which constitutes each pixel of a solid-state image sensor. It is a figure which shows the example of the plane structure in which four unit pixels are arranged two-dimensionally in a 2 × 2 matrix. It is a flow figure explaining the control method of the image pickup apparatus of this embodiment. It is a flow chart which shows the flow of PG voltage adjustment. It is a figure explaining PG voltage control. It is a figure explaining the luminance gradation adjustment. It is a block diagram which shows the structural example of the image pickup apparatus of 2nd Embodiment. It is a figure which shows the effect of a cooling means. It is a block diagram which shows the structural example of the image pickup apparatus of 3rd Embodiment.

Hereinafter, embodiments of the present invention will be described in detail.

FIG. 1 is a diagram showing a schematic configuration of an imaging device according to this embodiment. The image pickup apparatus of the present embodiment includes a solid-state image pickup unit 1 composed of a plurality of image pickup elements, a dark current detection means 2, a luminance gradation control means 3, a video signal detection means 4, and a video signal optimization means 5. And the PG voltage control means 6.

In the image sensor of the present embodiment, a PG type CMOS image sensor (photodetector element) capable of suppressing a dark current that increases due to exposure to gamma ray irradiation by a PG (photogate) voltage is configured as each pixel. Used as the solid-state image sensor 1, the effects of sensitivity and saturation capacitance, which change with the application of PG voltage for suppressing dark current, are measured, and different coefficients are determined for each luminance region according to the measured values. By correcting the voltage level output from the solid-state image sensor 1 with a different coefficient for each luminance region using the obtained coefficient, good image quality as a video signal is maintained.

The dark current detecting means 2 detects the dark current based on the voltage level output from the image sensor in the shaded pixel region of the solid-state imaging unit 1, and uses the fact that the dark current is detected as the image signal optimization means. Notice.

Here, the pixel region of the solid-state image sensor will be described. FIG. 2 is a diagram for explaining a pixel region of the solid-state image sensor of the present embodiment. The solid-state image pickup unit 1 is composed of a plurality of image pickup elements, each of which is a pixel, and has an effective pixel region 101 and a light-shielding pixel region 102 as shown in FIG. The effective pixel region 101 is a region that receives light, but the light-shielding pixel region 102 is a region that is always shielded from light. The dark current detecting means 2 detects the dark current by measuring the output from the image pickup device of all or a part of the light-shielding pixel region 102. It is considered that the absorption amount of gamma rays is substantially the same in the light-shielding pixel region 102 and the effective pixel region 101. This is because there is a light-shielding material on the light-shielding pixel region 102 surface, but since there is almost no density and thickness, the amount of blocking gamma rays is insignificant. Further, even if there is a difference in the absorption amount, since the ratio of the absorption amount between the two can be relatively determined, there is no problem even if the light-shielding pixel region 102 in the constantly light-shielded state is used for dark current detection.

Returning to FIG. 1, the video signal detecting means 4 acquires the voltage level output from each pixel of the solid-state image sensor 1 and detects the video signal. The video signal detecting means 4 can detect the voltage level output from the image pickup elements of the effective pixel region 101 and the light-shielding pixel region 102 of the solid-state image pickup unit 1 shown in FIG.

Upon receiving the notification from the dark current detecting means 2 that the dark current has been detected, the video signal optimizing means 5 determines the control amount of the PG voltage and instructs the PG voltage controlling means 6 to control the PG voltage. Further, the video signal optimizing means 5 calculates a reference coefficient for correcting the image quality deteriorated as a result of the PG voltage control based on the voltage level detected by the video signal detecting means 4.

The PG voltage control means 6 controls the PG voltage of the solid-state imaging unit 1 based on the control amount determined by the video signal optimization means 5.

The luminance gradation control means 3 determines the coefficient for each luminance region based on the reference coefficient calculated by the video signal optimization means 5, and sets the voltage level output from the solid-state image sensor 1 as the coefficient for each luminance region. Correct with.

As the image pickup device constituting the solid-state image pickup unit 1, a PG type CMOS image pickup device capable of suppressing a dark current by adjusting the PG voltage can be used, and the PG type CMOS image pickup device is described in, for example, Patent Document 1. Can be used. Here, a configuration example of the PG type CMOS image sensor will be described. 3 and 4 are views showing a configuration example of a photoelectric conversion region of the PG type CMOS image sensor, FIG. 3 is a plan view, and FIG. 4 is a cross-sectional view. As shown in FIGS. 3 and 4, the PG type CMOS imaging element includes a base region 11 made of a first conductive type (p type) semiconductor and a gate insulating film 23 provided in contact with the upper surface of the base region 11. The second conductive type (n type) charge generation embedding region 13 which is in contact with the gate insulating film 23 and is embedded in an annular shape (ring shape in the plan view of FIG. 3) above the base region 11, and the charge generation embedding. _{A second conductive type charge reading region 15 i, j} having a higher impurity density than the charge generation embedded region 13 and a charge reading region 15 embedded in an annular shape above the base region 11 located on the inner diameter side of the region 13. _{A second conductive type reset drain region 16 i, j} with a higher impurity density than the charge generation embedded region 13 embedded on the inner diameter side of the charge read region 15 _{i, j} , separated from i, j, and charge generation. A substrate between the _{transparent electrodes 21 i, j} provided in an annular shape on the gate insulating film 23 above the embedded region 13 and the charge reading region 15 _{i, j} and the reset drain region (RD) 16 _{i, j. It includes reset gate electrodes (RX) 22 i, j} provided on the gate insulating film 23 above the region 11. As shown in FIG. 3, the charge reading regions 15 _{i and j} are in contact with the charge generation embedded region 13.

In the plan view of FIG. 3, as an example of the annular topology, _{the shapes of the transparent electrode (PG) 21 i, j} and the reset gate electrode (RX) 22 _{i, j on} the outer diameter side and the inner diameter side are both octagonal continuous. Although the shape of the band is shown, it is not limited to the topology shown in FIG.

As shown in FIG. 4, in the PG type CMOS image sensor, transparent electrodes 21 _{i, j} are arranged in an annular shape on the outside as a so-called photogate (PG), and a charge reading region 15 _{is arranged inside the pattern of the transparent electrodes 21 i, j. i and j} are arranged. Actually, depending on the thermal process in the manufacturing process, as shown by the broken line in the plan view of FIG. 3, the outer diameter of the charge reading region 15 _{i, j is in the region outside the inner diameter line of the transparent electrodes 21 i, j. The second conductive type impurity elements constituting the charge reading regions 15 i and j} may be thermally diffused laterally from the boundary position of the pattern determined by the mask level so as to form a plane pattern in which the lines are located. Similarly, in the plan view of FIG. 3, the annular reset gate electrodes 22 _{i, j are arranged inside the charge reading regions 15 i, j} , but as shown by the broken line, the reset gate electrodes 22 _i, charge readout area 15 i than the outer diameter line in the inner region of _j, as the inner diameter line of the _j becomes flat pattern positioned, the charge read area 15 _i, the impurity element is a mask level of the second conductivity type constituting the _j The heat may be diffused laterally from the boundary position of the pattern determined by. In the corresponding cross-sectional view of FIG. 4, _{the lateral ends of the charge reading regions 15 i, j} overlap with the inner ends of the transparent electrodes 21 _{i, j and} the outer ends of the reset gate electrodes 22 _{i, j.} It is shown to be. By providing an annular reset gate electrode 22 _{i, j} inside the charge reading region 15 _{i, j} , it is turned off by irradiation at the boundary of the channel side wall oxide film, which is unavoidable in a general transistor having a square gate shape. It is also possible to suppress the leakage current at the time.

In the plan view of FIG. 3, the reset drain region 16 _{i, j is arranged inside the reset gate electrode 22 i, j} , but as shown by the broken line, it is outside the inner diameter line _{of the reset gate electrode 22 i, j.} The boundary of the pattern in which the second conductive type impurity elements constituting the _{reset drain region 16 i, j} are determined by the mask level so that the outer diameter line of the reset drain region 16 _{i, j is located in the region of.} The heat may be diffused laterally from the position. The corresponding cross-sectional view of FIG. 3 shows that _{the lateral ends of the reset drain regions 16 i, j} overlap with the inner ends of the reset gate electrodes 22 _{i, j.}

As shown in FIG. 4, a _{well region 12 i} , which is a first conductive type and has a higher impurity density than the substrate region 11, is arranged _{above the base region 11 directly below the reset gate electrodes 22 i and j.} .. Although the plane pattern is not shown, the well region 12 _i is arranged in an octagon so as to surround the reset drain regions 16 _{i and j, and the outer diameter line of the well region 12 i} is a charge reading region on the plane pattern. 15 It has an octagonal shape sandwiched between the outer and inner diameter lines of _{i and j.} In the cross-sectional view of FIG. 3, the well region 12 _i is arranged so as to surround the entire side surface and bottom surface of the reset drain region 16 _{i, j , and the side surface of the well region 12 i} is in contact with the bottom surface of the _{charge reading region 15 i, j.} You can see that. It is desirable that the outer diameter line of the well region 12 _i is separated from the inner diameter line of the transparent electrodes 21 _{i and j.}

In the PG-type CMOS image pickup device shown in FIG. 4, since the well region 12 _i is composed of the p-type semiconductor region, the reset gate electrodes 22 _{i and j} , the gate insulating film 23, the well region 12 _i , and the charge reading region 15 The reset transistor is composed of an nMOS transistor consisting of _{i, j} and the reset drain region 16 _{i, j.} Then, the reset gate electrode 22 _i, the voltage applied to the _j, the charge read area 15 _i, to discharge the charges accumulated in the _j reset drain region 16 _i, the _j, are stored in the charge read area 15 _{i, j} Resets the charge.

As shown on both end sides of the cross-sectional view of FIG. 4, _{the element separation region 12 o,} which is the first conductive type and has a higher impurity density than the substrate region 11, is charged _{outside the transparent electrodes 21 i and j.} It is arranged so as to surround the embedded area 13. Furthermore the first conductivity type on the surface of the isolation region 12 _o, the channel stop region 17 of high impurity density is located than the element isolation region 12 _o. As shown by the broken line in the plan view of FIG. 3, the plane in which the inner diameter line of the element separation region 12 _{o is located in the region inside the outer diameter line of the transparent electrodes 21 i and j depending on the thermal process in the manufacturing process.} The first conductive type impurity element constituting the element separation region 12 _o may be thermally diffused in the lateral direction from the boundary position of the pattern determined by the mask level so as to form a pattern.

Inner diameter line of the element isolation region 12 _o is, transparent electrodes 21 _i, that a plane pattern located inside at equal intervals than the outer diameter line of _j, the closed geometric shapes are the inner diameter line of the element isolation region 12 _o I'm doing it. On the other hand, the inner diameter line of _{the channel stop region 17 surrounds the plane pattern of the transparent electrodes 21 i and j} , and the inner diameter line of the channel stop region 17 also has a closed geometric shape. Transparent electrodes 21 _i, by disposing the element isolation region 12 _o on the outside of _j, the transparent electrode 21 _i, to suppress the generation of dark current at the periphery of the formed charge generating buried region 13 immediately below the _j Is possible.

Although the planar pattern is not shown, the topology of the charge generation embedded region 13 arranged on the surface side of the substrate region 11 is also a closed geometric shape. That is, the outer diameter line of the charge generation embedded region 13 is an octagonal line that is common to the inner diameter line of the _{element separation region 12 o in FIG. 3, and the inner diameter line of the charge generation embedded region 13 is} On the plane pattern of FIG. 3, it has an octagonal shape passing between the outer diameter line and the inner diameter line of _{the charge reading regions 15 i and j.} In this way, an annular and octagonal charge generation embedding region 13 is formed on the surface side of the substrate region 11, and an annular and octagonal charge generation embedding region 13 is formed on the annular and octagonal charge generation embedding region 13 via a thin gate insulating film 23. An annular and octagonal transparent electrodes 21 _{i, j} are provided.

If the transparent electrodes 21 _{i and j} are formed of a polycrystalline silicon (hereinafter referred to as "doped polysilicon") film doped with a second conductive type impurity such as phosphorus (P) and arsenic (As), the transparent electrodes 21 i and j can be formed. It is convenient in the manufacturing process because the boundary between the transparent electrode 21 _{i, j} and the charge reading region 15 _{i, j} can be determined in a self-consistent manner, but tin oxide (SnO ₂ ) and tin (Sn) are added. Indium oxide (ITO), zinc oxide (AZO) added with aluminum (Al), zinc oxide (GZO) added with gallium (Ga), zinc oxide (IZO) added with indium (In), and other oxide thin films. (Transparent conductive oxide) may be used.

For the reset gate electrodes 22 _{i, j} , if doped polysilicon doped with a second conductive type impurity is used _{, the boundary between the reset gate electrodes 22 i, j} and the charge reading region 15 _{i, j} , and the reset gate electrode It is preferable because the boundary between 22 _{i, j} and the reset drain region 16 _{i, j} can be defined in a self-consistent manner.

In PG-type CMOS image sensor, the transparent electrode 21 i is PG _electrode, applying a negative voltage (PG voltage) to _j, the transparent electrode 21 _{i, j} is the charge generation buried region 13 via a gate insulating film 23 The surface potential exerted on the surface is pinned on the surface of the charge generation embedding region 13 with a charge that becomes a minority carrier of the charge generation embedding region 13.

For example, if the charge generation embedded region 13 is n-type, the minority carriers are holes, so that the interface between the gate insulating film 23 directly under the _{transparent electrodes 21 i and j and the semiconductor, that is, charge generation} An inversion layer 14 is formed on the surface of the embedded region 13 by a large amount of holes, and the surface potential is pinned by holes which are minority carriers. By pinning with holes, the interface state of the interface between the gate insulating film 23 and the semiconductor is inactivated. On the contrary, if the charge generation embedded region 13 is p-type, the minority carriers are electrons, so that the interface between the gate insulating film 23 directly under the _{transparent electrodes 21 i and j and the semiconductor, that is, the charge generation embedded region} An inversion layer 14 is formed on the surface of 13 by a large amount of electrons, and the surface potential is pinned by the electrons. By pinning the interface with electrons, the interface state of the interface between the gate insulating film 23 and the semiconductor is inactivated. When the PG-type CMOS image sensor according to the first embodiment is irradiated with gamma rays, holes are also generated in the thin gate insulating film 23, but since the film thickness is thin, the gate insulating film 23 The absolute amount of holes produced in is small.

FIG. 5 shows the charge generation embedded region 13, the charge reading region 15 _{i, j} , and the reset gate electrode 22 _{i from the outer element separation region 12 o} , corresponding to the positions in the lateral direction shown in the cross-sectional view of FIG. It is a figure which showed the example of the potential distribution which becomes the profile of the central symmetry which reaches the central reset drain region 16 _{i, j through, j ,.} Figure central well level indicated at RD in the bottom of the 5, namely the upper end level of that shown by hatched consisting dashed left-side up in FIG. 5, the reset drain region 16 _i, the reset voltage is the voltage of the _j It becomes VRD.

In the PG-type CMOS image sensor according to the first embodiment, as shown in FIG. 5, the depletion potential of the channel immediately below the _{transparent electrodes 21 i, j} is shallower than the _{potential of the charge reading region 15 i, j.} The charge photoelectrically converted in the channel portion immediately below the transparent electrodes 21 _{i, j} is always transferred to _{the charge read region 15 i, j.} That is, according to the shape of the potential distribution shown in FIG. 5, the signal charges (electrons) generated in the charge generation embedded region 13 directly below the _{transparent electrodes 21 i and j are indicated by arrows toward the center of FIG.} , Always carried from the charge generation embedding area 13 to the inner charge reading area 15 _{i, j.}

In FIG. 5, the charges transferred _{and accumulated in the charge reading regions 15 i and j} are indicated by hatching of diagonal lines consisting of solid lines rising to the right. By realizing the profile of the potential distribution as shown in FIG. 5, _{the capacitance of the charge reading regions 15 i and j} of the PG type CMOS image sensor according to the first embodiment can be reduced, and the conversion gain due to the signal charge can be increased. Can be done. Therefore, it is possible to increase the voltage sensitivity of the PG type CMOS image sensor according to the first embodiment.

The charge photoelectrically converted in the charge generation embedded region 13 directly below the transparent electrodes 21 _{i, j is accumulated in the charge read region 15 i, j} for a certain period of time, then reads the signal level of the _{charge read region 15 i, j, and then reads the signal level.} The reset operation allows you to read the reset level. In FIG. 5, in order to increase the conversion gain, the signal charge is _{stored only in the charge reading areas 15 i and j,} but depending on the application, the conversion gain may be reduced to handle a large amount of signal charge. It is useful.

In the PG-type CMOS image pickup device according to the first embodiment, in which the structure of the cross section is exemplified in FIG. 4, the first conductive type (p-type) semiconductor substrate (Si substrate) is designated as the “base region 11”. Is illustrated, but instead of the semiconductor substrate, a first conductive type epitaxial growth layer having a lower impurity density than the semiconductor substrate is formed on the first conductive type semiconductor substrate, and the epitaxial growth layer is used as a substrate. It may be adopted as the region 11, or the epitaxial growth layer of the first conductive type (p type) may be formed on the semiconductor substrate of the second conductive type (n type) and the epitaxial growth layer may be adopted as the substrate region 11. Often, the first conductive type semiconductor layer (SOI layer) having an SOI structure may be adopted as the substrate region 11.

The PG-type CMOS image sensor according to the first embodiment is not limited to a simple MOS-type transistor using a silicon oxide film as the gate insulating film 23. That is, as the gate insulating film 23 of the PG type CMOS image pickup device according to the first embodiment, in addition to the silicon oxide film, a strontium oxide (SrO) film, a silicon nitride (Si ₃ N ₄ ) film, and an aluminum oxide (Al ₂ O ₃ ) film, magnesium oxide (MgO) film, yttrium oxide (Y ₂ O ₃ ) film, hafnium oxide (HfO ₂ ) film, zirconium oxide (ZrO ₂ ) film, tantalum oxide (Ta) _A MIS type transistor may be configured by using a single-layer film of any one of a 2 O ₅ ) film and a bismuth oxide (Bi ₂ O _{3) film, or a composite film in which a plurality of these is laminated.} However, it is a prerequisite that these gate insulating film materials are resistant to radiation.

In the image pickup apparatus of the present embodiment, the solid-state image pickup unit 1 is configured by arranging a plurality of image pickup devices shown in FIGS. 3 and 4 which are pixels in parallel. The configuration of the solid-state image sensor 1 will be described. FIG. 6 is a diagram showing a logic circuit of a PG type CMOS image sensor constituting each pixel of the solid-state imaging unit 1, and FIG. 7 is a planar structure example in which four unit pixels are two-dimensionally arranged in a 2 × 2 matrix. It is a figure which shows.

As shown in FIG. 6, a pixel selection transistor TS is connected to the read electrode 15 of the PG type CMOS image sensor via an amplification transistor QA. By inputting the selection signal SL to the gate electrode of the pixel selection transistor TS, the value of the read electrode 15 is read from the vertical signal line B. Further, the reset drain RD16 is connected to the read electrode 15 via the reset gate RX22, and by applying a voltage to the reset gate RX22, the electric charge accumulated in the read electrode 15 can be discharged from the reset drain RX22. it can.

The solid-state imaging unit 1 relates to the first embodiment of the present invention if the PG-type CMOS image sensor having the structures shown in FIGS. 3 and 4 is used as a unit pixel and a large number of unit pixels are two-dimensionally arranged in a matrix. The pixel array area of the solid-state image sensor 1 (two-dimensional image sensor) can be realized. For convenience of explanation, in FIG. 7, among a large number of unit pixels constituting the pixel array region, in FIG. 7, a solid-state imaging according to the first embodiment is performed by a planar structure in which four unit pixels are two-dimensionally arranged in a 2 × 2 matrix. The device will be schematically described. That is, the solid-state image sensor according to the first embodiment shown in FIG. 7 has the upper left (i, j) th pixel, the upper right (i, j + 1) th pixel, and the lower left (i-1, j) th pixel. An example of a plane pattern in a part of the pixel array region constituting the 2 × 2 matrix structure is shown by the pixel of the above and the (i-1, j + 1) th pixel in the lower right.

The pixel array region constitutes, for example, a rectangular imaging region. Peripheral circuit units are arranged around the pixel array region, and the pixel array region and peripheral circuit units are integrated on the same semiconductor chip. The peripheral circuit section includes a horizontal shift register, a vertical shift register, a timing generation circuit, and the like.

More specifically, for example, it is possible to design a layout in which a horizontal shift register is provided along the direction of the pixel rows shown in the horizontal direction in FIG. 7 at the lower side of the rectangular pixel array region. In this case, for example, a vertical shift register is provided on the left side of the pixel array region along the direction of the pixel array shown in the vertical direction in FIG. 7, and a timing generation circuit is connected to the vertical shift register and the horizontal shift register. You just have to do it.

Although only two lines are illustrated in FIG. 7, vertical signal lines B _j , B _{j + 1} , ... Are provided for each pixel sequence. Then, a MOS transistor serving as a constant current load is connected to one end above or below _{each of the vertical signal lines B j} , B _{j + 1} , ... In the arrangement shown in FIG. 7, _{and the MOS transistor QA ij in the pixel is connected.} Etc. to form a source follower circuit, and output a pixel signal to _{the vertical signal line B i or the like.} A column processing circuit is connected to one end on the same side or opposite side of the constant current load of each of the vertical signal lines B _j , B _{j + 1, ....} Each column processing circuit includes a noise canceling circuit and an A / D conversion circuit. The noise canceling circuit may be configured by correlated double sampling (CDS) or the like.

The cross-sectional structure of the (i, j) th pixel constituting the solid-state image sensor according to the first embodiment shown in the upper left of FIG. 7 has the PG type CMOS image sensor shown in FIG. 3 as a unit pixel. Therefore, it is the same as the cross-sectional structure of the PG type CMOS image sensor shown in FIG. Therefore, the base region 11, the gate insulating film 23, the charge generation embedded region 13, and the like shown in FIG. 3 are not represented in the plan view of FIG. 7, but the cross-sectional structure of the (i, j) th pixel is It is basically the same as the cross-sectional structure shown in FIG.

That is, the (i, j) th pixels constituting the solid-state imaging device according to the first embodiment shown in the upper left of FIG. 7 are a base region (not shown) made of a first conductive type semiconductor and a base region. A gate insulating film provided in contact with the upper surface (not shown), a second conductive type charge generation embedded region (not shown) which is annularly embedded in the upper part of the substrate region in contact with the gate insulating film, and charge generation. _{The second conductive type charge reading region 15 i, j} and the charge reading region 15 _i , which are annularly embedded in the upper part of the base region located on the inner diameter side of the embedded region and have a higher impurity density than the charge generation embedded region. _{A reset drain region 16 i, j} with a higher impurity density than the charge generation embedding region, which is _{separated from, j} and embedded on the inner diameter side of the charge reading region 15 _{i, j} , and above the charge generation embedding region 13. _{A transparent electrode 21 i, j} provided in an annular shape on the gate insulating film, and provided on the gate insulating film above the substrate region between the charge reading region 15 _{i, j} and the reset drain region 16 _{i, j.} The reset gate electrodes 22 _{i and j} are provided. Although not shown in FIG. 7, the charge reading regions 15 _{i and j} are in contact with the charge generation embedding region and are directly below the reset gate electrodes 22 _{i and j, as in the cross-sectional structure shown in FIG. A well region 12 i} , which is a first conductive type and has a higher impurity density than the substrate region, is arranged above the substrate region. Similar to the cross-sectional structure shown in FIG. 3, a first conductive type device separation region having a higher impurity density than the substrate region surrounds the charge generation embedding region 13 on the outside _{of the transparent electrodes 21 i and j.} Has been done. Further, a channel stop region 17 which is a first conductive type and has a higher impurity density than the element separation region is arranged on the surface of the element separation region.

Similarly, as shown in the upper right of FIG. 7, the (i, j + 1) th pixel in the two-dimensional matrix includes a first conductive type substrate region and a gate insulating film provided in contact with the upper surface of the substrate region. , Higher impurities than the second conductive type charge generation embedding region embedded in the upper part of the substrate region in contact with the gate insulating film and the charge generation embedding region embedded on the inner diameter side of the charge generation embedding region. Charge generation embedding embedded on the inner diameter side of _{the charge read area 15 i, j + 1} of the second conductive type of density and the charge read area 15 _{i, j + 1} separated from the charge read area 15 _{i, j + 1. The reset drain region 16 i, j + 1,} which has a higher impurity density than _{the charge region, and the transparent electrodes 21 i, j + 1,} which are annularly provided on the gate insulating film above the charge generation embedding region 13, and the electric charge. It is provided with reset gate electrodes 22 _{i, j + 1} provided above between the read area 15 _{i, j + 1} and the reset drain area 16 _{i, j + 1} . Similar to the structure of FIG. 3, the charge reading region 15 _{i, j + 1} is in contact with the charge generation embedded region, and below the reset gate electrode 22 _{i, j + 1} , the first conductive type is formed from the substrate region. A well region 12 _i with a high impurity density is arranged, and an element separation region of the first conductive type having a higher impurity density than the substrate region is a charge generation embedded region 13 outside _{the transparent electrodes 21 i and j + 1.} It is arranged as a continuous area from the area of other pixels such as the (i, j) th pixel so as to surround the area. Then, on the surface of the element separation region, a channel stop region 17 of the first conductive type having a higher impurity density than the element separation region is arranged as a region continuous from the region of another pixel such as the (i, j) th pixel. Has been done.

Further, as shown in the lower left of FIG. 7, the (i-1, j) th pixel in the two-dimensional matrix is provided in contact with the first conductive type base region and the upper surface of the base region. And, the second conductive type charge generation embedding region embedded in the upper part of the substrate region in contact with the gate insulating film, and the higher impurities than the charge generation embedding region embedded on the inner diameter side of the charge generation embedding region. a second conductivity type charge reading region 15 _{i-1, j} of the density, the charge readout area 15 _i-1, embedded in _j the inner diameter side of the reset drain region 16 of high impurity concentration than the charge generation buried region _{The i-1, j , the transparent electrode 21 i-1, j} provided above the charge generation embedded region 13, the charge read region 15 _{i-1, j,} and the reset drain region 16 _{i-1, j} . A reset gate electrode 22 _{i-1, j} provided above the space is provided. Similar to the structure of FIG. 3, the charge reading region 15 _{i-1, j} is in contact with the charge generation embedded region, and below the reset gate electrode 22 _{i-1, j} is the first conductive type from the substrate region. A well region 12 _i-1 having a high impurity density is arranged, and an element separation region of the first conductive type having a higher impurity density than the substrate region is charged and embedded outside _{the transparent electrodes 21 i-1 and j.} It is arranged as a continuous region from the region of another pixel such as the (i, j) th pixel so as to surround the region 13. Then, on the surface of the element separation region, a channel stop region 17 of the first conductive type having a higher impurity density than the element separation region is arranged as a region continuous from the region of another pixel such as the (i, j) th pixel. ing.

Further, as shown in the lower right of FIG. 7, the (i-1, j + 1) th pixel in the two-dimensional matrix is provided with the first conductive type base region and the gate insulation provided in contact with the upper surface of the base region. Higher than the film, the second conductive type charge generation embedding region embedded in the upper part of the substrate region in contact with the gate insulating film, and the charge generation embedding region embedded on the inner diameter side of the charge generation embedding region. Higher impurity density than the charge generation embedded region embedded in the inner diameter side of the second conductive type charge reading region 15 _{i-1, j + 1} and the charge reading region 15 _{i-1, j + 1 of the impurity density.} Reset drain region 16 _{i-1, j + 1 , transparent electrode 21 i-1, j + 1} provided above the charge generation embedding region 13, and charge read region 15 _{i-1, j + 1} It is provided with a reset gate electrode 22 _{i-1, j + 1} provided above the reset drain region 16 _{i-1, j + 1} . Similar to the structure of FIG. 3, the charge reading region 15 _{i-1, j + 1} is in contact with the charge generation embedded region, and the first conductive type is below the reset gate electrode 22 _{i-1, j + 1. A well region 12 i-1} having a higher impurity density than the substrate region is arranged in the above, and further, an element separation of the first conductive type having a higher impurity density than the substrate region is provided outside _{the transparent electrodes 21 i-1, j + 1.} The region is arranged as a continuous region from the region of other pixels such as the (i-1, j) th pixel and the (i, j + 1) th pixel so as to surround the charge generation embedded region 13. Then, on the surface of the element separation region, the channel stop region 17 of the first conductive type and having a higher impurity density than the element separation region is the (i-1, j) th pixel, the (i, j + 1) th pixel, and the like. It is arranged as a continuous area from the pixel area of.

_{As shown in FIG. 7, in the charge reading region 15 i, j} of the (i, j) th pixel in the two-dimensional matrix, the _{surface wiring 32 i,} which goes in the lower right direction through the contact holes 31 _{i, j, One end of j} is connected, and the gate electrodes of the amplification transistors (signal reading transistors) QA _{i and j} of the read circuit units 29 _{i and j} are connected to the other end of the surface wiring 32 _{i and j.} There is. That is, in the circuit configuration shown in FIG. 7, since the charge read area 15 _{i, j} functions as the source area of the reset transistor, the charge read area 15 _{i, j} is reset with the gate electrode of the amplification transistor QA _{i, j.} The source regions of the transistors TR _{i and j are connected. The surface wirings 32 i and j} shown in FIG. 7 are exemplary representations on a schematic equivalent circuit, and do not actually need to be wirings directed in the lower right direction as shown in FIG. For example, a multi-layer wiring structure may be used to realize surface wiring (metal wiring) orthogonal to each other at different wiring levels. That is, it may be realized by a configuration in which the interlayer insulating film is interposed between the surface wirings orthogonal to each other and the upper and lower surface wirings are connected by a contact plug or the like penetrating the interlayer insulating film. _{That is, surface wiring 32 i, j of} any topology can be adopted according to the requirements of the layout design on the semiconductor chip. Amplifying transistor QA _i, the pixel selection in the source region of the _j Trang Njisuta (switching transistor) TS i, the drain region of _j is connected, an amplification transistor QA _i, the power supply line V _DD to the drain region of the _j are connected .. Pixel selection Trang Njisuta TS _i, the source region of _j is j-th vertical signal line B _j arranged along the column is connected, the pixel selection Trang Njisuta TS _i, the gate electrode of the _j is the vertical shift register The selection signal SL (i) on the i-th line is input. _{The output amplified by the amplification transistors QA i, j} by the voltage corresponding to the amount of charge transferred to the charge reading region 15 _{i, j} is output to the vertical signal line B _j via the pixel selection transistor TS _{i, j.} Will be done.

In FIG. 7, the octagonal outer diameter line indicating _{the read circuit unit 29 i, j} indicates the outer boundary of the field insulating film region for forming the _{amplification transistor QA i, j} and the pixel selection transistor TS _{i, j.} .. A thick oxide film corresponding to a field insulating film is formed between the active region of the amplification transistors QA _{i and j and} the active region of the pixel selection transistor TS _{i and j in} the read circuit unit 29 _{i and j.} There is no thick oxide film between the surface of the substrate region where the pattern of the transparent electrodes 21 _{i, j} is arranged and the surface of the substrate region where the pattern of the reading circuit section 29 _{i, j is arranged, and the substrate region. On the surface of the above, the element separation region 12o} and the channel stop region 17 similar to those illustrated in the cross-sectional view of FIG. 3 are arranged as regions continuous from the regions of other pixels in the two-dimensional matrix.

In FIG. 7, the octagonal outer diameter wire indicating _{the read circuit unit 29 i, j + 1} is a field insulating film for forming the _{amplification transistor QA i, j + 1} and the pixel selection transistor TS _{i, j + 1.} Indicates the outer boundary of the area. Thick oxidation corresponding to a field insulating film between the active region of the amplification transistors QA _{i, j + 1 and} the active region of the pixel selection transistor TS _{i, j + 1 in} the read circuit unit 29 _{i, j + 1.} A film is formed. There is no thick oxide film between the surface of the substrate region where the pattern of the transparent electrodes 21 _{i, j + 1} is arranged and the surface of the substrate region where the pattern of the reading circuit section 29 _{i, j + 1 is arranged. Instead, on the surface of the substrate region, the element separation region 12o} and the channel stop region 17 similar to those illustrated in the cross-sectional view of FIG. 2 are continuous from the regions of other pixels such as the (i, j) th pixel. It is arranged as an area.

_{Further, in the charge reading region 15 i-1, j} of the (i-1, j) th pixel, the surface wiring 32 _{i-1, j extending in} the lower right direction via the contact hole 31 _{i-1, j} One end is connected, and the gate electrode of the amplification transistor QA _{i-1, j} of the read circuit unit 29 _{i-1, j} is connected to the other end of the surface wiring 32 _{i-1, j.} .. That is, in the circuit configuration shown in FIG. 7, since the charge reading region 15 _{i-1, j} functions as the source region of the reset transistor, the charge reading region 15 _{i-1, j} is covered by the amplification transistor QA _i-1, a source region of the gate electrode and the reset transistor TR _{i-1, j} of the _j so that is connected. A source region of the amplifying transistor QA _{i-1, j} is connected to the drain region of the pixel selection Trang Njisuta TS _{i-1, j,} power wiring V _DD is connected to the drain region of the amplifying transistor QA _{i-1, j} ing. Vertical signal line Bi is connected to the source region of the pixel selection Trang Njisuta TS _{i-1, j,} to the gate electrode of the pixel selection Trang Njisuta TS _{i-1, j} from the vertical shift register (i-1) th row The selection signal SL (i-1) of is input. _{The output amplified by the amplification transistor QA i-1, j} by the voltage corresponding to the amount of charge transferred to the charge reading region 15 _{i-1, j} is vertical via the pixel selection transistor TS _{i-1, j.} It is output to the signal line Bj.

In the plan view shown in FIG. 7, the octagonal outer diameter line indicating the position (boundary) of the outer periphery of _{the read circuit unit 29 i-1, j is the amplification transistor QA i-1, j} and the pixel selection transistor TS _i-. Indicates a region provided with a field insulating film region that defines the active region in which _{1, j is formed.} That is, each active region of the amplification transistor QA _{i-1, j} and the pixel selection transistor TS _{i-1, j} constituting the read circuit unit 29 _{i-1, j} has a field insulating film as a planar pattern. It is defined by being surrounded by a thick oxide film corresponding to. There is no thick oxide film between the surface of the substrate region where the pattern of the transparent electrodes 21 _{i-1, j} is arranged and the surface of the substrate region where the pattern of the reading circuit section 29 _{i-1, j is arranged. Instead, on the surface of the substrate region, the element separation region 12o} and the channel stop region 17 similar to those illustrated in the cross-sectional view of FIG. 4 are continuous from the regions of other pixels such as the (i, j) th pixel. It is arranged as an area.

_{Further, in the charge reading region 15 i-1, j + 1} of the (i-1, j + 1) th pixel _{, the surface wiring 32 i-} directed to the lower right through the contact hole 31 _{i-1, j + 1. One end of 1, j + 1} is connected, and the amplification transistor QA _i-1 of the read circuit unit 29 _{i-1, j + 1} is connected to the other end of the surface wiring 32 _{i-1, j + 1. , j + 1} gate electrodes are connected. That is, in the circuit configuration shown in FIG. 7, since the charge read area 15 _{i-1, j + 1} functions as the source area of the reset transistor, the amplification transistor QA _{is set in the charge read area 15 i-1, j + 1. i-1, j +} gate electrode and the reset transistor TR _i-1 of _{1, j + 1} of the source region so that is connected. Amplifying transistor QA _{i-1, j + 1} pixel selection in a source region Trang Njisuta TS _{i-1, j + 1} of the drain region is connected, the power supply to the amplifying transistor QA _{i-1, j + 1} of the drain region Wiring V _DD is connected. Vertical signal line B _{j + 1} is connected to the source region of the pixel selection Trang Njisuta TS _{i-1, j + 1,} the gate electrode of the pixel selection Trang Njisuta TS _{i-1, j + 1,} from the vertical shift register The selection signal SL (i-1) on the (i-1) line is input. _{The output amplified by the amplification transistor QA i-1, j + 1} by the voltage corresponding to the amount of charge transferred to the charge reading region 15 _{i-1, j + 1} is the pixel selection transistor TS _{i-1, j.} It is output to the vertical signal line B _{j + 1 via +1.}

In FIG. 7, the octagonal outer diameter wire showing _{the read circuit unit 29 i-1, j + 1 forms the amplification transistor QA i-1, j + 1} and the pixel selection transistor TS _{i-1, j + 1} . The outer boundary of the field insulating film region for the purpose is shown. Field insulation between the active region of the amplification transistor QA _{i-1, j + 1 and} the active region of the pixel selection transistor TS _{i-1, j + 1 in} the read circuit unit 29 _{i-1, j + 1.} A thick oxide film corresponding to the film is formed. Thick oxidation between the surface of the substrate region where the pattern of the transparent electrodes 21 _{i-1, j + 1} is arranged and the surface of the substrate region where the pattern of the read circuit unit 29 _{i-1, j + 1 is arranged.} There is no film, and on the surface of the substrate region, the element separation region _12o and the channel stop region 17 similar to those illustrated in the cross-sectional view of FIG. 4 are the (i-1, j) th pixel and (i, j + 1). ) It is arranged as a continuous area from the area of other pixels such as the th pixel.

In particular, in the solid-state image sensor according to the first embodiment, when the charge generation embedded region 13 of each pixel is n-type, a negative voltage is applied to _{the transparent electrodes 21 i and j of each pixel.} , The action of holes generated by irradiation with gamma rays in the gate insulating film 23 of each pixel is canceled. Therefore, it is possible to obtain an image in which the increase in dark current is suppressed, noise due to dark current is small, and the dynamic range as a signal operation margin is maintained. That is, as described above, if the charge generation embedded region 13 of each pixel is n-type, the minority carriers are holes, so that the gate insulating film 23 directly below the _{transparent electrodes 21 i and j} An inversion layer 14 with a large number of holes is formed on the interface with the semiconductor, that is, on the surface of the charge generation embedded region 13, and the surface potential is pinned by holes which are minority carriers. In each pixel, the interface state of the interface between the gate insulating film 23 and the semiconductor is inactivated by pinning with holes.

In the solid-state image sensor according to the first embodiment, when each pixel is irradiated with gamma rays, holes are also generated in the thin gate insulating film 23 of each pixel, but the film thickness is thin. The absolute amount of holes generated in the gate insulating film 23 of each pixel is also small.

In the solid-state image sensor according to the first embodiment, the charges immediately below the _{transparent electrodes 21 i, j} , 21 _{i, j + 1} , 21 _{i-1, j} and 21 _{i-1, j + 1 of the respective pixels.} The charge photoelectrically converted in the generation embedded region 13 is transferred to the charge reading regions 15 _{i, j} , 15 _{i, j + 1} , 15 _{i-1, j} and 15 _{i-1, j + 1} , respectively, of the corresponding pixels. Accumulates for a certain period of time. The signal read from the pixel is performed line by line. First, for line i, this line is selected from the vertical shift register by the selection signal SL (i), and the signal levels of _{the charge read areas 15 i, j} , 15 _{i, j + 1, etc. are read.} Then the charge readout area 15 i by the vertical shift _{register, j,} 15 _i, after a reset operation, such as _{j + 1,} reading the charge read area 15 _{i, j,} 15 _i, the reset level, such as _{j + 1.} After that, for the next line (i-1), this line is selected from the vertical shift register by the selection signal SL (i-1), and the charge read areas 15 _{i-1, j} , 15 _{i-1, j + 1 are selected. Etc., and then the charge read area 15 i-1, j} , 15 _{i-1, j + 1} etc. are reset by the vertical shift register on that line, and then the charge read area 15 _i-1, Read reset levels such as _j , 15 _{i-1, j + 1.} The signal read from the pixels is subjected to a correlated double sampling operation that reads the difference between the signal level and the reset level in a column processing circuit provided in the peripheral circuit for each column, thereby removing offsets and the like. Only the net signal is output sequentially. However, there is no noise correlation between the signal level and the reset level read immediately after that. Therefore, the reset noise is not removed even by the correlated double sampling operation.

Next, a control method of the image pickup apparatus of the present embodiment equipped with the solid-state image pickup unit 1 described above will be described. FIG. 8 is a flow chart illustrating a control method for the image pickup apparatus of the present embodiment. First, in the image pickup apparatus, the dark current detection means 2 measures the voltage level output from the image pickup element located in the light-shielding pixel region 101 of the solid-state image pickup unit 1 (S1), and calculates the average value of the measured voltage levels. (S2). As this average value, the average of the voltage levels of a plurality of image pickup devices located in the light-shielding pixel region 101 measured in one frame can be used. The dark current detecting means 2 may process the measured dark current for a plurality of frames in succession and calculate the average value of the dark current over the plurality of frames.

Next, the dark current detecting means 2 determines whether or not the average value of the measured voltage levels exceeds the threshold value (predetermined range) (S3). When it is determined that the average value of the measured voltage levels exceeds the threshold value (S3: Yes), it is determined that the dark current is detected, and the dark current detecting means 2 optimizes the video signal that the dark electric pole is detected. Send to means 5. The dark current is not detected by an average value, but may be another embodiment such as taking the median value of the voltage level measured in the light-shielding pixel region 102.

When it is determined that a dark current is detected because the average value of the measured voltage levels exceeds the threshold value, the PG voltage is adjusted by the video signal detection means 4, the video signal optimization means 5, and the PG voltage control means 6. Processing is performed (S4). In the PG voltage adjusting process (S4), the video signal optimizing means 5 determines to change the control value of the PG voltage in response to receiving the fact that the dark current is detected from the dark current detecting means 2. The control value of the PG voltage is output to the PG voltage control means 6. At this time, the video signal optimization means 5 may determine whether or not the control value of the PG voltage exceeds the adjustable range. When the control value of the PG voltage exceeds the adjustable range, the dark current cannot be suppressed by further controlling the PG voltage, so a signal indicating that the image sensor is broken or prompting the replacement of the solid-state image sensor 1 is sent. It can also be configured to output. The PG voltage control means 6 changes the PG voltage of all the image pickup elements constituting the solid-state image pickup unit 1 based on the control value of the PG voltage received from the video signal optimization means 5.

FIG. 9 is a flow chart showing the flow of the PG voltage adjustment process (S4). As shown in FIG. 9, the video signal optimization means 5 that has received the fact that the dark current has been detected instructs the PG voltage control means 6 to raise (lower) the PG voltage by a predetermined value, and the PG voltage control means. No. 6 raises (lowers) the PG voltage of all the pixels of the solid-state image sensor 1 by an instructed value (S41).

With the PG voltage changed, the voltage level output from each pixel of the solid-state image sensor 1 is detected as a video signal by the video signal detecting means 4 (S42).

The video signal optimization means 5 calculates the saturated charge amount level based on the voltage level of each pixel detected as the video signal (S43). The saturated charge amount level is an index showing how much the saturated charge amount that fluctuates with the change of the PG voltage fluctuates from the saturated charge amount that is set when the gamma ray irradiation is zero. The fluctuation of the saturated charge amount was estimated by comparing the voltage level of the image obtained by normal shooting with a certain reference level, without strictly giving the pixel a light amount corresponding to the saturated charge amount and measuring it. Can be used. For example, the maximum voltage level is set to "1023", the reference value is set to "18%", the number of effective pixels is "1,300,000", and the effective pixels detected by the video signal detecting means 4 Consider the case where the sum of the voltage levels in the region 101 is 200,000. First, the sum of the voltage levels of all the effective pixels can be calculated as 1023 × 1,300,000 = 1,329,900,000, and if a reference value is given to the sum of the calculated voltage levels of all the pixels, , The reference level can be calculated. The reference level is the voltage level obtained in the initially set state. For example, the reference level can be calculated as 1,329,900,000 (sum of voltage levels of all pixels) x 0.18 (reference value) = 239,382,000. Further, the ratio of the calculated reference level to the total voltage level of the effective pixel region 101 detected by the video signal detecting means 4 is taken, and the saturated charge amount level is 239,382,000 / 200,000,000 = 1.197. Can be calculated. In this example, as long as the pixel used for the calculation includes at least an effective pixel region, it does not prevent the pixel from including the light-shielding pixel region from being included in the effective pixel region.

The video signal optimization means 5 can instruct the PG voltage control means to further increase or decrease the PG voltage based on the calculated saturated charge amount level 1.197 (S44). Of course, it may be instructed not to change the PG voltage. When the saturation charge level is increased, decreased, or fixed, the PG voltage can be freely set according to the characteristics of the solid-state image sensor 1, the image pickup target, the image pickup environment, and the like. Here, the case where the processing of S42 to S44 is performed only once is described as an example, but S42 to S44 may be repeated a plurality of times until the instruction that the PG voltage is not changed is given in S44.

On the other hand, when the dark current detecting means 2 determines that the dark current exceeding the threshold value has not been detected (S3: No), the dark current detecting means 2 notifies the luminance gradation control means 3 of the end of the dark current detection (S5). Upon receiving the notification of the end of dark current detection, the luminance gradation control means 3, the video signal detection means 4, and the video signal optimization means 5 perform a coefficient calculation process (S6).

In the reference coefficient calculation process (S6), the voltage level of each pixel of the solid-state image sensor 1 is sent to the video signal detecting means 4 via the luminance gradation control means 3. The video signal detecting means 4 detects the voltage level per frame of each pixel in the effective pixel region 101 of the solid-state imaging unit 1, and the video signal optimizing means 5 uses the detected voltage level as a reference for the correction coefficient. Calculate the reference coefficient.

The video signal optimization means 5 calculates a reference level based on the maximum voltage level and the number of effective pixels determined in advance for each solid-state imaging unit 1, and calculates the calculated reference level and all the pixels per detected frame. The reference coefficient for luminance gradation correction is determined from the ratio with the sum of the voltage levels of. The reference level may be calculated each time, but since it is determined in advance by the solid-state image sensor 1, the first calculated one may be stored and used thereafter. Since the reference coefficient can be calculated by the same method as, for example, the saturated charge amount level, the saturated charge amount level calculated in S4 can be used. For example, the maximum voltage level is set to "1023", the reference value is set to "18%", the number of effective pixels is "1,300,000", and the effective pixels detected by the video signal detecting means 4 Consider the case where the sum of the voltage levels in the region 101 is 200,000. First, the sum of the voltage levels of all the effective pixels can be calculated as 1023 × 1,300,000 = 1,329,900,000, and if a reference value is given to the sum of the calculated voltage levels of all the pixels, , The reference level can be calculated. For example, the reference level can be calculated as 1,329,900,000 (sum of voltage levels of all pixels) x 0.18 (reference value) = 239,382,000. Further, the ratio of the calculated reference level to the total voltage level of the effective pixel region 101 detected by the video signal detecting means 4 is taken, and the brightness gradation correction is 239,382,000 / 200,000,000 = 1.197. The reference coefficient for can be calculated. The video signal optimization means 5 sends the calculated reference coefficient for luminance gradation correction to the luminance gradation control means 3. In the reference coefficient calculation process, if the pixel used for the calculation includes at least an effective pixel region, it does not prevent the pixel from including the light-shielding pixel region in addition to the effective pixel region.

Since the coefficient calculated by the reference coefficient calculation process (S6) in this way is calculated using the actual output and the output that should be originally, that is, the output at the time of initial setting, the current output characteristic and the output characteristic that should be originally set. It can be said that the relationship with is properly expressed.

Upon receiving the reference coefficient for luminance gradation correction, the luminance gradation control means 3 determines the correction coefficient from the received reference coefficient for luminance gradation correction (S7), and outputs each output from the solid-state imaging unit 1. The voltage level of each pixel is corrected using the correction coefficient determined for the voltage level of the pixel (S8). The corrected voltage level of each pixel is output as an output video signal via the video signal detecting means 4.

Examples of the correction coefficient include the following three examples. (Example 1) These are P1 and P2 when the corrected value Y is obtained by multiplying the voltage level X by the coefficient P1 and subtracting the coefficient P2. In this case, the correction in S8 can be performed by Y = (X × P1) -P2. For example, the reference coefficient can be used as P1, and the reference coefficient multiplied by 0.05 can be used as P2.

(Example 2) These are P1 and P3 when the corrected value Y is obtained by multiplying the voltage level X by the coefficient P1 and multiplying the coefficient P3 by a power. In this case, the correction in S8 can be performed by ^{Y = (X × P1) P3.} In this example, so-called gamma correction, which corrects the video output characteristics on the display side on the image pickup device side, is also added. For example, the reference coefficient can be used as P1, and 0.45, which is the reciprocal of the gamma coefficient 2.2, which is a characteristic of the display, can be used as P3.

(Example 3) The correction coefficients P1, P2, and P3 determined in the above (Example 1) and (Example 2) are changed according to the amount of light (voltage level). For example, if P3 = 0.45 in the intermediate region, P3 = 0.40 when the amount of light (voltage level) is smaller than that in the intermediate region, and P3 = 0.50 when the amount of light is larger than that in the intermediate region. be able to.

The luminance gradation control means 3 repeats the correction until a predetermined time elapses (S9: No). When the dark current detecting means 2 determines that the predetermined time has elapsed, the dark current detecting means 2 returns to S1 and performs the dark current detecting process again (S9: Yes).
Here, the output video signal finally output will be described with reference to the figure for explaining the PG voltage control of FIG. 10 and the figure for explaining the luminance gradation adjustment of FIG.

Before absorbing gamma rays, the solid-state image sensor 1 is set so that the voltage level (output) with respect to the amount of light (light amount) incident on each pixel shows the characteristics of the curves A of FIGS. 10 and 11. The curve B in FIG. 10 shows the relationship between the amount of light and the output when each pixel of the solid-state imaging unit 1 absorbs a predetermined amount or more of gamma rays by using the image pickup device in a gamma ray environment. According to the curve B, it can be seen that the output of the portion where the amount of light is low is increased, and the dark current is increased from the initial state shown by the curve A. When it is determined that the dark current detecting means 2 has detected the dark current (S3: Yes in FIG. 8), the solid-state imaging unit 1 exhibits the characteristics shown in the curve B.

Curves C in FIGS. 10 and 11 show the relationship between the amount of light and the output when the solid-state image sensor 1 that has absorbed a predetermined amount or more of gamma rays is subjected to the PG voltage adjustment process (S4 in FIG. 8). .. The characteristic of the solid-state image sensor 1 as shown in the curve C is that the dark current is suppressed by the PG voltage adjustment process, but the saturation capacity is also reduced at the same time.

The curve D in FIG. 11 shows an output image when the voltage level output after performing the PG voltage adjustment process on the solid-state image sensor 1 that has absorbed a predetermined amount or more of gamma rays is further corrected by the luminance gradation control means 3. It shows the signal level (output) output as a signal with respect to the amount of light. In this way, the signal level characteristics output from the curve C to the curve D in FIG. 11 are as close as possible to the curve A before gamma ray absorption by correcting the luminance gradation (light intensity). It turns out that it can be done.

In the present embodiment, the processing of the coefficient calculation processing (S5) and the determination of the correction coefficient (S6) is only an example. Any method may be used as long as the coefficient is calculated based on the voltage level actually detected by the image sensor and the reference voltage level, and the correction coefficient can be further determined based on the calculated coefficient.

According to the image pickup apparatus of the present embodiment, radiation is achieved by adjusting the dynamic range by correcting the brightness level while suppressing the dark current by controlling the PG voltage while balancing the decrease in the saturated charge amount. It is possible to capture a good image even in an environment.

(Second Embodiment)
FIG. 12 is a block diagram showing a configuration example of the image pickup apparatus of the second embodiment. As shown in FIG. 12, the image pickup device of the second embodiment has a configuration in which a cooling means 7 for cooling the solid-state image pickup unit 1 is added to the image pickup device of the first embodiment. Since the configuration is the same as that of the first embodiment except for the configuration related to the cooling means 7, the description thereof will be omitted.

In the image sensor of this embodiment, the increase in dark current due to the absorption of gamma rays can be suppressed not only by adjusting the PG voltage but also by cooling the solid-state image sensor 1. It is preferable to suppress the dark current by cooling in advance of adjusting the PG voltage. As the cooling means 7, for example, a Peltier element arranged adjacent to the solid-state imaging unit 1 can be used. The solid-state imaging unit 1 can be cooled by lowering the temperature of the Peltier element by controlling the voltage applied to the Peltier element.

FIG. 13 is a diagram showing the effect of the cooling means 7. When the gamma ray is absorbed, the voltage level output characteristic of the solid-state image sensor 1 with respect to the amount of incident light changes from the characteristic shown by a straight line to the characteristic shown by a broken line. When an increase in dark current is detected when the characteristic changes to the characteristic shown by the broken line, the voltage applied to the cooling means 7 is controlled so as to suppress the increased dark current, and the solid-state image sensor 1 is cooled. When the solid-state image sensor 1 is cooled, the output characteristics of the solid-state image sensor 1 change so that the dark current decreases, as shown by the alternate long and short dash line in FIG. Suppression of the dark current by the cooling means 7 can reduce the dark current without causing a decrease in the saturation capacity, but the effect is limited. Therefore, the cooling means 7 can be used in combination with the PG voltage control means 6 to further improve the image quality.

(Third Embodiment)
FIG. 14 is a block diagram showing a configuration example of the image pickup apparatus of the third embodiment. The image pickup apparatus of the third embodiment has a colorized configuration of the image pickup apparatus of the first embodiment. Since the configuration other than the colorization is the same as that of the other embodiments, the description thereof will be omitted. In the image pickup device of the third embodiment, as shown in FIG. 14, the solid-state imaging unit 1, the dark current detection means 2, the luminance gradation control means 3, the video signal detection means 4, and the PG voltage control means 6 Are provided for each of the colors constituting the three primary colors, and further, the color correction control means 9 and the video signal optimization means 5 to which the output from the video signal detection means 4 of these three primary colors is input, and the color correction control. The color image signal detecting means 10 for detecting the colorized image signal from the means 9 is provided.

In the image sensor of this embodiment, a filter of any of the three primary colors of RGB is arranged at the incident portion of the solid-state image sensor 1, and each solid-state image sensor 1 measures the amount of light for any of the three primary colors. Measure and output the voltage level.

The color correction control means 9 performs color correction so that the color balance becomes appropriate based on the voltage level output from the image sensor of the solid-state image sensor 1 corresponding to each color. For example, the color video signal detecting means 10 detects the voltage level per frame of each pixel for each color and detects the total sum of all the pixels. The sum of all pixels for each color detected by the video signal optimizing means 5 is received, compared for each color, and a coefficient (color correction coefficient) for making the sum of all pixels the same for all colors is calculated. The color correction control means 9 corrects the voltage level of each color based on the calculated color correction coefficient.

According to the image sensor of this embodiment, for example, even when browning progresses due to exposure to gamma ray irradiation, the output sensitivity of the solid-state image sensor 1 corresponding to B (blue) is amplified, so that aging occurs. It is possible to suppress deterioration of image quality due to deterioration of typical color balance.

In this embodiment, the colors constituting the color image have been described by dividing them into the three primary colors of RGB, but the three primary colors other than RGB may be used, or the four primary colors or a combination of other colors may be used.

Further, the image pickup apparatus of the present embodiment has been described by taking as an example a configuration without cooling means like the image pickup apparatus shown in the first embodiment, but like the image pickup apparatus shown in the second embodiment, the cooling means May be provided.

In any of the embodiments, other noise removing means may be added.

1 Solid-state imaging unit 2 Dark current detection means 3 Brightness gradation control means 4 Video signal detection means 5 Video signal optimization means 6 PG voltage control means 7 Cooling means 9 Color correction control means 10 Color video signal detection means 11 Base area 12 _i Well region 12 _o Element separation region 13 Charge generation embedded region 14 Inversion layer 15 _{i, j} , 15 _{i, j + 1} , 15 _{i-1, j} , 15 _{i-1, j + 1} Charge read region 16 _{i, j} , 16 _{i, j + 1} , 16 _{i-1, j} , 16 _{i-1, j + 1} reset drain area 17 channel stop area 21 _{i, j} , 21 _{i, j + 1} , 21 _{i-1, j} , 21 _{i-1, j + 1} transparent electrode 22 _{i, j} , 22 _{i, j + 1} , 22 _{i-1, j} , 22 _{i-1, j + 1} reset gate electrode 23 Gate insulating film 29 _{i, j} , 29 _{i , j + 1} , 29 _{i-1, j} , 29 _{i-1, j + 1} Read circuit unit 31 _{i, j} , 31 _{i, j + 1} , 31 _{i-1, j} , 31 _{i-1, j + 1} Contact hole 32 _{i, j} , 32 _{i, j + 1} , 32 _{i-1, j} , 32 _{i-1, j + 1} Surface wiring 101 Effective pixel area 102 Light-shielding pixel area

Claims (2)

A solid-state image sensor having a plurality of pixels, each of which is composed of a PG (photogate) type CMOS image sensor.
A dark current detecting means that detects a dark current based on a voltage level obtained in a state where the PG type CMOS image sensor is shielded from light.
When the dark current is detected by the dark current detecting means, the PG voltage control means for suppressing the dark current by controlling the PG voltage of the PG type CMOS image sensor constituting the plurality of pixels of the solid-state imaging unit. ,
A correction coefficient determining means for determining a correction coefficient based on a voltage level obtained in a state where the PG type CMOS image sensor of the solid-state imaging unit is not shielded from light when the dark current is not detected by the dark current detecting means. ,
Luminance that controls the brightness gradation of the finally output video signal by correcting the voltage level output from each of the PG-type CMOS image sensors of the solid-state imaging unit using the determined correction coefficient. Equipped with a gradation control means
The PG voltage control means is an imaging device characterized in that the PG voltage is set to a PG voltage according to a saturation charge amount level that fluctuates when the PG voltage is changed by a predetermined value. The dark current detecting means calculates the average value of the voltage levels obtained in a state where the PG type CMOS image sensor is shielded from light, and if the average value is within a predetermined range, it is determined that the dark current has not been detected. The image pickup apparatus according to claim 1, wherein when the average value exceeds a predetermined range, it is determined that a dark current has been detected.

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