JP6834335B2 - Non-volatile associative memory - Google Patents

Description

The present invention relates to a non-volatile associative memory using a non-volatile storage element.

The associative memory (CAM: Content Addressable Memory) instantly compares the search data with the stored data and outputs the address of the matched stored data. In general, since the associative memory performs a completely parallel comparison operation on all the stored data arranged in a grid pattern, it is possible to execute a data search at a higher speed than the CPU operation. In recent years, such associative memory has been used for network routers, cache memories, and the like as the speed of networks increases, the number of servers increases, and the number of Internet users increases.

As an associative memory storage element, an associative memory using SRAM (Static Random Access Memory) is widely known. There are known associative memories that can store two logical states "0" and "1" and those that can store three logical states "0", "1" and "X". The latter is also referred to as a three-value associative memory (TCAM: Ternary Content Addressable Memory). Here, the bit in the "X" state means "Don't care", and it is regarded as a match regardless of whether "0" or "1" is input as the stored data.

The associative memory using SRAM can perform data search in a few ns. However, SRAM-based associative memory loses data when the power is cut off, so it is not possible to continue operation after the power is cut off, and the power must be kept on all the time, which causes a problem of large current consumption. there were. One method for solving this problem is to replace the SRAM of the volatile memory with a non-volatile memory. For example, Patent Documents 1 to 4 disclose an associative memory incorporating the non-volatile memory. Is written.

Patent Document 1 discloses a pair of magnetoresistive elements that are differentially connected in a memory cell, and a write circuit and a detection circuit that are connected to the magnetoresistive sensor. In the writing operation, a writing wiring is formed below the paired magnetoresistive element, and a writing magnetic field is generated by passing a current through the wiring, and the complementary information data is paired at one time. Write to. In the search operation, the paired magnetoresistive sensor functions as a differential pair type memory, and further includes a differential amplifier, and a detection circuit that outputs a match detection result to the match line works. Since the memory cell has 14T-2MTJ elements, the circuit configuration is slightly smaller in area compactness than the case where it is configured only by SRAM.

Patent Document 2 is similar to the circuit configuration of Patent Document 1, and discloses a differential pair type memory and a write circuit and a detection circuit connected to the differential pair type memory in the memory cell. Patent Document 2 discloses both a spin-injected domain wall moving memory and a spin-injected magnetoresistive sensor in the differential paired memory, and in particular, a write operation assuming a spin-injected domain wall moving memory. And the search and read operation is described. In the writing operation, the magnetic wall moves by passing an electric current through the writing wiring, and complementary information data is written at one time. In the search / read operation, the magnetic transfer type memory functions as a differential pair type memory, and data is transferred from the differential pair type memory to the paired inverter circuit composed of transistors to hold the potential of complementary information data. It is planned. Furthermore, the detection circuit that receives the output of the paired inverter circuit and outputs the match detection result to the match line works. Since the timing of the above data transfer is required, a delay time may be required due to the memory function. When the non-volatile associative memory of Patent Document 2 is used as a synchronous memory, smooth operation can be expected if data transfer is performed in accordance with the synchronous clock, but when used as an asynchronous memory, the timing of data transfer is expected. Is the delay time, so the operation speed is slow. Further, since the memory cell has the number of elements of 12T-2MTJ, the circuit configuration is slightly smaller in area and compactness than the case where the memory cell is composed only of SRAM.

Patent Document 3 discloses a pair of magnetoresistive elements and a writing circuit and a detection circuit connected to the paired magnetoresistive sensor in the memory cell. During the search / read operation, the paired magnetoresistive sensor does not function as a differential paired memory, but is considerably different from Patent Documents 1 and 2. Further, the paired magnetoresistive sensor has a feature that allows it to have three state values (0, 1), (1, 0), and (0, 0), and the writing operation is performed by one of the magnetic resistances. It should take two timings, such as writing "0" or "1" to the effect element first and writing "0" or "1" to the other magnetoresistive sensor later. No details are written. The non-volatile associative memory of Patent Document 3 is provided with a special state value of (0,0) in order to realize the function of "Don't care" of TCAM for each bit, but it is widely used at present. When used from the 8, 16, 32, or 64-bit central processing unit (CPU), it is somewhat difficult to handle because it must be handled so that one bit has three state values. The circuit of the 6T-2MTJ non-volatile TCAM cell is disclosed in the memory cell, the area compactness is very excellent, and the search can be operated at high speed, so that the circuit configuration is ideal.
Patent Document 4 is an improvement of Patent Document 3, and includes a single-ended sense amplifier. The circuit of the 9T-2MTJ non-volatile TCAM cell was disclosed in the memory cell, and the number of transistors increased a little. However, the search / read operation can be output as a voltage signal with a large amplitude to improve the accuracy, and The charge on the match line can be extracted at high speed, and the delay time can be significantly reduced.

Special table 2004-525473 Registration No. 5843265 JP 2012-190530 JP 2013-200920

In the conventional associative memory, one match line extending in the word direction is sequentially connected to a plurality of memory cells arranged in a grid pattern by a method of NOR type connection or NAND type connection, and generally, the match line has a high potential. The match line potential state is either kept at high potential or pushed down to low potential through comparison calculation processing in the search and read operation, and the result of match / mismatch is output. It was.
Since the memory cell is usually composed of an SRAM for storing and holding 1-bit data, that is, a pair of inverters, there are two output signal lines for outputting complementary data of the paired inverters. Due to the technical background of making memory elements non-volatile, it was quite natural that the paired inverter circuits themselves composed of transistors were replaced with paired magnetoresistive elements. One method is the configuration of a pair of magnetoresistive elements as a differential paired memory as disclosed in Patent Documents 1 and 2, and another method is Patent Documents 3 and 4. It is a configuration of a magnetoresistive sensor paired so as to write complementary data to each other as disclosed in.
In the case of Patent Documents 1 and 2, the operation of transferring data from the paired magnetoresistive element to the paired inverter and the delay time are required.
In the case of Patent Documents 3 and 4, the paired magnetoresistive sensor has three state values (0, 1), (1, 0), and (0, 0), and in particular, "Don't care". By intentionally providing the meaning state value (0,0), the writing operation becomes a little complicated. That is, the central processing unit (CPU) at the center of the system writes "0" or "1" to one magnetoresistive sensor first, and writes "0" or "1" to the other magnetoresistive sensor later. It requires two timings such as writing, and it is necessary to write three state values to the non-volatile storage unit of 1-bit data, which is inconvenient unlike access because it is in units of 8, 16, 32, and 64 bits. There was a problem that it occurred and could not be rewritten at high speed. The memory cell is composed of two magnetoresistive elements and six transistors, and is excellent in area compactness, but there is room for further reduction in the number of parts.

It is desirable to provide a magnetoresistive element for preliminary replacement with respect to the manufacturing yield and characteristic variation of the magnetoresistive element. When a pair of magnetoresistive sensor elements are used in a memory cell, even if one magnetoresistive sensor is a good storage element, the other magnetoresistive sensor is defective. There is no choice but to discard the cell itself, and a remedy for the storage element in the memory cell is desired. Therefore, it is desirable that one magnetoresistive sensor is used to store 1-bit data as much as possible in the memory cell, and another magnetoresistive sensor is provided as a preliminary replacement. In order to improve the manufacturing yield of the magnetoresistive sensor, the authors carried out Write Endurance10E 10 times (rewrite resistance), induced a defective initial failure, and replaced it with a preliminary replacement magnetoresistive element to improve the yield. ing.

The problem to be solved in this patent is to reduce the number of non-volatile storage units in the memory cell while maintaining the high speed, area compactness, and low power consumption of the memory cell in the non-volatile associative memory.
However, there is a limit to the reduction in the number of parts in the configuration having one match line of the prior art and a pair of non-volatile storage units.

The means for solving the problem is as follows.
(1) An associative memory having a plurality of memory cells in a grid pattern, in which at least one or more non-volatile storage units, a write circuit, a read circuit, and a comparison calculation circuit are integrated in each memory cell. To
By being connected to a first matchline precharged to a high potential and a second matchline precharged to a low potential, the circuit function in the memory cell is particularly mentioned. The existence of two match lines is different from the conventional non-volatile associative memory.
(2) The memory cell has a first switch element that supplies a current for reading the non-volatile storage unit and a second switch element that supplies a current for writing to the non-volatile storage unit. And a third switch element arranged between the non-volatile storage unit and the first match line in order to perform a comparison calculation between the potential of the non-volatile storage unit and the potential of the first match line. And a fourth switch element arranged between the non-volatile storage unit and the second match line in order to perform a comparison calculation between the potential of the non-volatile storage unit and the potential of the second match line. The non-volatile associative memory according to (1), which comprises the above, can be composed of four switch elements in the memory cell, and the number of parts can be reduced.
(3) In the memory cell, one end of the non-volatile storage unit is connected to a first connection point, and the other end of the non-volatile storage unit is connected to a second current energization bit wire. Department and
A second switch element in which a switch control electrode for controlling a write current supply is connected to a second word line, and one end of the second switch element are connected to a first current energizing bit line, and a second The other end of the second switch element is connected to the first connection point, and the first current energizing bit wire, the second switch element, the first connection point, the non-volatile storage unit, and the second A writing circuit in which the current energizing bit wire of the
A switch control electrode for controlling the read current supply is connected to the first switch element connected to the first word line, and one end of the first switch element is connected to the terminal Vdd which is the starting point on the high potential side of the read current. At the same time, the other end of the first switch element is connected to the first connection point, and the terminal Vdd of the high potential side starting point, the first switch element, the first connection point, the non-volatile storage unit, and the above. A readout circuit in which a second current energizing bit wire is connected in series, and
A third switch element in which a switch control electrode for controlling a comparison operation with the first match line is connected to the first search line, and one end of the third switch element are connected to the first match line. At the same time, the other end of the third switch element is connected to the first connection point, and the first match line, the third switch element, the first connection point, and the high potential side of the non-volatile storage unit are connected. A comparison arithmetic circuit with one end connected in series,
A fourth switch element in which a switch control electrode for controlling a comparison operation with the second match line is connected to the second search line, and one end of the fourth switch element are connected to the second match line. At the same time, the other end of the fourth switch element is connected to the first connection point, and the second match line, the fourth switch element, the first connection point, and the high potential side of the non-volatile storage unit. The non-volatile associative memory according to (1) and (2), characterized in that one end is composed of a comparison arithmetic circuit connected in series, and clarification of an external signal line that controls four switch elements. At the same time, since the comparison calculation can be performed by using one end on the high potential side of one non-volatile storage unit, there is an effect of reducing the non-volatile storage unit.
(4) In the memory cell search operation, the first switch element that supplies the read current is turned on.
When the first search line is in the high potential state and the second search line is in the low potential state, the third switch element is turned on, depending on the product of the resistance state of the non-volatile storage unit and the read current. A comparison calculation is performed between the first voltage and the second voltage precharged to the high potential state of the first match line.
When the first search line is in a high potential state and the second search line is in a low potential state, the fourth switch element is turned off, depending on the product of the resistance state of the non-volatile storage unit and the read current. No comparison calculation is performed between the first voltage and the third voltage precharged to the low potential state of the second match line.
When the first search line is in the low potential state and the second search line is in the high potential state, the third switch element is turned off, depending on the product of the resistance state of the non-volatile storage unit and the read current. No comparison calculation is performed between the first voltage and the second voltage precharged to the high potential state of the first match line.
When the first search line is in the low potential state and the second search line is in the high potential state, the fourth switch element is turned on, depending on the product of the resistance state of the non-volatile storage unit and the read current. The non-volatility according to (1) and (2), wherein a comparison calculation is performed between the first voltage and the second voltage precharged in the low potential state of the second match line. It is an associative memory, and realizes a function of outputting a comparison calculation result to only one side of two match lines through two switch elements controlled by two search lines.
(5) The first word line transmitted by the switch control signal for supplying the read current and the second word line transmitted by the switch control signal for supplying the write current are used in combination. The non-volatile associative memory according to (1) to (4), wherein the number of word-side external signal lines for controlling the switch element can be reduced, and the number of switch elements can be reduced.
(6) The memory cell has a first connection point to which one end of the non-volatile storage unit and an input end of a sense amplifier are connected, and further has a second connection point to which an output end of the sense amplifier is connected. One end is connected to the first connection point, and a switch control electrode for supplying a read current is connected to a first switch element connected to the first word line, and the first The connection point has a function of a signal line that propagates a voltage according to the resistance state of the non-volatile storage unit, one end is connected to the second connection point, and the respective switch control electrodes are the first and first. The fifth and sixth switch elements connected to the second search line and the other ends of the fifth and sixth switch elements are connected to the first and second match lines, respectively.
Further, a second switch element in which one end is connected to the first connection point and a switch control electrode for supplying a write current is connected to a second word line, and a second switch element. The non-volatile associative memory according to (1), wherein the other end is connected to the first writing line and the other end of the non-volatile storage unit is connected to the second writing line. The signal difference of the read potential of the storage unit, that is, the potential difference between the high resistance and the low resistance can be greatly amplified, the detection margin can be secured, and the comparison calculation can be performed at high speed.
(7) The non-volatile associative memory described in (1) to (6) is arranged in close proximity to a memory cell divided into a plurality of n-bit areas and the n-bit area. By including a memory cell having a value of X "(Don't care), it is possible to obtain a non-volatile TCAM having a valid bit in the entire system.
(8) The non-volatile associative memory described in (1) to (6) is arranged in close proximity to a memory cell divided into a plurality of n-bit areas and the n-bit area. By including a memory cell having an X ”(Don't care) value and a memory cell having a calculated parity value, a non-volatile TCAM having a parity bit can be obtained in the entire system. Data accuracy can be improved.
(9) The memory cell has at least two or more non-volatile storage units in which a selection switch element for preliminary replacement and a non-volatile magnetic storage element connected in series are connected in parallel. 2. The method (1) to (6), wherein one of the selection switch elements is turned on and the other selection switch element is turned off by a selection signal drawn from the external control unit of the cell. This is a non-volatile associative memory of the above, and even if a defective memory cell exists in the memory cell, it can be replaced, and the manufacturing yield can be improved.
(10) The memory cell has at least two or more non-volatile storage units in which a selection switch element for preliminary replacement and a non-volatile magnetic storage element connected in series are connected in parallel. It has a decoder circuit that inputs a selection signal drawn from the external control unit of the cell, and decodes and outputs so that one selection switch element is in the ON state and the other selection switch element is in the OFF state. The non-volatile associative memory according to (1) to (6) is characterized, and even if a defective memory cell exists in the memory cell, it can be replaced, and the manufacturing yield can be improved.
(11) The memory cell has at least two or more non-volatile storage units in which a selection switch element for preliminary replacement and a non-volatile magnetic storage element connected in series are connected in parallel. It has a fuse storage circuit or a memory storage circuit for inputting a selection signal drawn from an external control unit of a cell, and a decoding circuit for decoding the stored numerical value, and one of the selection switch elements is turned on. The non-volatile associative memory according to (1) to (6), characterized in that the other selection switch element is decoded and output so as to be in the OFF state, and a defective memory cell exists in the memory cell. Can be replaced, and the manufacturing yield can be improved.

According to the present invention, the number of non-volatile storage units can be reduced by providing the non-volatile associative memory with two match lines. In the non-volatile associative memory of the present invention, the number of non-volatile storage units in the memory cell is one, and the number of switch elements is four, while maintaining the high speed and low power consumption of the memory cell. It was possible to configure it, and it was possible to achieve a significant area compactness.
Further, by having two match lines of the present invention and having only one non-volatile storage unit in the memory cell, the overall size of the non-volatile associative memory can be significantly reduced. It is not possible to memorize the three values as in Documents 3 and 4. Instead, in the present proposal, TCAM can be realized by providing a valid bit for each n bits in the entire system of the non-volatile associative memory, and in addition, the data accuracy can be improved by providing the parity bit.
Further, by providing the two match lines of the present invention and having one non-volatile storage unit carry out 1-bit data storage, it is easy to place the non-volatile storage unit for preliminary replacement in the same memory cell. became. The reason is that the reconnection wiring for replacement can be simplified, and the size can be reduced even when two non-volatile storage units, one for regular replacement and the other for preliminary replacement, are provided.

Explanatory drawing showing the relationship between the tunnel-type magnetoresistive element and the write current Explanatory drawing of RI hysteresis curve of tunnel magnetoresistive element 4T-1MTJ type non-volatile associative memory cell according to the present invention Truth table showing the operation of the non-volatile TCAM according to the present invention 4T-1MTJ type non-volatile associative memory cell according to the present invention 4T-1MTJ type non-volatile associative memory cell according to the present invention Non-volatile associative memory cell including sense amplifier according to the present invention Overall configuration of non-volatile associative memory Matchline sensing control / output driver circuit Truth table of judgment circuit of p-ML and n-ML Overall configuration of the TCAM including the ballid bit according to the present invention Overall configuration of TCAM including ballit bit and parity bit according to the present invention 6T-2MTJ type non-volatile associative memory cell that can be replaced according to the present invention Non-volatile associative memory cell capable of preliminary alternation including decoding circuit according to the present invention Pre-replaceable non-volatile content addressable memory cells including fuse / memory and decoding circuits according to the present invention

The structure of the magnetoresistive sensor 10 used in the non-volatile associative memory of the present invention is shown in FIGS. 1A and 1B, and the circuit notation of the magnetoresistive sensor 10 is shown in FIG. The magnetic resistance effect element 10 is composed of two magnetic material layers called a free magnetizing layer 11 and a fixed magnetizing layer 13 and a non-magnetic layer 12 sandwiched between them, and the free magnetizing layer 11 and the fixed magnetizing layer 13 are magnetized in different directions. When are parallel, the electric resistance of the magnetic resistance effect element is low (Rp: resistance value when parallel), and when the magnetization directions are antiparallel, the electric resistance of the magnetic resistance effect element is high (Rap: when antiparallel). Resistance values). Since these resistance states are maintained even when the power is turned off, non-volatile data storage becomes possible. Compared with other non-volatile memory elements, the magnetoresistive sensor has features of high rewrite resistance, low power writing, compatibility with CMOS processes, and high-speed rewriting, and is extremely useful. Data is written to the magnetoresistive sensor 10 by a spin injection type magnetization reversal phenomenon that causes magnetization reversal of the magnetization free layer 11 by passing a current of a certain value or more through the element. By passing a current from the magnetizing free layer 11 of the magnetic resistance effect element 10 to the magnetization fixing layer 13, the magnetization direction of the magnetizing free layer 10 becomes parallel (Rp) to the magnetization fixing layer 13, and conversely, the current is transmitted from the magnetization fixing layer 13. By flowing the current through the magnetizing free layer 11, the magnetization direction of the magnetizing free layer 11 becomes antiparallel (Rap) with the magnetizing fixed layer 13. In the circuit notation of the magnetoresistive sensor 10 in (c), the upper side is the magnetization free layer 11 and the lower side is the magnetization fixed layer 13, and the phenomenon of magnetization reversal occurs according to the direction in which the current flows. For example, when the upward current IPtoAP is energized, the magnetization state of the magnetization free layer 11 changes from the parallel state to the antiparallel state, and when the downward current IAPtoP is energized, the magnetization state of the magnetization free layer 11 changes from the antiparallel state to the parallel state. To do. In FIG. 1, the magnetized free layer 11 and the magnetized fixed layer 13 depict a magneto-resistive magnetic resistance effect element (Parpendicular Magneto-reactive) of a vertical magnetization type that is magnetized substantially in the normal direction with respect to the film surface. An internal magnetization type magnetoresistive element (In-plane Magneto-resistive) can be similarly configured.

FIG. 2 shows the RI hysteresis curve of the magnetoresistive sensor. The low resistance value (Rp) when the magnetization states of the magnetoresistive sensor 10 are parallel is set to the logical value "0", and the high resistance value (Rap) when the magnetization states are antiparallel is set to the logical value "1". There is. The arrow drawn near the RI hysteresis curve shows the state of the storage memory by applying a write current to the magnetoresistive element 10. As a function of the non-volatile storage memory, the state of storing and retaining the memory even when the current is cut is that the logical value “0” in the low resistance state (Rp) is obtained when Current = 0 (zero) on the X axis in FIG. And, it means that there are two statuses of the logical value "1" in the high resistance state (Rap). Further, regarding the rewriting operation of the storage memory, when "1" is written, it passes through the write "1" of the arrow, and the logical value "0" in the low resistance state (Rp) to the logical value "1" in the high resistance state (Rap). When writing "0", it passes through the write "0" of the arrow and changes from the logical value "1" in the high resistance state (Rap) to the logical value "0" in the low resistance state (Rp). It shows the transitional magnetization reversal.

FIG. 3 shows the 4T-1M type non-volatile associative memory cell 15 according to the present invention divided into (a) to (d). FIG. 3A shows a basic circuit of a memory cell, which is characterized by having one magnetoresistive sensor R as a storage unit in the memory cell and outputting a match detection result. It has lines, that is, signal lines p-ML and n-ML, each of which extends in the word direction, and the signal line p-ML of the match line is precharged to a high potential, whereas the signal line n of the match line. -ML is precharged to a low potential.
As a conventional example, Patent Documents 1 and 2 have two magnetoresistive elements as differential paired memories, and Patent Documents 3 and 4 have two magnetoresistive elements for writing complementary data. It is disclosed. Further, in Patent Documents 1, 2, 3, and 4, there is only one match line that outputs a match detection result, which extends in the word direction and is precharged to a high potential.
The difference between the non-volatile associative memory cell of the present invention and the conventional example is remarkable.

In FIG. 3B, the writing circuit 16 in the memory cell is surrounded by a dotted line, and the contents of the circuit include a signal line WBL through which a writing current flows, a transistor M2, a magnetoresistive sensor R, and writing. The signal line WBLB through which current flows is connected in series. In the 1-bit data writing operation, a high potential with a logic value of "1" is applied to the read signal line CLK, the transistor M1 is turned off, and a low potential with a logic value "0" is applied to the search signal line SL. Then, the transistor M3 is turned off, and the search signal line SLB needs to be turned off by applying a low potential of the logic value “0”, and the above-mentioned writing circuit 16 is operated. In order to make the signal line WEN effective for the write operation, a high potential of a logical value "1" is applied, the transistor M2 is turned on, and the magnetic force is applied between the two signal lines WBL and WBLB through which the write current flows. The rewriting operation of the stored data is completed by giving an appropriate voltage difference for causing the magnetization reversal of the resistance effect element R.

In FIG. 3C, the read circuit 17 in the memory cell is surrounded by a dotted line, and the contents of the circuit include a Vdd terminal serving as a starting point on the high potential side of the read current, a transistor M1, and a magnetoresistive effect. The element R and the signal line WBLB through which the write current flows are connected in series. However, the signal line WBLB at the time of the read operation has a function of drawing the current as a SINK and a function of drawing the current as a SINK as well as a function of giving a voltage Vsink in a low potential state close to the GND level. In the 1-bit data read operation, a low potential of a logical value "0" is applied to the write signal line WE, the transistor M2 is turned off, and the signal line WBLB through which the write current flows becomes the lead-in end of the read current. Further, in order to operate the read circuit 17, the read signal line CLK is applied with a low potential of the logic value “0” to turn on the transistor M1, and the read operation of the stored data is completed. The transistor M1 having a switch function also serves as a load resistor in the ON state in which the read current is energized. The load resistance of the transistor M1 and the resistance value of the magnetoresistive sensor R distribute the applied voltage of Vdd-Vsink, and the potential Vr is present at the connection point between the transistor M1 and the magnetoresistive element R. appear.

In FIG. 3D, the comparison calculation circuit 18 in the memory cell is surrounded by a dotted line, and the content of the circuit is for capturing the potential Vr generated between the transistor M1 and the magnetic resistance effect element R. A connected signal connection point, a transistor M3 switch-controlled by the signal line SL for search, and a match line signal line p-ML that holds a high potential Vp-ML as a comparison target with the potential Vr. Search It is composed of a transistor M4 switch-controlled by the signal line SLB for search, and a match line signal line n-ML that holds Vn-ML as a comparison target with the potential Vr. In particular, the signal connection point of the potential Vr, the transistor M3, and the signal line p-ML of the match line have a first series connection relationship, and the signal connection point of the potential Vr, the transistor M4, and the signal line n- of the match line are connected. The ML has a second series connection relationship, and the first series connection series and the second series connection are arranged in parallel with each other.

When the comparison calculation circuit 18 operates, the read circuit 17 also needs to operate at the same time. During the search comparison operation, in the 1-bit data read operation, a low potential of a logic value "0" is applied to the write signal line WEN, the transistor M2 is turned off, and the signal line WBLB through which the write current flows is the read current. In order to operate the read-out circuit 17 as described above, a low potential with a logical value of “0” is applied to the read-out signal line CLK to turn on the transistor M1 to turn on the transistor M1 and the magnetic resistance. An electric potential Vr is generated at the connection point with the effect element R. Next, in the search comparison operation between the read value of the 1-bit data in the memory cell and the search data, if the logical value of the search data is "1", the signal line SL for the search search is the logical value "1". By applying the high potential state of "" to turn on the transistor M3, the signal connection point having the potential Vr and the signal line holding the high potential Vp-ML are connected, and the potential of the high potential Vp-ML becomes high. It is either held as it is or pushed down, which means that the potential change of Vp-ML is acting as a comparison calculation function, and if the logical value of the search data is "0", the search is performed. When the high potential state of the logic value "1" is applied to the signal line SLB for the search and the transistor M4 is turned ON, the signal connecting point having the potential Vr and the signal holding the low potential Vn-ML are held. The lines are connected and the low potential Vn-ML potential is either held as it is or pushed up, which means that the potential change of the Vn-ML acts as a comparative calculation function.

FIG. 4 is a truth table in the non-volatile associative memory cell of the present invention shown in FIG. FIG. 4A shows the logical state of the search comparison operation of the 1-bit data and the search data in the memory cell. When the signal line WBLB in FIG. 3 is in the Vsink low potential state of the logical value “0” and a pulse signal having the logical value “0” is applied to the signal line CLK, a read current flows through the magnetoresistive effect element R. A potential Vr is generated at the signal connection point between the transistor M1 and the magnetoresistive sensor. When the magnetoresistive sensor R is in a low resistance state, the potential Vr is in a low resistance state with a logic value of “0”, and when the magnetoresistive sensor R is in a high resistance state, the potential Vr is a high potential with a logic value of “1”. The state is reached and the digitally determined value is listed in the truth table.

Search The signal lines SL and SLB for searching are in a complementary relationship with each other so that if one logical value is "1", the other logical value is "0". Assuming that the search data is "1", a high potential of a logical value "1" is applied to the signal line SL of one of the searches, the transistor M3 is turned on, and the signal line p- holding the high potential Vp-ML is turned on. The signal line SLB is connected to the ML with low impedance, the low potential of the logic value "0" is applied to the signal line SLB of the other search, the transistor M4 is turned off, and the signal line n-ML holding the low potential Vn-ML is turned off. Is connected with high impedance. Assuming that the search data is "0", a low potential of a logical value "0" is applied to the signal line SL of one of the searches, the transistor M3 is turned off, and the signal line p- holding the high potential Vp-ML is turned off. The signal line SLB is connected to the ML with high impedance, the high potential of the logic value "1" is applied to the signal line SLB of the other search, the transistor M4 is turned on, and the signal line n-ML holding the low potential Vn-ML is turned on. Is connected with low impedance. Although not shown in FIG. 4A, the WEN is always set to a low potential state with a logical value of “0” during the 1-bit data search / comparison operation, and the transistor M2 in FIG. 3 is always in the OFF state. The potential Vr of one terminal of the magnetoresistive sensor connected to M1 and the connection point is not affected.

FIG. 4B shows the logical state at the time of writing to the CAM cell of 1-bit data. During the data writing operation, the signal line WBL (write bit line) and the signal line WBLB (write bit line bar) are "0" if one is "1" and the other if one is "0". Are complementary to each other, such as "1". When the signal line WBLB has a high potential value of "1" in FIG. 3, the signal line WBLB has a low potential value of "0", and a positive pulse signal is applied to the WEN terminal, the magnetoresistive effect The element is written so as to be in a low resistance state with a logic value of “0”. When the signal line WBLB has a low potential value of “0” in FIG. 3, the signal line WBLB has a high potential value of “1”, and a positive pulse signal is applied to the WEN terminal, the magnetoresistive effect The element is written so as to be in a high resistance state with a logical value of "1".
Although not shown in FIG. 4B, during the operation of writing data, the high potential state of the logical value “1” is always input to CLK, and the transistor M1 in FIG. 3 is always in the OFF state, which leads to series connection. The potential states of the signal line WBL, the transistor M2, the magnetoresistive effect element R, and the signal line WBLB are not affected.
In the circuit operation in the cell of FIG. 3, when the search data is "1", the signal line SL for one of the search searches shows a logical value "1" in a high potential state, and the gate electrode of the transistor M3 is ON. The search comparison function is effective because the transistor M3 becomes conductive and the potential Vr due to the voltage drop of the magnetic resistance effect element R is connected to the signal line p-ML of the match line precharged in the high potential state. In that state, that is, when the magnetic resistance effect element R is in a high resistance state, the signal line p-ML of the match line maintains a high potential state, but when the magnetic resistance effect element R is in a low resistance state, the match line The signal line p-ML of the above acts to push down the precharged high potential. Further, if the search data is "1", the signal line SLB for the other search search shows a logical value "0" in the low potential state, the gate electrode of the transistor M4 is in the OFF state, and the transistor M4 is in the cutoff state. It becomes a high impedance state with respect to the signal line n-ML of the match line precharged to the low potential state, and becomes the signal line n-ML of the match line regardless of the potential Vr due to the voltage drop of the magnetic resistance effect element R. Does not affect.
In the search comparison operation of the CAM cell circuit of FIG. 3, when the search data is "0", the signal line SL of one of the search searches shows a logical value "0" in a low potential state, and the gate electrode of the transistor M3 is OFF. The transistor M3 is cut off, and the impedance is high with respect to the signal line p-ML of the match line precharged in the high potential state regardless of the potential Vr due to the voltage drop of the magnetic resistance effect element R. It does not affect the signal line p-ML of the match line precharged in the high potential state. Further, if the search data is "0", the signal line SLB for the other search search shows a logical value "1" in a high potential state, the gate electrode of the transistor M4 is turned ON, and the transistor M4 is in a conductive state. Therefore, the potential Vr due to the voltage drop of the magnetic resistance effect element R is connected to the signal line n-SL of the match line precharged in the low potential state, so that the search comparison function is enabled, that is, the magnetic resistance effect element. When R is in a high resistance state, the signal line n-ML of the match line acts so as to push up the precharged low potential, and when the magnetic resistance effect element R is in a low resistance state, the signal line of the match line. n-ML maintains a low potential state.

FIG. 5 shows an example of another 4T-1MTJ type non-volatile associative memory cell according to the present invention. While maintaining the same function as the non-volatile associative memory cell of FIG. 3, the signal line CLK and the signal line WEN are reduced to one of the signal line CLK / WEN. However, when the non-volatile associative memory is in a low power consumption mode such as a standby standby state, it has a hibernation state in which the read current is stopped. Therefore, the voltage difference between the signal lines WBL and WBLB of the write current is close to 0 volt so that the write operation does not occur even when the signal line CLK / WEN is set to the high potential state of the logical value “1”. A method is provided in which either the signal line WBL or WBLB of the write current is controlled to the High-Z state, and the circuit is devised so that the write current does not flow into the magnetoresistive effect element R during standby standby. There is a need.

FIG. 6 shows an example of another 4T-1MTJ non-volatile associative memory cell according to the present invention. While maintaining the same function as the non-volatile associative memory cell of FIG. 3, in FIG. 6A, the NMOS transistor M3 remains the same NMOS transistor M3, and the NMOS transistor M4 is changed to the MOSFET transistor M4Rev. On the other hand, in FIG. 6B, the NMOS transistor M3 is changed to the NMOS transistor M3Rev, and the NMOS transistor M4 remains the same MOSFET transistor M4. Search It also has a feature that either one of the signal lines SL or SLB of the search can be deleted. However, the true purpose of the change in this case is when the potential Vr at the signal connection point between the transistor M1 and the magnetic resistance effect element R is compared with the high potential state Vp-ML or the low potential state Vn-ML. When both the transistor M3 and the transistor M4 are composed of an NMOS transistor, the switching control voltage between the gate and source of both transistors is considerably different, and problems such as a difference in ON resistance and a difference in switching speed of both transistors are faced. To solve this problem, transistors M3 and transistors M4 are used as transistors having different polarities of NMOS and NMOS. In the example of FIG. 6B, the MOSFET transistors M3Rev and the NMOS transistors M4 having different polarities are used, and the source terminals are the signal lines p-ML of the high potential state Vp-ML or the signal line p-ML of the low potential state Vn-. It is connected to the ML signal line n-ML. By applying a low potential with a logic value of "0" to the gate terminal of the MOSFET transistor M3Rev, a large voltage difference between the gate and source can be obtained, the ON resistance can be reduced, and the switching speed can be increased. By applying a high potential with a logic value of "1" to the gate terminal of the NMOS transistor M4, a large voltage difference between the gate and source can be obtained, the ON resistance is reduced, and the switching speed is increased. Improvement can be expected.

FIG. 7 shows an example of another non-volatile associative memory according to the present invention. By incorporating the single-ended sense amplifier circuit SA1 in the cell, the signal voltage difference (change in Vr) between the low resistance state and the high resistance state of the magnetoresistive sensor R is output as a full-amplitude signal voltage and matches. -The mismatch detection margin can be improved. The sense amplifier SA1 is composed of an inverter circuit IV and a transistor M15. Therefore, although it has a feature of being compact in area, it outputs data inverted with respect to the input data. Therefore, in order to repair the inversion caused by the sense amplifier SA1, the signal lines SL and SLB of the search search are replaced with those of FIG. 3 in the opposite direction to that of FIG. In the circuit operation of FIG. 7, when the magnetic resistance effect element R is in the high resistance state, the potential Vr is in the high potential state of the logical value “1”, and when it passes through the sense amplifier SA1, it reaches the GND level of the logical value “0”. A close low potential state is output, which is connected to the signal line n-ML, a comparison calculation is performed with the low potential state Vn-ML, and the comparison result is reflected in the signal line n-ML. When is in the low resistance state, the potential Vr is in the low potential state of the logical value "0", and when it passes through the sense amplifier SA1, it outputs the high potential state close to the Vdd level of the logical value "1". It is connected to p-ML, a comparison calculation is performed with the high potential state Vp-ML, and the comparison result is reflected on the signal line p-ML.

FIG. 8 shows the overall configuration of the non-volatile associative memory 100 that performs a completely parallel search. A plurality of associative memory cells 104 are arranged in a grid pattern in the center thereof. The non-volatile associative memory 100 includes a column-side direction control unit 101 at one end in the bit line direction (on the Y-axis), and the column-side direction control unit 101 is “0” depending on the stored values of the search data memory and the search data memory. Alternatively, it is equipped with a search line driver that outputs a logical value of "1", a column decoder of the address, and a write bit line decoder that transmits the write current. The non-volatile associative memory 100 includes a row side direction control unit 102 at one end in the word line direction (on the X axis), outputs a low decoder of the address, a read control unit that outputs and controls the read signal line CLK, and outputs a write signal WEN. It has a write control unit to control. The non-volatile associative memory 100 is provided with two match lines that output match / mismatch results between the search data memory and the stored data in the word line direction, and a match line sensing control / output driver 103 at one end thereof. ing.
The overall configuration of the non-volatile content addressable memory 100 includes a register group in which search data is stored in the column side direction control unit 101, and each register has a complementary signal for searching according to the register value. The lines SLx and SLBx are output, and the complementary write current lines WBLx and WBLBx for rewriting the stored data of the associative memory cell 104 are output.
In the completely parallel type search, a match line sensing control is performed by performing an instantaneous comparison operation between the register value of the search data in the column side direction control 101 and the stored data of each associative memory cell 104 connected in the word direction. -Finally, the match determination result is output to the signal ML Output m (m is a natural number of 1, 2, ...) Output from the output driver 103.

FIG. 9 shows the circuit 110 of the match line sensing control unit / output driver according to the present embodiment.
The matchline sensing control unit / output driver circuit 110 inputs the signal lines p-ML and n-ML of the two matchlines connected to the plurality of associative memory cells 104 arranged in the word direction, and finally Output the judgment result. The contents of the circuit are composed of a sensing circuit unit 112 of the signal line p_ML, a sensing circuit unit 113 of the signal line n_ML, an inverter 114, an AND 115, and an output driver 116.
FIG. 10 is a truth table in the circuit 110 of the match line sensing control unit / output driver shown in FIG.

FIG. 11 shows the overall configuration of a fully parallel TCAM 200 including a valid bit meaning “Don't care” according to the present invention. Detailed description of the column side direction control 101, the row side direction control 102, and the match line sensing control / output driver 103 will be omitted. The plurality of associative memory cells 105 arranged in a grid pattern are composed of a CAM cell 201 for normal 1-bit data storage and a valid bit CAM cell. The CAM cells 201 are arranged by connecting 8 adjacent bits in the word line direction (on the X-axis), and they are numbered as CAM cells 0 to CAM cells 7, and the CAM of the valid bits is close to the CAM cells 7. It is configured in 1-byte units including cell 202. One CAM cell 201 can only store "0" and "1". Therefore, it has a separate valid bit CAM cell 202, and when a logical value "1" is input therein, it functions so as to consider that all 8 bits of the CAM cell 201 match.
The reason why the CAM cells are connected in 8-bit units is that the frequency of character code searches in 1-byte units such as character searches is high, and the central processing unit (CPU), which is more widely used, reads and writes data. This is because 1-byte units are a convenient size for doing so. The valid bit becomes more convenient if a reset signal is used so that the signal line Reset can be used to clear a plurality of valid bids arranged in the word direction to the logical value "0" all at once. Next, in the internal circuit and operation of the CAM cell of the valid bit, a secondary signal that similarly outputs the comparison calculation result to the signal lines p-ML and n-ML that finally output the comparison calculation result. The lines Sub_p-ML and Sub_n-ML are provided, and the signal lines p-ML and n-ML are circuit-separated from the secondary signal lines Sub_p-ML and Sub_n-ML. At the time of search comparison operation, the comparison calculation result of CAM cell 0 to CAM cell 7 is output to the signal lines Sub_p-ML and Sub_n-ML, but if the logical value of the CAM cell of the valid bit is "0", the signal line The switch element works as ON so as to connect Sub_p-ML and Sub_n-ML to the signal lines p-ML and n-ML, respectively, and the match / mismatch result of CAM cells 0 to CAM cells 7 is controlled by match line sensing in the subsequent stage. It is reflected in the unit / output driver 110, and if the logical value of the CAM cell of the valid bit is "1", the signal lines Sub_p-ML and Sub_n-ML can be connected to the signal lines p-ML and n-ML, respectively. The switch element works as OFF so that it is not reflected in the match line sensing control unit / output driver 110 in the subsequent stage regardless of the comparison calculation result of the CAM cells 0 to CAM cells 7.
When this comparison calculation result is not reflected, CAM cells 0 to CAM cells 7 have the same meaning as matching. In FIG. 11, a picture of a switch element for connecting the signal lines Sub_p-ML and Sub_n-ML to the signal lines p-ML and n-ML is drawn in the contents of the CAM cell 202 of the valid bit, but another method is used. However, there is a method of creating "Don't care" using a ballid bit, but it is omitted.

FIG. 12 shows the overall configuration of the TCAM 300 including the valid bit and the parity bit according to the present invention. A parity bit 301 is newly included in the memory cell 105 shown in FIG. 11, and a multi-input exclusive OR logic 302, which is a parity calculation circuit, is written. In general, the parity check instantly compares the parity of the search data with the parity of the stored data to determine whether or not the correct data has been transmitted.

FIG. 13 shows a 6T-2 MTJ type non-volatile associative memory cell provided with a storage unit for preliminary replacement according to the present invention. The memory cell has two circuits of a selection transistor and a magnetoresistive sensor connected in series, and is input via a table that controls external replacement control and a signal line SEL that instructs a replacement request from the control unit 51. Then, the storage units are sequentially selected. If the logical value "1" of the signal line SEL is input, the transistor M11 is turned on and the read current or the write current can be energized, and the transistor M11 and the magnetic resistance effect element R11 become effective. However, if the logical value "0" of the signal line SEL is input, the transistor M12 is turned on and the read current or the write current can be energized, and the transistor M12 and the magnetic resistance effect element R12 are effective. Become. If it is determined in the post-manufacturing inspection that either the magnetoresistive element R11 or R12 is defective, the table and control unit 51 that controls the external replacement control will avoid the defect so that the non-defective product will be effective. It will be adjusted.

FIG. 14 shows an example of a non-volatile content addressable memory cell provided with a storage unit for another preliminary replacement according to the present invention. Since the selection transistor M11 in FIG. 13 is an NMOS and the selection transistor M12 is a MPa, the ON resistances of the two are different, and the margin for comparison determination may be impaired. Therefore, it is disclosed that the selected transistors 21 and 22 of FIG. 14 are composed of the same type of NMOS.
Further, the memory cell is newly provided with a decoding circuit 61, and is input via a signal line SEL instructing a replacement request from a table and a control unit (not shown in FIG. 14) that controls external replacement control, and is stored in the storage unit. Are selected in sequence.
The decoding circuit 61 includes a distribution circuit and an inverter circuit. One of the SEL signals is directly connected to the gate terminal of the transistor M21, and the other is inverted once by the inverter circuit and connected to the gate terminal of the transistor M22.

FIG. 15 shows a non-volatile content addressable memory cell including a fuse / memory circuit and a decoding circuit according to the present invention and a storage unit for preliminary replacement. In the memory cell, the selection signal lines SEL1 and SEL2 and the rewriting signal line Transistor are input from the table and the control unit 52 that control the external alternation control, and are stored once in the fuse or the memory, and then through the decoding circuit. Only one is selected from the storage unit (combination of selection transistor and magnetoresistive element).

Although an example of using a spin injection type magnetoresistive sensor as the non-volatile storage unit according to the present invention is disclosed, other storage elements may be used as long as they show a resistance change, for example, ReRAM or PCRAM. It may be composed of such as.
Although the schematic diagram is omitted, ReRAM has a structure in which a recording layer is sandwiched between the upper electrode and the lower electrode, and the set state (low resistance) and reset are performed by controlling the applied voltage between the upper electrode and the lower electrode. It can be set to the state (high resistance).
Although the schematic diagram is omitted, the PCRAM has a structure in which the upper electrode, the recording layer, the heater layer, and the lower electrode are laminated in this order.
The storage layer is composed of a phase change material, and can be set to a crystalline phase (low resistance) and an amorphous phase (high resistance) by controlling the energization of a current pulse between the upper electrode and the lower electrode. ..
Although an example of using a MOS transistor is disclosed as the switch element according to the present invention, other switch elements may be used as long as they are of the 3-terminal type, and may be configured by, for example, a bipolar transistor.

10 Magnetic resistance effect element 11 Magnetizing free layer 12 Non-magnetic layer 13 Magnetizing fixed layer 15 Memory cell basic circuit 51 Reference table and decoding driver that control the preliminary replacement memory cell 52 Reference table and control unit that controls the preliminary replacement memory cell 61 Decoder Circuit 71 Pre-replacement storage unit composed of fuse or memory 72 Decoder circuit that receives the output signal of the preliminary replacement storage unit 100 Overall configuration of non-volatile associative memory 101 Column-side direction control unit 102 Row-side direction control unit 103 Match Line sensing control / output driver 104 Memory cell 105 Memory cell with valid bit of "Don't care" 106 Memory cell with valid bit and parity bit of "Don't care" 110 p-ML and n-ML at the same time Judgment circuit 112 P-ML sensing circuit 113 n-ML sensing circuit 114 Inverter circuit 115 AND circuit 116 Driver circuit 200 Overall configuration of non-volatile TCAM 201 1-bit data storage memory cell 202 “Don't care” valid bit Memory cell 300 Overall configuration of non-volatile TCAM with parity bit 301 Parity bit memory cell 302 Parity arithmetic circuit (multi-input exclusive logical sum logic)

Claims (10)

An associative memory having a plurality of memory cells in a grid pattern, in which at least one or more non-volatile storage units, a write circuit, a read circuit, and a comparison calculation circuit are integrated in each memory cell.
It is connected to a first match line precharged to a high potential and a second match line precharged to a low potential.
The memory cell is
A first switch element that supplies a current to read out the non-volatile storage unit, and
A second switch element that supplies a current for writing to the non-volatile storage unit, and
A third switch element arranged between the non-volatile storage unit and the first match line in order to perform a comparison calculation between the potential of the non-volatile storage unit and the potential of the first match line.
A fourth switch element arranged between the non-volatile storage unit and the second match line in order to perform a comparison calculation between the potential of the non-volatile storage unit and the potential of the second match line. Non-volatile associative memory , including. An associative memory having a plurality of memory cells in a grid pattern, in which at least one or more non-volatile storage units, a write circuit, a read circuit, and a comparison calculation circuit are integrated in each memory cell.
It is connected to a first match line precharged to a high potential and a second match line precharged to a low potential.
In the memory cell, one end of the non-volatile storage unit is connected to a first connection point, and the other end of the non-volatile storage unit is connected to a second current energizing bit wire.
A second switch element in which a switch control electrode for controlling a write current supply is connected to a second word line, and one end of the second switch element are connected to a first current energizing bit line, and a second The other end of the second switch element is connected to the first connection point, and the first current energizing bit wire, the second switch element, the first connection point, the non-volatile storage unit, and the second A writing circuit in which the current energizing bit wire of the
A switch control electrode for controlling the read current supply is connected to the first switch element connected to the first word line, and one end of the first switch element is connected to the terminal Vdd which is the starting point on the high potential side of the read current. At the same time, the other end of the first switch element is connected to the first connection point, and the terminal Vdd of the high potential side starting point, the first switch element, the first connection point, the non-volatile storage unit, and the above. A readout circuit in which a second current energizing bit wire is connected in series, and
A third switch element in which a switch control electrode for controlling a comparison operation with the first match line is connected to the first search line, and one end of the third switch element are connected to the first match line. At the same time, the other end of the third switch element is connected to the first connection point, and the first match line, the third switch element, the first connection point, and the high potential side of the non-volatile storage unit are connected. A comparison arithmetic circuit with one end connected in series,
A fourth switch element in which a switch control electrode for controlling a comparison operation with the second match line is connected to the second search line, and one end of the fourth switch element are connected to the second match line. At the same time, the other end of the fourth switch element is connected to the first connection point, and the second match line, the fourth switch element, the first connection point, and the high potential side of the non-volatile storage unit. The non-volatile associative memory according to claim 1, further comprising a comparison arithmetic circuit having one end connected in series. In the memory cell search operation, the first switch element that supplies the read current is turned on.
When the first search line is in the high potential state and the second search line is in the low potential state, the third switch element is turned on, depending on the product of the resistance state of the non-volatile storage unit and the read current. A comparison calculation is performed between the first voltage and the second voltage precharged to the high potential state of the first match line.
When the first search line is in a high potential state and the second search line is in a low potential state, the fourth switch element is turned off, depending on the product of the resistance state of the non-volatile storage unit and the read current. No comparison calculation is performed between the first voltage and the third voltage precharged to the low potential state of the second match line.
When the first search line is in the low potential state and the second search line is in the high potential state, the third switch element is turned off, depending on the product of the resistance state of the non-volatile storage unit and the read current. No comparison calculation is performed between the first voltage and the second voltage precharged to the high potential state of the first match line.
When the first search line is in the low potential state and the second search line is in the high potential state, the fourth switch element is turned on, depending on the product of the resistance state of the non-volatile storage unit and the read current. The non-volatile associative memory according to claim 2 , wherein a comparison calculation is performed between the first voltage and the second voltage precharged in the low potential state of the second match line. A claim characterized in that the first word line transmitted by a switch control signal for supplying a read current and the second word line transmitted by a switch control signal for supplying a write current are used in combination. Item 2. The non-volatile associative memory according to item 2. An associative memory having a plurality of memory cells in a grid pattern, in which at least one or more non-volatile storage units, a write circuit, a read circuit, and a comparison calculation circuit are integrated in each memory cell.
It is connected to a first match line precharged to a high potential and a second match line precharged to a low potential.
The memory cell has a first connection point to which one end of the non-volatile storage unit and an input end of the sense amplifier are connected, and further has a second connection point to which the output end of the sense amplifier is connected. One end is connected to the first connection point, and a switch control electrode for supplying a read current is connected to a first switch element connected to the first word line, so that the first connection point is connected. Has the function of a signal line that propagates a voltage according to the resistance state of the non-volatile storage unit, one end is connected to the second connection point, and the respective switch control electrodes are the first and second searches. The fifth and sixth switch elements connected to the line and the other ends of the fifth and sixth switch elements are connected to the first and second match lines, respectively.
Further, a second switch element in which one end is connected to the first connection point and a switch control electrode for supplying a write current is connected to a second word line, and a second switch element. the other end is connected to a first write line, the other end of the nonvolatile memory unit is connected to the second write line, a non-volatile content addressable memory. The non-volatile associative memory according to any one of claims 1 to 5 is arranged in close proximity to a memory cell divided into a plurality of n-bit areas and the n-bit area. A non-volatile TCAM comprising a memory cell having a value of "X"(Don't care). The non-volatile associative memory according to any one of claims 1 to 5 is arranged in close proximity to a memory cell divided into a plurality of n-bit areas and the n-bit area. A non-volatile TCAM comprising a memory cell having a value of "X"(Don't care) and a memory cell having parity. The memory cell has at least two or more non-volatile storage units in which a selection switch element for preliminary replacement and a non-volatile magnetic storage element connected in series are connected in parallel, and is outside the memory cell. The method according to any one of claims 1 to 5 , wherein one of the selection switch elements is turned on and the other selection switch element is turned off by a selection signal drawn from the control unit. Non-volatile associative memory. The memory cell has at least two or more non-volatile storage units in which a selection switch element for preliminary replacement and a non-volatile magnetic storage element connected in series are connected in parallel, and is outside the memory cell. It has a decoder circuit for inputting a selection signal drawn from a control unit, and is characterized in that one of the selection switch elements is turned on and the other selection switch elements are decoded and output so as to be in the OFF state. The non-volatile associative memory according to any one of claims 1 to 5. The memory cell has a non-volatile storage unit in which at least two or more selection switch elements for preliminary replacement and a non-volatile magnetic storage element connected in series are connected in parallel, and is outside the memory cell. It has a fuse storage circuit or a memory storage circuit for inputting a selection signal drawn from a control unit, and a decoding circuit for decoding the stored numerical value, and one said selection switch element is turned on and the other said The non-volatile associative memory according to any one of claims 1 to 5 , wherein the selection switch element is decoded and output so as to be in the OFF state.

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