JP4577334B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a highly integrated memory using a memory cell that stores information by utilizing a change in magnetoresistance.

  Magneto-resistive random access memory (MRAM) has been developed as a non-volatile memory typified by ferrodielectric memory (FeRAM) and flash memory but with unlimited read / write times. ing. The MRAM stores information using a magnetoresistive effect in which the resistance of an element differs depending on the direction of magnetization. In recent years, development of a magnetic tunnel junction (MTJ) element called magneto-resistance (MR) having a larger magnetoresistive change rate than a conventional element and its application to an MRAM have been promoted, and a static random access memory. (SRAM) high-speed read / write operation is possible, and the possibility of realizing a high degree of integration equivalent to DRAM was shown. For this reason, MRAM is gaining more attention as a promising candidate for next-generation memory.

As shown in FIG. 3, the MTJ element has a three-layer structure in which an insulating film TB is sandwiched between two ferromagnetic layers FRL and FXL. The insulating film TB is formed so thin that electrons can be conducted by the tunnel effect. The magnetization direction of the ferromagnetic layer FXL is fixed as indicated by the arrow AMF2, whereas the magnetization direction of the ferromagnetic layer FRL is controlled by the external magnetic field as indicated by the arrow AMF1. . The resistance between the terminals A and B varies depending on the direction of magnetization in the two ferromagnetic layers, and is in a low resistance state when they are in the same direction and in a high resistance state when they are opposite to each other. The MRAM to which such an MTJ element is applied is described in Non-Patent Document 1 and Non-Patent Document 2, for example. In both
A basic configuration of a memory cell is a configuration in which one MTJ element and one transistor are connected in series. When the transistor in the selected memory cell is turned on, a voltage is applied between the terminals of the MTJ element, and the stored information is read by detecting the current flowing through the data line according to the magnetic resistance.
IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL, International Solid-State Circuits Conference, Digest of Technical Papers, pages 128-129 (2000) PAPERS, pp. 128-129, 2000.) IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL, International Solid-State Circuits Conference, Digest of Technical Papers, pages 130-131 (2000) PAPERS, pp. 130-131, 2000.)

FIG. 4 shows a current generated by applying a voltage between the terminals of the MTJ element at time T1. Here, it is assumed that the MTJ element is in the high resistance state when the storage information “0” is held, and is in the low resistance state when the storage information “1” is held. At this time, the current ID (1) obtained by reading the memory cell holding the storage information '1' is more than the current ID (0) obtained by reading the memory cell holding the storage information '0'. Are both large and take positive values. Due to the characteristics of the MTJ element, the MRAM has two problems in the read operation. First, in order to separate stored information from a read signal having one polarity, a reference signal is necessary. Second, since the MTJ MR is several tens of percent, the read signal amount is small, and a stable read operation is difficult.

  In order to solve these problems, Non-Patent Document 1 employs a twin-cell system including two MTJ elements and two transistors in a memory cell. In this method, complementary read signals can be obtained according to the stored information of the memory cells, so that information can be easily separated and the signal amount is large. However, since the memory cell area is doubled, it is expected to be relatively disadvantageous for increasing the capacity. On the other hand, in Non-Patent Document 2, a reference signal composed of one MTJ element and one transistor, which is the same as a memory cell, is arranged for each word line to generate a reference signal. Although this method can reduce the area of the memory array, it is predicted that it is relatively difficult to form a reference cell that generates a reference signal with high accuracy while taking into account characteristic variations that occur in each memory cell. . In addition, when some defect such as disconnection or short circuit occurs in the reference cell or the data line to which the reference cell is connected, the reference signal is not generated, so the storage information of the corresponding memory cells cannot be read, It may cause a decrease in yield. The present invention was born from the above examination results.

  A first problem of the present invention is to provide a dummy cell that generates a reference signal with high accuracy and to accurately read out stored information held in a memory cell composed of one MTJ element and one transistor. is there. Secondly, it is to provide a repair method capable of replacing both memory cells and dummy cells. The third is to realize a high-capacity MRAM with high integration density and high reliability.

  The feature of the representative means of the present invention for achieving the above object is that the memory cell is composed of one MTJ element and one transistor, and two memory cells holding complementary storage information are connected in parallel. Dummy cell configuration. This dummy cell is arranged for each word line pair.

  A highly-integrated large-capacity memory using a memory cell that stores information using a change in resistance can be realized.

The present invention will be described with respect to an MRAM having a memory cell composed of one MTJ element and one transistor according to the following embodiments. As will be described in detail later, FIG. 13 shows an example of a synchronous memory using the present invention. FIG. 12 shows an example of the memory array MAR shown in FIG.
Further, FIG. 1 shows an example of the memory block BLK in FIG. 12, which is an example of a configuration in which the memory cell array MCA and the dummy cell array DCA1 are arranged on one side of the word driver array WDA. The memory block BLK further includes multiplexers MUXU1, MUXL1, MUXUD, MUXLD, write circuits WCU1, WCL1, dummy write circuit DWU1, and read circuit RDC1. The feature of the memory block according to the present embodiment is that two memory cells MCL and MCH having the same structure as the memory cell MC are arranged in parallel in each word line pair, and two cells each holding complementary information. A reference signal is generated by activating MCL and MCH. Below, each circuit block is demonstrated.

  The memory cell array MCA has a configuration example having 8 × 8-bit memory cells MC, and the memory cells MC include a plurality (eight here) word line pairs and a plurality (here eight) data lines Dj. They are arranged at the intersections with (j = 0,..., 7). The dummy cell array DCA1 has 8 × 1 bit dummy cells DC according to the configuration of the memory cell array MCA. The dummy cell DC has a configuration in which two memory cells MCL and MCH having the same structure as the memory cell MC are respectively arranged at intersections between a plurality of word line pairs and dummy data lines DD0 and DD1.

  The word driver array WDA is composed of a plurality of (in this case, eight) word drivers, which will be described later, and drives a plurality of word line pairs in accordance with the row decode address DXB and the array control bus ABS. The plurality of word line pairs are respectively constituted by a read word line WRk (k = 0,..., 7) and a write word line WWk (k = 0,..., 7), and the write word line WWk is grounded at the far end. Here, the row decode address DXB is composed of a plurality of row decode signals XBk (k = 0,..., 7). The array control bus ABS is composed of a plurality of signals having different roles, and signals as necessary are connected to each circuit block. The contents of the array control bus ABS will be described in the specific circuit configuration of the circuit block.

  The multiplexers MUXU1 and MUXL1 are arranged at both ends of the memory cell array MCA, and operate in pairs with each other. One multiplexer MUXU1 has a plurality (eight in this case) of switches SRW arranged between the common data line DS and the plurality of data lines Dj (hereinafter, the switches in the multiplexer are simply referred to as switches for simplicity). The data line D to be selected is connected to the common data line DS according to the inputted column decode address DYM. The other multiplexer MUXL1 is arranged between a plurality of (eight in this case) switches SRB arranged between the ground potential VSS and the plurality of data lines Dj, and between the write common node WCOM and the plurality of data lines Dj. And a plurality of (in this case, 8) switches SW. The former switch SRB cuts off the connection between the data line D to be selected and the ground potential VSS according to the input column decode address DYM, and the latter switch SW is connected to the data line D to be selected and the write common node WCOM. Connect.

  Multiplexers MUXUD and MUXLD are arranged at both ends of dummy cell array DCA1, and operate in pairs with each other. One multiplexer MUXUD is composed of two switches SRW arranged between the common data line RS and the dummy data lines DD0 and DD1, and the dummy data lines DD0 and DD1 according to the input column decode address DYM. And the common data line RS are connected. The other multiplexer MUXLD includes two switches SRB arranged between the ground potential VSS and the dummy data lines DD0 and DD1, and between the ground potential VSS, the dummy data line DD0, the power supply voltage VDD, and the dummy data line DD1. It is composed of two switches SW arranged in the. The former switch SRB cuts off the connection between the dummy data lines DD0 and DD1 and the ground potential VSS according to the input column decode address DYM. The latter switch SW connects the dummy data line DD0 and the ground potential VSS, and the dummy data line DD1 and the power supply voltage VDD according to the input column decode address DYM. The switches SRW, SRB, and SW are schematically indicated by symbols in the figure, but are actually configured by, for example, NMOS transistors, and the connection state is controlled by the presence or absence of a current path between the source and drain.

  The write circuits WCU1 and WCL1 are arranged further outside the multiplexers MUXU1 and MUXL1, respectively, and operate in pairs with each other. The write circuit WCU1 drives the common data line DS according to the input column selection signal WYS, write data line WIB, and array control bus ABS, and the write circuit WCL1 receives the input column selection signal WYS, write data line WIT The write common node WCOM is driven according to the array control bus ABS. The dummy write circuit DWU1 is arranged further outside the multiplexer MUXUD according to the write circuit WCU1, and drives the common data line RS according to the array control bus ABS.

  The read circuit RDC1 supplies power to the memory cells and dummy cells according to the input array control bus ABS and bias voltage VB1, detects and amplifies read signals generated on the common data lines DS and RS, and further selects a column. In accordance with the signal RYS, the read data lines ROT and ROB are driven to a potential corresponding to the read data.

  Next, the circuit configuration of the memory cell MC will be described with reference to FIG. The left figure is a block symbol of the memory cell MC shown in FIG. 1. Specifically, as shown in the right figure, it is composed of one MTJ element MTJ and one NMOS transistor N1 indicated by a circuit symbol of resistance. Has been. The terminals A and B correspond to the terminals in the cross section of the MTJ element shown in FIG. 3, and the terminal A is connected to the data line Dj and the terminal B is connected to the drain of the NMOS transistor N1. The source of the transistor N1 is grounded and the gate is connected to the read word line WRk. Although omitted in FIG. 3, the write word line WWk is three-dimensionally formed below the ferromagnetic layer FXL via an interlayer insulating film. On the other hand, the data lines Dj are formed on the ferromagnetic layer FRL and connected to each other.

  The operation of the memory cell in such a configuration is performed as follows. First, in the case of a read operation, when the write word line WWk is held at the ground potential VSS and the read word line WRk is driven to the power supply voltage VDD, the transistor N1 is turned on to cause a current between the data line Dj and the ground potential VSS. A path is formed, and a current is output on the data line Dj. Next, in the case of a write operation, the read word line WRk is held at the ground potential VSS, the transistor N1 is kept off, and a current flows in the direction of the arrow AWW to the write word line WWk, thereby generating a first magnetic field. Is done. Further, a current flows in the direction of the arrow ADL or ADH according to the write data on the data line Dj, thereby generating a second or third magnetic field, respectively. Since the direction of the current is different, the second and third magnetic fields are opposite to each other according to Ampere's law. Therefore, in the memory cell arranged at the intersection of the write word line WWk and the data line Dj, the first and second combined magnetic fields having different directions are generated according to the write data, and the ferromagnetic material shown in FIG. The magnetization direction AMF1 of the layer FRL is controlled. Hereinafter, the storage information of the memory cell is “1” when the MTJ element is in the low resistance state and “0” when the MTJ element is in the high resistance state. When the stored information '1' is written, a current flows in the direction of the arrow ADL through the data line Dj and a second magnetic field is generated, thereby generating a first combined magnetic field. As a result, the magnetization directions of the ferromagnetic layers FRL and FXL are parallel to each other, and the MTJ element is in a low resistance state. On the other hand, when the stored information '0' is written, a current flows in the direction of the arrow ADH on the data line Dj and a third magnetic field is generated, thereby generating a second combined magnetic field. As a result, the magnetization directions of the ferromagnetic layers FRL and FXL are opposite to each other, and the MTJ element is in a high resistance state. In addition, it is assumed that the memory cell MCL in the dummy cell DC is in a low resistance state and the MCH is in a high resistance state.

  FIG. 5 shows a circuit configuration of the read circuit RDC1, which includes a column selection circuit YSW1, a precharge circuit PCEQ, a sense amplifier SA, current mirror circuits CM and CMD1, and a bias circuit BC1. Further, in the array control bus ABS shown in FIG. 1, a precharge enable signal EQ, a sense amplifier activation signal SDP, a read control signal REB are input, and a column selection signal RYS is further input. First, the configuration of each circuit will be described.

  The precharge circuit PCEQ includes NMOS transistors N71, N72, and N73. When the precharge enable signal EQ connected to each gate is driven to the power supply voltage VDD, all the transistors are turned on to precharge the sense data lines DT and DB to the ground potential VSS. At this time, the transistor N73 has an effect of equalizing the potentials of the sense data lines DT and DB.

  The sense amplifier SA is composed of a cross-coupled latch circuit composed of PMOS transistors P81 and P82 and NMOS transistors N81 and N82, and a PMOS transistor P83 which is a power cutoff switch. When the sense amplifier activation signal SDP connected to the gate of the transistor P83 is driven to the ground potential VSS, the transistor P83 becomes conductive, and the power supply voltage VDD is supplied to the sources of the transistors P81 and P82. By activating the sense amplifier in this manner, it is possible to amplify a minute potential difference generated on the sense data lines DT and DB. Here, since the standby sense data lines DT and DB are precharged to the ground potential VSS by the precharge circuit PCEQ, the gate-source voltages of the transistors N81 and N82 are each 0V. Therefore, since the transistors N81 and N82 are in the off state, no switching transistor is provided on the ground potential VSS side, thereby reducing the layout area.

  The column selection circuit YSW1 includes NMOS transistors N91 and N92, and column selection signals RYS are input to the gates, respectively. The source of the transistor N91 is connected to the sense data line DT, and the drain is connected to the read data line ROT. Further, the source of the transistor N92 is connected to the sense data line DB, and the drain is connected to the read data line ROB. With such a configuration, data read to the sense data lines DT and DB can be selectively output to the read data lines ROT and ROB.

  The current mirror circuit CM is composed of PMOS transistors P41, P42, P43, and P44. The gates of the transistors P41 and P42 and the drain of the transistor P41 are connected to the internal common data line NDS, and the drain of the transistor P42 is connected to the sense data line DT. Further, the transistors P43 and P44 are power control switches having the power supply voltage VDD input to the source and the read control signal REB input to the gate, respectively, and are connected in series with the transistors P41 and P42, respectively. Therefore, when the read control signal REB at the power supply voltage VDD is driven to the ground potential VSS, the transistors P43 and P44 are turned on and the current mirror circuit CM is activated. Here, the gates of the transistors P41 and P42 are formed with the same dimensions, and the gates of the transistors P43 and P44 are formed with the same dimensions, thereby forming a current mirror circuit with a mirror ratio of 1: 1. Therefore, a current having the same value as the current flowing between the source and drain of the transistor P41 can be passed through the transistor P42.

  The current mirror circuit CMD1 includes PMOS transistors P51, P52, P53, P54, P55, and P56. The transistors P51, P53, P54, and P56 correspond to the transistors P41, P42, P43, and P44 in the current mirror circuit CM, respectively. The gates of the transistors P51, P52, and P53 and the drains of the transistors P51 and P52 are connected to the internal common data line NRS, and the drain of the transistor P53 is connected to the sense data line DB. Further, the transistors P54, P55, and P56 are power control switches having the power supply voltage VDD input to the source and the read control signal REB input to the gate, respectively, and are connected in series with the transistors P51, P52, and P53, respectively. Therefore, when the read control signal REB at the power supply voltage VDD is driven to the ground potential VSS, the transistors P54, P55, and P56 are turned on and the current mirror circuit CMD1 is activated. Here, the gates of the transistors P51, P52, and P53 are formed with the same dimensions as the transistors P41 and P42, respectively, and the gates of the transistors P54, P55, and P56 are formed with the same dimensions as the transistors P43 and P44, respectively. By making the current values flowing between the source and drain of P52 and P53 equal, a current mirror circuit having a mirror ratio of 2 to 1 is formed. Therefore, a current having a value half that of the current flowing through the internal common data line NRS can be passed through the sense data line DB. As shown in FIG. 4, this current is a current IREF that has an almost intermediate value of the current ID (1) or ID (0) flowing through the memory cell holding the stored information “1” or “0”.

  The bias circuit BC1 includes NMOS transistors N61 and N62. The internal common data line NDS and the common data line DS are connected to the drain and source of the transistor N61, respectively, and the internal common data line NRS and the common data are connected to the drain and source of the transistor N62. Connect each line RS. Further, a bias voltage VB1 is applied to the gates of the transistors N61 and N62, respectively. The bias voltage VB1 is generated by a bias control circuit as shown in Figure 7.2.5 of Non-Patent Document 1 so that the potential difference between the common data line DS and the ground potential VSS becomes the reference voltage Vref. Control. The reference voltage Vref is fixed at a low voltage so that the voltage applied to the MTJ element MTJ does not increase, and the potential difference between the common data line DS and the ground potential VSS is kept at a constant low value. Therefore, even when the MTJ element MTJ has voltage dependency and MR decreases as the applied voltage increases, control can be performed so that a stable MR value can be obtained. Here, by setting the gate length of the transistor N62 to be the same as that of the transistor N61 and forming the gate width twice that of the transistor N61, the on-resistance of the transistor N62 is ½ that of the transistor N61. Further, the internal common data line NRS is formed to have the same wiring length as the internal common data line NDS, and the internal common data line NRS has a wiring width twice that of the internal common data line NDS. Furthermore, the common data line RS has the same wiring length as the common data line DS, and the common data line RS is formed twice as wide as the common data line DS. Is doubled between the power supply voltage VDD and the common data line DS, and the wiring resistance is halved. With such a configuration of the bias circuit BC1, applied voltages in the memory cell MC and the dummy cell DC can be made equal. Further, the load capacity and resistance per memory cell in the dummy cell DC can be made the same as the load capacity and resistance for the memory cell MC, and a current having the same value as the current flowing in the memory cell MC according to the stored information is set in the dummy cell. The current can flow through the complementary memory cells MCL and MCH.

Next, a reference signal generation mechanism by the read circuit RDC1 will be described. Here, currents flowing through the common data lines DS and RS are represented as IDS and IRS, respectively, and currents flowing when the MTJ element MTJ is in the low resistance state are represented as IDS (1). The current that flows when the memory cell holds the stored information “0” and the MTJ element MTJ is in the high resistance state is represented as IDS (0). The current IDS (1) is a larger value than IDS (0). Furthermore, the current IRS flowing through the common data line RS is the sum of the currents flowing through the dummy data lines DD0 and DD1 to which the two memory cells MCH and MCL holding complementary storage information are connected.
IRS = IDS (0) + IDS (1) (Equation 1)
It can be expressed as.

When the above symbols are used, one current mirror circuit CM shown in FIG. 5 charges the sense data line DT with the current IDS (1) or IDS (0) having the same value as the current flowing through the common data line DS. The other current mirror CMD1 circuit charges the sense data line DB with a current IRS / 2 that is half the value of the current flowing through the common data line RS. This current IRS / 2 is an average value of the current flowing through the memory cell MC according to the stored information, and corresponds to the reference signal IREF having the relationship as shown in FIG. Here, it is assumed that the load capacitances of the sense data lines DT and DB are equal to each other as CD, and it is assumed that the voltage dependency between the power supply voltage VDD and the sense data line of the current flowing in the current mirror circuit is so small that it can be ignored. Also, assuming that the current flowing in the current mirror circuit is a constant value immediately after activation for the sake of simplicity, the voltage VDT (1) of the sense data line DT when reading the stored information '1' is
VDT (1) = (IDS (1) × T) / CD (Equation 2)
Where T represents the time since the current mirror circuit was activated. On the other hand, the voltage VDB of the sense data line DB is from (Equation 1)
VDB = [(IRS / 2) × T] / CD
= [(IDS (0) + IDS (1)) x T] / (2 x CD) ... (Formula 3)
It can be expressed as. From (Equation 2) and (Equation 3), the read signal ΔV1 when reading the stored information '1' is
ΔV1 = VDT (1) -VDB
= [(IDS (0) -IDS (1)) x T] / (2 x CD) (4)
It can be expressed as. In addition, the voltage VDT (0) of the sense data line DT when reading the stored information '0' is
VDT (0) = (IDS (0) × T) / CD ... (Formula 5)
It can be expressed as. Therefore, from (Equation 3) (Equation 5), the read signal ΔV0 when reading the stored information '0' is
ΔV0 = VDT (0) -VDB
=-[(IDS (0) -IDS (1)) x T] / (2 x CD) ... (Formula 6)
It can be expressed as.

  From the above, by using the current mirror circuit CMD1 having a mirror ratio of 2: 1, the reference signal IRS is generated as an intermediate value between the positive binary read signals IDS (1) and IDS (0) (Equation 4). Positive and negative read signals as shown in (Equation 6) can be generated. Therefore, when the stored information '1' is read, as the potential difference between the sense data lines DT and DB increases, the drive capability of the transistors N81 and P82 in the sense amplifier SA increases, and the sense data line DT Each data line DB is driven to the ground potential VSS. In addition, when reading the stored information '0', as the potential difference between the sense data line DT and DB increases, the drive capability of the transistors P81 and N82 in the sense amplifier SA increases, and the sense data line DT is connected to the ground potential VSS, sense The data lines DB are driven to the power supply voltage VDD. Thus, the stored data can be sorted by amplifying the sense data lines DT and DB to the power supply voltage VDD or the ground potential VSS according to the positive and negative read signals.

  FIG. 6 shows a circuit configuration example of the multiplexers MUXU1, MUXL1, MUXUD, MUXLD, write circuits WCU1, WCL1, and dummy write circuit DWU1 shown in FIG. Hereinafter, first, the multiplexers MUXU1, MUXL1, MUXUD, and MUXLD will be described. The multiplexer MUXU1 is composed of eight NMOS transistors N11j (j = 0, 1,..., 7) corresponding to the switch SRW shown in FIG. A corresponding column address signal YMTj (j = 0, 1,..., 7) is input to the gate of the transistor N11j. The multiplexer MUXL1 includes eight NMOS transistors N13j (j = 0, 1,..., 7) corresponding to the switch SRB shown in FIG. 1 and eight NMOS transistors N14j (j) corresponding to the switch SW shown in FIG. j = 0, 1, ..., 7). The corresponding column address signal YMBj (j = 0, 1,..., 7) is input to the gate of the transistor N13j, and the corresponding column address signal YMWj (j = 0, 1,..., 7) is input to the gate of the transistor N14j. Is done. Here, each of the column address signals YMTj, YMBj, and YMWj is a signal in the column decode address DYM shown in FIG. 1, and the connection state of the data line Dj is controlled as follows according to the operation.

  First, in the standby state, the column address signals YMTj and YMWj are held at the ground potential VSS, the column address signal YMBj is held at the power supply voltage VDD, the transistors N11j and N14j are turned off, and the transistor N13j is turned on. Ground data line D. Next, for example, in the read operation in which the data line D0 is selected, the column address signal YMT0 is driven to the power supply voltage VDD, the column address signals YMB0 and YMW0 are respectively driven to the ground potential VSS, the transistor N110 is turned on, and the transistors N130 and N140 Is turned off, the data line D0 is connected to the common data line DS. Therefore, the current flowing through the memory cell MC can be output to the common data line DS. Further, for example, in the write operation in which the data line D0 is selected, the column address signals YMT0 and YMW0 are driven to the power supply voltage VDD, the column address signal YMB0 is driven to the ground potential VSS, the transistors N110 and N140 are turned on, and the transistor N130 is turned on. By turning off, the data line D0 is connected to the common data line DS and the write common node WCOM. Therefore, a current path can be formed in the selected data line.

  The multiplexer MUXUD is composed of two NMOS transistors N120 and N121 corresponding to the switch SRW shown in FIG. A column address signal YMDT is input to the gates of the transistors N120 and N121. The multiplexer MUXLD includes two NMOS transistors N150 and N151 corresponding to the switch SRB shown in FIG. 1, and two NMOS transistors N190 and N191 corresponding to the switch SW shown in FIG. A column address signal YMDB is input to the gates of the transistors N150 and N151, and a column address signal YMDW is input to the gates of the transistors N190 and N191. Here, each of the column address signals YMDT, YMDB, and YMDW is a signal in the column decode address DYM shown in FIG. Control.

  First, in the standby state, the column address signals YMDT and YMDW are held at the ground potential VSS, the column address signal YMDB is held at the power supply voltage VDD, the transistors N120, N121, N190, and N191 are off, and the transistors N150 and N151 are on. As a result, the dummy data lines DD0 and DD1 are grounded. Next, in the case of a read operation, in response to selection of one of the data lines Dj, the column address signal YMDT is driven to the power supply voltage VDD, and the column address signals YMDB, YMDW are respectively driven to the ground potential VSS, and the transistors N120, When N121 is turned on and the transistors N150, N151, N190, and N191 are turned off, the dummy data lines DD0 and DD1 are connected to the common data line RS. Therefore, the current flowing through the dummy cell DC can be output to the common data line RS. Further, in the write operation, the column address signals YMDT and YMDW are driven to the power supply voltage VDD, the column address signal YMDB is driven to the ground potential VSS, the transistors N120, N121, N190, and N191 are turned on, and the transistors N150 and N151 are turned off. Thus, a current path from the dummy data line DD1 to the common data line RS and the dummy data line DD0 is formed between the power supply voltage VDD and the ground potential VSS. Therefore, since the directions of the currents flowing through the dummy data lines DD0 and DD1 are directions of arrows ADL and ADH, respectively, complementary storage information can be simultaneously written in the dummy cells DC as described with reference to FIG. Here, since the direction of the magnetic field written in the MTJ element does not generally change even when the applied voltage is set to 0 V, it is maintained even when the power of the chip is turned off. Therefore, it is sufficient to perform the dummy cell write operation once as an initialization operation, for example, in a test before shipment.

  Next, a circuit configuration example of the write circuits WCU1 and WCL1 and the dummy write circuit DWU1 will be described with reference to FIG. First, the write circuit WCU1 includes PMOS transistors P161, P162, and P163 and NMOS transistors N161, N162, N163, and N164, and receives the write control signals WET and WEB and the precharge enable signal EQ in the array control bus ABS. The The transistor N164 is a write data line selection switch, and connects the write data line WIB to the source, the internal write node WDB to the drain, and the column selection signal WYS to the gate. In addition, a clocked inverter is formed by connecting transistors P161, P162, N161, and N162 in series. The write control signal WEB is connected to the gate of the transistor P161, the write control signal WET is connected to the gate of N161, the transistors P162 and N162 which are data input terminals of the clocked inverter, the internal write node WDB and the transistor which is the output terminal A common data line DS is connected to the drains of P161 and N161, respectively. Further, each of the transistors P163 and N163 is a precharging transistor for the internal write node WDB which is the data input terminal of the clocked inverter and the common data line DS which is the output terminal. A column selection signal WYS is input to the gate of the transistor P163, and a precharge enable signal EQ is input to the gate of the N163.

  The write circuit WCL1 includes the same transistor as the write circuit WCU1 described above, but differs in the following four points. First, the source of the transistor N164 is connected to the write data line WIT. Second, the gate terminals of the transistors P162 and N162 which are data input terminals of the clocked inverter are referred to as an internal write node WDT. Third, the drains of the transistors P161 and N161 which are output terminals of the clocked inverter are connected to the write common node WCOM. Fourth, the write control signal WEB is connected to the gate of the transistor N163. The data lines DS and the write common node WCOM are driven as follows by the write circuits WCU1 and WCL1 configured as described above.

  First, in the standby state, in the write circuit WCU1, the write control signal WET is driven to the ground potential VSS, the write control signal WEB and the precharge enable signal EQ are respectively driven to the power supply voltage VDD, the transistors P161 and N161 are turned off, and the N163 is turned on. By turning on, the common data line is grounded. In the write circuit WCU1, similarly, the transistors P161 and N161 are turned off and the N163 is turned on, whereby the write common node WCOM is grounded.

  Next, in the read operation, the write control signal WET and the precharge enable signal EQ are driven to the ground potential VSS, the write control signal WEB is driven to the power supply voltage VDD, and the transistors P161, N161, and N163 are turned off. The output of the write circuit WCU1 is set to a high resistance state. On the other hand, in the write circuit WCL1, the write common node WCOM is grounded by holding the transistors P161 and N161 in the off state and N163 in the on state.

  Further, in the write operation, the column selection signal WYS is the boosted potential VDH (where VTHN is the threshold voltage of the NMOS transistor, VDH ≧ VDD + VTHN), the write control signal WET is the power supply voltage VDD, and the write control signal. By driving WEB and the precharge enable signal EQ to the ground potential VSS, the transistor N164 in the write circuits WCU1 and WCL1 is turned on, the clocked inverter is activated, and the transistors P163 and N163 are turned off. By this operation, a current path between the power supply voltage VDD and the ground potential VSS via the write circuits WCU1, WCL1, the common data line DS, the write common node WCOM, and the data line D selected by the multiplexers MUXU1 and MUXL1 described above. Form. Here, when the write data lines WIB and WIT are driven to the ground potential VSS and the power supply voltage VDD, respectively, the transistor P162 in the write circuit WCU1 and the transistor N162 in the write control circuit WCL1 are turned on to connect the selected data line D to the arrow ADL. Is stored in the selected memory cell MC. On the other hand, when the write data lines WIB and WIT are driven to the power supply voltage VDD and the ground potential VSS, respectively, the transistor N162 in the write circuit WCU1 and the transistor P162 in the write control circuit WCL1 are turned on, and the selected data line D is connected to the arrow ADH. By generating a current in the direction, the storage information “0” is written into the selected memory cell MC.

  The dummy write circuit DWU1 includes load PMOS transistors P181 and P182 and precharge NMOS transistors N181 and N182. The power supply voltage VDD is input to the sources and gates of the transistors P181 and P182, respectively, and the drain is connected to the common data line RS. Further, the precharge enable signal EQ is input to the gates of the transistors N181 and N182, the ground potential VSS is input to the source, and the drain is connected to the common data line RS. With such a configuration, in the standby state, the precharge enable signal EQ is driven to the power supply voltage VDD, and the transistors N181 and N182 are turned on to ground the common data line RS.

  In the read operation, the precharge enable signal EQ is driven to the ground potential VSS, and the transistors N181 and N182 are turned off. Therefore, as with the write circuit WCU1, the output of the dummy write circuit DWU1 is set to the high resistance state. Here, the gate dimensions of the transistors P181 and P182 are respectively formed to the same dimensions as the transistor P161. Further, for example, when the gate dimensions of the transistors N161 and N163 are the same, the gate lengths of the transistors N181 and N182 are the same as those of the transistors N161 and N163, and the gate width is the sum of the gate widths of the transistors N161 and N163, respectively. As a result, a diffusion capacity twice as large as the diffusion capacity generated in the common data line DS is generated in the common data line RS.

  Further, in the case of the write operation, the output of the dummy write circuit DWU1 has a high resistance by driving the precharge enable signal EQ to the ground potential VSS and turning off the transistors N181 and N182 as in the case of the read operation. It becomes a state. The above configuration and operation are summarized. First, in the write circuits WCU1 and WCL1, in the case of the write operation, a current having a direction corresponding to the stored information is generated on the selected data line D, thereby reversing the magnetization direction of the ferromagnetic layer FRL shown in FIG. It is possible to generate a magnetic field necessary for the measurement. In the read operation, the current flowing through the memory cell MC can be output to the read circuit RDC1 via the common data line DS by setting the output of the write circuit WCU1 to the high resistance state. Here, by using a clocked inverter in which the transistors to which the write control signals WEB and WET are input to the gate are provided on the output terminal side instead of the power supply side, the common data line DS is used during the read operation in which the output is in a high resistance state. Can be suppressed to the diffusion capacitance of the transistors P161 and N161. Further, in the standby state, the common data line DS and the write common node WCOM are grounded in the same manner as the data line Dj, so that the selected data line is connected when the common data line DS and the write common node WCOM are connected. The current is not generated in the data line. Therefore, destruction of stored information in the memory cell MC can be prevented.

  Next, in the dummy write circuit DWU1, in the initialization operation, by setting the output to a high resistance state, as described in the description of the multiplexers MUXUD and MUXLD, the current flowing through the dummy data lines DD0 and DD1 is changed to the common data line. A current path that turns back at RS can be formed. In the case of a read operation, each transistor is formed so as to generate a diffusion capacitance in the common data line RS that is twice the diffusion capacitance generated in the common data line DS. The capacitance can be set to the same value as that of the memory cell MC connected to the common data line DS. Therefore, the reference signal having the relationship as shown in FIG. 4 can be accurately generated immediately after the activation of the memory cell MC and the dummy cell DC. Further, in the standby state, the common data line RS is grounded in the same manner as the dummy data lines DD0 and DD1, so that no current is generated in the dummy data lines DD0 and DD1 when they are connected. Therefore, destruction of stored information in the dummy cell DC can be prevented.

  FIG. 7 shows a word driver constituting the word driver array WDA, which includes a read driver WRD for driving the read word line WRk and a write driver WWD for driving the write word line WWk. The read driver WRD is a NOR circuit composed of PMOS transistors P21 and P22 and NMOS transistors N21 and N22. A row decode signal XBk corresponding to the gates of the transistors P21 and N21 which are one input terminal is connected to each other, and a write control signal WET is connected to the gates of the transistors P22 and N22 which are the other input terminals. The output terminal is connected to the read word line WRk. Here, the write control signal WET is one of the array control bus ABS shown in FIG. The write driver WWD includes a PMOS transistor P31 and an NMOS transistor N31. Connected in series with each other, the power supply voltage VDD is input to the source of the transistor P31, and the source of the transistor N31 is connected to the write word line WWk. Further, the row decode signal XBk corresponding to the gate of the transistor P31 and the write control signal WET are connected to the gate of the transistor N31, respectively. The operation of this word driver will be described below.

  First, in the case of a read operation, the write control signal WET is held at the ground potential VSS, so that the transistor N22 is kept in an off state, the transistor P22 is turned on, and the power supply voltage VDD is supplied to the transistor P21. WRD is activated. Therefore, when the kth word line is selected and the row decode signal XBk at the power supply voltage VDD is driven to the ground potential VSS and the transistor P21 is turned on, the read word line WRk at the ground potential VSS Is driven to the power supply voltage VDD. At this time, in the write driver WWD, since the transistor N31 is in the off state, the write word line WWk is held at the ground potential VSS.

  Next, in the write operation, when the write control signal WET at the ground potential VSS is driven to the power supply voltage VDD, the transistor N31 in the write driver WWD is turned on. Therefore, when the k-th word line is selected and the row decode signal XBk at the power supply voltage VDD is driven to the ground potential VSS and the transistor P31 is turned on, the current in the direction of the arrow AWW is applied to the write word line WWk. appear. At this time, the read driver WRD is in a standby state, the transistor P22 is in the off state, and the transistor N22 is conductive, so that the read word line WRk is held at the ground potential VSS. From the above, the word driver according to the present embodiment can drive the read word line and the write word line separately according to the operation.

  Next, the overall read operation of the memory block according to the present invention will be described. FIG. 8 shows a timing waveform of the read operation. In the following, the memory cell MCnm to be selected is arranged at the intersection of the nth word line and the mth data line, and as an example, the memory information MC1 is held, and the MTJ element MTJ in the selected memory cell MCnm has a low resistance. Suppose that it is in a state. Although omitted in FIG. 1, it is assumed that the read data lines ROT and ROB and the write data lines WIT and WIB are connected to the precharge circuit and are driven to VDD / 2 during standby. Based on these assumptions, the description will be made with reference to FIGS. 1, 2, 5, 6, and 7. FIG.

  First, in a read operation, the column selection signal WYS and the write control signal WET are held at the ground potential VSS, respectively, and the write circuits WCU1 and WCL1 are kept in an inactive state. First, the memory cell MCnm is selected. 8 is input, the precharge enable signal EQ, which is the power supply voltage VDD, is driven to the ground potential VSS, and the write circuit WCU1 and the dummy write circuit DWU1 shown in FIG. Are turned off, and the common data lines DS and RS and the ground potential VSS are cut off. Further, since the precharge circuit PCEQ shown in FIG. 5 is also turned off, the sense data lines DT and DB are held at the ground potential VSS which is the precharge potential. Next, the column address signals YMWm and YMDW are held at the ground potential VSS, the column address signals YMTm and YMDT at the ground potential VSS are the power supply voltage VDD, and the column address signals YMBm and YMDB at the power supply voltage VDD are grounded. By driving to the potential VSS, the data line Dm and the dummy data lines DD0 and DD1 shown in FIG. 6 are disconnected from the ground potential VSS, the common data line DS and the data line Dn, the common data line RS and the dummy data line DD0, Connect to DD1 respectively. Further, by driving the row decode signal XBn at the power supply voltage VDD to the ground potential VSS, the read word line WRn in the word driver shown in FIG. 7 is driven to the power supply voltage VDD, and the write word line WWn is connected to the ground potential. Hold in VSS. Therefore, the memory cell MCnm and the dummy cell DCn in the memory block shown in FIG. 1 are selected, and the transistor N1 in the memory cell shown in FIG. 2 is turned on. Subsequently, the read control signal RDB at the power supply voltage VDD is driven to the ground potential VSS, and the current mirror circuits CM and CMD1 in the read circuit RDC1 shown in FIG. Between the potential VSS, two current paths are formed from the current mirror circuit CM and CMD1 through the bias circuit BC1, the multiplexers MUXU1, MUXUD, the memory cell MCnm, and the dummy cell DCn.

  Next, the stored information is detected and amplified. As described in the description of the read circuit RDC1, in response to the memory cell MCnm holding the storage information '1', the current IDS (1) indicated by the solid line flows through one common data line DS, By receiving the current mirror circuit CM with a mirror ratio of 1: 1, the sense data line DT is charged with the current IDS (1). In the figure, the current flowing through the sense data line DT is represented by IDT and is indicated by a solid line. On the other hand, the current IRS = IDS (0) + IDS (1) indicated by the alternate long and short dash line flows through the other common data line RS in response to the dummy cell DCn holding complementary storage information, which is mirrored. By receiving the current mirror circuit CMD1 with a ratio of 2 to 1, the sense data line DB is charged with the current IRS / 2. In the figure, the current flowing through the sense data line DB is represented by IDB and is indicated by a one-dot chain line. In FIG. 8, for comparison, the waveform when the current IDS (0) flows through the common data line DS and the sense data line DT in accordance with the stored information “0” is indicated by a dotted line. From the above, a sense amplifier starting signal SDP that is at the power supply voltage VDD is generated at the timing when a small potential difference is generated between the sense data lines DT and DB and the positive read signal ΔV1 shown in (Equation 4) becomes sufficiently large. Is driven to the ground potential VSS to activate the sense amplifier SA shown in FIG. 5 and amplify the sense data lines DT and DB to the power supply voltage VDD and the ground potential VSS, respectively. Further, the column selection signal RYS at the ground potential VSS is driven to the boosted potential VDH, and the column selection circuit YSW1 shown in FIG. 5 is activated, whereby the read data line ROT precharged to VDD / 2. , ROB is driven to power supply voltage VDD and ground potential VSS, respectively, and stored information is output.

  Further, an operation for returning to the standby state is performed. First, the column selection signal RYS at the boosted potential VDH is driven to the ground potential VSS to turn off the column selection circuit. Next, the row decode signal XBk at the ground potential VSS is driven to the power supply voltage VDD, the read word line WRk at the power supply voltage VDD is driven to the ground potential VSS, and the transistor N1 in the memory cell is turned off. As a result, the current paths formed in the memory cell MCnm and the dummy cell DCn are cut off. Further, the read control signal REB at the ground potential VSS is driven to the power supply voltage VDD, and the current mirror circuits CM and CMD1 are set in a standby state. Further, the column address signals YMTm and YMDT at the power supply voltage VDD are driven to the ground potential VSS, and the column address signals YMBm and YMDB at the ground potential VSS are driven to the power supply voltage VDD, so that the data line Dm and the dummy data line DD0 , Ground DD1. Subsequently, the sense amplifier start signal SDP at the ground potential VSS is driven to the power supply voltage VDD to place the sense amplifier SA in a standby state, and finally the precharge enable signal EQ at the ground potential VSS is set to the power supply voltage VDD. By driving, the sense data lines DT and DB and the common data lines DS and RS are precharged to the ground potential VSS. Finally, the read data lines ROT and ROB that are at the power supply voltage VDD and the ground potential VSS are driven to VDD / 2, and the standby state is restored.

  Next, the entire writing operation of the memory block according to the present invention will be described. FIG. 9 shows a timing waveform of the write operation. In the following, it is assumed that the memory cell MCnm to be selected is arranged at the intersection of the nth word line and the mth data line, and the storage information “1” is written as an example. Although omitted in FIG. 1, it is assumed that the read data lines ROT and ROB and the write data lines WIT and WOB are connected to the precharge circuit and are driven to VDD / 2 during standby. Based on the above assumptions, description will be made with reference to FIGS. 1, 2, 5, 6, and 7. FIG.

  First, in the case of the write operation, the column selection signal RYS is held at the ground potential VSS, the sense amplifier activation signal SDP and the read control signal RDB are held at the power supply voltage VDD, and the read circuit RDC1 is set in a standby state. First, write data input operation is performed. When a write start signal and storage information '1' omitted in FIG. 9 are input, the write data lines WIB and WIT precharged to VDD / 2 are driven to the ground potential VSS and the power supply voltage VDD, respectively. . Next, the column selection signal WYS at the ground potential VSS is driven to the boosted potential VDH, and the transistor N164 in the write circuits WCU1 and WCL1 shown in FIG. The ground potential VSS and the other internal write node WDT are driven to the power supply voltage VDD, respectively.

  Next, the memory cell MCnm is selected and written. First, the precharge enable signal EQ at the power supply voltage VDD is driven to the ground potential VSS, and the transistor N163 in the write circuit WCU1 shown in FIG. 6 is turned off, whereby the common data line DS and the ground potential VSS are set. Cut off. Further, the column address signals YMTm and YMWm at the ground potential VSS are driven to the power supply voltage VDD, and the column address signal YMBm at the power supply voltage VDD is driven to the ground potential VSS, respectively, so that the data line Dm shown in FIG. It is disconnected from the ground potential VSS and connected to the common data line DS and the write common node WCOM. Furthermore, by driving the write control signal WET at the ground potential VSS to the power supply voltage VDD and the write control signal WEB at the power supply voltage VDD to the ground potential VSS, respectively, and activating the write circuits WCU1 and WCL1 respectively. The current IDS indicated by the solid line is formed between the power supply voltage VDD and the ground potential VSS by forming a current path from the write circuit WCU1 to the common data line DS, the data line Dm, the write common node WCOM, and the write circuit WCL1. Run (W1). This current is a positive value corresponding to the direction of the arrow ADL shown in FIG. In FIG. 9, for comparison, the waveform when the current IDS (W0) flows through the common data line DS in accordance with the stored information “0” is indicated by a dotted line. This current is a negative value corresponding to the direction of the arrow ADH shown in FIG. Subsequently, the row decode signal XBn at the power supply voltage VDD is driven to the ground potential VSS, and the write driver unit WWD in the word driver shown in FIG. 7 is activated, whereby the current IW is applied to the write word line WWn. Shed. Therefore, a combined magnetic field is generated at the intersection of the data line Dm and the write word line WWn, and the storage information “1” is written in the memory cell MCnm.

  Further, an operation for returning to the standby state is performed. First, the row decode signal XBk at the ground potential VSS is driven to the power supply voltage VDD to cut off the current path in the write word line WWk. Further, the write control signal WET at the power supply voltage VDD is driven to the ground potential VSS and the write control signal WEB at the ground potential VSS is driven to the power supply voltage VDD, respectively, so that the write circuits WCU1 and WCL1 are inactivated. By doing so, the current path between the power supply voltage VDD and the ground potential VSS is cut off. Further, the column address signals YMTm and YMWm having the power supply voltage VDD are driven to the ground potential VSS, and the column address signal YMBm having the ground potential VSS is driven to the power supply voltage VDD, thereby grounding the data line Dm. Subsequently, the precharge enable signal EQ at the ground potential VSS is driven to the power supply voltage VDD to precharge the common data line DS to the ground potential VSS. Further, the Y selection signal WYS at the boosted potential VDH is driven to the ground potential VSS, and the transistors P163 in the write circuits WCU1 and WCL1 shown in FIG. 6 are turned on, so that the internal write nodes WDB and WDT are turned on. Each is precharged to the power supply voltage VDD. Finally, the write data lines WIT and WIB are driven to VDD / 2 to return to the standby state.

  The effects of the configuration and operation of the memory block described above are summarized below. First, the dummy cell according to the present embodiment has a configuration in which two memory cells MCL and MCH having the same structure as the memory cell MC are arranged in parallel at the intersection of a word line pair and two dummy data lines as shown in FIG. Holds complementary storage information. In the read operation, by simultaneously activating these memory cells MCL and MCH, the current and storage information '0' when the storage information '1' is stored in the two dummy data lines short-circuited by the common data line RS. Outputs current when '. Here, as shown in FIG. 5, the current generated in the memory cell MC is received by the current mirror circuit CM having a mirror ratio of 1: 1, and one terminal of the sense amplifier is charged, whereas the current generated in the dummy cell DC. The received current is received by the current mirror circuit CMD1 having a mirror ratio of 2: 1 so that the other terminal of the sense amplifier is charged with the average current flowing through the memory cell in accordance with the stored information. Therefore, positive and negative read signals as shown in (Equation 4) and (Equation 6) are obtained, and the stored information can be discriminated and amplified by the sense amplifier SA. Since the dummy cell according to the present embodiment is composed of cells having the same structure as the memory cell, the average current of the memory cell can be generated with high accuracy even when the characteristics change due to processing variations. The margin of the read signal can be secured and the stored information can be read accurately.

  Second, since the direction of the magnetic field written in the MTJ element is generally not changed even when the applied voltage is set to 0 V, it is maintained even when the power of the chip is turned off. Therefore, when the manufacturer performs the dummy cell write operation before shipping the chip, the startup time of the MRAM according to the present invention can be shortened.

  Third, the column address signals YMDT, YMDB, and YMDW required for dummy cell initialization are generated by inputting external addresses (to be described later). It can be done easily.

  So far, the memory cell array MCA having an 8 × 8 bit configuration and the dummy cell array DCA1 having an 8 × 1 bit configuration have been described as examples. However, the array configuration is not limited to this. For example, it is possible to adopt a memory cell array configuration in which several hundreds of bits of memory cells are arranged for each pair of word lines and one data line. By increasing the size of the memory cell array in this manner, the read circuit RDC1 and the write circuits WCU1 and WCL1 can be shared by a large number of memory cells MC, and the occupation ratio of the memory cell array with respect to the entire chip can be increased.

  The effects described above can also be realized by modifying the configuration of each circuit block in the memory block shown in FIG. As an example, a modification of the current mirror circuit CMD1 shown in FIG. 5 will be described here. FIG. 10 shows another configuration example of a current mirror circuit having a mirror ratio of 2: 1. The current mirror circuit CMD1 is composed of six transistors, but the example of FIG. 10 is composed of four PMOS transistors P231, P232, P233, and P234. The gates of the transistors P231 and P232 and the drain of P231 are connected to the internal common data line NRS, respectively. Further, the drain of the transistor P232 is connected to the sense data line DB. Further, the transistors P233 and P234 are power control switches having the power supply voltage VDD input to the source and the read control signal REB input to the gate, respectively, and are connected in series to the transistors P231 and P232, respectively. Here, the transistors P232 and P234 are formed to have the same gate dimensions as the transistors P42 and P44 in the current mirror circuit CM of FIG. Further, the gate length of the transistors P231 and P233 is the same as that of the transistors P41 and P43, and the gate width is formed twice that of the transistors P41 and P43, thereby forming a current mirror circuit with a mirror ratio of 2: 1. Yes. In this way, the two transistors P51 and P52 or P53 and P54 of the same size connected in parallel by the current mirror circuit CMD1 in FIG. 5 can be replaced by one transistor P231 or P233, respectively. This eliminates the need for a transistor isolation region and reduces the layout area.

  Further, a dummy write circuit will be described as another example of the circuit configuration in the circuit block shown in FIG. FIG. 11 shows another configuration example of the dummy write circuit. The dummy write circuit DWU1 shown in FIG. 6 is composed of four transistors, but the example of FIG. 11 is composed of one PNOS transistor P241 and one NMOS transistor N241. Here, the gate length of the transistor P241 is the same as that of the transistors P181 and P182, and the gate width is formed to be the sum of the gate widths of the transistors P181 and P182. The gate length of the transistor N241 is set to be the same as that of the transistors N181 and N182, and the gate width is formed to be the sum of the gate widths of the transistors N181 and N182. Thus, it is possible to replace two transistors of the same size connected in parallel by the dummy write circuit DWU1 in FIG. 6 with one transistor each. This eliminates the need for a transistor isolation region and reduces the layout area.

  Hereinafter, an example of the entire configuration of a semiconductor device to which the memory block according to this embodiment is applied will be described. FIG. 12 shows a configuration example (here, t × s configuration) of the memory array MAR in which the memory blocks BLK according to the present embodiment shown in FIG. 1 are arranged in a matrix. Around the memory array MAR, a column decoder YSDEC is arranged on the upper side. On the left side, a plurality of (here, t) column decoders YMD, a row decoder XDEC, and an array control circuit ACTL are arranged for each row of the matrix. Further, a main data input line MI and a main data output line MO are connected to each memory block BLK. Although not shown in the figure, the main data input line MI is composed of the plurality of write data lines WIT and WIB shown in FIG. 1, and the main data output line MO is composed of the plurality of read data lines ROT and ROB. Has been. Each circuit block plays the following role.

  The column decoder YSDEC generates the plurality of column selection signals RYS and WYS shown in FIG. 1 according to the input column predecode address CYS, and inputs each to the memory block BLK arranged in the corresponding column. To do. In response to the column selection signal RYS, read data is output from the memory block BLK in which the memory cell to be selected is arranged to the main data output line MO. Also, write data is input from the main data input line MI to the memory block BLK in which the memory cell to be selected is arranged by the column selection signal WYS. The column decoder YMD generates a column decode address DYM according to the input column predecode address CYM and the mat selection signal MS, and inputs them to the memory blocks BLK arranged in the corresponding rows. The column decode address DYM includes a plurality of column address signals YMTj, YMBj, YMWj, YMDT, YMDB, and YMDW shown in FIG. 1, and the data lines and the memory lines BLK in which the memory cells to be selected are arranged as described above. Control is performed so that the dummy data line is activated. The row decoder XDEC generates a row decode address DXB according to the input row predecode address CX and the mat selection signal MS, and inputs the row decode address DXB to the word driver array WDA in the memory block BLK arranged in the corresponding row. The array control circuit ACTL generates a plurality of control signals on the array control bus ABS according to the input mat selection signal MS, and inputs them to the memory blocks BLK arranged in the corresponding rows. The plurality of control signals are the sense amplifier activation signal SDP, the precharge enable signal EQ, the read control signal RDB, the write control signal WET, and WEB shown in FIGS. 1, 6, and 7, and designate the memory cell to be selected. Each is activated.

  FIG. 13 is a principal block diagram of a configuration example of a synchronous memory. A clock buffer CLKB, a command buffer CB, a command decoder CD, an address buffer AB, an input buffer DIB, an output buffer DOB, and a plurality of units UNT1, UNT2,... Including a memory array MAR are provided. A unit corresponds to a bank, but a plurality of units may be provided per bank. The unit further includes a row predecoder XPD, a column predecoder YPD, a write buffer WB, and a read buffer RB. Each circuit block plays the following role.

  The clock buffer CLKB distributes the external clock CLK as the internal clock CLKI to the command decoder CD, the address buffer AB, the input buffer DIB, the output buffer DOB, and the like. The command decoder CD controls the control signal CM for controlling the address buffer AB, the input buffer DIB, the output buffer DOB, etc. at a desired timing according to the internal control signal CMDI generated from the external control signal CMD via the command buffer CB. Occurs.

  The address buffer AB takes in an external address ADR at a desired timing according to the external clock CLK, and outputs the row address BX to the row address predecoder XPD. The row address predecoder XPD predecodes the row address BX and outputs the row predecode address CX and the mat selection signal MS to the memory array MAR. The address buffer AB further outputs the column address BY to the column address predecoder YPD. The column address predecoder YPD predecodes the column address BY and outputs the column predecode address CYM and the Y predecode address CYS to the memory array MAR. Here, as an example, it is assumed that a row address and a column address are simultaneously fetched from an external address. In this case, the read / write operation can be speeded up by simultaneously performing the row operation and the column operation. As another example, the row address and the column address may be fetched in a time division manner. In this case, the number of pins required for address input can be reduced, and the package mounting cost and board cost can be reduced.

  The input buffer DIB takes in the external input data DQ at a desired timing and inputs the write data GI to the write buffer WB. The write buffer WB outputs write data GI to the main input line MI. On the other hand, the read buffer RB receives the signal of the main output line MO and inputs the read data GO to the output buffer DOB. The output buffer DOB outputs the read data GO to the input / output data DQ at a desired timing.

  Thus, a synchronous memory can be realized using the memory block BLK according to the present embodiment. In this case, it is possible to operate at a high frequency by capturing a command or address in synchronization with the external clock CLK, and further inputting / outputting data, and a high data rate can be realized. Although not shown in the figure, a column address counter is provided between the address buffer AB and the column address predecoder YPD, and data is generated by generating a column address BY that performs a burst operation using the column address as an initial value. It is also possible to input / output these continuously.

  In this embodiment, another configuration example and operation of the memory block will be described. FIG. 14 shows a block diagram of the main part of the memory block. Read circuit RDC2, write circuit WCU10, WCU11, WCL10, WCL11, dummy write circuit DWU1, multiplexer MUXU20, MUXL20, MUXU21, MUXL21, MUXUD, MUXLD, memory cell array It consists of MCA10, MCA11, and dummy cell array DCA1. In the figure, the word driver array WDA, the column decode address DYM, the row decode address DXB, and the array control bus ABS as shown in FIG. 1 are omitted for simplicity. The feature of this embodiment is that a dummy cell array DCA1 is arranged between the two memory cell arrays MCA10 and MCA11 to reduce the near-end difference between the read circuit RDC2 and the data line Dj. In the following, the circuit block shown in FIG. 14 and its circuit configuration will be described with a focus on differences from FIG. 1, and the reference signal generation method and read / write operation according to this embodiment will be described.

  As shown in FIG. 14, the memory cell arrays MCA10 and MCA11 according to the present embodiment are half the size of the memory cell array MCA shown in FIG. 1, and each has 8 × 4 bits of memory cells MC. In one memory cell array MCA10, memory cells MC are arranged at the intersections between the word line pair WRk, WWk (k = 0,..., 7) and the data line Dj (j = 0,..., 3). In the other memory cell array MCA11, memory cells MC are arranged at the intersections of the word line pairs WRk, WWk (k = 0,..., 7) and the data lines Dj (j = 4,..., 7), respectively. The dummy cell array DCA1 includes 8 × 1 bit dummy cells DC according to the configuration of the memory cell array MCA.

  The multiplexers MUXU20 and MUXL20 are arranged at both ends of the memory cell array MCA10 and operate in pairs with each other. One multiplexer MUXU20 is composed of a plurality (four in this case) of switches SRW arranged between the common data line DS0 and a plurality of data lines Dj (j = 0,..., 3). The data line D to be selected and the common data line DS0 are connected according to the omitted column decode address DYM. The other multiplexer MUXL20 is arranged between a plurality (four in this case) of switches SRB arranged between the ground potential VSS and the plurality of data lines Dj, and between the write common node WCOM0 and the plurality of data lines Dj. And a plurality of (in this case, four) switches SW. The former switch SRB cuts off the connection between the data line D to be selected and the ground potential VSS according to the column decode address DYM omitted in the figure, and the latter switch SW writes to the data line D to be selected. Connect to common node WCOM0.

  The multiplexers MUXU21 and MUXL21 are arranged at both ends of the memory cell array MCA11, and operate in pairs with each other. One multiplexer MUXU21 includes a plurality (four in this case) of switches SRW arranged between the common data line DS1 and a plurality of data lines Dj (j = 4,..., 7). The data line D to be selected and the common data line DS1 are connected according to the omitted column decode address DYM. The other multiplexer MUXL21 is arranged between a plurality of (four in this case) switches SRB arranged between the ground potential VSS and the plurality of data lines Dj, and between the write common node WCOM1 and the plurality of data lines Dj. And a plurality of (in this case, four) switches SW. The former switch SRB cuts off the connection between the data line D to be selected and the ground potential VSS according to the column decode address DYM omitted in the figure, and the latter switch SW writes to the data line D to be selected. Connect to common node WCOM1. The switches SRW, SRB, and SW are schematically indicated by symbols in the figure, but are actually configured by, for example, NMOS transistors, and the connection state is controlled by the presence or absence of a current path between the source and drain.

  The write circuits WCU10 and WCL10 have the same circuit configuration as the write circuits WCU1 and WCL1 shown in FIG. 6, and are arranged further outside the multiplexers MUXU20 and MUXL20, respectively, and operate in pairs with each other. The write circuit WCU10 drives the common data line DS0 in accordance with the input column selection signal WYS and the write data line WIB0, and the write circuit WCL10 has write common in accordance with the input column selection signal WYS and the write data line WIT0. Drives node WCOM0.

  Similarly, the write circuits WCU11 and WCL11 have the same circuit configuration as the write circuits WCU1 and WCL1 shown in FIG. 6, and are arranged on the outer sides of the multiplexers MUXU21 and MUXL21, respectively, and operate in pairs with each other. The write circuit WCU11 drives the common data line DS1 according to the input column selection signal WYS and the write data line WIB1, and the write circuit WCL11 writes in common according to the input column selection signal WYS and the write data line WIT1. Drives node WCOM1.

  The read circuit RDC2 discriminates and amplifies the read signals output to the common data lines DS0, DS1, and RS, and drives each of the read data lines ROT0, ROB0, ROT1, and ROB1 to potentials according to the read data.

  By selecting the data lines D in the memory cell arrays MCA10 and MCA11 one by one with the circuit block configuration as described above, 2-bit stored information is read or written. In the following, the circuit configuration of the read circuit will be described, and the reference signal generation method and read operation according to this embodiment will be described.

  FIG. 15 shows a circuit configuration of the readout circuit RDC2, and two sets of column selection circuits YSW10 and YSW11, precharge circuits PCEQ0 and PCEQ1, sense amplifiers SA0 and SA1, current mirror circuits CM10 and CM11, and a current mirror circuit CMD2 The bias circuit BC2. Also, among the element components of the array control bus ABS shown in FIG. 1, a precharge enable signal EQ, a sense amplifier activation signal SDP, a read control signal REB are input, and a column selection signal RYS is input. Column selection circuits YSW10, YSW11, precharge circuits PCEQ0, PCEQ1, sense amplifiers SA0, SA1, current mirror circuits CM10, CM11 are the column selection circuit YSW1, precharge circuit PCEQ, sense amplifier SA, current mirror circuit shown in FIG. Each CM has the same circuit configuration. The circuit configurations of the current mirror circuit CMD2 and the bias circuit BC2 will be described below.

  The current mirror circuit CMD2 is obtained by adding PMOS transistors P57 and P58 to the circuit configuration of the current mirror circuit CMD1 shown in FIG. The drain of the transistor P53 is connected to the sense data line DB0, and the drain of the transistor P57 is connected to the sense data line DB1. Further, the gates of the transistors P51, P52, P53 and P57 and the drains of the transistors P51 and P52 are connected to the internal common data line NRS. The transistor P58 is a power control switch in which the power supply voltage VDD is input to the source and the read control signal REB is input to the gate, and is connected in series with the transistor P57. Here, the gate of the transistor P57 is formed with the same dimensions as the transistors P51, P52, and P53, and the gate of the transistor P58 is formed with the same dimensions as the transistors P54, P55, and P56, and the transistors P51, P52, P53, and P57 The current value flowing between the source and drain is made equal. Therefore, a two-output current mirror circuit with a mirror ratio of 2: 1 is formed by flowing a current having a value half of the total current flowing through the transistors P51 and P52 between the source and drain of P53 and P57.

  The bias circuit BC2 has a configuration in which an NMOS transistor N611 is added to the bias circuit BC1 shown in FIG. 5, and the transistor N610 corresponds to the transistor N61 in FIG. Common data line DS0 and internal common data line NDS0 are connected to the source and drain of transistor N610, respectively, and common data line DS1 and internal common data line NDS1 are connected to the source and drain of transistor N611, respectively. A bias voltage VB1 is applied to the gates of the transistors N610 and N611, respectively. Here, the gate length of the transistor N62 is the same as that of the transistors N610 and N611, and the data width is twice that of the transistors N610 and N611, so that the on-resistance of the transistor N62 is 1/2 that of the transistors N610 and N611. .

  With the circuit configuration of the read circuit RDC2 as described above, the currents output from the memory cell arrays MCA10 and MCA11 to the common data lines DS0 and DS1 are respectively received and selected by the current mirror circuits CM10 and CM11 having a mirror ratio of 1: 1. The sense data lines DT0 and DT1 are charged with a current having the same value as the current flowing through the two memory cells MC, respectively. On the other hand, the current output from the dummy cell DC to the common data line RS is received by the two-output current mirror circuit CMD2 having a mirror ratio of 2: 1 so that the average value of the current flowing through the memory cell MC according to the stored information is obtained. To charge the sense data lines DB0 and DB1. Therefore, positive and negative read signals as shown in (Equation 4) and (Equation 6) of the first embodiment are generated on the sense data lines DT0, DB0, DT1, and DB1, and the selection is performed by using the sense amplifiers SA0 and SA1. The 2-bit stored information is discriminated and amplified. Further, the 2-bit read data read by the column selection circuits YSW10 and YSW11 is output to the read data lines ROT0, ROB0, ROT1, and ROB1.

  The effects of the configuration and operation of the memory block described above are summarized below. First, a dummy cell array DCA1 is arranged between the two memory cell arrays MCA10 and MCA11, and a read signal is reduced by reducing the near-end difference between the read circuit RDC2 and the data line Dj as compared with the first embodiment. The position dependency of the data line to be selected can be reduced. Second, as in the first embodiment, the average current of the memory cell can be obtained even when a change in characteristics due to processing variations occurs by using a dummy cell having the same structure as the memory cell MC and holding complementary storage information. Therefore, the stored information can be read accurately.

  So far, the memory cell arrays MCA10 and MCA11 having an 8 × 4 bit configuration and the dummy cell array DCA1 having an 8 × 1 bit configuration have been described as examples. However, the array configuration is not limited to this. For example, as in the example described in the first embodiment, a memory cell array configuration in which several hundreds of bits of memory cells are arranged for each word line pair and each data line is provided. Occupancy can be increased. At that time, it is preferable to use the configuration of this embodiment because the dependency of the read signal amount on the data line position can be reduced.

  The effects described above can also be realized by modifying the configuration of each circuit block in the memory block shown in FIG. As an example, a modification of the current mirror circuit CMD2 shown in FIG. 15 will be described here. FIG. 16 shows another configuration example of a two-output current mirror circuit having a mirror ratio of 2: 1. The current mirror circuit CMD2 shown in FIG. 15 is composed of eight transistors, but the example of FIG. 16 is composed of six transistors in which PMOS transistors P235 and P236 are added to the current mirror circuit shown in FIG. Is done. The drain of the transistor P232 is connected to the sense data line DB0, and the drain of the transistor P235 is connected to the sense data line DB1. Further, the gates of the transistors P231, P232, and P235 and the drain of the transistor P232 are connected to the internal common data line NRS, respectively. The transistor P236 is a power control switch in which the power supply voltage VDD is input to the source and the read control signal REB is input to the gate, and is connected in series to the transistor P235. Here, the gate length of the transistor P231 is the same as that of the transistors P232 and P235, and the gate width of the transistor P231 is formed twice that of the transistors P232 and P235. Further, by setting the gate length of the transistor P233 to be the same as that of the transistors P234 and P236 and forming the gate width of the transistor P233 twice that of the transistors P234 and P236, a current having a value half that of the current flowing through the transistor P231 can be obtained. And a two-output current mirror circuit with a mirror ratio of 2 to 1 that flows between the source and drain of P235. In this way, the two transistors P51 and P52 or P53 and P54 of the same size connected in parallel by the current mirror circuit CMD2 in FIG. 15 can be replaced with one transistor P231 or P233, respectively. This eliminates the need for a transistor isolation region and reduces the layout area.

  In this embodiment, another configuration example and operation of the memory block will be described. FIG. 17 shows a block diagram of the main part of the memory block. Read circuit RDC3, write circuit WCU10, WCL10, WCU11, WCL11, multiplexer MUXU20, MUXL20, MUXU21, MUXL21, MUXUD0, MUXLD0, MUXUD1, MUXLD1, memory cell array MCA10 , MCA11, and dummy cell arrays DCA10 and DCA11. As in FIG. 14, the word driver array WDA, the column decode address DYM, the row decode address DXB, and the array control bus ABS as shown in FIG. The feature of this embodiment is that dummy cell arrays DCA10 and DCA11 are arranged between two memory cell arrays MCA10 and MCA11, and the terminals MUXU20 and MUXUD0 corresponding to the memory cell array MCA10 and dummy cell array DCA10 are connected to the common data line DL. By connecting one side of the multiplexers MUXU21 and MUXUD1 corresponding to the memory cell array MCA11 and the dummy cell array DCA11 to the common data line DR, the number of switches SRW connected to the common data lines DL and DR is made uniform. is there. Hereinafter, the circuit block shown in FIG. 17 will be described while paying attention to differences from FIG.

  The dummy cell arrays DCA10 and DCA11 have 8 × 1 bit dummy cells DC according to the configuration of the memory cell arrays MCA10 and MCA11, similarly to the DCA1 shown in FIG. In one dummy cell array DCA10, dummy cells DC are arranged at the intersections between the word line pair WRk, WWk (k = 0,..., 7) and the dummy data lines D100, D101, respectively. In the other dummy cell array DCA11, dummy cells DC are arranged at the intersections of the word line pairs WRk, WWk (k = 0,..., 7) and the dummy data lines D110, D111, respectively.

  The multiplexers MUXUD0 and MUXLD0 are arranged at both ends of the dummy cell array DCA10 and operate in pairs with each other. One multiplexer MUXUD0 is composed of two switches SRW arranged between the common data line DL and the dummy data lines D100 and D101, and the dummy data according to the column decode address DYM omitted in FIG. The lines D100 and D101 are connected to the common data line DL. Therefore, the number of switches SRW connected to the common data line DL is six, including the four multiplexers MUXU20. The other multiplexer MUXLD0 includes two switches SRB arranged between the ground potential VSS and the dummy data lines D100 and D101, and between the ground potential VSS, the dummy data line D100, the power supply voltage VDD, and the dummy data line D101. It consists of two switches SW arranged in the. The former switch SRB cuts off the connection between the dummy data lines D100 and D101 and the ground potential VSS according to the column decode address DYM which is omitted in FIG. The latter switch SW connects the dummy data line D100 and the ground potential VSS, and the dummy data line D101 and the power supply voltage VDD according to the column decode address DYM, which is omitted in FIG. The multiplexers MUXUD0 and MUXLD0 having such a configuration can generate currents in opposite directions to the dummy data lines D100 and D101 in the same manner as the multiplexers MUXUD and MUXLD shown in FIG. 1, and initialize the dummy cell array DCA10. be able to.

  The multiplexers MUXUD1 and MUXLD1 are arranged at both ends of the dummy cell array DCA11 and operate in pairs with each other. One multiplexer MUXUD1 is composed of two switches SRW arranged between the common data line DR and the dummy data lines D110 and D111, and the dummy data according to the column decode address DYM omitted in the figure. The lines D110 and D111 are connected to the common data line DR. Therefore, the number of switches SRW connected to the common data line DR is six, including the four multiplexers MUXU21. The other multiplexer MUXLD1 includes two switches SRB arranged between the ground potential VSS and the dummy data lines D110 and D111, and between the ground potential VSS, the dummy data line D110, the power supply voltage VDD, and the dummy data line D111. It consists of two switches SW arranged in the. The former switch SRB cuts off the connection between the dummy data lines D110 and D111 and the ground potential VSS according to the column decode address DYM which is omitted in FIG. The latter switch SW connects the dummy data line D110 and the ground potential VSS, and the dummy data line D111 and the power supply voltage VDD according to the column decode address DYM, which is omitted in FIG. The multiplexers MUXUD1 and MUXLD1 having such a configuration can generate opposite currents in the dummy data lines D110 and D111 in the same manner as the multiplexers MUXUD and MUXLD shown in FIG. 1, and initialize the dummy cell array DCA11. be able to. The switches SRW, SRB, and SW are schematically indicated by symbols in the figure, but are actually configured by, for example, NMOS transistors, and the connection state is controlled by the presence or absence of a current path between the source and drain.

  The write circuit WCU10 drives the common data line DL according to the input column selection signal WYSL and the write data line WIB, and the write circuit WCL10 is common to write according to the input column selection signal WYSL and the write data line WIT Drives node WCOM0. The write circuit WCU11 drives the common data line DR according to the input column selection signal WYSR and the write data line WIB, and the write circuit WCL11 writes in common according to the input column selection signal WYSR and the write data line WIT Drives node WCOM1. Here, one of the column selection signals WYSL and WYSR is activated in accordance with the position of the memory cell MC into which stored information is written.

  The read circuit RDC3 includes a common data line DLA arranged in parallel to the common data line DL and the common data line DL, and a read signal generated in the common data line DR and the common data line DRA arranged in parallel to the common data line DR. Are read out and output to read data lines ROT and ROB.

  Next, the operation of this memory block will be described. First, when reading the memory cell MC on the memory cell array MCA10, the multiplexers MUXU20 and MUXL20 are activated and the data line D to be selected is connected to the common data line DL, whereby the current flowing through the memory cell MC is changed to the common data line DL. Output to. At the same time, the multiplexers MUXUD1 and MUXLD1 are activated, the dummy cell DC on the dummy cell array DCA11 is selected, and the dummy data lines D110 and D111 are connected to the common data line DR, whereby the current flowing through the dummy cell DC is supplied to the common data line DR. Output. Next, when data is written to the memory cell MC on the memory cell array MCA10, the data line D to be selected, the common data line DL, and the write common node WCOM0 are connected, and the write control signal WYSL is used to activate the write circuits WCU10 and WCL10. As a result, a current having a direction corresponding to the stored information is generated in the data line D to be selected.

  On the other hand, when reading the memory cell MC on the memory cell array MCA11, the multiplexers MUXU21 and MUXL21 are activated and the selected data line D and the common data line DR are connected, so that the current flowing through the memory cell MC is shared. Output to data line DR. At the same time, the multiplexers MUXUD0 and MUXLD0 are activated, the dummy cell DC on the dummy cell array DCA10 is selected, and the dummy data lines D100 and D101 are connected to the common data line DL, whereby the current flowing through the dummy cell DC is applied to the common data line DL. Output. When data is written to the memory cell MC on the memory cell array MCA11, the data line D to be selected is connected to the common data line DR and the write common node WCOM1, and the write control signal WYSR is used to activate the write circuits WCU11 and WCL11. As a result, a current having a direction corresponding to the stored information is generated in the data line D to be selected.

  With the circuit block configuration as described above, the number of switches SRW connected to the common data lines DL and DR can be the same (here, 6). Further, since each of the common data lines DL and DR is wired so as to be orthogonal to the four data lines and the two dummy data lines, the wiring lengths of these portions can be made equal. Accordingly, the load capacitance and resistance of the common data lines DL and DR can be balanced, and a more stable read operation than in the second embodiment can be achieved. In the following, the configuration and operation of the readout circuit and a method for generating a reference signal are described.

  FIG. 18 shows a circuit configuration of the readout circuit RDC3, which includes a column selection circuit YSW2, a precharge circuit PCEQ, a sense amplifier SA, current mirror circuits CM20 and CM21, and a bias circuit BC3. In the array control bus ABS shown in FIG. 1, a precharge enable signal EQ, a sense amplifier activation signal SDP, and a read control signal REB are input, and column selection signals RYSL and RYSR are input. The dummy enable signals DEB0 and DEB1 are signals generated according to the input external address by the control circuit not shown in the figure, and are input to the current mirror circuits CM20 and CM21, respectively. Hereinafter, the configuration and operation of the current mirror circuits CM20 and CM21 and the bias circuit BC3 will be described first, and then the column selection circuit YSW2 will be described.

  The current mirror circuits CM20 and CM21 have the same configuration, and are configured by PMOS transistors P301, P302, P303, P304, P305, and P306. The transistors P301, P302, and P303 are formed with the same gate dimensions, and the transistors P304, P305, and P306 are formed with the same dimensions. In one current mirror circuit CM20, the gates of the transistors P301, P302, and P303 and the drain of the transistor P301 are connected to the internal common data line NDL, the drain of the transistor P302 is connected to the internal common data line NDLA, and the drain of the transistor P303 is the sense data line. Connect to each SDL. The transistors P304, P305, and P306 are power supply control transistors that have a power supply voltage VDD input to their sources, and are connected in series to the transistors P301, P302, and P303, respectively. Further, the read control signal REB is input to the gates of the transistors P304 and P306, and the dummy enable signal DEB0 is input to the gate of the transistor P305. In the other current mirror circuit CM21, the gates of the transistors P301, P302, and P303 and the drain of the transistor P301 are connected to the internal common data line NDR, the drain of the transistor P302 is connected to the internal common data line NDRA, and the drain of the transistor P303 is the sense data line. Connect to each SDR. Further, the dummy enable signal DEB1 is input to the gate of the transistor P305.

  The bias circuit BC3 includes NMOS transistors N321, N322, N323, and N324. The source and drain of the transistor N321 are connected to the common data line DL and the internal common data line NDL, respectively, and the source and drain of the transistor N322 are connected to the common data line DLA and the internal common data line NDLA, respectively. The source and drain of the transistor N323 are connected to the common data line DR and the internal common data line NDR, respectively, and the source and drain of the transistor N324 are connected to the common data line DRA and the internal common data line NDRA, respectively. Further, the bias voltage VB1 is input to the gates of the transistors P321, P322, P323, and P324. Here, transistors N321, N322, N323, and N324 are formed to have the same gate dimensions, and common data lines DL, DLA, DR, and DRA and internal common data lines NDL, NDLA, NDR, and NDRA are each set to the same wiring width and length. Thus, the impedance when the current mirror circuits CM20 and CM21 are viewed from the common data lines DL and DLA and the common data lines DR and DRA is made equal.

  The operation of the current mirror circuits CM20 and CM21 having such a configuration will be described below. As an example, in the current mirror CM20, the dummy enable signal DEB0 is held at the power supply voltage VDD, the read control signal REB at the power supply voltage VDD is driven to the ground potential VSS, and the power supply voltage VDD is supplied to the transistors P301 and P303. Thus, a current mirror circuit having a mirror ratio of 1: 1 is formed. On the other hand, the dummy enable signal DEB0 and the read control signal REB that are at the power supply voltage VDD are driven to the ground potential VSS, and the power supply voltage VDD is supplied to the transistors P301, P302, and P303, so that the mirror ratio becomes 2 pairs. 1 current mirror circuit is formed. In the current mirror circuit CM21, a similar operation is possible by controlling the dummy enable signal DEB1. Therefore, with the above configuration and operation, the mirror ratio of the current mirror circuits CM20 and CM21 can be controlled to 1: 1 or 2: 1 in accordance with the dummy enable signals DEB0 and DEB1.

  Next, the column selection circuit YSW2 will be described. The column selection circuit YSW2 includes NMOS transistors N331, N332, N333, and N334. A column selection signal RYSL is input to the gates of the transistors N331 and N332, and a column selection signal RYSR is input to the gates of the transistors N333 and N334, respectively. The drain of the transistor N331 is connected to the read data line ROT, the source is connected to the sense data line SDL, the drain of the transistor N332 is connected to the read data line ROB, and the source is connected to the sense data line SDR. The drain of the transistor N333 is connected to the read data line ROB, the source is connected to the sense data line SDL, the drain of the transistor N334 is connected to the read data line ROT, and the source is connected to the sense data line SDR. Therefore, by holding the column selection signal RYSR at the ground potential VSS and driving the column selection signal RYSL at the ground potential VSS to the boosted potential VDH to turn on the transistors N331 and N332, the sense data lines SDL and SDR are turned on. The read data lines ROT and ROB can be connected. In addition, the column selection signal RYSL is held at the ground potential VSS, the column selection signal RYSR at the ground potential VSS is driven to the boosted potential VDH, and the transistors N333 and N334 are turned on, so that the sense data lines SDL and SDR are turned on. It can be connected to read data lines ROB and ROT.

  Here, in this embodiment, when reading the memory cell MC on the memory cell array MCA10, the sense data line SDL is charged with a current having the same value as the current flowing through the selected memory cell MC, and conversely, the memory on the memory cell array MCA10 is read. When reading the cell MC, the sense data line SDR is charged with a current having the same value as the current flowing through the selected memory cell MC. Accordingly, the polarities of the sense data lines SDL and SDR with respect to the read data lines ROT and ROB differ depending on the position of the read memory cell MC. However, the sense data lines SDL and SDR and the read data are connected by connecting the sense data lines SDL and SDR to the read data lines ROT and ROB according to their polarities using the column selection circuit YSW2 having the configuration described above. The polarities of the lines ROT and ROB can be matched, and the read data can be output accurately.

  The overall operation and the generation method of the reference signal in the readout circuit RCD3 having such a configuration will be described. Here, as an example, a case where the memory cell MC in the memory cell array MCA10 shown in FIG. 17 is selected will be described. First, according to the memory cell array MCA10 to be selected, the dummy mirror enable signal DEB0 is held at the power supply potential VDD, thereby forming the current mirror circuit CM20 having a mirror ratio of 1: 1. Further, by driving the dummy enable signal DEB1 and the read control signal REB that are at the power supply voltage VDD to the ground potential VSS, a current mirror circuit CM21 having a mirror ratio of 2 to 1 is formed. Therefore, one sense data line SDL is charged with a current having the same value as the current flowing through the memory cell MC output to the common data line DL. The other sense data line SDR is charged with a current that is half the value of the current flowing through the dummy cells DC output to the common data lines DR and DRA. With the above operation, positive and negative read signals as shown in (Equation 4) and (Equation 6) of the first embodiment are generated, and the stored information can be discriminated and amplified by using the sense amplifier SA. Further, the column selection signal RYSL at the ground potential VSS is driven to the boosted potential VDH, and the transistors N331 and N332 are turned on, thereby reading the sense data line SDL and the sense data line SDR. Connect to each ROB and output the read data.

The effects of this embodiment are summarized below. By aligning the number of switches SRW connected to the common data lines DL and DR, the load capacitance and resistance of the common data lines DL and DR formed in parallel to the word line pair can be balanced, A more stable read operation than in the second embodiment is possible.
Here, by using the current mirror circuits CM20 and CM21 as shown in FIG. 18 to control the mirror ratio according to the position of the selected memory cell MC, a desired read signal is sent to the sense data lines SDL and SDR. A reference signal can be generated. Further, by using the column selection circuit YSW2 as shown in FIG. 18 and connecting the sense data lines SDL and SDR to the read data lines ROT and ROB according to their polarities, the sense data lines SDL and SDR are read out. The polarities of the data lines ROT and ROB can be matched, and the read data can be output accurately.

  Up to this point, the memory cell arrays MCA10 and MCA11 having an 8 × 4 bit configuration and the dummy cell arrays DCA10 and DCA11 having an 8 × 1 bit configuration have been described as examples. However, the array configuration is not limited to this. For example, like the example described in the first and second embodiments, the third embodiment also has a memory cell array configuration in which several hundreds of bits of memory cells are arranged for each word line pair and each data line. As a result, the occupation ratio of the memory cell array with respect to the entire chip can be increased.

  In this embodiment, another configuration example and operation of the memory block will be described. FIG. 19 shows a block diagram of the main part of the memory block. Read circuit RDC40, RDC41, write circuit WCU20, WCU21, WCL10, WCL11, multiplexer MUXU20, MUXL20, MUXU21, MUXL21, MUXUD0, MUXLD0, MUXUD1, MUXLD1, memory Cell arrays MCA10 and MCA11, dummy cell arrays DCA10 and DCA11, and a common data line control circuit DSW are configured. Similarly to FIGS. 14 and 17, in FIG. 19, the word driver array WDA, the column decode address DYM, the row decode address DXB, and the array control bus ABS as shown in FIG. 1 are omitted for simplicity. The feature of this embodiment is that, first, four common data lines DLE, DLO, DRE, DRO are formed, and switches SRW in multiplexers MUXU20, MUXU21, MUXUD0, MUXUD1 are regularly arranged on each common data line. By connecting, the number of switches SRW connected to each common data line is made uniform. Second, in the read operation, the common data line is connected by using the common data line control circuit DSW according to the position of the dummy cell DC to be activated. Hereinafter, differences from FIG. 17 will be described.

  First, each of the common data lines DLE, DLO, DRE, and DRO is formed in parallel with the word line pair so as to have the same wiring length and wiring width. First, the switch SRW connected to the even-numbered data line D (here, the data lines D0 and D2) in the multiplexer MUXU20 and the switch SRW connected to the dummy data line D100 in the multiplexer MUXUD0 are connected to the common data line DLE. . Next, switch SRW connected to odd-numbered data line D (here, data lines D1, D3) in multiplexer MUXU20 and switch SRW connected to dummy data line D101 in multiplexer MUXUD0 are connected to common data line DLO. To do. Further, the switch SRW connected to the even-numbered data line D (here, the data lines D4 and D6) in the multiplexer MUXU21 and the switch SRW connected to the dummy data line D110 in the multiplexer MUXUD1 are connected to the common data line DRE. . Further, the switch SRW connected to the odd-numbered data line D (here, the data lines D5 and D7) in the multiplexer MUXU21 and the switch SRW connected to the dummy data line D111 in the multiplexer MUXUD1 are connected to the common data line DRO. . With the above configuration, the number of switches SRW per common data line is the same (here, three).

  The common data line control circuit DSW includes two switches SE and SO. One switch SE is arranged between the common data lines DLE and DRE, and the other switch SO is arranged between the common data lines DLO and DRO. When the dummy cell array DCA10 is activated, the switch SE is turned on and the common data lines DLE and DRE are connected to connect the two memory cells MCL and MCH constituting the dummy cell DC in parallel. When the dummy cell array DCA11 is activated, the switch SO is turned on and the common data lines DLO and DRO are connected to connect the two memory cells MCL and MCH constituting the dummy cell DC in parallel.

  The read circuit RDC40 detects and amplifies read signals generated on the common data lines DLE and DLO by selecting the memory cell MC on the memory cell array MCA10. Further, the read data is output to the read data lines ROT0 and ROB0 according to the column selection signals RYSE and RYSO. On the other hand, the read circuit RDC41 detects and amplifies read signals generated on the common data lines DRE and DRO by selecting the memory cell MC on the memory cell array MCA11. Further, the read data is output to the read data lines ROT1 and ROB1 according to the column selection signals RYSE and RYSO.

  The write circuit WCU20 drives the common data lines DLE and DLO according to the input read control signal REB, column selection signal WYS, and write data line WIB0, and the write circuit WCL10 receives the input column selection signal WYS and write data. The write common node WCOM0 is driven according to the line WIT0. The write circuit WCU21 drives the common data lines DRE and DRO according to the input read control signal REB, column selection signal WYS, and write data line WIB1, and the write circuit WCL11 receives the input column selection signal WYS and write data. The write common node WCOM1 is driven according to the line WIT1.

  Next, the overall operation of this memory block will be described. First, as a first example of the read operation, a case where the memory cells MC on even-numbered data lines in the memory cell arrays MCA10 and MCA11 are read will be described. First, the switch SO in the common data line control circuit DSW is turned on to connect the common data lines DLO and DRO. Next, memory cells MC on even-numbered data lines in the memory cell arrays MCA10 and MCA11 are selected, and currents corresponding to stored information are output to the read circuits RDC40 and RDC41 via the common data lines DLE and DRE, respectively. At the same time, the dummy cells DC in the dummy cell array DCA11 are activated, and currents flowing through the dummy cells DC are output to the read circuits RDC40 and RDC41 via the shorted common data lines DLO and DRO, respectively.

  Next, as a second example of the read operation, a case where the memory cells MC on the odd-numbered data lines in the memory cell arrays MCA10 and MCA11 are read will be described. First, the switch SE in the common data line control circuit DSW is turned on to connect the common data lines DLE and DRE. Next, memory cells MC on odd-numbered data lines in the memory cell arrays MCA10 and MCA11 are selected, and currents corresponding to stored information are output to the read circuits RDC40 and RDC41 via the common data lines DLO and DRO, respectively. At the same time, the dummy cells DC in the dummy cell array DCA10 are activated, and currents flowing through the dummy cells DC are output to the read circuits RDC40 and RDC41 via the shorted common data lines DLE and DRE, respectively.

  As a first example of the write operation, a case of writing to the memory cells MC on the even-numbered data lines in the memory cell arrays MCA10 and MCA11 will be described. In this case, even-numbered data lines in the memory cell array MCA10 are connected to the common data line DLE and the write common node WCOM0, and the write circuits WCU20 and WCL10 generate a current having a direction according to the stored information. At the same time, the even-numbered data lines in the memory cell array MCA11 are connected to the common data line DRE and the write common node WCOM1, and the write circuits WCU21 and WCL11 generate a current having a direction corresponding to the stored information.

  Furthermore, as a second example of the write operation, a case where data is written to the memory cells MC on the odd-numbered data lines in the memory cell arrays MCA10 and MCA11 will be described. In this case, odd-numbered data lines in the memory cell array MCA10 are connected to the common data line DLO and the write common node WCOM0, and the write circuits WCU20 and WCL10 generate a current having a direction according to the stored information. At the same time, odd-numbered data lines in the memory cell array MCA11 are connected to the common data line DRO and the write common node WCOM1, and the write circuits WCU21 and WCL11 generate a current in a direction corresponding to the stored information.

  Finally, the initialization operation of the dummy cell arrays DCA10 and DCA11 is performed as follows. When one dummy cell array DCA10 is initialized, the switch SE in the common data line control circuit DSW is turned on, the common data lines DLE and DRE are short-circuited, and the multiplexers MUXUD0 and MUXLD0 are activated, as shown in FIG. Similar to the multiplexers MUXUD and MUXLD, currents in opposite directions are generated on the dummy data lines D100 and D101. When the other dummy cell array DCA11 is initialized, the switch SO in the common data line control circuit DSW is turned on, the common data lines DLO and DRO are short-circuited, and the multiplexers MUXUD1 and MUXLD1 are activated, as shown in FIG. Similar to the multiplexers MUXUD and MUXLD, currents in opposite directions are generated on the dummy data lines D110 and D111.

  Next, the configuration and operation of the read circuits RDC40 and RDC41 and a method for generating a reference signal will be described. FIG. 20 shows a configuration example of two readout circuits RDC40 and RDC41, each of which includes a column selection circuit YSW2, a precharge circuit PCEQ, a sense amplifier SA, current mirror circuits CM10 and CM11, and a bias circuit BC4. Each is composed. The precharge enable signal EQ, the sense amplifier activation signal SDP, and the read control signal REB that are input are signals in the array control bus ABS. The features of the read circuits RDC40 and RDC41 according to the present embodiment are firstly that the current mirror circuits CM10 and CM11 have the same configuration as the current mirror circuit CM having a mirror ratio of 1: 1 as shown in FIG. Second, the bias circuit BC4 is composed of NMOS transistors N101 and N102 having the same gate dimensions.

  First, the read circuit RDC40 will be described. The input terminal of one current mirror circuit CM10 is connected to the internal common data line NDLE, and the output terminal is connected to the sense data line SDLE. The other current mirror circuit CM11 has an input terminal connected to the internal common data line NDLO and an output terminal connected to the sense data line SDLO. In the bias circuit BC4, the source and drain of the transistor N101 are connected to the common data line DLE and the internal common data line NDLE, respectively, and the source and drain of the transistor N102 are connected to the common data line DLO and the internal common data line NDLO, respectively. Connecting. Further, the common data lines DLE and DLO and the internal common data lines NDLE and NDLO are formed to have the same wiring width and wiring length. With such a configuration, the impedance when the current mirror circuits CM10 and CM11 are viewed from the common data lines DLE and DLO can be made equal.

  The column selection circuit YSW2 connects the sense data lines SDLE and SDLO to one of the read data lines ROT0 and ROB0 according to the input column selection signals RYSE and RYSO. In this embodiment, when reading the memory cells MC on the even-numbered data lines in the memory cell array MCA10 shown in FIG. 19, the sense data line SDLE has a positive polarity and the memory cells MC on the odd-numbered data lines are read. Further, the sense data line SDLO has a positive polarity. Therefore, the sense data lines SDLE and SDLO are connected to the read data lines ROT0 and ROB0 according to their polarities using the column selection circuit YSW2.

  Next, the read circuit RDC41 will be described. One current mirror circuit CM10 has an input terminal connected to the internal common data line NDRE and an output terminal connected to the sense data line SDRE. The other current mirror circuit CM11 has an input terminal connected to the internal common data line NDRO and an output terminal connected to the sense data line SDRO. In the bias circuit BC4, the source and drain of the transistor N101 are connected to the common data line DRE and the internal common data line NDRE, respectively, and the source and drain of the transistor N102 are connected to the common data line DRO and the internal common data line NDRO, respectively. Connecting. Further, the common data lines DRE and DRO and the internal common data lines NDRE and NDRO are formed to have the same wiring width and wiring length. With such a configuration, the impedance when the current mirror circuits CM10 and CM11 are viewed from the common data lines DRE and DRO can be made equal.

  The column selection circuit YSW2 connects the sense data lines SDRE and SDRO to one of the read data lines ROT1 and ROB1 according to the input column selection signals RYSE and RYSO. In this embodiment, when reading the memory cells MC on the even-numbered data lines in the memory cell array MCA11 shown in FIG. 19, the sense data line SDRE has a positive polarity and the memory cells MC on the odd-numbered data lines are read. In addition, the sense data line SDRO has a positive polarity. Therefore, the sense data lines SDRE and SDRO are connected to the read data lines ROT1 and ROB1 according to their polarities using the column selection circuit YSW2.

  FIG. 20 further shows a configuration example of the common data line control circuit DSW. The NMOS transistor N411 corresponds to the switch SE shown in FIG. 19, has a source and a drain connected to the common data lines DLE and DRE, respectively, and a connection control signal CNE input to the gate. The NMOS transistor N412 corresponds to the switch SO shown in FIG. 19, and has a source and a drain connected to the common data lines DLO and DRO, respectively, and a connection control signal CNO input to the gate. Here, the connection control signals CNE and CNO are signals generated according to the input external address by a control circuit not shown in the figure.

  The overall operation of the read circuits RDC40 and RDC41 and the common data line control circuit DSW and the method for generating the reference signal will be described. Here, as an example, a case will be described in which memory cells MC on even-numbered data lines are selected in memory cell arrays MCA10 and MCA11 shown in FIG. In this case, the dummy cell DC on the dummy cell array DCA11 is selected. First, in the data line control circuit, the common data line DLO is connected to the common data line DLO by driving the connection control signal CNO at the ground potential VSS to the power supply voltage VDD and conducting the transistor N412. , DRO and dummy data lines D110 and D111 are short-circuited. Next, the read control signal REB at the power supply voltage VDD is driven to the ground potential VSS to activate the current mirror circuit CM10 having a mirror ratio of 1: 1 in the read circuit RDC40, thereby selecting the memory cell array MCA10. The sense data line SDLE is charged with a current corresponding to the stored information in the memory cell MC. Similarly, by activating the current mirror circuit CM10 having a mirror ratio of 1: 1 in the read circuit RDC41, the sense data line SDRE is charged with a current corresponding to the stored information in the selected memory cell MC on the memory cell array MCA11. Further, at this time, in the read circuits RDC40 and RDC41, the current mirror circuit CM11 having a mirror ratio of 1: 1 is activated. Here, the impedance when the corresponding current mirror circuit CM11 is viewed from the common data lines DLO and DRO is equal, and the common data lines DLO and DRO and the dummy data lines D110 and D111 are short-circuited to have the same potential. A current having a value half that of the current flowing through the dummy cell DC flows through each current mirror circuit CM11. Therefore, the sense data lines SDLO and SDRO are charged with an average current flowing through the dummy cell DC. Therefore, positive and negative read signals as shown in (Equation 4) and (Equation 6) of the first embodiment are generated on the sense data lines SDLE and SDLO, SDRE and SDRO, and the stored information is discriminated by the sense amplifier SA. Amplify. Further, the sense data line SDLE is read by driving the column selection signal RYSE at the ground potential VSS to the boosted potential VDH and turning on the transistors N331 and N332 in the column selection circuit YSW2 of the read circuits RDC40 and RDC41. The data line ROT0 and the sense data line SDLO are connected to the read data line ROB0, the sense data line SDRE is connected to the read data line ROT1, and the sense data line SDRO is connected to the read data line ROB1 to output the read data.

  Next, the write circuits WCU20 and WCU21 will be described. FIG. 21 shows write circuits WCU20 and WCU21 and a common data line control circuit DSW, and the common data line control circuit DSW has the same configuration as that shown in FIG. Each of the write circuits WCU20 and WCU21 is configured using the write circuit WCU1 shown in FIG. 1 and NMOS transistors N401 and N402. In one write circuit WCU20, the sources of the transistors N401 and N402 are connected to the output terminal of the write circuit WCU1, and the drains are connected to the common data lines DLE and DLO, respectively. In addition, the read control signal REB is input to each gate. In the other write circuit WCU21, the drains of the transistors N401 and N402 are connected to the common data lines DRE and DRO, respectively.

  In such a configuration, in the case of a read operation, the common data lines DLE, DLO, and DLO are driven by driving the read control signal REB at the power supply voltage VDD to the ground potential VSS and turning off the transistors N401 and N402. Disconnect DRE and DRO from the corresponding output terminals of write circuit WCU1. In a standby mode or a write operation, the common data lines DLE, DLO, DRE, and DRO are driven by holding the read control signal REB at the power supply voltage VDD and turning on the transistors N401 and N402, respectively.

With the configuration and operation as described above, the common data lines DLE, D
The corresponding write circuit WCU1 is disconnected from the LO, DRE, and DRO, respectively, and the connection of the common data lines DLE, DLO, DRE, and DRO can be controlled using the common data line control circuit DSW.

  The present example will be summarized below. First, four common data lines DLE, DLO, DRE, and DRO formed with the same wiring length and wiring width are arranged in parallel to the word line pair. Also, the data lines in the memory cell arrays MCA10 and MCA11 and the data lines in the dummy cell arrays DCA10 and DCA11 are divided into even-numbered and odd-numbered groups, and the switches SRW in the corresponding multiplexers MUXU20, MUXU21, MUXUD0, and MUXUD1 Connected regularly to the line. With such a configuration, the number of switches SRW connected to each common data line can be the same number (here, three). Furthermore, the number of switches SRW connected to the common data lines DLE, DLO, DRE, DRO can be reduced as compared with the third embodiment. Second, in the case of a read operation, since one data line or dummy data line is connected to each common data line, the two memory cells MCL and MCH constituting the activated memory cell MC and dummy cell DC are used. The impedance when viewing the corresponding common data line can be made equal. Third, the mirror ratios of the current mirror circuits CM10 and CM11 in the read circuits RDC40 and RDC41 are set to 1: 1, respectively, and further, the two current paths in the bias circuit BC4 are configured as targets, so that the common data lines DLE, DLO, The impedance when the corresponding current mirror circuit is viewed from DRE and DRO can be made equal. As described above, the load on each current path in the read operation can be more balanced than in the third embodiment, and a stable read operation can be realized.

  Up to this point, the memory cell arrays MCA10 and MCA11 having an 8 × 4 bit configuration and the dummy cell arrays DCA10 and DCA11 having an 8 × 1 bit configuration have been described as examples. However, the array configuration is not limited to this. For example, in the fourth embodiment as well as the examples described in the first embodiment, the second embodiment, and the third embodiment, a memory in which several hundreds of bits of memory cells are arranged for each word line pair and each data line. With the cell array configuration, the occupation ratio of the memory cell array with respect to the entire chip can be increased.

  In the embodiments so far, the configuration and operation for generating a reference signal by arranging dummy cells DC for each of a plurality of word line pairs have been described. When a defect occurs in the dummy cell DC having such a configuration, the memory cell MC on the word line pair to which the defective dummy cell DC is connected cannot be read, which may reduce the yield. In this embodiment, in order to solve this problem, a relief circuit is introduced in the memory block shown in FIG. 17 of the third embodiment.

  22 and 23 are main part block diagrams of the memory block in this embodiment. In FIG. 22, redundant cell arrays RCA10 and RDCA10 are arranged between the memory cell array MCA10 and the dummy cell array DCA10. Further, multiplexers MUXU30 and MUXL30 are arranged at both ends of the redundant cell array RCA10, and multiplexers MUXU40 and MUXL40 are arranged at both ends of the redundant cell array RDCA10. In FIG. 23, redundant cell arrays RCA11 and RDCA11 are arranged between the memory cell array MCA11 and the dummy cell array DCA11. Further, multiplexers MUXU31 and MUXL31 are arranged at both ends of the redundant cell array RCA11, and multiplexers MUXU41 and MUXL41 are arranged at both ends of the redundant cell array RDCA11. The feature of this embodiment having such a configuration is that, first, defective memory cells generated on the memory cell arrays MCA10 and MCA11 are respectively replaced with redundant memory cells on the redundant cell arrays RCA10 and RCA11. Second, defective memory cells generated on the dummy cell arrays DCA10 and DCA11 are respectively replaced with redundant memory cells on the redundant cell arrays RDCA10 and RDCA11. Hereinafter, for simplicity, a relief circuit for the memory cell array MCA10 and the dummy cell array DCA10 will be described.

  FIG. 24 shows a circuit configuration example of the memory cell array MCA10 and dummy cell array DCA10, redundant cell arrays RCA10 and RDCA10, multiplexers MUXU20, MUXL20, MUXU30, MUXL30, MUXU40, MUXL40, MUXUD0, and MUXLD0 shown in FIG. FIG. 39 shows the column address signal YMX input to each multiplexer MUX. Below, each circuit structure is demonstrated according to FIG. 24 and FIG. Similarly to FIG. 17, the memory cell array MCA10 has an 8 × 4 bit configuration, and memory cells MC are arranged at the intersections of eight word line pairs and data lines Dj (j = 0,..., 3). The dummy cell array DCA10 has an 8 × 1 bit configuration, and dummy cells DC are respectively arranged at the intersections of eight word line pairs and dummy data lines D100 and D101.

  On the other hand, the redundant cell array RCA10 is composed of 8 × 2 bit memory cells MC, and these memory cells MC are respectively arranged at the intersections of the eight word line pairs and the redundant data lines RD00 and RD01. Further, the redundant cell array RDCA10 is composed of 8 × 2 bit memory cells MC, and these memory cells MC are respectively arranged at the intersections of eight word line pairs and redundant dummy data lines RD100 and RD101.

  The multiplexer MUXU20 includes four NMOS transistors N11j (j = 0,..., 3). The data line Dj (j = 0,..., 3) is connected to the source of the transistor N11j, the common data line DL is connected to the drain, and the column address signal YMTj (j = 0,..., 3) as shown in FIG. . The multiplexer MUXL20 includes four NMOS transistors N13j (j = 0,..., 3) and four NMOS transistors N14j (j = 0,..., 3). A ground potential VSS is connected to the source of the transistor N13j, a data line Dj (j = 0,..., 3) is connected to the drain, and a column address signal YMBj (j = 0,..., 3) as shown in FIG. Further, the common node WCOM0 is written to the source of the transistor N14j, the data line Dj (j = 0,..., 3) is connected to the drain, and the column address signal YMWj (j = 0,..., 3) as shown in FIG. Connecting.

  The multiplexer MUXUD0 is composed of two NMOS transistors N120 and N121. Transistors N120 and N121 have their sources connected to dummy data lines D100 and D101, their drains connected to a common data line DL, and their gates connected to column address signals YMDT00 and YMDT01 as shown in FIG. The multiplexer MUXLD0 is composed of four NMOS transistors N150, N151, N190, and N191. NMOS transistors N150 and N151 have their sources connected to the ground potential VSS, their drains connected to dummy data lines D100 and D101, and their gates connected to column address signals YMDB00 and YMDB01 as shown in FIG. Further, the ground potential VSS is connected to the source of the transistor N190, the dummy data line D100 is connected to the drain, and the column address signal YMDW00 as shown in FIG. 39 is connected to the gate. Further, the power source voltage VDD is connected to the source of the transistor N191, the dummy data line D101 is connected to the drain, and the column address signal YMDW01 as shown in FIG. 39 is connected to the gate.

  The multiplexer MUXU30 is composed of two NMOS transistors N340 and N341. The redundant data lines RD00 and RD01 are connected to the sources of the transistors N340 and N341, the common data line DL is connected to the drain, and the redundant column address signals RYMT00 and RYMT01 as shown in FIG. The multiplexer MUXL30 includes four NMOS transistors N350, N351, N360, and N361. The ground potential VSS is connected to the sources of the transistors N350 and N351, the redundant data lines RD00 and RD01 are connected to the drain, and the redundant column address signals RYMB00 and RYMB01 as shown in FIG. Further, the write common node WCOM0 is connected to the sources of the transistors N360 and N361, the redundant data lines RD00 and RD01 are connected to the drain, and the redundant column address signals RYMW00 and RYMW01 as shown in FIG. Here, each of the redundant column address signals RYMT00 and RYMT01, RYMB00 and RYMB01, RYMW00 and RYMW01 are signals corresponding to the column address signals YMTj, YMBj, YMWj, and are stored in a normal address storage circuit as will be described later. Driven according to redundant information.

  The multiplexer MUXU40 is composed of two NMOS transistors N420 and N421. The redundant dummy data lines RD100 and RD101 are connected to the sources of the transistors N420 and N421, the common data line DL is connected to the drain, and the redundant column address signals RYMDT00 and RYMDT01 as shown in FIG. The multiplexer MUXL40 includes four NMOS transistors N430, N431, N440, and N441. The ground potential VSS is connected to the sources of the transistors N430 and N431, the redundant dummy data lines RD100 and RD101 are connected to the drains, and the redundant column address signals RYMDB00 and RYMDB01 as shown in FIG. Further, the ground potential VSS is connected to the source of the transistor N440, the redundant dummy data line RD100 is connected to the drain, and the redundant column address signal RYMDW00 as shown in FIG. 39 is connected to the gate. Further, the power supply voltage VDD is connected to the source of the transistor N441, the redundant dummy data line RD101 is connected to the drain, and the redundant column address signal RYMDW01 as shown in FIG. 39 is connected to the gate. Here, each of the redundant column address signals RYMDT00, RYMDT01, RYMDB00, RYMDB01, RYMDW00, RYMDW01 is a signal corresponding to the column address signals YMDT00, YMDT01, YMDB00, YMDB01, YMDW00, YMDW01, and a dummy address as shown later Driven according to the redundant information stored in the storage circuit. As shown in FIG. 39, the column address signals input to the multiplexers MUXUD0 and MUXLD0 are separated in correspondence with the dummy data lines D100 and D101, and the redundant column address signals input to the multiplexers MUXU40 and MUXL40 By separating the dummy data lines corresponding to the dummy data lines D100 and D101, the dummy data lines are replaced one by one.

  FIG. 25 shows, as an example, when data lines D2 and D3 in the memory cell array MCA10 and memory cells indicated by crosses on the dummy data lines D100 and D101 in the dummy cell array DCA10 are defective. Is a conceptual diagram in which redundant data lines RD00 and RD01 and dummy data lines D100 and D101 in the redundant cell array RCA10 are replaced with redundant dummy data lines RD100 and RD101 in the redundant cell array RDCA10, respectively. When writing data to the memory cells MC on one of the redundant data lines RD00 and RD01, data is written by controlling the multiplexers MUXU30 and MUXL30 shown in FIG. 24 and selecting one redundant data line one by one. When initializing the memory cells MC on the other redundant dummy data lines RD100 and RD101, the multiplexers MUXU40 and MUXL40 shown in FIG. 24 are respectively controlled so that the redundant dummy data lines are connected between the power supply voltage VDD and the ground potential VSS. By forming a current path from RD101 via common data line DL and redundant dummy data line RD100, complementary storage information is written in the same manner as dummy cell DC to form a dummy cell.

  As another example, FIG. 26 shows that when a defect occurs in the data line D2 in the memory cell array MCA10 and the memory cell indicated by the cross on the dummy data line D101 in the dummy cell array DCA10, the data line D2 is connected to the redundant cell array RCA10. A conceptual diagram is shown in which the redundant data line RD00 and the dummy data line D101 are replaced with the redundant dummy data line RD101 in the redundant cell array RDCA10. When initializing the memory cell MC on the redundant dummy data line RD101, the multiplexers MUXUD0, MUXLD0 and MUXU40, MUXL40 shown in FIG. By forming a current path from the line RD101 via the common data line DL and the dummy data line D100, complementary storage information is written to the memory cells on the dummy data line D100 and the redundant dummy data line RD101. Therefore, a dummy cell is formed in which the memory cell MCL on the dummy data line D100 and the memory cell MC on the redundant dummy data line RD101 are paired.

  Finally, this example is summarized. First, when a defect occurs in the memory cell MCL or MCH in the dummy cell DC, the dummy data line D100 to which the defective memory cell MCL is connected or the dummy data line D101 to which the defective memory cell MCH is connected is designated as redundant dummy data. A column remedy scheme was provided to replace line RD100 or RD101. As a result, a reference signal can be generated for the memory cell MC on the same word line pair as the defective dummy cell DC. Second, there is provided a column relief method in which when a defect occurs in the memory cell MC, the data line D connected to the defective memory cell MC is replaced with the redundant data line RD00 or RD01. As described above, a memory block having a higher yield than that of the third embodiment can be realized by the two column relief methods.

  Up to this point, an example in which redundant cell arrays RCA10, RCA11, RDCA10 and RDCA11 of 8 × 2 bits are introduced into the memory cell arrays MCA10 and MCA11 of 8 × 4 bits and the dummy cell arrays DCA10 and DCA11 of 8 × 1 bits is described. It was. However, the array configuration is not limited to this. For example, similarly to the example described in the third embodiment, it is possible to adopt a memory cell array configuration in which several pairs of word lines and several hundred bits of memory cells are arranged for each data line. Thereby, a large number of memory cells MC can share the read circuit RDC2 and the write circuits WCU10, WCL10, WCU11, and WCL11. Therefore, it is possible to effectively suppress the addition of the chip area due to the redundant cell array and increase the occupation ratio of the memory cell array with respect to the entire chip.

  In addition, when the column repair method according to the present embodiment is introduced into the memory cell block having an expanded array configuration, it is desirable that the number of redundant data lines is set in accordance with the number of defects occurring in the memory cell array. For example, in the currently widely used DRAM, the ratio of the redundant data line to the data line is about 1 to 2%, and it is desirable that the ratio is the same in the MRAM. For this purpose, the size of the memory cell array must be increased. As described above, the use of the reference signal generation method of the present invention is preferable because a high S / N ratio read operation can be realized.

  Further, the column relief method described so far can be applied to the memory block shown in FIG. For example, redundant cell arrays RCA10 and RDCA10 are arranged between the memory cell array MCA10 and the dummy cell array DCA10, the redundant data line RD00 and the redundant dummy data line RD100 are the common data line DLE, the redundant data line RD01 is the common data line DLO, and the redundant dummy A corresponding switch SRW in the multiplexer is formed so as to connect the data line RD101 to the common data line DRE. With such a configuration, a column remedy system that replaces defects on the memory cell array MCA10 and the dummy cell array DCA10 with the redundant cell arrays RCA10 and RDCA10, respectively, is realized, and a large-capacity MRAM with high yield and high integration can be realized.

  In the fifth embodiment, the column repair method for forming the redundant cell arrays RCA10 and RDCA10 corresponding to the memory cell array MCA10 and the dummy cell array DCA10 has been described. In this method, although the relief capability is high, the ratio of the redundant cell arrays RCA10 and RDCA10 to the memory cell array MCA10 and the dummy cell array DCA10 is large, so that the chip area increases. In order to solve this problem, in this embodiment, both the defective memory cell MC generated on the memory cell array and the defective memory cells MCL and MCH generated on the dummy cell DC in the dummy cell array are replaced with the same redundant cell array. The relief circuit will be described.

  FIG. 27 is a principal block diagram of the memory block in the present embodiment. Redundant cell array RCA10 is arranged between one memory cell array MCA10 and dummy cell array DCA10, and multiplexers MUXU30 and MUXL30 are arranged at both ends of redundant cell array RCA10. A redundant cell array RCA11 is arranged between the other memory cell array MCA11 and the dummy cell array DCA11, and multiplexers MUXU31 and MUXL31 are arranged at both ends of the redundant cell array RCA11. Therefore, the redundant cell arrays RDCA10 and RDCA11 and the multiplexers MUXU40, MUXL40, MUXU41, and MUXL41 are removed as compared with FIGS. 22 and 23 of the fifth embodiment. Hereinafter, for simplicity, a relief circuit for the memory cell array MCA10 and the dummy cell array DCA10 will be described.

  FIG. 28 shows a circuit configuration example of the memory cell array MCA10 and dummy cell array DCA10, redundant cell array RCA10, multiplexers MUXU20, MUXL20, MUXU30, MUXL30, MUXUD0, and MUXLD0 shown in FIG. Each circuit block has the same circuit configuration as that shown in FIG. 24, and the column address signal name input to each multiplexer is also the same as the signal name shown in FIG. Next, the operation concept of defect relief with such a configuration will be described.

  FIG. 29 shows, as an example, a conceptual diagram for replacing dummy data lines D100 and D101 with redundant data lines RD00 and RD01, respectively, when a defect occurs in a memory cell indicated by a cross on dummy data lines D100 and D101. Show. In this case, the redundant memory cell array RCA10 is initialized as follows. First, the multiplexers MUXU30 and MUXL30 shown in FIG. 27 are controlled to select the redundant data line RD00. Next, data corresponding to the stored information “1” is input from the outside of the chip, and the write circuits WCU10 and WCL10 shown in FIG. 27 are driven to generate a current in the direction of the arrow ADL on the redundant data line RD00. Then, the memory information “1” is written into the memory cell MC. Furthermore, the redundant data line RD01 is selected, data corresponding to the stored information '0' is input from the outside of the chip, and a current in the direction of the arrow ADH is generated on the redundant data line RD01, thereby storing the stored information in the memory cell MC. Write '0'. Thus, a dummy cell is formed in which the memory cells MC on the redundant data lines RD00 and RD01 are paired.

  As another example, FIG. 30 shows that when a memory cell indicated by a cross between the data line D2 and the dummy data line D101 has a defect, the data line D2 and the dummy data line D101 are respectively connected to the redundant data lines RD00 and RD01. The conceptual diagram to replace is shown. In this case, after initialization of the dummy cell array DCA10, the storage information '0' is written into the memory cell MC on the redundant data line RD01 as described with reference to FIG. A dummy cell is formed by pairing the memory cell MC on the data line RD01. Next, a mechanism for generating a column address signal for controlling the column repair method according to this embodiment will be described.

  FIG. 31 shows a principal block diagram of the column address decoder according to this embodiment. However, here, for the sake of simplicity, a normal column address decoder NYMD corresponding to a portion for controlling the memory cell array MCA10 and dummy cell array DCA10 shown in FIG. 27, and a portion for replacing the memory cell array MCA10 and dummy cell array DCA10 with the redundant cell array RCA10. A redundant column address decoder RYMD corresponding to is shown. A feature of the column address decoder having such a configuration is that, firstly, redundant information for the data line and the dummy data line is stored. Secondly, the redundant column address signal is activated according to the redundant information of both the data line and the dummy data line. Thirdly, the column address signal corresponding to the replacement source data line or dummy data line is deactivated according to the redundancy information. The column address decoder will be described below while paying attention to these features.

  The normal column address decoder NYMD includes a column address decoder YMDEC and a normal column address signal driver array NADA. The column address decoder YMDEC generates a plurality (here, five) of column address enable signals according to the input column predecode address CYM, and outputs it to the normal column address signal driver array NADA. The normal column address signal driver array NADA includes a dummy column address signal driver DDRVm (m = 0, 1) and a normal column address signal driver NDRVk (k = 0,..., 3). The dummy column address signal driver DDRVm controls the column data signals YMDT0m, YMDB0m, YMDW0m (m = 0, 1) for controlling the connection state of the dummy data lines according to the corresponding column address enable signal YMD and the dummy data line write signal TDWEB. Are output respectively. Here, the dummy data line write signal TDWEB is a signal generated by a test mode control circuit, which will be described later, and is driven to the ground potential VSS when the dummy cell array DCA10 is initialized. YMDW0m can be driven to the power supply voltage VDD. Further, the normal column address signal driver NDRVk includes column address signals YMTk, YMBk, which control the connection state of the data lines according to the corresponding column address enable signal YMk (k = 0,..., 3) and the write control signal WEB. YMWk (k = 0, ..., 3) is output. Here, the write control signal WEB is driven to the ground potential VSS during the write operation, thereby enabling the desired column address signal YMWk to be driven to the power supply voltage VDD.

  The redundant column address decoder RYMD includes a redundant column address detection circuit RDTC and a redundant column address signal driver array RADA. The redundant column address detection circuit RDTC further includes a plurality of (here, two depending on the number of redundant data lines) redundant column address storage circuits RMRYm (m = 0, 1), NOR circuits NR10, NR11, NR12, inverters It consists of circuits IV10 and IV11. The redundant column address signal driver array RADA is configured with redundant column address signal drivers RDRVm (m = 0, 1).

  The redundancy column address storage circuit RMRYm receives the precharge signal PREB, the corresponding normal redundancy test signal TNRBm (m = 0, 1), the dummy redundancy test signal TDRBm (m = 0, 1), and the column predecode address CYM. Thus, a normal redundancy enable signal NREm (m = 0, 1) and a dummy redundancy enable signal DREm (m = 0, 1) are generated.

  The NOR circuits NR10 and NR11 generate a redundant column address enable signal RYMBm (m = 0, 1) in response to the corresponding normal redundant enable signal NREm and dummy redundant enable signal DREm, respectively, to the corresponding redundant column address signal driver RDRVm. Output. Here, the normal redundancy enable signal NREm or dummy redundancy enable signal DREm of the power supply voltage VDD is input to the corresponding NOR circuit NR1m (m = 0, 1), and the redundancy column address enable signal RYMBm is driven to the ground potential VSS. When the redundant column address signal driver RDRVm is activated, the corresponding redundant data line is selected.

  The NOR circuit NR12 further generates a normal redundancy enable signal NREB according to the input normal redundancy enable signal NREm and outputs it to each normal column address signal driver NDRVk. When the data line is replaced with a redundant data line, the normal redundancy enable signal NREB is driven to the ground potential VSS by inputting the normal redundancy enable signal NRE0 or NRE1 of the power supply voltage VDD, and the normal column address signal driver NDRVk. Is inactivated.

  The inverter circuit IV1m (m = 0, 1) inverts the corresponding dummy redundancy enable signal DREm to generate the dummy redundancy enable signal DREBm (m = 0, 1), respectively, to the corresponding dummy column address signal driver DDRVm Output each. Here, when replacing the dummy data line with a redundant data line, the dummy redundancy enable signal DREBm is driven to the ground potential VSS when the dummy redundancy enable signal DREm of the power supply voltage VDD is input, and the corresponding dummy column address signal driver. Deactivate DDRVm. Next, a circuit configuration example of each circuit block shown in FIG. 31 will be described.

  FIG. 32 shows a configuration example of the redundant column address storage circuit RMRYm. The redundant column address storage circuit RMRYm includes a normal address storage circuit NMRY and a dummy address storage circuit DMRY. One regular address storage circuit NMRY is composed of a PMOS transistor P451, an NMOS transistor N471, and a plurality (six in this case) of redundant information storage circuits F. The transistor P451 is a transistor for precharging the normal redundancy enable signal NREm to the power supply voltage VDD. A precharge signal PREB is input to the gate of the transistor P451, and the transistor P451 and the transistor N471 are connected in series. Further, the normal redundancy test signal TNRBm is input to the gate of the transistor N471, and a plurality of redundant information storage circuits F are connected in parallel between the node Am which is the source terminal of the transistor N471 and the ground potential VSS. Further, the signal CYMTn (n = 0, 1, 2) constituting the column predecode address CYM and the signal CYMBn (n = 0, 1) obtained by inverting these signals by the inverter circuit IV2n (n = 0, 1, 2) , 2) are respectively input to the six redundant information storage circuits F. Here, the precharge signal PREB is one of the array control buses ABS. The normal redundancy test signal TNRBm is a signal generated by a test mode control circuit described later.

  In such a configuration, the column predecode address CYM is input after the precharge enable signal PREB having the ground potential VSS is driven to the power supply voltage VDD. Here, when the normal redundancy enable signal NREm is held at the power supply voltage VDD at the precharge level, the data line corresponding to the column predecode address CYM is replaced with the redundancy data line.

  The other dummy address storage circuit DMRY includes a PMOS transistor P461, an NMOS transistor N461, and a plurality (two in this case) of redundant information storage circuits F. The transistor P461 is a transistor for precharging the dummy redundancy enable signal DREm to the power supply voltage VDD. A precharge signal PREB is input to the gate of the transistor P461, and the transistor P461 and the transistor N461 are connected in series. A dummy redundancy test signal TDRBm is input to the gate of the transistor N461, and two redundant information storage circuits F are connected in parallel between the node Bm, which is the source terminal of the transistor N461, and the ground potential VSS. Further, for example, the most significant bit complementary signals (here, CYMT2 and CYMB2) constituting the column predecode address CYM are input to the two redundant information storage circuits F, respectively. Here, the dummy redundancy test signal TDRBm is a signal generated by a test mode control circuit described later.

  In such a configuration, the column predecode address CYM is input after the precharge enable signal PREB having the ground potential VSS is driven to the power supply voltage VDD. Here, when the dummy redundancy enable signal DREm is held at the power supply voltage VDD at the precharge level, the dummy data line corresponding to the column predecode address CYM is replaced with the redundancy data line.

  FIG. 33 shows a configuration of the redundant information storage circuit F in the normal address storage circuit NMRY as an example. The redundant information storage circuit F is a known circuit in which an NMOS transistor N460 and a fuse FY are connected in series. Address signal ADD (here, signals CYMTn and CYMBn (n = 0, 1, 2) constituting column predecode address CYM) are input to the gate of transistor N460, and fuse FY is formed of a wiring layer such as polysilicon. .

  FIG. 34 shows the test mode control circuit TCTL. This circuit receives the control signal CM, the row address BX, and the column address BY shown in FIG. 13, generates the test mode bus TBS according to them, and outputs it to each circuit block. The normal redundancy test signal TNRBm, dummy redundancy test signal TDRBm, and dummy data line write signal TDWEB described above are one of a plurality of control signals constituting the test mode bus TBS, and correspond to defect detection and initialization operations. Driven to the ground potential VSS.

  Next, the control and operation of the redundant column address storage circuit RMRYm will be described. Here, as an example, assuming that the data line on the memory cell array MCA10 shown in FIG. 30 is replaced with the redundant data line RD00, the operation of the redundant column address storage circuit RMRY0 will be described with reference to FIG. First, in order to detect a defect, the normal redundancy test signal TNRB0 at the power supply voltage VDD is driven to the ground potential VSS, the transistor N471 in the normal address storage circuit NMRY is turned off, and the corresponding normal redundancy enable signal NRE0 is set. By holding the power supply voltage VDD at the precharge level, the data line connected to the malfunctioning memory cell MC is temporarily replaced with the redundant data line RD00. Next, after confirming that the memory cell MC on the redundant data line RD00 operates correctly, the fuse FY corresponding to the corresponding column predecode address CYM is cut using a laser cutting device to store the normal address. Write redundant information to the circuit NMRY. On the other hand, in the normal read / write operation, the normal redundancy test signal TNRB0 is held at the power supply voltage VDD, thereby turning on the transistor N471 in the normal address storage circuit NMRY. Here, when the data line connected to the malfunctioning memory cell MC is selected and the corresponding column predecode address CYM is input, the current path in the normal address storage circuit NMRY is blocked by the above-described fuse FY. Therefore, the normal redundant enable signal NRE0 is held at the power supply voltage VDD at the precharge level, whereby the selected data line is replaced with the redundant data line RD00.

  Similarly, when the dummy data line is replaced, the dummy address storage circuit DMRY shown in FIG. 32 is detected after detecting a defect in the memory cells MCL and MCH connected to the dummy data line using the dummy redundancy test signal TDRBm. Write redundant information to.

  Hereinafter, the circuit configuration of each column address signal driver will be described. FIG. 35 shows a configuration example of the normal column address signal driver NDRVk. The normal column address signal driver NDRVk includes a NAND circuit ND10, a NOR circuit NR20, and an inverter circuit IV30. In ND10, a column address enable signal YMk is input to one terminal, a normal redundancy enable signal NREB is input to the other terminal, and an output terminal is connected to the column address signal YMBk. In NR20, the column address signal YMBk is input to one terminal, the write control signal WEB is input to the other terminal, and the output terminal is connected to the column address signal YMWk. Further, the column address signal YMBk is inverted at IV30 to obtain the column address signal YMTk.

  FIG. 36 shows a configuration example of the dummy column address signal driver DDRVm, which includes a NAND circuit ND10, a NOR circuit NR20, and an inverter circuit IV30 in the same manner as the normal column address signal driver NDRVk shown in FIG. In ND10, a column address enable signal YMD is input to one terminal, a dummy redundancy enable signal DREBm is input to the other terminal, and an output terminal is connected to the column address signal YMDB0m. In NR20, the column address signal YMDB0m is input to one terminal, the dummy data line write signal TDWEB is input to the other terminal, and the output terminal is connected to the column address signal YMDW0m. Further, the column address signal YMDB0m is inverted at IV30 to obtain the column address signal YMDT0m.

  FIG. 37 shows a configuration example of the redundant column address signal driver RDRVm, which includes a NOR circuit NR20 and inverter circuits IV30, IV40, and VI41. The figure differs from the column address signal driver shown in FIGS. 35 and 36 in that the NAND circuit ND10 is replaced with IV40 and IV41. The redundant column address signal RYMB0m is a signal obtained by buffering the redundant column address enable signal RYMBm with IV40 and IV41 connected in series, and a signal obtained by further inverting the redundant column address signal RYMB0m at IV30 is the redundant column address signal RYMT0m. In NR20, the redundant column address signal RYMB0m is input to one terminal, the write control signal WEB is input to the other terminal, and the output terminal is connected to the redundant column address signal RYMW0m.

  The operation of each column address signal driver described above will be described below. First, when a redundant data line is used, the redundant column address enable signal RYMBm is held at the ground potential VSS, thereby activating the redundant column address signal driver RDRVm. On the other hand, the normal redundancy enable signal NREB or dummy redundancy enable signal DREBm is held at the ground potential VSS according to the replacement source of the redundant data line, and the NAND circuit ND10 shown in FIG. 35 or FIG. 36 is deactivated. The normal column address signal driver NDRVk or the dummy column address signal driver DDRVm is deactivated.

  Next, when the redundant data line is not used, the redundant column address signal driver RDRVm is deactivated by driving the redundant column address enable signal RYMBm at the ground potential VSS to the power supply voltage VDD. On the other hand, in response to the selection of the data line and the dummy data line, normal redundancy enable signal NREB and dummy redundancy enable signal DREBm, which are at ground potential VSS, are driven to power supply voltage VDD, as shown in FIGS. By activating the NAND circuit ND10 shown, the normal column address signal driver NDRVk and the dummy column address signal driver DDRVm are activated.

Here, the NOR circuit NR20 shown in FIG. 35 and FIG. 37 is activated when the write control signal WEB at the power supply voltage VDD is driven to the ground potential VSS in the write operation, and the selected data is selected. The column address signal YMWk or the redundant column address signal RYMW0m is driven according to the line. 36 is activated when the dummy data line write signal TDWEB at the power supply voltage VDD is driven to the ground potential VSS in the initialization operation, and the column address enable signal YMD is activated. In response to this, the column address signal YMDW0m is driven.
FIG. 37 shows an example in which the redundant column address enable signal RYMm is buffered by IV40 and IV41 connected in series. However, the NOR circuits NR10 and NR11 in the redundant column address detection circuit RDTC shown in FIG. If larger, IV40 and IV41 may be removed, and the redundant column address enable signal RYMm may be used as it is as the redundant column address signal RYMB0m. In this case, the layout area of the redundant column address signal driver RDRVm can be reduced.

  From the above, the effects of the column repair method using the memory block shown in FIG. 27 and the column address decoder shown in FIG. 31 are summarized. First, as shown in FIG. 28 as an example, the memory cell MCA in the memory cell array MCA10 and the memory cells MCL and MCH in the dummy cell DC on the dummy cell array DCA10 have the same configuration. Each can share a redundant cell array RCA10 composed of memory cells MC as a replacement destination of defective memory cells. Further, in the redundant column address storage circuit RMRYm shown in FIG. 32, the redundant information for the data line and the dummy data line is stored using the normal address storage circuit NMRY and the dummy address storage circuit DMRY. Further, in the redundant column address detection circuit RDTC shown in FIG. 31, the normal redundancy enable signal NREm and the dummy redundancy enable signal DREm, which are the output signals of the normal address storage circuit NMRY and the dummy address storage circuit DMRY, are converted into corresponding NOR circuits NR10, By inputting each to NR11 and generating the redundant column enable signal RYMBm, it is possible to replace both the data line and the dummy data line with the same redundant data line. From the above, it is possible to realize a column relief system in which the proportion of redundant cell arrays is reduced as compared with the memory blocks shown in FIGS. 22 and 23 of the fifth embodiment, thereby realizing a highly integrated, highly reliable and large capacity MRAM. can do.

  Second, as shown in FIG. 32, by using the normal redundancy test signal TNRBm and the dummy redundancy test signal TDRBm, the data line or the dummy data line is temporarily replaced with the redundancy data line, so that the effect is obtained in advance. Can be confirmed. That is, a defect in the memory cell MC and the dummy cell DC can be detected. Here, the normal redundancy test signal TNRBm and the dummy redundancy test signal TDRBm can be generated by inputting a command or an address signal from the outside to the test mode control circuit shown in FIG. 34, so that the control is simple. Therefore, if defect detection and redundant information storage operation are performed at the time of chip testing, it can be performed at a low cost in a short time.

  So far, an example in which redundant cell arrays RCA10 and RCA11 having an 8 × 2 bit configuration are introduced into the memory cell arrays MCA10 and MCA11 having an 8 × 4 bit configuration and dummy cell arrays DCA10 and DCA11 having an 8 × 1 bit configuration has been described. However, the array configuration is not limited to this. For example, similarly to the example described in the fifth embodiment, a memory cell array configuration in which several hundreds of bits of memory cells are arranged for each pair of word lines and one data line is provided. Occupancy can be increased.

  Further, when applying column relief, the yield is improved while maintaining the occupation ratio of the memory cell array with respect to the entire chip by forming redundant data lines of several percent with respect to the number of data lines as in the case of the fifth embodiment. Can be improved. Further, when the number of defects is small, the data line or the dummy data line can be replaced by the number of redundant data lines. Therefore, the defects can be efficiently relieved with a smaller redundant cell array than in the fifth embodiment. be able to.

  Further, the column relief method described so far can be applied to the memory block shown in FIG. For example, the redundant cell array RCA10 is arranged between the memory cell array MCA10 and the dummy cell array DCA10, and the redundant data line RD00 is connected to the common data line DLE and the redundant data line RD01 is connected to the common data line DLO. A switch SRW is formed. In contrast, a redundant cell array is arranged between the memory cell array MCA10 and the dummy cell array DCA10, and one redundant data line is connected to the common data line DRE and the other redundant data line is connected to the common data line DRO. And a corresponding switch SRW in the multiplexer. With such a configuration, a column relief system is realized in which defects on the memory cell array MCA10 and the dummy cell array DCA10 are replaced with the redundant cell array RCA10 or the other redundant cell array, respectively, and a large-capacity MRAM with high yield and high integration is realized. be able to.

  In the above, according to various embodiments, the MRAM having the memory cell composed of one MTJ element and one transistor has been described. However, the configuration of the memory cell is not limited to this. For example, the present invention can be applied to a memory cell using a diode as an element having a rectifying action, which is disclosed in US Pat. No. 5,793,697 (US patent No. 5,793,697). In this case, one word line can be reduced, and the number of steps for forming a memory cell can be reduced. Further, the area of the memory cell can be reduced by reducing the number of terminals of the memory cell from three to two, and a high-capacity MRAM with a high degree of integration can be realized. However, in the read operation, since selection and non-selection are controlled by a diode, the applied voltage is limited and is influenced by the nonlinear characteristics of the diode. Therefore, it is composed of one MTJ element and one diode. In order to use a memory cell, the reference signal generation method is more important than the case of using a memory cell composed of one MTJ element and one transistor, and the method of the present invention is considered effective.

  Finally, an application example of the MRAM according to the present invention will be described. FIG. 38 shows a block diagram of the main part of a cordless telephone system incorporating an MRAM according to the present invention as an example. The antenna ATN, the analog front end block AFE, the analog-digital modulation circuits ADC1, ADC2, and the digital-analog modulation circuit. It consists of DAC1, DAC2, baseband block BBD, speaker SPK, liquid crystal display LCD, microphone MIK, and input key KEY. Although not shown in the figure, the analog front-end block AFE consists of an antenna switch, bandpass filter, various amplifiers, power amplifier, phase locked loop (PLL), voltage controlled oscillator (VCO), quadrature demodulator, quadrature It is a known circuit block that transmits and receives radio waves composed of a modulator or the like. The baseband block BBD includes a signal processing circuit SGC, a central processing unit CPU, and an MRAM according to the present invention.

  Next, the operation of the mobile phone according to FIG. 38 will be described. When receiving an image including voice and text information, the radio wave input from the antenna is input to the analog-digital modulation circuit ADC1 via the analog front end block AFE, and is subjected to waveform equalization and analog-digital conversion. The output signal of ADC1 is input to the signal processing circuit SGC in the baseband block BBD and subjected to sound and image processing. The sound signal is transmitted from the digital-analog conversion circuit DAC2 to the speaker, and the image signal is transmitted to the liquid crystal display. . When an audio signal is transmitted, the signal input from the microphone is input to the signal processing circuit SGC via the analog-digital conversion circuit ADC2, and audio processing is performed. The SGC output is transmitted from the digital-analog conversion circuit DAC1 to the antenna via the analog front end block AFD. Further, when transmitting character information, a signal input from the input key KEY is transmitted from the baseband block BBD and the digital-analog conversion circuit DAC1 to the antenna via the analog front end block AFD.

  In the baseband block BBD, the MRAM, the central processing unit CPU, and the signal processing circuit SGC according to the present invention are respectively connected bidirectionally. Here, the central processing unit CPU performs control in the baseband block BBD and control of peripheral blocks (not shown in the figure) according to the signal input from the input key KEY, ADC1 output, and SGC output. For example, information such as a dial number or an abbreviated number is written into the MRAM according to the present invention or read back in accordance with a signal input from the input key KEY. As another example, the signal processing circuit SGC is controlled in accordance with the input ADC1 output signal and SGC output signal, and a program necessary for signal processing is read from the MRAM according to the present invention or written in reverse. The MRAM according to the present invention is also used as a buffer for temporarily storing an image signal input from the SGC and outputting it to a liquid crystal display.

  As described above, by applying the MRAM according to the present invention to the programmable ROM that has used EPROM and flash memory, the main memory, the cache memory, and the image memory that have used SRAM, The mobile phone can be reduced in size and weight. In addition, since the MRAM according to the present invention can perform a stable read operation by using a dummy cell that holds complementary storage information, a mobile phone having excellent environmental resistance can be realized. Furthermore, since the MRAM according to the present invention is a highly integrated and highly reliable memory having a relief circuit, it is easy to increase the capacity, and a mobile phone with high information processing capability can be realized.

  Another application example of the MRAM according to the present invention is a system LSI in which a plurality of element circuits in the circuit block shown in FIG. 38 and the MRAM according to the present invention are formed on one chip. For example, by mounting a system LSI in which a baseband block BBD is formed on one chip on a mobile phone, the size and weight of this portion can be improved. Further, since the data processing speed can be improved by the system LSI, a mobile phone with high processing capability can be realized.

  Yet another application is a memory card equipped with the MRAM according to the present invention. The MRAM is a non-volatile memory as described above, and there is no limit on the number of reading and writing. Non-Patent Document 1 reports that the MRAM write time is 10 ns, which is faster than the flash memory write time. Therefore, the MRAM of the present invention can realize a high-capacity memory card that is high-speed, highly integrated, excellent in reliability and environmental resistance.

  Note that the scope of application of the present invention is not limited to MRAM, but also to memories other than MRAM, in which the resistance value of the memory cell differs depending on the stored information, and the stored information is read by detecting the current flowing through the data line. The present invention can be applied. Therefore, as an example, a phase-change memory will be described next.

  Phase change memory is, for example, Proceedings, 2000, IEE, Aerospace Conference, Big Sky Montana, pages 385 to 390 (March 18 to 25, 2000) ( Proceedings 2000 IEEE Aerospace Conference, Big Sky MT, pp. 385-390, Mar. 18-25, 2000.) As shown in FIG. 40, the memory cell PMC in the phase change memory includes a selection transistor TR, a wiring resistance RL, and a storage element CA. These elements are connected in series, the word line WLk is connected to the gate of the selection transistor TR, the data line Dj is connected to the drain, and one end of the storage element CA is grounded. FIG. 41 shows an example of a cross-sectional structure of the memory cell. The selection transistor TR is an NMOS transistor formed on a P-type silicon substrate PSUB, and the gate portion is formed of a polysilicon gate PS, a gate oxide film GOX, and an insulating film SDW. Each of the source and drain electrodes is formed of an N-type diffusion layer ND, and the electric field between the substrate and the source and drain is relaxed by reducing the impurity concentration at the boundary between the N-type diffusion layer ND and the substrate. Yes. SGI is an element isolation insulator formed by oxidizing silicon. The source electrode of the selection transistor TR and the storage element (chalcogenide alloy) CA are connected by a metal wiring contact PG1, and the storage element CA and the metal wiring layer MT1 are connected by a metal wiring contact PG2. Further, the drain electrode of the select transistor TR and the metal wiring layer MT2 are connected by a metal wiring interlayer contact PG3. Each of the metal wiring layers MT1, MT2 and the metal wiring contacts PG1, PG2, PG3 is formed of tungsten, for example. In such a configuration, the gate electrode of the selection transistor TR, that is, the polysilicon gate PS corresponds to the word line, and the metal wiring layers MT1 and MT2 correspond to the ground electrode and the data line, respectively. Further, the combined resistance by the metal wiring interlayer contacts PG1 and PG2 is shown as wiring resistance RL in FIG. The composition of the memory element CA is, for example, IEE, Transactions on Nuclear Science, Vol. 47, No. 6, pages 2528 to 2533 (December 2000) (IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 47, NO. 6, pp. 2528-2533, Dec. 2000.), a chalcogenide alloy formed of germanium, antimony and tellurium. A portion of the chalcogenide alloy changes to a low-resistance single crystal state or a high-resistance amorphous state by heat generated by the current flowing through the memory cell. Utilizing this property, the memory information is written to the memory cell by controlling the current applied to the element, and the memory information is read by detecting the current flowing through the data line in accordance with the resistance. Here, the current detected in the read operation is a binary value of one polarity. In addition, the memory element in an amorphous state has voltage dependency on its resistance value, and changes from a high resistance state to a low resistance state when a high voltage is applied. Therefore, in order not to destroy the stored information, a read operation is performed while applying a low voltage to the storage element.

  From the above operation principle, the read operation of the phase change memory is the same as that of the MRAM. Therefore, as described in the first to fourth embodiments, dummy cells each storing complementary information in two cells having the same structure as the memory cell are arranged on each word line, and a reference signal is transmitted using a current mirror circuit. It is possible to apply the generated readout scheme to a phase change memory. In this case, the reference signal can be generated with high accuracy while suppressing the influence of the characteristic variation occurring in each memory cell, so that a stable read operation of the phase change memory can be realized. Further, since the dummy cell is composed of two cells having the same structure as that of the memory cell, the column relief method using the redundant cell array as described in the fifth and sixth embodiments can be applied to the phase change memory. . By this column relief method, a large-capacity phase change memory with high yield and high integration degree can be realized.

FIG. 3 is a diagram illustrating a configuration example of a memory block using a memory cell including one MTJ element and one transistor according to the first embodiment. The figure which shows the example of the memory cell comprised by one MTJ element and one transistor. The figure which shows the example of the cross section of an MTJ element. The figure which shows the relationship between the electric current which flows into an MTJ element, and the reference signal by this invention. FIG. 3 is a diagram illustrating a configuration example of a read circuit according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a multiplexer and a write circuit according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a word driver according to the first embodiment. FIG. 3 is a diagram illustrating an example of read operation timing of the memory block according to the first embodiment. FIG. 3 is a diagram illustrating an example of write operation timing of the memory block according to the first embodiment. FIG. 6 is a diagram illustrating another configuration example of the current mirror circuit according to the first embodiment. FIG. 6 is a diagram illustrating another configuration example of the dummy write circuit according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of a memory array using the memory block according to the first embodiment. FIG. 3 is a block diagram illustrating a configuration example of a synchronous memory using the memory array according to the first embodiment. FIG. 6 is a diagram illustrating a configuration example of a memory block using a memory cell including one MTJ element and one transistor according to the second embodiment. FIG. 10 is a diagram illustrating a configuration example of a reading circuit according to a second embodiment. FIG. 10 is a diagram illustrating another configuration example of the current mirror circuit according to the second embodiment. FIG. 10 is a diagram illustrating a configuration example of a memory block using a memory cell including one MTJ element and one transistor according to the third embodiment. FIG. 10 is a diagram illustrating a configuration example of a read circuit according to a third embodiment. FIG. 10 is a diagram illustrating a configuration example of a memory block using a memory cell including one MTJ element and one transistor according to the fourth embodiment. FIG. 10 is a diagram illustrating a configuration example of a read circuit according to Embodiment 4; FIG. 10 is a diagram illustrating a configuration example of a writing circuit according to a fourth embodiment. FIG. 18 is a diagram illustrating a configuration example of a memory block using a memory cell including one MTJ element and one transistor according to the fifth embodiment (part 1); FIG. 6B is a diagram illustrating a configuration example of a memory block using a memory cell including one MTJ element and one transistor according to the fifth embodiment (part 2); FIG. 10 is a diagram illustrating a configuration example of a redundant cell array and a multiplexer according to a fifth embodiment. FIG. 12 is a conceptual diagram (part 1) illustrating a replacement example of the column repair method according to the fifth embodiment. (2) The conceptual diagram which shows the replacement example of the column relief system by Example 5. FIG. FIG. 10 is a diagram illustrating a configuration example of a main part of a memory block using a memory cell including one MTJ element and one transistor according to Embodiment 6; FIG. 10 is a diagram illustrating a configuration example of a redundant cell array and a multiplexer according to a sixth embodiment. FIG. 10 is a conceptual diagram showing a replacement example of a column relief system according to Embodiment 6 (part 1); (2) The conceptual diagram which shows the replacement example of the column relief system by Example 6. FIG. FIG. 10 is a block diagram illustrating a configuration example of a column address decoder according to a sixth embodiment. FIG. 10 is a diagram illustrating a configuration example of a redundant column address storage circuit according to a sixth embodiment. FIG. 10 is a diagram illustrating a configuration example of a redundant information storage circuit according to a sixth embodiment. FIG. 10 is a block diagram illustrating a configuration example of a test mode control circuit according to a sixth embodiment. FIG. 10 is a diagram illustrating a circuit configuration example of a regular column address signal driver according to a sixth embodiment. FIG. 10 is a diagram illustrating a circuit configuration example of a dummy column address signal driver according to a sixth embodiment. FIG. 10 is a diagram illustrating a circuit configuration example of a redundant column address signal driver according to a sixth embodiment. The figure which shows the principal part block of the mobile telephone device which mounts MRAM of this invention. 10 is a table showing column addresses input to a multiplexer according to the fifth embodiment. FIG. 10 is a diagram illustrating a circuit configuration example of a memory cell in a phase change memory according to Embodiment 7; FIG. 10 is a diagram illustrating an example of a cross section of a memory cell in a phase change memory according to Embodiment 7;

Explanation of symbols

MTJ ... MTJ element, FXL, FRL ... ferromagnetic layer, TB ... insulating film, AWW, ADL, ADH ... current direction, ID (1), ID (0), IDS (1), IDS (0), IREF , IW, IDS (W1), IDS (W0) ... Current, BLK ... Memory block, WDA ... Word driver array, WRD ... Read driver, WWD ... Write driver, MCA, MCA10, MCA11 ... Memory cell array, DCA1, DCA10, DCA11 … Dummy cell array, RCA10, RCA11, RDCA10, RDCA11… Redundant cell array, MUXU1, MUXL1, MUXU20, MUXL20, MUXU21, MUXL21, MUXU30, MUXL30, MUXU31, MUXL31, MUXU40, MUXL40, MUXU41, MUXL41, MUXUD, MUX0 , MUXUD1, MUXLD1 ... Multiplexer, WCU1, WCL1, WCU10, WCL10, WCU11, WCL11, WCU20, WCU21 ... Write circuit, RDC1, RDC2, RDC3, RDC4, RDC40, RDC41 ... Read circuit, MC, MCL, MCH ... Memory cell, DC ... dummy cell, DXB ... row decode address, XBk ... row decode signal, ABS ... array control bus, WRk ... read word line, WWk ... write word line, D, Dj (j = 0, ..., 7) ... Data line, DD0, DD1, D100, D101, D110, D111 ... Dummy data line, DS, DS0, DS1, RS, DL, DLA, DR, DRA, DLE, DLO, DRE, DRO ... Common data line, DYM ... Column decode address, YMTj (j = 0, ..., 7), YMBj (j = 0, ..., 7), YMWj (j = 0, ..., 7), YMDT, YMDB , YMDW, YMDT00, YMDT01, YMDB00, YMDB01, YMDW00, YMDW01 ... Column address signal, RYMT00, RYMT01, RYMB00, RYMB01, RYMW00, RYMW01, RYMDT00, RYMDT01, RYMDB00, RYMDW01, RYMDW00, RYMDW00, RYMDW00, RYMDW00 WCOM0, WCOM1 ... Write common node, DWU1 ... Dummy write circuit, RYS, RYSL, RYSR, WYS, WYSL, WYSR ... Column selection signal, WIT, WIB, WIT0, WIB0, WIT1, WIB1 ... Write data line, VB1 ... Bias voltage, N1, N21, N22, N31, N61, N610, N611, N62, N71, N72, N73, N81, N82, N91, N92, N101, N102, N11j (j = 0, 1, ..., 7), N120, N121, N13j (j = 0, 1, ..., 7), N14j (j = 0, 1, ..., 7), N150, N151, N161, N162, N163, N164, N181, N182, N190, N191, N241, N270, N271, N280, N281, N290, N291, N331, N332, N333, N334, N401, N402, N411, N412, N340, N341, N350, N351, N360, N361, N420, N421, N430, N431, N440, N441, N460, N461, N471 ... NMOS transistor, P21, P22, P31, P41, P42, P43, P44, P51, P52, P53, P54, P55, P56, P57, P58, P81, P82, P83, P161, P162 , P163, P181, P182, P231, P232, P233, P234, P235, P236, P241, P301, P302, P303, P304, P305, P306, P321, P322, P323, P324, P451, P461… PMOS transistor, VSS… Ground potential, VDD ... Power supply voltage, VDH ... Boost voltage, VTH ... Threshold voltage of NMOS transistor, WET, WEB ... Write control signal, EQ ... Precharge enable signal, WDT, WDB ... Internal write node, YSW1, YSW10, YSW11 , YSW2 ... Column selection circuit, PCEQ ... Precharge circuit, SA ... Sense amplifier, CM, CMD1, CM10, CM11, CMD2, CM20, CM21 ... Current mirror circuit, BC1, BC2, BC3, BC4 ... Bias circuit, SDP ... Sense Amplifier start signal, REB ... Read control signal, ROT, R OB, ROT0, ROB0, ROT1, ROB1 ... Read data line, DT, DB, DT0, DB0, DT1, DB1, SDLE, SDLO, SDRE, SDRO ... Sense data line, NDS, NRS, NDS0, NDS1, NDL, NDLA, NDR, NDRA, NDLE, NDLO, NDRE, NDRO ... Internal common data line, MAR ... Memory array, YSDEC, YMD ... Column decoder, XDEC ... Row decoder, ACTL ... Array control circuit, MI ... Main data input line, MO ... Main Data output line, CX ... row predecode address, CYM ... column predecode address, MS ... mat select signal, DXB ... row decode address, DYM ... column decode address, CLKB ... clock buffer, CB ... command buffer, CD ... command decoder , AB ... Address buffer, DIB ... Input buffer, DOB ... Output buffer, UNT1, UNT2 ... Unit, XPD ... Row predecoder, YPD ... Column predecoder, WB ... Write buffer, RB ... Read buffer, CLK ... Clock, CMD ... Koman , ADR ... External address, DQ ... External input / output data, GI ... Write data, GO ... Read data, DSW ... Common data line control circuit, CNE, CNO ... Connection control signal, RD00, RD01, RD10, RD11 ... Redundant data line RD100, RD101, RD110, RD111 ... Redundant dummy data line, NYMD ... Regular column address decoder, RYMD ... Redundant column address decoder, YMDEC ... Column address decoder, YMD, YMk (k = 0, ..., 3) ... Column address enable Signal, NADA ... Normal column address signal driver array, DDRV0, DDRV1 ... Dummy column address signal driver, NDRVk (k = 0, ..., 3) ... Regular column address signal driver, TDWEB ... Dummy data line write signal, RYMD ... Redundant column Address decoder, RDTC ... Redundant column address detection circuit, RADA ... Redundant column address signal driver array, RMRY0, RMRY1 ... Redundant column address storage circuit, ND10 ... NAND circuit NR10, NR11, NR12, NR20 ... NOR circuit, IV10, IV11, IV2n (n = 0, 1, 2), IV30, IV40, IV41 ... Inverter circuit, RDRV0, RDRV1 ... Redundant column address signal driver, PREB ... Precharge Signal, TNRB0, TNRB1 ... Normal redundancy test signal, TDRB0, TDRB1 ... Dummy redundancy test signal, NRE0, NRE1, NREB ... Normal redundancy enable signal, DRE0, DRE1, DREB0, DREB1 ... Dummy redundancy enable signal, RYMB0, RYMB1 ... Redundancy column Address enable signal, NMRY ... Regular address storage circuit, DMRY ... Dummy address storage circuit, F ... Redundant information storage circuit, FY ... Fuse, TCTL ... Test mode control circuit, TBS ... Test mode bus, ANT ... Antenna, AFE ... Analog front End block, ADC1, ADC2 ... Analog-digital modulation circuit, DAC1, DAC2 ... Digital-analog modulation circuit, BBD ... Baseband block, SPK ... Speaker, LCD ... Liquid crystal display, MIK ... Microphone, KE Y ... input key, SGC ... signal processing circuit, CPU ... central processing unit, TR ... select transistor, RL ... wiring resistance, CA ... memory element, PMC ... memory cell, PSUB ... P-type silicon substrate, SGI ... insulation for element isolation Body, PS ... polysilicon gate, GOX ... gate oxide film, SDW ... insulating film, ND ...
N-type diffusion layer, PG1, PG2, PG3 ... Metal wiring interlayer contact, MT1, MT2 ... Metal wiring layer.

Claims (12)

Multiple word lines,
A plurality of first memory cells provided at intersections of the plurality of word lines and a plurality of first data lines for storing first information or second information;
A plurality of first dummy cells provided at intersections of the plurality of word lines and the first dummy data line, for storing the first information;
A plurality of second dummy cells provided at intersections of the plurality of word lines and second dummy data lines, for storing the second information;
A first multiplexer for applying a first potential to the plurality of first data lines;
A second multiplexer for connecting the plurality of first data lines to a first write circuit;
A third multiplexer for applying the first potential to the first and second dummy data lines;
A fourth multiplexer connected to the first and second dummy data lines;
The first write circuit applies the first potential to any one of the plurality of first data lines when writing the first information to any one of the plurality of first memory cells, and the plurality of first memories. When writing the second information to any of the cells, a second potential higher than the first potential is applied to any of the plurality of first data lines,
Said fourth multiplexer, when writing the second information into the plurality of first second dummy cell to the first information in the dummy cell write the plurality provides the first potential to the first dummy data line, wherein A semiconductor device, wherein the second potential is applied to a second dummy data line. The semiconductor device according to claim 1,
The third and fourth multiplexers are turned on or off based on an external address signal input from the outside of the semiconductor device. The semiconductor device according to claim 1,
A fifth multiplexer connected to the first and second dummy data lines;
When writing the first information to the plurality of first dummy cells and writing the second information to the plurality of second dummy cells, the fourth and fifth multiplexers are turned on, and the third multiplexer is turned off. A semiconductor device, wherein currents in opposite directions flow through the first dummy data line and the second dummy data line. The semiconductor device according to claim 3.
A sixth multiplexer connected to the plurality of first data lines;
A first common data line connected to the sixth multiplexer;
A second common data line connected to the fifth multiplexer;
A second write circuit connected to the first common data line;
A third write circuit connected to the second common data line;
The second write circuit applies the second potential to any of the plurality of first data lines when writing the first information to any of the plurality of first memory cells, and the plurality of first data When writing the second information to any of the memory cells, the first potential is applied to any of the plurality of first data lines,
The third write circuit has a high resistance state when the first information is written into the plurality of first dummy cells and the second information is written into the plurality of second dummy cells. apparatus. The semiconductor device according to claim 4.
When the semiconductor device is on standby, the third write circuit applies the first potential to the second common data line. The semiconductor device according to claim 4.
When writing the first information to any of the plurality of first memory cells, the second and sixth multiplexers are turned on, the first multiplexer is turned off, and the second write circuit causes the plurality of the plurality of first information to be written. The second potential is applied to any of the first data lines, and the first potential is applied to any of the plurality of first data lines to the first write circuit,
When writing the second information to any one of the plurality of first memory cells, the second and sixth multiplexers are turned on, the first multiplexer is turned off, and the plurality of the plurality of first memory cells are turned on by the second write circuit. The semiconductor device, wherein the first potential is applied to any one of the first data lines, and the second potential is applied to any one of the plurality of first data lines by the first write circuit. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of first memory cells and the plurality of first and second dummy cells store the first information or the second information using a magnetoresistive effect. The semiconductor device according to claim 1,
A fifth multiplexer connected to the first and second dummy data lines;
A sixth multiplexer connected to the plurality of first data lines;
A plurality of second memory cells provided at intersections of the plurality of word lines and a plurality of second data lines for storing the first information or the second information;
A seventh multiplexer for applying the first potential to the plurality of second data lines;
An eighth multiplexer for connecting the plurality of second data lines to the first write circuit;
A ninth multiplexer connected to the plurality of second data lines;
A plurality of third dummy cells provided at intersections of the plurality of word lines and a third dummy data line, for storing the first information;
A plurality of fourth dummy cells provided at intersections of the plurality of word lines and a fourth dummy data line, for storing the second information;
A tenth multiplexer for applying the first potential to the third and fourth dummy data lines;
An eleventh multiplexer connected to the third and fourth dummy data lines;
A twelfth multiplexer connected to the third and fourth dummy data lines;
A plurality of third memory cells provided at intersections of the plurality of word lines and a plurality of third data lines for storing the first information or the second information;
A thirteenth multiplexer for applying the first potential to the plurality of third data lines;
A fourteenth multiplexer for connecting the plurality of third data lines to a third write circuit;
A fifteenth multiplexer connected to the plurality of third data lines;
A plurality of fourth memory cells provided at intersections of the plurality of word lines and a plurality of fourth data lines for storing either the first information or the second information;
A sixteenth multiplexer for applying the first potential to the plurality of fourth data lines;
A seventeenth multiplexer for connecting the plurality of fourth data lines to the third write circuit;
An eighteenth multiplexer connected to the plurality of fourth data lines;
A first common data line connected to the plurality of first data lines by the sixth multiplexer and connected to the first dummy data line by the fifth multiplexer;
A second common data line connected to the plurality of second data lines by the ninth multiplexer and connected to the third dummy data line by the twelfth multiplexer;
A third common data line connected to the plurality of third data lines by the fifteenth multiplexer and connected to the second dummy data line by the fifth multiplexer;
A fourth common data line connected to the plurality of fourth data lines by the eighteenth multiplexer and connected to the fourth dummy data line by the twelfth multiplexer;
A second write circuit connected to the first and second common data lines;
A fourth write circuit connected to the third and fourth common data lines;
A first switch for connecting the first common data line and the third common data line;
A second switch for connecting the second common data line and the fourth common data line;
The eleventh multiplexer applies the first potential to the third dummy data line when writing the first information into the plurality of third dummy cells and writing the second information into the plurality of fourth dummy cells, Applying the second potential to the fourth dummy data line;
The first write circuit applies the first potential to any one of the plurality of second data lines when writing the first information into any of the plurality of second memory cells, and the plurality of second data When writing the second information to any of the memory cells, the second potential is applied to any of the plurality of second data lines,
The second write circuit applies the second potential to any of the plurality of first data lines when writing the first information to any of the plurality of first memory cells, and the plurality of first data When writing the second information in any of the memory cells, the first potential is applied to any of the plurality of first data lines, and the first information is applied to any of the plurality of second memory cells. When writing, the second potential is applied to any of the plurality of second data lines, and when writing the second information to any of the plurality of second memory cells, Applying the first potential to any one of them,
The third write circuit applies the first potential to any of the plurality of third data lines when writing the first information to any of the plurality of third memory cells, and When writing the second information to any one of the memory cells, the second potential is applied to any of the plurality of third data lines, and the first information is written to any of the plurality of fourth memory cells. If the first potential is applied to any of the plurality of fourth data lines, and the second information is written to any of the plurality of fourth memory cells, any of the plurality of fourth data lines may be used. Applying the second potential to
When writing the first information to any of the plurality of third memory cells, the fourth write circuit applies the second potential to any of the plurality of third data lines, and the plurality of third data When writing the second information to any one of the memory cells, the first potential is applied to any of the plurality of third data lines, and the first information is written to any of the plurality of fourth memory cells. If the second potential is applied to any of the plurality of fourth data lines, and the second information is written to any of the plurality of fourth memory cells, any of the plurality of fourth data lines may be used. Applying the first potential to
When writing the first information into the plurality of first dummy cells and writing the second information into the plurality of second dummy cells, the first switch and the fourth and fifth multiplexers are turned on, and the third information The multiplexer is turned off, and currents in opposite directions flow through the first dummy data line and the second dummy data line,
When writing the first information into the plurality of third dummy cells and writing the second information into the plurality of fourth dummy cells, the second switch and the eleventh and twelfth multiplexers are turned on, and the tenth 2. A semiconductor device according to claim 1, wherein the multiplexer is turned off and currents flowing in opposite directions flow through the third dummy data line and the fourth dummy data line. A word line,
A first memory cell provided at an intersection of the word line and the first data line and having a first variable resistance element for storing first information or second information;
When writing the first information to the first data line , a current flows in the first direction, and when writing the second information, a second current flows in the second direction opposite to the first direction. 1 writing circuit;
A first multiplexer for connecting the first data line and the first write circuit;
A second variable resistance element is provided at an intersection of the word line and the first dummy data line and stores the first information, and generates a reference signal for reading stored information from the first memory cell. A first dummy cell used for
A third variable resistance element is provided at the intersection of the word line and the second dummy data line for storing the second information, and generates a reference signal for reading the stored information from the first memory cell. A second dummy cell used for
When writing the first information into the first dummy cell and writing the second information into the second dummy cell, a current is passed through the first dummy data line in the first direction, and the second dummy data line is subjected to the second information. And a second multiplexer for flowing current in two directions. The semiconductor device according to claim 9 .
Before Symbol first write circuit, when writing the first information to the first variable resistive element, it provides a first potential to the first data line, to write the second information to the first variable resistor element In this case, a second potential higher than the first potential is applied to the first data line,
The second multiplexer applies the first potential to the first dummy data line when writing the first information to the second variable resistance element and writing the second information to the third variable resistance element. A semiconductor device, wherein the second potential is applied to the second dummy data line. The semiconductor device according to claim 10.
A third multiplexer for connecting the first data line to a first common data line;
A fourth multiplexer for connecting the first and second dummy data lines to a second common data line;
A second write circuit connected to the first common data line;
A third write circuit connected to the second common data line;
When writing the first information to the first variable resistance element, the first potential is applied to the first data line by the first write circuit, and the first data line is applied to the first data line by the second write circuit. When the second potential is applied and the second information is written to the first variable resistance element, the second potential is applied to the first data line by the first write circuit, and the second write circuit The first potential is applied to the first data line;
When the first information is written to the second variable resistance element and the second information is written to the third variable resistance element, the output of the third write circuit is in a high resistance state. Semiconductor device. The semiconductor device according to claim 9.
The semiconductor device is characterized in that the second multiplexer is turned on or off based on an external address signal input from the outside of the semiconductor device.

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