JP6832668B2 - Self-supporting board and manufacturing method of self-supporting board - Google Patents

Self-supporting board and manufacturing method of self-supporting board Download PDF

Info

Publication number
JP6832668B2
JP6832668B2 JP2016199366A JP2016199366A JP6832668B2 JP 6832668 B2 JP6832668 B2 JP 6832668B2 JP 2016199366 A JP2016199366 A JP 2016199366A JP 2016199366 A JP2016199366 A JP 2016199366A JP 6832668 B2 JP6832668 B2 JP 6832668B2
Authority
JP
Japan
Prior art keywords
impurity
group iii
concentration
growth
iii nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016199366A
Other languages
Japanese (ja)
Other versions
JP2018058742A (en
Inventor
裕輝 後藤
裕輝 後藤
砂川 晴夫
晴夫 砂川
拓哉 中川
拓哉 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Co Ltd
Original Assignee
Furukawa Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Co Ltd filed Critical Furukawa Co Ltd
Priority to JP2016199366A priority Critical patent/JP6832668B2/en
Publication of JP2018058742A publication Critical patent/JP2018058742A/en
Application granted granted Critical
Publication of JP6832668B2 publication Critical patent/JP6832668B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)

Description

本発明は、自立基板、及び、自立基板の製造方法に関する。 The present invention relates to a self-supporting substrate and a method for manufacturing a self-supporting substrate.

HVPE(Hydride Vapor Phase Epitaxy)法でC面以外の成長面にIII族窒化物半導体をエピタキシャル成長させた場合、成長したIII族窒化物半導体の結晶中に多くの酸素(不純物)がドープされることがある。特許文献1に、C面から傾いた面でGaN結晶を成長させた場合、結晶中にドープされる酸素(O)等の不純物濃度が1×1019/cm〜5×1019/cmと高くなることが記載されている。 When a group III nitride semiconductor is epitaxially grown on a growth plane other than the C plane by the HVPE (Hydride Vapor Phase Epitaxy) method, a large amount of oxygen (impurity) may be doped into the crystal of the grown group III nitride semiconductor. is there. According to Patent Document 1, when a GaN crystal is grown on a plane inclined from the C plane, the concentration of impurities such as oxygen (O) doped in the crystal is 1 × 10 19 / cm 3 to 5 × 10 19 / cm 3 It is stated that it will be higher.

特開2013−75815号公報Japanese Unexamined Patent Publication No. 2013-75815

酸素(O)が高濃度にドープされることにより、(1)Siドープ、Geドープによるキャリヤ濃度制御が困難になる(通常、1018cm−3程度のキャリヤ濃度に制御するが、Oの濃度が上記の通りこれを超える場合がある)、(2)GaN基板表面に存在するOの存在や同原子の拡散等により、MOCVD(Metal Organic Chemical Vapor Deposition)法によるその上への(デバイス)成長が阻害される可能性がある、等の問題が発生し得る。このため、酸素(不純物)濃度を小さくすることが望まれている。本発明は、HVPE法でC面以外の成長面にIII族窒化物半導体をエピタキシャル成長させた場合におけるIII族窒化物半導体の結晶中にドープされる酸素(不純物)の濃度を制御することを課題とする。 When oxygen (O) is doped at a high concentration, it becomes difficult to control the carrier concentration by (1) Si doping and Ge doping (usually, the carrier concentration is controlled to about 10 18 cm -3, but the concentration of O is controlled. (2) Due to the presence of O present on the surface of the GaN substrate, diffusion of the same atom, etc., (device) growth on it by the MOCVD (Metal Organic Chemical Vapor Deposition) method. May be hindered, and other problems may occur. Therefore, it is desired to reduce the oxygen (impurity) concentration. An object of the present invention is to control the concentration of oxygen (impurities) doped in the crystal of a group III nitride semiconductor when a group III nitride semiconductor is epitaxially grown on a growth surface other than the C plane by the HVPE method. To do.

本発明によれば、
III族窒化物半導体で構成され、
{11−22}面から30°傾いた面である成長面を有し、
第1の不純物であるOと、第2の不純物であるSi又はGeとを含み、
SIMS(Secondary Ion Spectrometry)で測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たす自立基板が提供される。
According to the present invention
Consists of group III nitride semiconductors
It has a growth plane that is tilted 30 ° from the {11-22} plane and has a growth plane.
It contains O, which is the first impurity, and Si or Ge, which is the second impurity.
Assuming that the concentration of the first impurity measured by SIMS (Secondary Ion Spectrometry) is D1 and the concentration of the second impurity is D2, a self-supporting substrate satisfying 1.5 ≦ D1 / D2 ≦ 4 is provided.

また、本発明によれば、
III族窒化物半導体で構成され、
{11−22}面から30°傾いた面である成長面を有し、
第1の不純物であるOと、第2の不純物であるSi又はGeとを含み、
SIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすIII族窒化物半導体層を有する基板が提供される。
Further, according to the present invention,
Consists of group III nitride semiconductors
It has a growth plane that is tilted 30 ° from the {11-22} plane and has a growth plane.
It contains O, which is the first impurity, and Si or Ge, which is the second impurity.
Assuming that the concentration of the first impurity measured by SIMS is D1 and the concentration of the second impurity is D2, a substrate having a group III nitride semiconductor layer satisfying 1.5 ≦ D1 / D2 ≦ 4 is provided. ..

また、本発明によれば、
{11−22}面から30°傾いた面を成長面として有する下地基板を準備する準備工程と、
前記下地基板の上に、HVPE(Hydride Vapor Phase Epitaxy)法により、第1の不純物であるOと、第2の不純物であるSi又はGeとをドーピングしながらIII族窒化物半導体を成長させる成長工程と、
を有し、
前記成長工程では、前記成長工程の後に前記III族窒化物半導体の層を測定対象としてSIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすように、前記III族窒化物半導体の成長条件を最適化する自立基板の製造方法が提供される。
Further, according to the present invention,
A preparatory step for preparing a base substrate having a surface inclined by 30 ° from the {11-22} surface as a growth surface, and
A growth step of growing a group III nitride semiconductor while doping O, which is a first impurity, and Si or Ge, which is a second impurity, on the base substrate by the HVPE (Hydride Vapor Phase Epitaxy) method. When,
Have,
In the growth step, assuming that the concentration of the first impurity measured by SIMS with the layer of the group III nitride semiconductor as the measurement target after the growth step is D1 and the concentration of the second impurity is D2, 1. A method for manufacturing a self-supporting substrate that optimizes the growth conditions of the group III nitride semiconductor so as to satisfy 5 ≦ D1 / D2 ≦ 4 is provided.

また、本発明によれば、
自立基板上に、III族窒化物半導体で構成され、{11−22}面から30°傾いた面を成長面として有する第1の層が形成された積層体を準備する準備工程と、
前記第1の層の上に、HVPE法により、第1の不純物であるOと、第2の不純物であるSi又はGeとをドーピングしながらIII族窒化物半導体を成長させる成長工程と、
を有し、
前記成長工程では、前記成長工程の後に前記III族窒化物半導体の層を測定対象としてSIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすように、前記III族窒化物半導体の成長条件を最適化する基板の製造方法が提供される。
Further, according to the present invention,
A preparatory step for preparing a laminated body composed of a group III nitride semiconductor on a free-standing substrate and having a first layer having a plane inclined by 30 ° from the {11-22} plane as a growth plane.
A growth step of growing a group III nitride semiconductor while doping the first impurity O and the second impurity Si or Ge on the first layer by the HVPE method.
Have,
In the growth step, assuming that the concentration of the first impurity measured by SIMS with the layer of the group III nitride semiconductor as the measurement target after the growth step is D1 and the concentration of the second impurity is D2, 1. A method for manufacturing a substrate that optimizes the growth conditions of the group III nitride semiconductor so as to satisfy 5 ≦ D1 / D2 ≦ 4 is provided.

本発明によれば、HVPE法でC面以外の成長面にIII族窒化物半導体をエピタキシャル成長させた場合におけるIII族窒化物半導体の結晶中にドープされる酸素(不純物)の濃度を制御することができる。 According to the present invention, it is possible to control the concentration of oxygen (impurity) doped in the crystal of the group III nitride semiconductor when the group III nitride semiconductor is epitaxially grown on the growth plane other than the C plane by the HVPE method. it can.

本実施形態の製造方法の処理の流れの一例を示すフローチャートである。It is a flowchart which shows an example of the process flow of the manufacturing method of this embodiment. 本実施形態の下地基板上にIII族窒化物半導体層を形成した積層体の一例を示す側面模式図である。It is a side schematic diagram which shows an example of the laminated body which formed the group III nitride semiconductor layer on the base substrate of this embodiment. HVPE装置の模式図である。It is a schematic diagram of the HVPE apparatus. 本実施形態の自立基板上にIII族窒化物半導体層を形成した積層体の一例を示す側面模式図である。It is a side schematic diagram which shows an example of the laminated body which formed the group III nitride semiconductor layer on the self-supporting substrate of this embodiment. 実施例1のSIMS分析結果を示す図である。It is a figure which shows the SIMS analysis result of Example 1. FIG. 比較例1のSIMS分析結果を示す図である。It is a figure which shows the SIMS analysis result of the comparative example 1. FIG.

以下、本発明の自立基板の製造方法の実施形態について図面を用いて説明する。なお、図はあくまで発明の構成を説明するための概略図であり、各部材の大きさ、形状、数、異なる部材の大きさの比率などは図示するものに限定されない。 Hereinafter, embodiments of the method for manufacturing a self-supporting substrate of the present invention will be described with reference to the drawings. It should be noted that the figure is merely a schematic view for explaining the configuration of the invention, and the size, shape, number, ratio of different member sizes, etc. of each member are not limited to those shown.

まず、本実施形態の概要について説明する。HVPE法でC面以外の成長面にIII族窒化物半導体をエピタキシャル成長させた場合、成長したIII族窒化物半導体の結晶中にO(不純物)が意図せず高濃度でドープされやすい。例えば、濃度がM×1019/cm(1≦M≦9)程度と高くなる。Oのソースは、HVPE装置の部材であるSiOで構成された反応管等であると推測される。 First, the outline of the present embodiment will be described. When a group III nitride semiconductor is epitaxially grown on a growth surface other than the C plane by the HVPE method, O (impurities) are likely to be unintentionally doped in a high concentration in the crystal of the grown group III nitride semiconductor. For example, the concentration is as high as M × 10 19 / cm 3 (1 ≦ M ≦ 9). It is presumed that the source of O is a reaction tube or the like made of SiO 2 , which is a member of the HVPE apparatus.

本発明者らは、III族窒化物半導体の結晶の成長条件を調整し、他の不純物、具体的にはSi及びGeの少なくとも一方をIII族窒化物半導体の結晶中にドープさせ、これらの濃度を高くすると、III族窒化物半導体の結晶中におけるOの濃度が低減することを見出した。また、本発明者らは、V/III比を最適化することで、Si及びGeの少なくとも一方をIII族窒化物半導体の結晶中に多くドープさせ、III族窒化物半導体の結晶中におけるOの濃度を低減できることを見出した。 The present inventors adjust the growth conditions of the crystal of the group III nitride semiconductor, dope other impurities, specifically at least one of Si and Ge, into the crystal of the group III nitride semiconductor, and concentrate these. It was found that when the value is increased, the concentration of O in the crystal of the group III nitride semiconductor decreases. Further, by optimizing the V / III ratio, the present inventors dope at least one of Si and Ge in a large amount in the crystal of the group III nitride semiconductor, and O in the crystal of the group III nitride semiconductor. We have found that the concentration can be reduced.

本実施形態では、HVPE法でC面以外の成長面にIII族窒化物半導体をエピタキシャル成長させる際、V/III比を最適化し、SiをIII族窒化物半導体の結晶中に多くドープすることで、当該結晶中におけるOの濃度を低減する。Geを高濃度にドープする例は、第2の実施形態で説明する。 In the present embodiment, when the group III nitride semiconductor is epitaxially grown on a growth surface other than the C plane by the HVPE method, the V / III ratio is optimized and Si is doped in a large amount in the crystal of the group III nitride semiconductor. The concentration of O in the crystal is reduced. An example of high-concentration doping of Ge will be described in the second embodiment.

次に、図1のフローチャートを用いて、本実施形態の自立基板の製造方法の一例について説明する。図示するように、本実施形態の自立基板の製造方法は、準備工程S10と、成長工程S20とを有する。 Next, an example of the method for manufacturing the self-supporting substrate of the present embodiment will be described with reference to the flowchart of FIG. As shown in the figure, the method for manufacturing a self-supporting substrate of the present embodiment includes a preparation step S10 and a growth step S20.

準備工程S10では、C面と異なる面を成長面として有する下地基板を準備する。下地基板は、III族窒化物半導体で構成された基板であってもよいし、サファイア基板等の異種基板であってもよい。 In the preparation step S10, a base substrate having a surface different from the C surface as a growth surface is prepared. The base substrate may be a substrate composed of a group III nitride semiconductor, or may be a dissimilar substrate such as a sapphire substrate.

成長工程S20では、下地基板の上に、HVPE法により、第1の不純物であるOと、第2の不純物であるSiをドーピングしながらIII族窒化物半導体を成長させる。なお、第1の不純物であるOは、例えばHVPE装置100の部材等をソースとして、意図せずドープされる不純物であってもよい。 In the growth step S20, a group III nitride semiconductor is grown on the base substrate by the HVPE method while doping O, which is the first impurity, and Si, which is the second impurity. The first impurity, O, may be an impurity that is unintentionally doped using, for example, a member of the HVPE apparatus 100 as a source.

当該工程の結果、図2に示すように、下地基板10と、III族窒化物半導体層20との積層体が得られる。本実施形態では、このような積層体を自立基板とすることもできるし、また、当該積層体から下地基板10を研磨等により除去したものを自立基板とすることもできる。さらに、III族窒化物半導体層20から一部をスライス等で切り出して、自立基板としてもよい。 As a result of this step, as shown in FIG. 2, a laminate of the base substrate 10 and the group III nitride semiconductor layer 20 is obtained. In the present embodiment, such a laminated body can be used as a self-standing substrate, or a self-supporting substrate can be obtained by removing the base substrate 10 from the laminated body by polishing or the like. Further, a part thereof may be cut out from the group III nitride semiconductor layer 20 by slicing or the like to form a self-standing substrate.

なお、成長工程S20では、成長工程S20の後にIII族窒化物半導体層20を測定対象としてSIMSで測定した第1の不純物の濃度をD1、第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすように、III族窒化物半導体の成長条件を最適化する。例えば、成長工程S20では、V/III比が20以上50以下、好ましくは30以上50以下の成長条件で、III族窒化物半導体を成長させる。その他の成長条件は従来技術と同様であり、例えば成長温度:900℃以上1100℃以下等とすることができる。以下の実施例で示すように、当該成長条件でIII族窒化物半導体を成長させると、上記1.5≦D1/D2≦4を満たすことができる。 In the growth step S20, assuming that the concentration of the first impurity measured by SIMS with the group III nitride semiconductor layer 20 as the measurement target after the growth step S20 is D1 and the concentration of the second impurity is D2, it is 1.5. The growth conditions of the group III nitride semiconductor are optimized so as to satisfy ≦ D1 / D2 ≦ 4. For example, in the growth step S20, the group III nitride semiconductor is grown under growth conditions in which the V / III ratio is 20 or more and 50 or less, preferably 30 or more and 50 or less. Other growth conditions are the same as those of the prior art, and for example, the growth temperature can be 900 ° C. or higher and 1100 ° C. or lower. As shown in the following examples, when the group III nitride semiconductor is grown under the growth conditions, the above 1.5 ≦ D1 / D2 ≦ 4 can be satisfied.

ここで、図3を用いて、ハイドライド気相成長(HVPE)装置100でGaNをエピタキシャル成長させる一例を説明する。 Here, an example of epitaxially growing GaN in the hydride vapor phase growth (HVPE) apparatus 100 will be described with reference to FIG.

図示するHVPE装置100は、反応管121と、反応管121内に設けられている基板ホルダ123とを備える。反応管121は、SiO(石英等)で構成される。基板ホルダ123には下地基板41(上述した下地基板10)が保持される。また、HVPE装置100は、III族原料ガスを反応管121内に供給するIII族原料ガス供給部139と、窒素原料ガスを反応管121内に供給する窒素原料ガス供給部137とを備える。さらに、HVPE装置100は、ガス排出管135と、ヒータ129、130とを備える。 The illustrated HVPE device 100 includes a reaction tube 121 and a substrate holder 123 provided in the reaction tube 121. The reaction tube 121 is made of SiO 2 (quartz or the like). The substrate holder 123 holds the substrate 41 (the substrate 10 described above). Further, the HVPE apparatus 100 includes a group III raw material gas supply unit 139 that supplies the group III raw material gas into the reaction tube 121, and a nitrogen raw material gas supply unit 137 that supplies the nitrogen raw material gas into the reaction tube 121. Further, the HVPE device 100 includes a gas discharge pipe 135 and heaters 129 and 130.

基板ホルダ123は、反応管121の下流側に回転軸132により回転自在に設けられている。ガス排出管135は、反応管121のうち基板ホルダ123の下流側に設けられている。 The substrate holder 123 is rotatably provided on the downstream side of the reaction tube 121 by a rotating shaft 132. The gas discharge pipe 135 is provided on the downstream side of the substrate holder 123 in the reaction pipe 121.

III族原料ガス供給部139は、ガス供給管126とソースボート128とIII族(Ga)原料127と反応管121のうち遮蔽板136の下の層とを含む。 The Group III raw material gas supply unit 139 includes a gas supply pipe 126, a source boat 128, a Group III (Ga) raw material 127, and a layer of the reaction pipe 121 under the shielding plate 136.

窒素原料ガス供給部137は、ガス供給管124と反応管121のうち遮蔽板136の上の層とを含む。 The nitrogen source gas supply unit 137 includes a gas supply pipe 124 and a layer above the shielding plate 136 of the reaction pipe 121.

III族原料ガス供給部139は、III族原子のハロゲン化物(たとえば、GaCl)を生成し、これを基板ホルダ123に保持された下地基板41の表面に供給する。 The group III raw material gas supply unit 139 generates a halide (for example, GaCl) of a group III atom and supplies the halide (for example, GaCl) to the surface of the base substrate 41 held by the substrate holder 123.

ガス供給管126の供給口は、III族原料ガス供給部139内の上流側に配置されている。このため、供給されたハロゲン化水素ガス(たとえば、HClガス)は、III族原料ガス供給部139内でソースボート128中のIII族原料127と接触するようになっている。 The supply port of the gas supply pipe 126 is arranged on the upstream side in the group III raw material gas supply unit 139. Therefore, the supplied hydrogen halide gas (for example, HCl gas) comes into contact with the group III raw material 127 in the source boat 128 in the group III raw material gas supply unit 139.

これにより、ガス供給管126から供給されるハロゲン含有ガスは、ソースボート128中のIII族原料127の表面または揮発したIII族分子と接触し、III族分子をハロゲン化してIII族のハロゲン化物を含むIII族原料ガスを生成する。なお、このIII族原料ガス供給部139の周囲にはヒータ129が配置され、III族原料ガス供給部139内は、たとえば800〜900℃程度の温度に維持される。 As a result, the halogen-containing gas supplied from the gas supply pipe 126 comes into contact with the surface of the group III raw material 127 in the source boat 128 or the volatilized group III molecules, and halogenates the group III molecules to form a group III halide. Produces Group III source gas containing. A heater 129 is arranged around the group III raw material gas supply unit 139, and the temperature inside the group III raw material gas supply unit 139 is maintained at, for example, about 800 to 900 ° C.

反応管121の上流側は、遮蔽板136により2つの層に区画されている。図中の遮蔽板136の上側に位置する窒素原料ガス供給部137中を、ガス供給管124から供給されたアンモニアが通過し、熱により分解が促進される。なお、この窒素原料ガス供給部137の周囲にはヒータ129が配置され、窒素原料ガス供給部137内は、たとえば800〜900℃程度の温度に維持される。 The upstream side of the reaction tube 121 is divided into two layers by a shielding plate 136. Ammonia supplied from the gas supply pipe 124 passes through the nitrogen raw material gas supply unit 137 located above the shielding plate 136 in the figure, and decomposition is promoted by heat. A heater 129 is arranged around the nitrogen raw material gas supply unit 137, and the temperature inside the nitrogen raw material gas supply unit 137 is maintained at, for example, about 800 to 900 ° C.

図中の右側に位置する成長領域122には、基板ホルダ123に保持された下地基板41が配置され、この成長領域122内でGaN等のIII族窒化物半導体の成長が行われる。この成長領域122の周囲にはヒータ130が配置され、成長領域122内は、たとえば1000℃〜1050℃程度の温度に維持される。 The base substrate 41 held by the substrate holder 123 is arranged in the growth region 122 located on the right side in the drawing, and the group III nitride semiconductor such as GaN is grown in the growth region 122. A heater 130 is arranged around the growth region 122, and the temperature inside the growth region 122 is maintained at, for example, about 1000 ° C. to 1050 ° C.

以下の実施例で示すように、III族窒化物半導体の成長を、部材の一部(例:反応管121)がSiO(石英等)で構成されたHVPE装置を用いてV/III比が20以上50以下の成長条件で行った場合、成長したIII族窒化物半導体の結晶中にSi(不純物)がドープされる。Siのソースは、反応管121を構成するSiO(石英等)等であると推測される。このように、本実施形態によれば、Siのソースを別途用意する必要がなく、成長条件を最適化するのみで、Siを高濃度にドープすることができる。 As shown in the following examples, the growth of the group III nitride semiconductor is performed by using an HVPE device in which a part of the member (example: reaction tube 121) is composed of SiO 2 (quartz or the like) and the V / III ratio is high. When the growth condition is 20 or more and 50 or less, Si (impurity) is doped in the crystal of the grown group III nitride semiconductor. It is presumed that the source of Si is SiO 2 (quartz or the like) or the like constituting the reaction tube 121. As described above, according to the present embodiment, it is not necessary to separately prepare a Si source, and Si can be doped at a high concentration only by optimizing the growth conditions.

このような本実施形態の自立基板の製造方法によれば、以下の自立基板が得られる。 According to the method for manufacturing a self-supporting substrate of this embodiment, the following self-supporting substrate can be obtained.

III族窒化物半導体で構成され、
C面と異なる面で構成された成長面を有し、
第1の不純物であるOと、第2の不純物であるSi又はGeとを含み、
SIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たす自立基板。
Consists of group III nitride semiconductors
It has a growth surface composed of a surface different from the C surface,
It contains O, which is the first impurity, and Si or Ge, which is the second impurity.
Assuming that the concentration of the first impurity measured by SIMS is D1 and the concentration of the second impurity is D2, a self-supporting substrate satisfying 1.5 ≦ D1 / D2 ≦ 4.

すなわち、本実施形態の製造方法によれば、第1の不純物の濃度に対する第2の不純物の濃度の割合を十分に高め、第1の不純物の濃度を十分に低減した自立基板が得られる。そして、本実施形態の製造方法によれば、第1の不純物の濃度D1を、5×1017/cm≦D1≦9×1017/cmまで低減した自立基板が得られる。結果、本実施形態の製造方法によれば、O以外の不純物(例:Si)によるキャリヤ濃度制御が可能となる。また、GaN基板表面に存在するOの存在や同原子の拡散等により、MOCVD法によるその上への(デバイス)成長が阻害される不都合を軽減できる。 That is, according to the production method of the present embodiment, a self-supporting substrate can be obtained in which the ratio of the concentration of the second impurity to the concentration of the first impurity is sufficiently increased and the concentration of the first impurity is sufficiently reduced. Then, according to the manufacturing method of the present embodiment, a self-standing substrate in which the concentration D1 of the first impurity is reduced to 5 × 10 17 / cm 3 ≦ D1 ≦ 9 × 10 17 / cm 3 can be obtained. As a result, according to the production method of the present embodiment, the carrier concentration can be controlled by impurities other than O (eg, Si). Further, the inconvenience that the (device) growth on the surface of the GaN substrate is hindered by the MOCVD method due to the presence of O present on the surface of the GaN substrate, the diffusion of the atoms, and the like can be alleviated.

さらに、本実施形態の製造方法によれば、上記自立基板に対してホール効果測定装置で測定したホール濃度をHとすると、(D1+D2)×0.7≦H≦(D1+D2)×1.3を満たすことができる。すなわち、ホール濃度は、第1の不純物の濃度及び第2の不純物の濃度の和と、ほぼ同等となる。このことから、第1の不純物及び第2の不純物いずれも、キャリヤとして機能することが分かる。本実施形態の場合、第1の不純物の濃度を小さくするが、代わりにドープする第2の不純物もキャリヤとして機能するため、十分なキャリヤ濃度を確保することができる。 Further, according to the manufacturing method of the present embodiment, assuming that the Hall concentration measured by the Hall effect measuring device for the self-standing substrate is H, (D1 + D2) × 0.7 ≦ H ≦ (D1 + D2) × 1.3. Can be met. That is, the hole concentration is substantially equal to the sum of the concentration of the first impurity and the concentration of the second impurity. From this, it can be seen that both the first impurity and the second impurity function as carriers. In the case of the present embodiment, the concentration of the first impurity is reduced, but the second impurity to be doped instead also functions as a carrier, so that a sufficient carrier concentration can be secured.

<変形例1>
第1の不純物であるOと、第2の不純物であるSiとを含み、SIMSで測定した第1の不純物の濃度をD1、第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすIII族窒化物半導体の層は、下地基板10の上に形成されるもの(図2の20)に限定されない。
<Modification example 1>
If the concentration of the first impurity measured by SIMS is D1 and the concentration of the second impurity is D2, which contains O which is the first impurity and Si which is the second impurity, 1.5 ≦ D1 /. The layer of the group III nitride semiconductor satisfying D2 ≦ 4 is not limited to that formed on the base substrate 10 (20 in FIG. 2).

例えば、準備工程S10では、III族窒化物半導体で構成される自立基板30上に、III族窒化物半導体で構成され、C面と異なる面を成長面として有する第1の層40が形成された積層体を準備してもよい。第1の層40は、自立基板30の直上に形成されてもよいし、自立基板30上に他の層(単層、複層いずれでもよい)を介して形成されてもよい。 For example, in the preparation step S10, a first layer 40 composed of a group III nitride semiconductor and having a surface different from the C surface as a growth surface was formed on the self-standing substrate 30 composed of the group III nitride semiconductor. A laminate may be prepared. The first layer 40 may be formed directly above the free-standing substrate 30, or may be formed on the free-standing substrate 30 via another layer (either a single layer or a plurality of layers).

そして、成長工程S20では、このような積層体の第1の層40の直上に、III族窒化物半導体をエピタキシャル成長させてもよい。成長工程S20の詳細は、上述の通りである。 Then, in the growth step S20, the group III nitride semiconductor may be epitaxially grown directly above the first layer 40 of such a laminate. The details of the growth step S20 are as described above.

当該変形例によれば、図4に示すように、自立基板30と、第1の層40と、III族窒化物半導体層50とを有する基板が得られる。 According to the modification, as shown in FIG. 4, a substrate having a free-standing substrate 30, a first layer 40, and a group III nitride semiconductor layer 50 can be obtained.

III族窒化物半導体層50は、III族窒化物半導体で構成され、C面と異なる面で構成された成長面を有する。そして、第1の不純物であるOと、第2の不純物であるSi又はGeとを含み、SIMSで測定した第1の不純物の濃度をD1、第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たす。 The group III nitride semiconductor layer 50 is composed of a group III nitride semiconductor and has a growth surface formed of a surface different from the C surface. Then, assuming that the concentration of the first impurity measured by SIMS is D1 and the concentration of the second impurity is D2, which contains O which is the first impurity and Si or Ge which is the second impurity. 5 ≦ D1 / D2 ≦ 4 is satisfied.

すなわち、当該変形例によれば、第2の不純物の割合を十分に高め、第1の不純物の濃度を十分に低減したIII族窒化物半導体層を有する基板が得られる。そして、当該変形例によれば、III族窒化物半導体層中の第1の不純物の濃度D1を、5×1017/cm≦D1≦9×1017/cmまで低減することができる。結果、上記と同様な作用効果を実現できる。 That is, according to the modification, a substrate having a group III nitride semiconductor layer in which the ratio of the second impurity is sufficiently increased and the concentration of the first impurity is sufficiently reduced can be obtained. Then, according to the modification, the concentration D1 of the first impurity in the group III nitride semiconductor layer can be reduced to 5 × 10 17 / cm 3 ≦ D1 ≦ 9 × 10 17 / cm 3. As a result, the same action and effect as described above can be realized.

さらに、当該変形例によれば、上記自立基板に対してホール効果測定装置で測定したホール濃度をHとすると、(D1+D2)×0.7≦H≦(D1+D2)×1.3を満たすことができる。すなわち、ホール濃度は、第1の不純物の濃度及び第2の不純物の濃度の和と、ほぼ同等となる。このことから、第1の不純物及び第2の不純物いずれも、キャリヤとして機能することが分かる。本実施形態の場合、第1の不純物の濃度を小さくするが、代わりにドープする第2の不純物もキャリヤとして機能するため、十分なキャリヤ濃度を確保することができる。 Further, according to the modification, assuming that the Hall concentration measured by the Hall effect measuring device with respect to the self-supporting substrate is H, (D1 + D2) × 0.7 ≦ H ≦ (D1 + D2) × 1.3 can be satisfied. it can. That is, the hole concentration is substantially equal to the sum of the concentration of the first impurity and the concentration of the second impurity. From this, it can be seen that both the first impurity and the second impurity function as carriers. In the case of the present embodiment, the concentration of the first impurity is reduced, but the second impurity to be doped instead also functions as a carrier, so that a sufficient carrier concentration can be secured.

<変形例2>
第2の不純物をSiに代えて、Geとすることもできる。例えば、Ge(第2の不純物)のソースとして、GeClを使用することができる。そして、Hガス(キャリヤガス)を、温度を10℃程度に保ったGeCl(液体)内にくぐらせ、GeClを蒸気として反応炉内に送り込む。例えば、反応炉内におけるGeClの分圧は1×10−6atm程度にする。なお、Ge(第2の不純物)のソースとして、Geを含む部材を反応炉内に設置してもよい。
<Modification 2>
Ge can be used instead of Si as the second impurity. For example, GeCl 4 can be used as a source of Ge (second impurity). Then, H 2 gas (carrier gas) is passed through GeCl 4 (liquid) whose temperature is maintained at about 10 ° C. , and GeCl 4 is sent into the reactor as vapor. For example, the partial pressure of GeCl 4 in the reactor is about 1 × 10-6 atm. As a source of Ge (second impurity), a member containing Ge may be installed in the reactor.

そして、第2の不純物がSiの場合と同様に、成長工程S20におけるIII族窒化物半導体の成長条件を1.5≦D1/D2≦4を満たすように最適化する。例えば、成長工程S20では、V/III比が20以上50以下、好ましくは30以上50以下の成長条件で、III族窒化物半導体を成長させる。当該変形例においても、上記と同様の作用効果を実現できる。 Then, as in the case where the second impurity is Si, the growth conditions of the group III nitride semiconductor in the growth step S20 are optimized so as to satisfy 1.5 ≦ D1 / D2 ≦ 4. For example, in the growth step S20, the group III nitride semiconductor is grown under growth conditions in which the V / III ratio is 20 or more and 50 or less, preferably 30 or more and 50 or less. Also in the modified example, the same action and effect as described above can be realized.

<実施例1>
(11−22)面を約30°傾けた面を成長面として有するGaN基板を準備した。そして、当該GaN基板の上に、図3を用いて説明したHVPE装置で、以下の成長条件でGaNをエピタキシャル成長させた。
<Example 1>
A GaN substrate having a surface (11-22) tilted by about 30 ° as a growth surface was prepared. Then, GaN was epitaxially grown on the GaN substrate under the following growth conditions by the HVPE apparatus described with reference to FIG.

成長温度:1040℃
V/III比:40
成長時間:120分
成長速度:7.5μm/h
Growth temperature: 1040 ° C
V / III ratio: 40
Growth time: 120 minutes Growth rate: 7.5 μm / h

図5に、エピタキシャル成長させたGaN中のO、Si、Cの濃度をSIMSで分析した結果を示す。Oの濃度は7×1017/cm、ホール測定により算出したキャリヤ濃度は1.2×1018/cmであった。 FIG. 5 shows the results of SIMS analysis of the concentrations of O, Si, and C in the epitaxially grown GaN. The concentration of O was 7 × 10 17 / cm 3 , and the carrier concentration calculated by Hall measurement was 1.2 × 10 18 / cm 3 .

<実施例2>
(11−22)面を約30°傾けた面を成長面として有するGaN基板を準備した。そして、当該GaN基板の上に、図3を用いて説明したHVPE装置で、以下の成長条件でGaNをエピタキシャル成長させた。
<Example 2>
A GaN substrate having a surface (11-22) tilted by about 30 ° as a growth surface was prepared. Then, GaN was epitaxially grown on the GaN substrate under the following growth conditions by the HVPE apparatus described with reference to FIG.

成長温度:1040℃
V/III比:20
成長時間:60分
成長速度:239μm/h
Growth temperature: 1040 ° C
V / III ratio: 20
Growth time: 60 minutes Growth rate: 239 μm / h

図6に、ピタキシャル成長させたGaN中のO、Si、Cの濃度をSIMSで分析した結果を示す。Oの濃度は5×1018/cm、ホール測定により算出したキャリヤ濃度は5.7×1018/cmであった。 FIG. 6 shows the results of SIMS analysis of the concentrations of O, Si, and C in the pivotally grown GaN. The concentration of O was 5 × 10 18 / cm 3 , and the carrier concentration calculated by Hall measurement was 5.7 × 10 18 / cm 3 .

以上より、V/III比を最適化することで、Siの濃度及びOの濃度を調整できることが分かる。そして、V/III比を最適化することで、Siの濃度を高め、Oの濃度を低減できることが分かる。実施例1及び実施例2いずれにおいても、Oの濃度は、M×1019/cm(1≦M≦9)よりも小さくなっている。また、Siの濃度とOの濃度の和は、ホール濃度とほぼ同等であり、これら不純物がキャリヤとして機能することが分かる。 From the above, it can be seen that the Si concentration and the O concentration can be adjusted by optimizing the V / III ratio. Then, it can be seen that the concentration of Si can be increased and the concentration of O can be decreased by optimizing the V / III ratio. In both Example 1 and Example 2, the concentration of O is smaller than M × 10 19 / cm 3 (1 ≦ M ≦ 9). Further, the sum of the Si concentration and the O concentration is almost the same as the Hall concentration, and it can be seen that these impurities function as carriers.

以下、参考形態の例を付記する。
1. III族窒化物半導体で構成され、
C面と異なる面で構成された成長面を有し、
第1の不純物であるOと、第2の不純物であるSi又はGeとを含み、
SIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たす自立基板。
2. 1に記載の自立基板において、
ホール効果測定装置で測定したホール濃度をHとすると、
(D1+D2)×0.7≦H≦(D1+D2)×1.3を満たす自立基板。
3. 1又は2に記載の自立基板において、
5×1017/cm≦D1≦9×1017/cmを満たす自立基板。
4. III族窒化物半導体で構成され、
C面と異なる面で構成された成長面を有し、
第1の不純物であるOと、第2の不純物であるSi又はGeとを含み、
SIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすIII族窒化物半導体層を有する基板。
5. 4に記載の基板において、
ホール効果測定装置で測定したホール濃度をHとすると、
(D1+D2)×0.7≦H≦(D1+D2)×1.3を満たす基板。
6. 4又は5に記載の基板において、
5×1017/cm≦D1≦9×1017/cmを満たす基板。
7. C面と異なる面を成長面として有する下地基板を準備する準備工程と、
前記下地基板の上に、HVPE法により、第1の不純物であるOと、第2の不純物であるSi又はGeとをドーピングしながらIII族窒化物半導体を成長させる成長工程と、
を有し、
前記成長工程では、前記成長工程の後に前記III族窒化物半導体の層を測定対象としてSIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすように、前記III族窒化物半導体の成長条件を最適化する自立基板の製造方法。
8. 7に記載の自立基板の製造方法において、
前記成長工程では、V/III比が20以上50以下の成長条件で、III族窒化物半導体を成長させる自立基板の製造方法。
9. 自立基板上に、III族窒化物半導体で構成され、C面と異なる面を成長面として有する第1の層が形成された積層体を準備する準備工程と、
前記第1の層の上に、HVPE法により、第1の不純物であるOと、第2の不純物であるSi又はGeとをドーピングしながらIII族窒化物半導体を成長させる成長工程と、
を有し、
前記成長工程では、前記成長工程の後に前記III族窒化物半導体の層を測定対象としてSIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすように、前記III族窒化物半導体の成長条件を最適化する基板の製造方法。
10. 9に記載の基板の製造方法において、
前記成長工程では、V/III比が20以上50以下の成長条件で、III族窒化物半導体を成長させる基板の製造方法。
Hereinafter, an example of the reference form will be added.
1. 1. Consists of group III nitride semiconductors
It has a growth surface composed of a surface different from the C surface,
It contains O, which is the first impurity, and Si or Ge, which is the second impurity.
Assuming that the concentration of the first impurity measured by SIMS is D1 and the concentration of the second impurity is D2, a self-supporting substrate satisfying 1.5 ≦ D1 / D2 ≦ 4.
2. 2. In the self-supporting substrate according to 1.
Assuming that the Hall concentration measured by the Hall effect measuring device is H,
A self-supporting substrate that satisfies (D1 + D2) × 0.7 ≦ H ≦ (D1 + D2) × 1.3.
3. 3. In the self-supporting substrate according to 1 or 2,
A self-standing substrate that satisfies 5 × 10 17 / cm 3 ≦ D1 ≦ 9 × 10 17 / cm 3.
4. Consists of group III nitride semiconductors
It has a growth surface composed of a surface different from the C surface,
It contains O, which is the first impurity, and Si or Ge, which is the second impurity.
Assuming that the concentration of the first impurity measured by SIMS is D1 and the concentration of the second impurity is D2, a substrate having a group III nitride semiconductor layer satisfying 1.5 ≦ D1 / D2 ≦ 4.
5. In the substrate according to 4.
Assuming that the Hall concentration measured by the Hall effect measuring device is H,
A substrate that satisfies (D1 + D2) × 0.7 ≦ H ≦ (D1 + D2) × 1.3.
6. In the substrate according to 4 or 5.
A substrate satisfying 5 × 10 17 / cm 3 ≦ D1 ≦ 9 × 10 17 / cm 3.
7. A preparatory process for preparing a base substrate having a surface different from the C surface as a growth surface, and
A growth step of growing a group III nitride semiconductor while doping O, which is a first impurity, and Si or Ge, which is a second impurity, on the base substrate by the HVPE method.
Have,
In the growth step, assuming that the concentration of the first impurity measured by SIMS with the layer of the group III nitride semiconductor as the measurement target after the growth step is D1 and the concentration of the second impurity is D2, 1. A method for manufacturing a self-supporting substrate that optimizes the growth conditions of the group III nitride semiconductor so as to satisfy 5 ≦ D1 / D2 ≦ 4.
8. In the method for manufacturing a self-supporting substrate according to 7.
In the growth step, a method for manufacturing a self-supporting substrate for growing a group III nitride semiconductor under growth conditions having a V / III ratio of 20 or more and 50 or less.
9. A preparatory step for preparing a laminated body composed of a group III nitride semiconductor and having a first layer having a surface different from the C surface as a growth surface formed on the self-supporting substrate.
A growth step of growing a group III nitride semiconductor while doping the first impurity O and the second impurity Si or Ge on the first layer by the HVPE method.
Have,
In the growth step, assuming that the concentration of the first impurity measured by SIMS with the layer of the group III nitride semiconductor as the measurement target after the growth step is D1 and the concentration of the second impurity is D2, 1. A method for manufacturing a substrate that optimizes the growth conditions of the group III nitride semiconductor so as to satisfy 5 ≦ D1 / D2 ≦ 4.
10. In the method for manufacturing a substrate according to 9.
In the growth step, a method for manufacturing a substrate for growing a group III nitride semiconductor under growth conditions having a V / III ratio of 20 or more and 50 or less.

10 下地基板
20 III族窒化物半導体層
30 自立基板
40 第1の層
50 III族窒化物半導体層
100 HVPE装置
121 反応管
122 成長領域
123 基板ホルダ
124 ガス供給管
125 配管
126 ガス供給管
127 III族原料
128 ソースボート
129 ヒータ
130 ヒータ
132 回転軸
135 ガス排出管
136 遮蔽板
137 窒素原料ガス供給部
139 III族原料ガス供給部
10 Base substrate 20 Group III nitride semiconductor layer 30 Self-supporting substrate 40 First layer 50 Group III nitride semiconductor layer 100 HVPE device 121 Reaction tube 122 Growth area 123 Substrate holder 124 Gas supply tube 125 Piping 126 Gas supply tube 127 Group III Raw material 128 Source boat 129 Heater 130 Heater 132 Rotating shaft 135 Gas discharge pipe 136 Shielding plate 137 Nitrogen raw material gas supply unit 139 Group III raw material gas supply unit

Claims (10)

III族窒化物半導体で構成され、
{11−22}面から30°傾いた面である成長面を有し、
第1の不純物であるOと、第2の不純物であるSi又はGeとを含み、
SIMS(Secondary Ion Spectrometry)で測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たす自立基板。
Consists of group III nitride semiconductors
It has a growth plane that is tilted 30 ° from the {11-22} plane and has a growth plane.
It contains O, which is the first impurity, and Si or Ge, which is the second impurity.
Assuming that the concentration of the first impurity measured by SIMS (Secondary Ion Spectrometry) is D1 and the concentration of the second impurity is D2, a self-supporting substrate satisfying 1.5 ≦ D1 / D2 ≦ 4.
請求項1に記載の自立基板において、
ホール効果測定装置で測定したホール濃度をHとすると、
(D1+D2)×0.7≦H≦(D1+D2)×1.3を満たす自立基板。
In the self-supporting substrate according to claim 1,
Assuming that the Hall concentration measured by the Hall effect measuring device is H,
A self-supporting substrate that satisfies (D1 + D2) × 0.7 ≦ H ≦ (D1 + D2) × 1.3.
請求項1又は2に記載の自立基板において、
5×1017/cm≦D1≦9×1017/cmを満たす自立基板。
In the self-supporting substrate according to claim 1 or 2.
A self-standing substrate that satisfies 5 × 10 17 / cm 3 ≦ D1 ≦ 9 × 10 17 / cm 3.
III族窒化物半導体で構成され、
{11−22}面から30°傾いた面である成長面を有し、
第1の不純物であるOと、第2の不純物であるSi又はGeとを含み、
SIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすIII族窒化物半導体層を有する基板。
Consists of group III nitride semiconductors
It has a growth plane that is tilted 30 ° from the {11-22} plane and has a growth plane.
It contains O, which is the first impurity, and Si or Ge, which is the second impurity.
Assuming that the concentration of the first impurity measured by SIMS is D1 and the concentration of the second impurity is D2, a substrate having a group III nitride semiconductor layer satisfying 1.5 ≦ D1 / D2 ≦ 4.
請求項4に記載の基板において、
ホール効果測定装置で測定したホール濃度をHとすると、
(D1+D2)×0.7≦H≦(D1+D2)×1.3を満たす基板。
In the substrate according to claim 4,
Assuming that the Hall concentration measured by the Hall effect measuring device is H,
A substrate that satisfies (D1 + D2) × 0.7 ≦ H ≦ (D1 + D2) × 1.3.
請求項4又は5に記載の基板において、
5×1017/cm≦D1≦9×1017/cmを満たす基板。
In the substrate according to claim 4 or 5,
A substrate satisfying 5 × 10 17 / cm 3 ≦ D1 ≦ 9 × 10 17 / cm 3.
{11−22}面から30°傾いた面を成長面として有する下地基板を準備する準備工程と、
前記下地基板の上に、HVPE(Hydride Vapor Phase Epitaxy)法により、第1の不純物であるOと、第2の不純物であるSi又はGeとをドーピングしながらIII族窒化物半導体を成長させる成長工程と、
を有し、
前記成長工程では、前記成長工程の後に前記III族窒化物半導体の層を測定対象としてSIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすように、前記III族窒化物半導体の成長条件を最適化する自立基板の製造方法。
A preparatory step for preparing a base substrate having a surface inclined by 30 ° from the {11-22} surface as a growth surface, and
A growth step of growing a group III nitride semiconductor while doping O, which is a first impurity, and Si or Ge, which is a second impurity, on the base substrate by the HVPE (Hydride Vapor Phase Epitaxy) method. When,
Have,
In the growth step, assuming that the concentration of the first impurity measured by SIMS with the layer of the group III nitride semiconductor as the measurement target after the growth step is D1 and the concentration of the second impurity is D2, 1. A method for manufacturing a self-supporting substrate that optimizes the growth conditions of the group III nitride semiconductor so as to satisfy 5 ≦ D1 / D2 ≦ 4.
請求項7に記載の自立基板の製造方法において、
前記成長工程では、V/III比が20以上50以下の成長条件で、III族窒化物半導体を成長させる自立基板の製造方法。
In the method for manufacturing a self-supporting substrate according to claim 7.
In the growth step, a method for manufacturing a self-supporting substrate for growing a group III nitride semiconductor under growth conditions having a V / III ratio of 20 or more and 50 or less.
自立基板上に、III族窒化物半導体で構成され、{11−22}面から30°傾いた面を成長面として有する第1の層が形成された積層体を準備する準備工程と、
前記第1の層の上に、HVPE法により、第1の不純物であるOと、第2の不純物であるSi又はGeとをドーピングしながらIII族窒化物半導体を成長させる成長工程と、
を有し、
前記成長工程では、前記成長工程の後に前記III族窒化物半導体の層を測定対象としてSIMSで測定した前記第1の不純物の濃度をD1、前記第2の不純物の濃度をD2とすると、1.5≦D1/D2≦4を満たすように、前記III族窒化物半導体の成長条件を最適化する基板の製造方法。
A preparatory step for preparing a laminated body composed of a group III nitride semiconductor on a free-standing substrate and having a first layer having a plane inclined by 30 ° from the {11-22} plane as a growth plane.
A growth step of growing a group III nitride semiconductor while doping the first impurity O and the second impurity Si or Ge on the first layer by the HVPE method.
Have,
In the growth step, assuming that the concentration of the first impurity measured by SIMS with the layer of the group III nitride semiconductor as the measurement target after the growth step is D1 and the concentration of the second impurity is D2, 1. A method for manufacturing a substrate that optimizes the growth conditions of the group III nitride semiconductor so as to satisfy 5 ≦ D1 / D2 ≦ 4.
請求項9に記載の基板の製造方法において、
前記成長工程では、V/III比が20以上50以下の成長条件で、III族窒化物半導体を成長させる基板の製造方法。
In the method for manufacturing a substrate according to claim 9,
In the growth step, a method for manufacturing a substrate for growing a group III nitride semiconductor under growth conditions having a V / III ratio of 20 or more and 50 or less.
JP2016199366A 2016-10-07 2016-10-07 Self-supporting board and manufacturing method of self-supporting board Active JP6832668B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2016199366A JP6832668B2 (en) 2016-10-07 2016-10-07 Self-supporting board and manufacturing method of self-supporting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016199366A JP6832668B2 (en) 2016-10-07 2016-10-07 Self-supporting board and manufacturing method of self-supporting board

Publications (2)

Publication Number Publication Date
JP2018058742A JP2018058742A (en) 2018-04-12
JP6832668B2 true JP6832668B2 (en) 2021-02-24

Family

ID=61909660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016199366A Active JP6832668B2 (en) 2016-10-07 2016-10-07 Self-supporting board and manufacturing method of self-supporting board

Country Status (1)

Country Link
JP (1) JP6832668B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7497222B2 (en) * 2020-06-12 2024-06-10 パナソニックホールディングス株式会社 Group III nitride crystal, Group III nitride substrate, and method for manufacturing Group III nitride crystal

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004296640A (en) * 2003-03-26 2004-10-21 Furukawa Co Ltd GROWTH METHOD OF GaN SEMICONDUCTOR LAYER, SEMICONDUCTOR SUBSTRATE MANUFACTURING METHOD USING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
JP5446622B2 (en) * 2009-06-29 2014-03-19 住友電気工業株式会社 Group III nitride crystal and method for producing the same
JP6036155B2 (en) * 2011-10-21 2016-11-30 三菱化学株式会社 GaN crystal

Also Published As

Publication number Publication date
JP2018058742A (en) 2018-04-12

Similar Documents

Publication Publication Date Title
JP6031733B2 (en) GaN crystal manufacturing method
JP5560528B2 (en) Method for producing group III nitride single crystal ingot and method for producing group III nitride single crystal substrate
JP7255817B2 (en) GaN crystal manufacturing method
JP2009126723A (en) Growing method of group iii nitride semiconductor crystal, fabrication method of group iii nitride semiconductor crystal substrate, and group iii nitride semiconductor crystal substrate
JP2009126722A (en) Group iii nitride semiconductor crystal substrate and semiconductor device
JP2007217227A (en) METHOD FOR PRODUCING GaN CRYSTAL, GaN CRYSTAL SUBSTRATE, AND SEMICONDUCTOR DEVICE
WO2016136548A1 (en) Nitride semiconductor template, manufacturing method thereof, and epitaxial wafer
JP5910430B2 (en) Method for manufacturing epitaxial silicon carbide wafer
JP2009126721A (en) Growing method of group iii nitride semiconductor crystal, fabrication method of group iii nitride semiconductor crystal substrate, and group iii nitride semiconductor crystal substrate
US11094539B2 (en) Method for manufacturing nitride semiconductor substrate and nitride semiconductor substrate
JP6437736B2 (en) Method for manufacturing free-standing substrate and free-standing substrate
JP2007223878A (en) Method for producing group iii nitride crystal and group iii nitride crystal substrate
JP6832668B2 (en) Self-supporting board and manufacturing method of self-supporting board
JP2019048766A (en) α-Ga 2O3 SINGLE CRYSTAL, METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR ELEMENT USING α-Ga2O3 SINGLE CRYSTAL
US10059590B2 (en) Method for producing group III nitride crystal
JP5040708B2 (en) Method for manufacturing nitride semiconductor crystal
JP2010248022A (en) Group iii nitride semiconductor self-standing substrate
US20120258581A1 (en) Mocvd fabrication of group iii-nitride materials using in-situ generated hydrazine or fragments there from
JP2013049621A (en) Nitride semiconductor crystal, growing method thereof, material, and gallium nitride single crystal substrate
JP6250368B2 (en) Method for manufacturing free-standing substrate and free-standing substrate
JP2016094309A (en) Single crystal semiconductor layer, free-standing substrate, laminated structure and method for manufacturing them
JP5629340B2 (en) Doped III-N bulk crystal and free-standing doped III-N substrate
JP6826627B2 (en) Single crystal semiconductor layer, self-supporting substrate, laminated structure and manufacturing method thereof
JP6827369B2 (en) Manufacturing method of nitride crystal substrate
JP2021109813A (en) Production method of nitride crystal substrate, nitride crystal substrate, and laminate structure

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190904

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200519

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200616

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200804

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210126

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210202

R150 Certificate of patent or registration of utility model

Ref document number: 6832668

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250