JP6825294B2 - Power semiconductor drive circuit device - Google Patents

Description

The present invention relates to a power semiconductor drive circuit device for insulatingly transmitting a control signal for driving a power semiconductor via a transformer.

The input of the control signal generated by the external device is received by the transmitting side device, the received control signal is isolated and transmitted from the transmitting side device to the receiving side device via a transformer, and the power semiconductor is generated by the control signal output from the receiving side device. A power semiconductor drive circuit device for driving is known (see, for example, Patent Document 1).

In this type of power semiconductor drive circuit device, the control signal may not be normally isolated and transmitted due to the influence of the capacitance between the primary and secondary windings of the transformer, noise, and malfunction of the control circuit of each part. Therefore, in Patent Document 1, the control signal output from the receiving side device to the power semiconductor is isolated and transmitted from the receiving side device to the transmitting side device via a transformer as a verification signal, and the control input from the external device in the transmitting side device is performed. By comparing the signal with the verification signal, it is determined whether or not the control signal is normally isolated and transmitted.

Japanese Unexamined Patent Publication No. 2010-10762

However, in the prior art, a delay time occurs when performing isolated transmission or when converting a control signal into a pulse signal capable of isolated transmission, so that the verification signal is a control signal input from an external device in the transmitting side device. On the other hand, the signal is delayed. Therefore, when the input control signal and the verification signal do not match for the delay time or more, error detection is performed, and there is a problem that the time accuracy until error detection is lowered.

An object of the present invention is to provide a power semiconductor drive circuit device capable of solving the above problems of the prior art and improving the time accuracy of error detection.

The power semiconductor drive circuit device of the present invention is a power semiconductor drive circuit device that drives a power semiconductor on the secondary side by insulatingly transmitting a control signal input to the primary side to the secondary side and drives the power semiconductor on the secondary side. A control signal transmission circuit that receives the input control signal as an input control signal and converts it into a transmission continuous pulse signal that can be isolated and transmitted, and a first that isolates and transmits the transmission continuous pulse signal from the primary side to the secondary side. A control signal receiving circuit that restores the transmission continuous pulse signal isolated and transmitted to the secondary side to the control signal and outputs the restored control signal as an output control signal to the power semiconductor. A verification signal transmission circuit that converts the output control signal into a feedback continuous pulse signal that can be isolated and transmitted as a verification signal, a second transformer that isolates and transmits the feedback continuous pulse signal from the secondary side to the primary side, and 1. A verification signal receiving circuit that restores the feedback continuous pulse signal isolated and transmitted to the next side to the verification signal, the first transformer, the control signal receiving circuit, the verification signal transmitting circuit, the second transformer, and the verification. The comparison signal generation circuit that generates a comparison signal from the continuous pulse signal for transmission in consideration of the delay time of the signal reception circuit, the verification signal restored by the verification signal reception circuit, and the comparison signal generation circuit generated by the comparison signal generation circuit. It is equipped with a signal comparison circuit that detects an error by comparing it with a comparison signal .
The comparison signal generation circuit performs isolated transmission in the same operation as the first transformer by a pseudo first transformer having the same configuration as the first transformer, and the pseudo control signal receiving circuit having the same configuration as the control signal receiving circuit. The restoration operation is executed in the same operation as the control signal receiving circuit, the conversion operation is executed in the same operation as the verification signal transmitting circuit by the pseudo verification signal transmitting circuit having the same configuration as the verification signal transmitting circuit, and the second transformer is used. Insulation transmission is performed by the pseudo second transformer having the same configuration as the second transformer in the same operation as the second transformer, and the restoration operation is performed by the pseudo verification signal receiving circuit having the same configuration as the verification signal receiving circuit in the same operation as the verification signal receiving circuit. Is characterized in that the comparison signal is generated from the continuous pulse signal for transmission .

According to the present invention, error detection is performed by comparing the verification signal isolated and transmitted from the secondary side to the primary side and the comparison signal in consideration of the delay time of the verification signal, without providing a nuisance period in which no mismatch is detected. This has the effect of improving the time accuracy of error detection.

It is a circuit block diagram which shows the embodiment of the power semiconductor drive circuit apparatus which concerns on this invention. It is a waveform diagram explaining the operation of the comparison signal generation circuit shown in FIG. It is a figure which shows the circuit structure example of the comparison signal generation circuit shown in FIG.

Next, an embodiment of the present invention will be specifically described with reference to the drawings.
The power semiconductor drive circuit device 1 of the present embodiment drives the power semiconductor 3 based on the control signal generated by the microcomputer 2, referring to FIG. The power semiconductor drive circuit device 1 includes a transmitting side device 10, a first transformer 20, a receiving side device 30, and a second transformer 40. The power semiconductor 3 is composed of an IGBT (Insulated GateBipolor Transistor), an NPN bipolar transistor, a FET (FieldEffect Transistor), and the like.

For example, the microcomputer 2 generates a control signal for controlling a load of a motor or the like via a power semiconductor 3, and inputs the generated control signal to the control signal input terminal T1 of the transmitting side device 10. Then, the transmitting side device 10 isolates and transmits the control signal input from the control signal input terminal T1 to the receiving side device 30 via the first transformer 20. Then, the receiving side device 30 outputs the control signal isolated and transmitted via the first transformer 20 from the control signal output terminal T2 to the drive terminal (gate terminal in the case of the IGBT or FET) of the power semiconductor 3. Drives the power semiconductor 3.

The transmitting side device 10 includes a control signal transmitting circuit 11, a verification signal receiving circuit 12, and a comparison signal generating circuit 13, and the receiving side device 30 includes a control signal receiving circuit 31, a drive circuit 32, and a verification signal transmitting circuit. It is equipped with 33.

The control signal transmission circuit 11 is for transmission in which the high level period of the input control signal A is converted into a continuous pulse based on the control signal (hereinafter referred to as the input control signal A) input from the microcomputer 2 to the control signal input terminal T1. The continuous pulse signal B is generated, and the continuous pulse signal B for transmission is output to the primary winding of the first transformer 20 and the comparison signal generation circuit 13. The continuous pulse signal B for transmission is a signal that can be isolated and transmitted via the first transformer 20, and each pulse width of the continuous pulse is a value sufficiently smaller than the pulse width of 25 μs of the input control signal A. ing. Further, the control signal transmission circuit 11 may generate a transmission continuous pulse signal B obtained by converting the low level period of the input control signal A into a continuous pulse.

The transmission continuous pulse signal B is isolated and transmitted from the primary winding of the first transformer 20 to the secondary winding, and is input to the control signal receiving circuit 31 of the receiving side device 30 as the transmission continuous pulse signal C.

The control signal receiving circuit 31 restores the input continuous pulse signal C for transmission to a control signal by returning the continuous pulse period to the high level period, and the restored control signal (hereinafter referred to as output control signal D) is used. Output to the drive circuit 32. The output control signal D is output from the control signal output terminal T2 as a drive signal of the power semiconductor 3 by the drive circuit 32.

Further, the output control signal D is also input to the verification signal transmission circuit 33 as a verification signal. The verification signal transmission circuit 33 generates a feedback continuous pulse signal E in which the high level period of the output control signal D is converted into a continuous pulse based on the output control signal D input as the verification signal, and the feedback continuous pulse signal E is generated. Is output to the secondary winding of the second transformer 40. The feedback continuous pulse signal E is a signal that can be isolated and transmitted via the second transformer 40, and each pulse width of the continuous pulse is a value sufficiently smaller than the pulse width of the output control signal D. There is. Further, the control signal transmission circuit 11 may generate a feedback continuous pulse signal E obtained by converting the low level period of the output control signal D into a continuous pulse.

The feedback continuous pulse signal E is isolated and transmitted from the secondary winding of the second transformer 40 to the primary winding, and is input to the verification signal receiving circuit 12 of the transmitting side device 10 as the feedback continuous pulse signal F.

The verification signal receiving circuit 12 restores the input continuous pulse signal F for feedback to a verification signal by returning the continuous pulse period to a high level period, and the restored verification signal (hereinafter referred to as verification signal G) is a signal. Output to the comparison circuit 14.

The comparison signal generation circuit 13 generates and generates a comparison signal H by executing a restoration operation for returning the continuous pulse period of the transmission continuous pulse signal B to a high level period and a delay operation for delaying a preset time. The resulting comparison signal H is output to the signal comparison circuit 14. In the comparison signal generation circuit 13, the comparison signal H is generated by executing a delay operation of delaying the transmission continuous pulse signal B by a preset time and then performing a restoration operation of returning the continuous pulse period to the high level period. You may try to do it.

FIG. 2 shows the operation waveforms of each part of the power semiconductor drive circuit device 1. From the top, the waveforms shown in FIG. 2 include an input control signal A, a continuous pulse signal B for transmission, a continuous pulse signal C for transmission, an output control signal D, a continuous pulse signal E for feedback, and a continuous pulse signal F for feedback. The verification signal G and the comparison signal H are shown.

Referring to FIG. 2, due to the conversion operation from the control signal to the continuous pulse signal, the transmission continuous pulse signal B is delayed from the input control signal A (delay time T1), and the feedback continuous pulse signal E is from the output control signal D. Is also delayed (delay time T4). When the control signal transmission circuit 11 and the verification signal transmission circuit 33 have the same configuration, the delay time T1 = the delay time T4.

Further, due to the isolated transmission of the continuous pulse signal, the transmission continuous pulse signal C is delayed from the transmission continuous pulse signal B (delay time T2), and the feedback continuous pulse signal F is delayed from the feedback continuous pulse signal E (delay). Time T5). When the first transformer 20 and the second transformer 40 have the same configuration, the delay time T2 = the delay time T5.

Further, due to the restoration operation from the continuous pulse signal to the control signal, the output control signal D is delayed from the transmission continuous pulse signal C (delay time T3), and the verification signal G is delayed from the feedback continuous pulse signal F (delay time). T6). When the control signal receiving circuit 31 and the verification signal receiving circuit 12 have the same configuration, the delay time T3 = the delay time T6.

Therefore, the delay time Ta of the verification signal G with respect to the continuous pulse signal B for transmission is Ta = (T2 + T3 + T4 + T5 + T6). Therefore, the comparison signal generation circuit 13 generates a comparison signal H in which the delay time Tb with respect to the continuous pulse signal B for transmission is Tb = Ta, and the signal comparison circuit 14 compares the verification signal G with the comparison signal H. , When the verification signal G and the comparison signal H do not match, an error detection signal is output. The error detection signal is input to the microcomputer 2 via the error detection signal output terminal T3, and the microcomputer 2 outputs a signal to stop the power semiconductor 3 and turns off the power semiconductor 3.

As a result, the comparison signal H to be compared with the verification signal G is the first transformer 20, the control signal receiving circuit 31, the verification signal transmitting circuit 33, the second transformer 40, and the verification signal receiving circuit 12 in the same manner as the verification signal G. Since the delay is added and compensated for, the comparison in the signal comparison circuit 14 can be easily performed.

In addition, in generating the comparison signal H by the comparison signal generation circuit 13, a restoration operation for returning the continuous pulse period to the high level period is required. In this case, the delay time T3 or the delay time T6 is compensated by executing the same restoration operation as the verification signal receiving circuit 12 or the control signal receiving circuit 31. Thereby, in the delay operation, the delay time (T2 + T4 + T5 + T6 or T2 + T3 + T4 + T5) other than the delay time T3 or the delay time T6 is compensated.

Further, the comparison signal generation circuit 13a shown in FIG. 3 may be configured to generate the comparison signal H from the transmission continuous pulse signal B. The comparison signal generation circuit 13a includes a pseudo first transformer 20a having the same configuration as the first transformer 20, a pseudo control signal receiving circuit 31a having the same configuration as the control signal receiving circuit 31, and a pseudo verification having the same configuration as the verification signal transmitting circuit 33. It includes a signal transmission circuit 33a, a pseudo second transformer 40a having the same configuration as the second transformer 40, and a pseudo verification signal reception circuit 12a having the same configuration as the verification signal reception circuit 12.

In the comparison signal generation circuit 13a, the pseudo first transformer 20a performs isolated transmission in the same operation as the first transformer 20 (compensates the delay time T2 of the transmission continuous pulse signal B to the transmission continuous pulse signal C) and performs pseudo control. The signal receiving circuit 31a executes a restoration operation in the same operation as the control signal receiving circuit 31 (compensates the delay time T3 of the output control signal D from the continuous pulse signal C for transmission), and the pseudo verification signal transmitting circuit 33a transmits the verification signal. The conversion operation is executed in the same operation as the circuit 33 (compensating the delay time T4 of the feedback continuous pulse signal E from the output control signal D), and the pseudo second transformer 40a performs isolated transmission in the same operation as the second transformer 40. (Compensating the delay time T5 of the feedback continuous pulse signal F from the feedback continuous pulse signal E), the pseudo verification signal receiving circuit 12a executes a restoration operation in the same operation as the verification signal receiving circuit 12 (returning continuous pulse). Compensate for the delay time T6 of the verification signal G from the signal F).

As described above, according to the present embodiment, it is a power semiconductor drive circuit device that drives the power semiconductor on the secondary side by insulatingly transmitting the control signal input to the primary side to the secondary side. The control signal transmission circuit 11 that receives the control signal input to the next side as the input control signal A and converts it into the transmission continuous pulse signal B capable of isolated transmission, and the transmission continuous pulse signal B from the primary side to the secondary side. The first transformer 10 that is isolated and transmitted to the secondary side and output as the transmission continuous pulse signal C and the transmission continuous pulse signal C that is isolated and transmitted to the secondary side are restored to the control signal, and the restored control signal is output to the output control signal D. The control signal receiving circuit 31 that outputs to the power semiconductor 3 as a verification signal, the verification signal transmission circuit 33 that converts the output control signal D into a feedback continuous pulse signal E that can be isolated and transmitted as a verification signal, and a feedback continuous pulse signal E. Is isolated from the secondary side to the primary side and output as a feedback continuous pulse signal F. Verification that restores the feedback continuous pulse signal F isolated and transmitted to the primary side to the verification signal G. A comparison signal H considering the delay times of the signal receiving circuit 12, the first transformer 20, the control signal receiving circuit 31, the verification signal transmitting circuit 33, the second transformer 40, and the verification signal receiving circuit 12 is transmitted from the continuous pulse signal B for transmission. A signal comparison circuit 14 that detects an error by comparing the generated comparison signal generation circuit 13 with the verification signal G restored by the verification signal reception circuit 12 and the comparison signal H generated by the comparison signal generation circuit 13. It has.
With this configuration, error detection is performed by comparing the verification signal G isolated and transmitted from the secondary side to the primary side with the comparison signal in consideration of the delay time of the verification signal G, without providing a nuisance period in which no mismatch is detected. It is possible to improve the time accuracy of error detection. Further, the comparison signal H to be compared with the verification signal G is the first transformer 20, the control signal receiving circuit 31, the verification signal transmitting circuit 33, the second transformer 40, and the verification signal receiving circuit 12 in the same manner as the verification signal G. Since the delay is added and compensated, the comparison in the signal comparison circuit 14 can be easily performed.

Further, according to the present embodiment, the comparison signal generation circuit 13 executes a restoration operation for restoring the transmission continuous pulse signal B to the control signal and a delay operation for delaying the signal. In the restoration operation, the control signal is further executed. The continuous pulse signal B for transmission is restored to the control signal in the same operation as the receiving circuit 31 or the verification signal receiving circuit 14, and in the delayed operation, the delay in the control signal receiving circuit 31 or other circuits other than the verification signal receiving circuit 12 is delayed. Delay the time (T2 + T4 + T5 + T6 or T2 + T3 + T4 + T5).
With this configuration, the delay time in the delayed operation can be shortened by simulating the actual restoration operation, and the delay time can be compensated more accurately.

Further, according to the present embodiment, the comparison signal generation circuit 13 performs isolated transmission in the same operation as the first transformer 20, executes a restoration operation in the same operation as the control signal receiving circuit 31, and transmits a verification signal. A continuous pulse signal for transmission is executed by executing a conversion operation in the same operation as the circuit 33, performing isolated transmission in the same operation as the second transformer 40, and executing a restoration operation in the same operation as the verification signal receiving circuit 12. The comparison signal H is generated from B.
With this configuration, the comparison signal H can be generated by simulating the actual insulation operation, restoration operation, and conversion operation, so that the delay time can be compensated more accurately in consideration of the environment and changes over time.

Although the present invention has been described above with specific embodiments, it goes without saying that the above-described embodiment is an example and can be modified and implemented without departing from the spirit of the present invention.

1 Power semiconductor drive circuit device 2 Microcomputer 3 Power semiconductor 10 Transmission side device 11 Control signal transmission circuit 12 Verification signal reception circuit 13 Comparison signal generation circuit 14 Signal comparison circuit 20 First transformer 30 Reception side device 31 Control signal reception circuit 32 Drive circuit 33 Verification signal transmission circuit 40 Second transformer

Claims (1)

A power semiconductor drive circuit device that drives a power semiconductor on the secondary side by insulatingly transmitting a control signal input to the primary side to the secondary side.
A control signal transmission circuit that receives the control signal input to the primary side as an input control signal and converts it into a continuous pulse signal for transmission that can be isolated and transmitted.
A first transformer that insulates and transmits the continuous pulse signal for transmission from the primary side to the secondary side, and
A control signal receiving circuit that restores the transmission continuous pulse signal isolated and transmitted to the secondary side to the control signal and outputs the restored control signal as an output control signal to the power semiconductor.
A verification signal transmission circuit that converts the output control signal into a continuous pulse signal for feedback that can be isolated and transmitted as a verification signal.
A second transformer that insulates and transmits the feedback continuous pulse signal from the secondary side to the primary side,
A verification signal receiving circuit that restores the feedback continuous pulse signal isolated and transmitted to the primary side to the verification signal, and
A comparison signal generation circuit that generates a comparison signal from the transmission continuous pulse signal in consideration of the delay time of the first transformer, the control signal reception circuit, the verification signal transmission circuit, the second transformer, and the verification signal reception circuit. ,
A signal comparison circuit that detects an error by comparing the verification signal restored by the verification signal receiving circuit with the comparison signal generated by the comparison signal generation circuit is provided .
The comparison signal generation circuit performs isolated transmission in the same operation as the first transformer by a pseudo first transformer having the same configuration as the first transformer, and the pseudo control signal receiving circuit having the same configuration as the control signal receiving circuit. The restoration operation is executed in the same operation as the control signal receiving circuit, the conversion operation is executed in the same operation as the verification signal transmitting circuit by the pseudo verification signal transmitting circuit having the same configuration as the verification signal transmitting circuit, and the second transformer is used. Insulation transmission is performed by the pseudo second transformer having the same configuration as the second transformer in the same operation as the second transformer, and the restoration operation is performed by the pseudo verification signal receiving circuit having the same configuration as the verification signal receiving circuit in the same operation as the verification signal receiving circuit. A power semiconductor drive circuit device, characterized in that the comparison signal is generated from the continuous pulse signal for transmission by executing the above .

Images