JP6821317B2 - Semiconductor circuit - Google Patents

Description

The present invention relates to semiconductor circuits.

Semiconductor circuits are used in capacitive loads such as discharge tubes, inverters and converters for driving inductive loads such as transformers, inductors, and motors, or power supply circuits such as step-up, step-down, and buck-boost converters.

A semiconductor circuit is configured by using a power transistor such as a FET (Field Effect Transistor) or an IGBT. In applications that require high power, it is common to use multiple packages containing power transistors or diodes connected in parallel.

FIG. 1 is a layout diagram of a conventional semiconductor circuit 2. The plurality of semiconductor packages 10 are mounted on the printed circuit board 12, and a heat sink is attached to the rectangular region 14 including the plurality of semiconductor packages 10. Here, five semiconductor packages 10_1 to 10_5 are connected in parallel. The outputs (drains or sources) of the plurality of semiconductor packages 10 are connected to one output terminal 18 via wiring. Further, the gate terminals of the plurality of semiconductor packages 10 are also connected to the common driver 16 via wiring.

JP 2015-100029

When the heat sink 20 and the semiconductor package 10 are forcibly air-cooled by using the cooling fan 30, the plurality of semiconductor packages 10 are often arranged in a straight line in a direction orthogonal to the direction of the wind. However, when the semiconductor packages 10 are arranged in a straight line, the distance between the plurality of semiconductor packages 10 and the common gate driver becomes non-uniform, or the distance between the plurality of semiconductor packages 10 and the common output terminal becomes non-uniform. turn into. In addition, the positions of the output terminal 18 and the driver 16 are also restricted.

As a result, the switching timing, slew rate, switching speed, and the like of the plurality of semiconductor packages 10 vary, making it difficult to uniformly operate the plurality of transistors, which causes current concentration and the like.

Further, in the conventional design method, when laying out many semiconductor packages, the mounting area may become large. This problem becomes remarkable especially when cooling is considered.

The present invention has been made in view of such a problem, and one of the exemplary purposes of the embodiment is to provide a semiconductor circuit capable of solving any of the above problems.

A semiconductor circuit of an aspect of the present invention comprises three or more electrically connected semiconductor packages in parallel. The plurality of semiconductor packages are laid out in a non-linear manner on the printed circuit board.
According to this aspect, the degree of freedom in layout of a plurality of semiconductor packages, common nodes (or circuits) on the printed circuit board connected to them, wiring, etc. is increased, and the operation uniformity of the plurality of semiconductor packages is improved. It can be increased, or the mounting density can be increased. This effect becomes more remarkable as the number of semiconductor packages increases to more than three.

Multiple semiconductor packages are laid out so that the distance between each corresponding terminal and a common node on the printed circuit board is more uniform than when laid out in a straight line in the horizontal or vertical direction in the same rectangular area. You may.

The plurality of semiconductor packages may be laid out so that a larger number of semiconductor packages can be arranged in the same rectangular region than when they are laid out in a straight line in the horizontal direction or the vertical direction. As a result, the size of the heat sink can be reduced when a plurality of semiconductor packages are laid out in contact with the heat sink.

The orientation of the plurality of semiconductor packages may be gradually changed. By changing the orientation, the distance from the corresponding terminal (pin) of each of the plurality of semiconductor packages to the common node connected to them can be further made uniform. Further, the number of semiconductor packages that can be arranged in the same rectangular region can be increased, in other words, the size of the heat sink can be reduced.

The plurality of semiconductor packages may be laid out on a curved line. The plurality of semiconductor packages may be laid out in an arc shape.

The relative positional relationship between the i-th (i is a natural number) semiconductor package and the (i + 1) th semiconductor package is the relative positional relationship between the (i + 1) th semiconductor package and the (i + 2) th semiconductor package. It may be equal to the positional relationship. As a result, the positions of the plurality of semiconductor packages 102 can be determined according to a predetermined arithmetic expression or routine (procedure).

It should be noted that any combination of the above components or components and expressions of the present invention that are mutually replaced between methods, devices, systems, and the like are also effective as aspects of the present invention.

According to an aspect of the present invention, it is possible to solve a problem that occurs in a semiconductor circuit including a plurality of semiconductor packages.

It is a layout diagram of a conventional semiconductor circuit. FIG. 2A is a plan layout view of the semiconductor circuit according to the embodiment, and FIG. 2B is a sectional view thereof. It is a figure which shows the state which a plurality of semiconductor packages are laid out in a straight line in a horizontal direction in the same mounting area as FIG. It is a figure which shows the state which a plurality of semiconductor packages are laid out in a straight line in a horizontal direction in the same mounting area as FIG. It is a figure explaining the design procedure of the layout of a semiconductor package. 6 (a) to 6 (d) are diagrams for explaining the use of the semiconductor circuit. 7 (a) and 7 (b) are diagrams showing a modified example of the layout.

Hereinafter, the present invention will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. Further, the embodiment is not limited to the invention but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

FIG. 2A is a plan layout view of the semiconductor circuit 100 according to the embodiment, and FIG. 2B is a sectional view thereof. The semiconductor circuit 100 includes a plurality of semiconductor packages 102_1 to 102_M that are electrically connected in parallel. Although the case of M = 7 is shown in FIG. 2, the number thereof is not particularly limited. The plurality of semiconductor packages 102 are mounted on the printed circuit board 104. A heat sink 110 is attached to a position on the back surface of the printed circuit board 104 that overlaps with the mounting areas 106 of the plurality of semiconductor packages 102.

In the present embodiment, the semiconductor package 102 is a FET (or IGBT) having a drain pin (D), a source pin (S), and a gate pin (G), and is a TO (Transistor Outline) -247 package. The invention is not limited thereto.

As described above, the plurality of semiconductor packages 102 are electrically connected in parallel. Therefore, the gates of the plurality of semiconductor packages 102 are connected to the common gate driver 120, and their drains are connected to the common output node 122.

The plurality of semiconductor packages 102 are laid out on a non-linear line. For example, the plurality of semiconductor packages 102 may be laid out on a curved line, or more preferably in an arc shape as shown in FIG. The "arc shape" is not limited to a perfect circular or elliptical arc shape, but may be a shape similar to the arc shape, for example, a parabola or another geometric shape.

By allowing the layout on a non-linear line, the degree of freedom in the layout of the plurality of semiconductor packages can be increased, and the uniformity of operation of the plurality of semiconductor packages can be improved or the mounting area can be reduced.

When laying out the plurality of semiconductor packages 102, it is desirable to consider at least one of the following two design conditions.

(First design condition)
FIG. 3 shows a state in which a plurality of semiconductor packages 102 are laid out in a straight line in the vertical direction or the horizontal direction (here, the horizontal direction) in the same rectangular area (mounting area 106) as in FIG.

In the first design condition, attention is paid to the distance of the path on the input side or the output side of the semiconductor package 102. Specifically, in the plurality of semiconductor packages 102, the distances L _{1 to} L ₇ between the corresponding terminals (here, the drain) and the common node (here, the output node 122) on the printed circuit board 104 are as shown in FIG. as uniform as compared with the distance L _{1 '~L} 7' when the layout is laid.

Alternatively, in the plurality of semiconductor packages 102, when the distances l _{1 to} l ₇ between the corresponding terminals (here, the gate) and the common node (gate driver 120) on the printed circuit board 104 are laid out as shown in FIG. distance l ₁ so as to be uniform in comparison with 'to l _7', it is laid.

Note that in FIG. 3, even if the output node 122 is at the position of the broken line 123, the layout of FIG. 2 is superior in the uniformity of the line L on the output side. Similarly, in FIG. 3, even if the gate driver 120 is at the position of the broken line 121, it should be noted that the layout of FIG. 2 is superior in terms of uniformity.

In the comparison between FIGS. 3 and 2, both the distance l on the gate driver side and the distance L on the output node side are improved, but only one of them may be improved.

According to the first design condition, the uniformity of operation of the plurality of semiconductor packages 102 can be improved.

Even if a plurality of semiconductor packages 102 are arranged in a matrix, the non-uniform distance between the paths on the input side or the output side is not eliminated. Therefore, when the first design condition is taken into consideration, the arrangement in the matrix is also possible. Not suitable.

(Second design condition)
FIG. 4 shows a state in which a plurality of semiconductor packages 102 are laid out in a straight line in the vertical direction or the horizontal direction (here, the horizontal direction) in the same rectangular area (mounting area 106) as in FIG. In this layout, only five semiconductor packages 102_1 to 102_7 can be laid out in the mounting area 106, and a wider mounting area 107 is required for all seven mountings.

In the second design condition, attention is paid to the number of semiconductor packages 102. Specifically, the plurality of semiconductor packages 102 are laid out so as to be larger than when laid out as shown in FIG. 4 (that is, 5 pieces).

According to the second design condition, the number of semiconductor packages 102 that can be mounted in the same area can be increased. Therefore, the size of the semiconductor circuit can be reduced. The size of the printed circuit board 104 and the heat sink 110 is defined according to the area of the mounting area 106 of the semiconductor package 102. By laying out the required number of semiconductor packages 102 in the smallest possible mounting area, the size of the printed circuit board 104 and the heat sink 110 can be reduced. As a result, the cost can be reduced or the degree of freedom in layout can be increased.

From the viewpoint of the number, the number is the maximum when arranged in a matrix. However, when arranged in a matrix, it becomes difficult to apply cooling wind to the semiconductor packages 102 near the center of the matrix or near the downstream of the wind, and since the plurality of semiconductor packages 102 have a heat distribution, uniform operation is difficult. Become. On the other hand, according to the layout of FIG. 2, since all the semiconductor packages 102 can receive the cooling air, uniform operation is guaranteed from the viewpoint of heat.

In the present embodiment, the orientations of the plurality of semiconductor packages 102 are gradually changed in order to more satisfy the first and second design conditions.

The orientation of the semiconductor package 102 is defined as an angle θ _i formed by the center line 103 of the semiconductor package 102_i and a reference line (here, the X axis parallel to one side E2 of the mounting region 106). When M semiconductor packages 102 are mounted, the angle θ _i of the i-th (1 ≦ i ≦ M) semiconductor package 102_i is
θ _i = (i-1) × 90 ° / (M-1)… (1)
It may be. In the example of FIG. 2, M = 7, and the angles of each gate driver 120 are as follows.
θ ₁ = 0 °
θ ₂ = 15 °
θ ₃ = 30 °
θ ₄ = 45 °
θ ₅ = 60 °
θ ₆ = 75 °
θ ₇ = 90 °

Alternatively, a constant K larger than the number M of the semiconductor packages 102 to be mounted is defined.
θ _i = (i-1) × 90 ° / (K-1)… (2)
In this way, θ ₁ to θ _M may be determined.

The formula (1) or (2) represents that the angle formed by the center line and the reference line of the semiconductor package 102 increases at equal intervals.

In the present embodiment, more specifically, the relative positional relationship between the i-th (i is a natural number) semiconductor package 102_i and the (i + 1) th semiconductor package 102_ (i + 1) is the (i + 1) th. The layout is made so as to be equal to the relative positional relationship between the semiconductor package 102_ (i + 1) and the (i + 2) th semiconductor package 102_ (i + 2). As a result, the positions of the plurality of semiconductor packages 102 can be determined according to a predetermined arithmetic expression or procedure as described below.

FIG. 5 is a diagram illustrating a layout design procedure of the semiconductor package 102. The origin is an arbitrary point (for example, lower left) in the mounting area, the horizontal direction is the X-axis, and the vertical direction is the Y-axis.
In the vicinity of the origin, it defines the first point P _1. The first point P ₁ is the coordinates of the lower left vertex of the first semiconductor package 102. The i-th point _Pi is the coordinates of the lower left vertex of the i-th semiconductor package 102.

Subsequently, the second point P ₂ is set at a point shifted from the first point P ₁ by a predetermined amount δX in the X direction and a predetermined amount δY in the Y direction. Transfer the origin to the second point P _2, a clockwise coordinate axis around the origin, is rotated 15 °, to define a new coordinate system (X'Y '). On new coordinate axes (X'Y '), a predetermined amount δX in the X direction, in that by a predetermined amount δY shifted in the Y direction, taking the third point P ₃ below. Similarly transferred the origin to the third point P _3, clockwise coordinate axes (X'Y ') about the origin, is rotated 15 °, to define a new coordinate system (X "Y"). On new coordinate axes (X "Y"), a predetermined amount δX in the X direction, in that by a predetermined amount δY shifted in the Y direction, taking the fourth point P ₄ follows. By repeating this work, the layout of the plurality of semiconductor packages 102 can be determined.

Subsequently, a specific example of the semiconductor circuit 100 will be described. 6 (a) to 6 (d) are diagrams for explaining the use of the semiconductor circuit 100. The semiconductor circuit of FIG. 6A is a three-phase converter or an inverter. A plurality of semiconductor packages 102 are configured for each of the upper arm switches MHU, MHV, MHW and the lower arm switches MLU, MLV, and MLW.

The semiconductor circuit of FIG. 6B is an H-bridge circuit. A plurality of semiconductor packages 102 are configured for each of the upper arm switches MHP and MHN and the lower arm switches MLP and MLN.

The semiconductor circuit of FIG. 6C is a step-up (step-up / down) converter. Each of the switches M1 and M2 is composed of a plurality of semiconductor packages 102. The semiconductor circuit of FIG. 6D is a buck converter. The switch M3 is composed of a plurality of semiconductor packages 102. The rectifier diode D3 is also composed of a plurality of semiconductor packages 102.

The present invention has been described above based on some embodiments. It will be appreciated by those skilled in the art that these embodiments are exemplary and that various modifications are possible for each of these components and combinations of processing processes, and that such modifications are also within the scope of the present invention. By the way. Hereinafter, such a modification will be described.

7 (a) and 7 (b) are diagrams showing a modified example of the layout. In FIG. 7A, a plurality of semiconductor packages 102 are arranged along a perfect arc. In this case, the distance between the node 130 and the pins of the plurality of semiconductor packages 102 is completely uniform.

FIG. 7B has a layout similar to that of FIG. 2A, but the orientations of the semiconductor packages 102 are the same.

100 ... semiconductor circuit, 102 ... semiconductor package, 104 ... printed circuit board, 106 ... mounting area, 110 ... heat sink, 120 ... gate driver, 122 ... output node.

Claims (7)

It has three or more semiconductor packages that are electrically connected in parallel.
The semiconductor circuit is characterized in that the plurality of semiconductor packages are laid out in a non-linear manner on a rectangular printed circuit board so that each of the plurality of semiconductor packages is forcibly air-cooled by receiving wind from the same fan. The plurality of semiconductor packages are laid out so that the distance between each corresponding terminal and a common node on the printed circuit board is more uniform than when the plurality of semiconductor packages are laid out in a straight line in the horizontal or vertical direction in the same rectangular area. The semiconductor circuit according to claim 1, wherein the semiconductor circuit is provided. Claim 1 or 2 is characterized in that the plurality of semiconductor packages are laid out so that a larger number of semiconductor packages can be arranged in the same rectangular region than when they are laid out in a straight line in the horizontal direction or the vertical direction. The semiconductor circuit described in. The semiconductor circuit according to any one of claims 1 to 3, wherein the orientation of the plurality of semiconductor packages is gradually changing. The semiconductor circuit according to any one of claims 1 to 4, wherein the plurality of semiconductor packages are laid out on a curved line. The semiconductor circuit according to any one of claims 1 to 5, wherein the plurality of semiconductor packages are laid out in an arc shape. The relative positional relationship between the i-th (i is a natural number) semiconductor package and the (i + 1) th semiconductor package is the relative position between the (i + 1) th semiconductor package and the (i + 2) th semiconductor package. The semiconductor circuit according to any one of claims 1 to 6, wherein the semiconductor circuit has the same positional relationship.

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