JP6816615B2 - Insulated gate bipolar transistor - Google Patents

Description

The techniques disclosed herein relate to insulated gate bipolar transistors. In the following, the insulated gate bipolar transistor will be referred to as an IGBT (insulated gate bipolar transistor).

The IGBT described in Patent Document 1 has a plurality of trenches. A gate insulating film and a gate electrode are arranged in each trench. Further, an n-type emitter region is arranged in each range (hereinafter, referred to as an inter-trench range) between two adjacent trenches at intervals. A plurality of emitter regions are arranged in the range between each trench. Each emitter region extends from a position in contact with one gate insulating film to a position in contact with the other gate insulating film in a range in contact with the emitter electrode. Within each trench range, a plurality of emitter regions are spaced apart in the longitudinal direction of the trench. In each range between two adjacent emitter regions at intervals, a p-shaped body region is in contact with the emitter electrode. The body region extends below each emitter region, separating each emitter region from each other. An n-type drift region and a p-type collector region are arranged below the body region.

Japanese Unexamined Patent Publication No. 2015-176891

When a potential equal to or higher than the threshold value is applied to the gate electrode, the IGBT is turned on. That is, electrons flow from the emitter region to the collector region via the channel (inverted layer formed in the body region) and the drift region. In addition, holes flow from the collector area to the drift area. The holes flow from the drift region through the body region to the emitter electrode. As the holes flow from the collector region into the drift region, the concentration of the holes in the drift region increases and the resistance in the drift region decreases. Therefore, the electrons pass through the drift region with low loss.

When the potential of the gate electrode is lowered to a potential lower than the threshold value, the channel disappears and the flow of electrons is stopped. Further, the holes existing in the drift region are discharged to the emitter electrode via the body region. Therefore, a current due to the discharge of holes flows through the IGBT for a short time immediately after the potential of the gate electrode is lowered.

Further, in the manufacturing process of the IGBT, a minute foreign substance may adhere to a part of the surface of the semiconductor substrate. Foreign matter can increase the resistance of the interface between the body region and the emitter electrodes.

As in Patent Document 1, in an IGBT in which a plurality of emitter regions extending from a position in contact with one gate insulating film to a position in contact with the other gate insulating film are arranged at intervals in a range between trenches, foreign matter adheres. There is a problem that latch-up is likely to occur. FIG. 14 shows a state in which the foreign matter 120 is attached to this type of IGBT as an example. Note that FIG. 14 shows an emitter region 102a to 102c, a body region 104, a drift region 106, a collector region 108, an emitter electrode 110, and a collector electrode 112. FIG. 14 shows a cross section obtained by cutting a trench-to-trench range between two trenches (not shown) arranged at intervals in the x-direction along the longitudinal direction (y-direction) of each trench. In FIG. 14, the surface of the body region 104 is covered with the foreign matter 120 in the range 130 between the emitter region 102a and the emitter region 102b. In the range 130 where the foreign matter 120 is present, the resistance at the interface between the body region 104 and the emitter electrode 110 is extremely high, and the body region 104 is substantially insulated from the emitter electrode 110. When the IGBT of FIG. 14 is turned off, the holes existing in the drift region 106 are discharged to the emitter electrode 110 via the body region 104. At this time, the hole that has flowed from the drift region 106 into the body region 104 directly below the foreign matter 120 cannot flow toward the emitter electrode 110 within the range 130. Therefore, such a hole flows laterally in the body region 104, passes under the emitter region 102b, and is discharged to the emitter electrode 110 in the range 132 adjacent to the range 130. A potential difference occurs in the path through which the holes flow laterally within the body region 104. Therefore, the potential of the body region 104 directly below the foreign matter 120 is higher than that of the surrounding body region 104. When the potential of the body region 104 directly below the foreign matter 120 becomes high, a voltage is applied in the forward direction to the pn junction at the interface between the body region 104 directly below the foreign matter 120 and the emitter region 102a (or the emitter region 102b). This voltage makes it easy for holes to flow from the body region 104 to the emitter region 102b. When a hole flows from the body region 104 into the emitter region 102b, the IGBT latches up and the IGBT cannot be controlled by the gate potential.

Therefore, the present specification provides a technique for suppressing latch-up in the IGBT in which the emitter region is arranged as described above.

The IGBT disclosed in the present specification is arranged in the semiconductor substrate, the first trench provided on the surface of the semiconductor substrate, the first trench, and is insulated from the semiconductor substrate by the first gate insulating film. The first gate electrode is provided, the second trench is provided on the surface of the semiconductor substrate along the first trench and is arranged at a distance from the first trench, and the inside of the second trench. A second gate electrode arranged in the semiconductor substrate and insulated from the semiconductor substrate by a second gate insulating film, and a second gate electrode arranged on the surface and insulated from the first gate electrode and the second gate electrode. Has an emitter electrode. The semiconductor substrate has a plurality of emitter regions, a plurality of body contact regions, a high-concentration body region, a low-concentration body region, and a drift region. The plurality of emitter regions are arranged between the first trench and the second trench, and are in contact with the second gate insulating film from a position in contact with the first gate insulating film in a range in contact with the emitter electrode. It extends to, and is arranged at intervals in the longitudinal direction of the first trench. The plurality of body contact regions are p-type regions that are in contact with the emitter electrodes in each range between the emitter regions that are adjacent to each other at intervals. The high-concentration body region extends along the longitudinal direction so as to be in contact with the plurality of emitter regions and the plurality of body contact regions from below, and has a higher p-type impurity concentration than the body contact regions. It is a p-type region. The low-concentration body region is in contact with the first gate insulating film and the second gate insulating film under the plurality of emitter regions, and is a p-type region having a lower p-type impurity concentration than the body contact region. is there. The drift region is an n-type region that is in contact with the first gate insulating film and the second gate insulating film below the low-concentration body region.

In this IGBT, the body region has a body contact region, a low-concentration body region, and a high-concentration body region. Foreign matter adhering to the surface of the semiconductor substrate may cover one of the body contact areas. In this case, the hole that has flowed into the body region directly under the foreign matter when the IGBT is turned off cannot flow from the body contact region covered with the foreign matter to the emitter electrode, and thus is inside the body region toward the adjacent body contact region. Flows laterally and is discharged from the adjacent body contact region to the emitter electrode. At this time, the hole flows to the adjacent body contact region through the high-concentration body region extending along the longitudinal direction of the trench so as to be in contact with the plurality of emitter regions and the plurality of body contact regions from below. .. Since the concentration of p-type impurities in the high concentration body region is high, the resistance in the high concentration body region is lower than the resistance in the low concentration body region. Therefore, even if the holes flow laterally in the high-concentration body region, almost no potential difference occurs in the high-concentration body region. Therefore, the potential of the body region directly under the foreign matter does not become so high. Therefore, it is difficult for holes to flow into the emitter region from the body region directly under the foreign matter. Therefore, latch-up is unlikely to occur in this IGBT.

Top view of the IGBT of the embodiment. Sectional view of the IGBT of Embodiment (cross-sectional view taken along line II-II of FIG. 1). Sectional view of the IGBT of the embodiment (cross-sectional view taken along the line III-III of FIG. 1). Sectional view of the IGBT of Embodiment (cross-sectional view taken along line IV-IV of FIG. 1). Cross-sectional view of the IGBT of the embodiment (cross-sectional view taken along the line VV of FIG. 1). The cross-sectional view of the IGBT of the embodiment when a foreign substance adheres. The equivalent circuit diagram of the IGBT of the embodiment. The explanatory view of the manufacturing method of the IGBT of an embodiment. The explanatory view of the manufacturing method of the IGBT of an embodiment. The explanatory view of the manufacturing method of the IGBT of an embodiment. The explanatory view of the manufacturing method of the IGBT of an embodiment. The explanatory view of the manufacturing method of the IGBT of an embodiment. The explanatory view of the manufacturing method of the IGBT of an embodiment. Sectional drawing of the IGBT of the comparative example. The equivalent circuit diagram of the IGBT of the comparative example.

1 to 5 show the semiconductor device 10 of the embodiment. As shown in FIGS. 2 to 5, the semiconductor device 10 includes a semiconductor substrate 12, an emitter electrode 60, and a collector electrode 62. The emitter electrode 60 covers the upper surface 12a of the semiconductor substrate 12. The collector electrode 62 covers the lower surface 12b of the semiconductor substrate 12. In FIG. 1, the emitter electrode 60 is not shown, and the structure of the upper surface 12a of the semiconductor substrate 12 is shown. Further, in the following description, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, the direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as the y direction, and the thickness direction of the semiconductor substrate 12 is the z direction. That is.

As shown in FIGS. 1 to 3, a plurality of trenches 40 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 1, each trench 40 extends long in the y direction on the upper surface 12a. The trenches 40 are parallel to each other and are spaced apart in the x direction. In the following, the range of the semiconductor substrate 12 sandwiched between two adjacent trenches 40 at intervals is referred to as an inter-trench range 18. The inner surface of each trench 40 is covered with a gate insulating film 42. A gate electrode 44 is arranged in each trench 40. The gate electrode 44 is insulated from the semiconductor substrate 12 by the gate insulating film 42. As shown in FIGS. 2 and 3, the upper surface of the gate electrode 44 is covered with the interlayer insulating film 46. The interlayer insulating film 46 is covered with an emitter electrode 60. The gate electrode 44 is insulated from the emitter electrode 60 by an interlayer insulating film 46.

As shown in FIGS. 1 to 5, the semiconductor substrate 12 has an emitter region 20, a body region 22, a drift region 26, a buffer region 30, and a collector region 32.

The emitter region 20 is an n-type region. As shown in FIGS. 1, 2, 4 and 5, a plurality of emitter regions 20 are provided in each trench range 18. Each emitter region 20 is exposed on the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the emitter electrode 60. As shown in FIGS. 1 and 2, each emitter region 20 extends from one of the two trenches 40 sandwiching the inter-trench range 18 to the other at a position in contact with the emitter electrode 60. That is, each emitter region 20 extends from a position in contact with the gate insulating film 42 in one trench 40 to a position in contact with the gate insulating film 42 in the other trench 40. As shown in FIGS. 1, 4 and 5, in each trench range 18, a plurality of emitter regions 20 are arranged at intervals in the y direction (that is, the longitudinal direction of the trench 40).

The body region 22 is a p-type region. The body region 22 has a body contact region 22a, a low-concentration body region 22b, and a high-concentration body region 22c.

As shown in FIGS. 1, 3 and 4, a plurality of body contact regions 22a are provided in each trench range 18. Each body contact region 22a is exposed on the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the emitter electrode 60. As shown in FIGS. 1 and 2, each body contact region 22a is provided at the central portion of the inter-trench range 18 in the x direction and is not in contact with each trench 40. As shown in FIGS. 1 and 4, each body contact region 22a is arranged in a range between adjacent emitter regions 20 at intervals in the y direction. That is, as shown in FIG. 1, in the central portion of the intertrench range 18 in the x direction, the body contact region 22a and the emitter region 20 are arranged so as to appear alternately and repeatedly along the y direction.

As shown in FIGS. 2 to 4, a high-concentration body region 22c is provided in each trench range 18. One high concentration body region 22c is provided in each trench range 18. The high concentration body region 22c has a higher p-type impurity concentration than the body contact region 22a. Therefore, the resistance of the high concentration body region 22c is lower than the resistance of the body contact region 22a. Each high-concentration body region 22c is arranged below the emitter region 20 and the body contact region 22a. As shown in FIGS. 2 and 3, each high-concentration body region 22c is provided in the central portion of the inter-trench range 18 in the x direction and is not in contact with each trench 40. As shown in FIG. 4, each high-concentration body region 22c extends long in the y direction. The high-concentration body region 22c is in contact with each of the emitter region 20 and the body contact region 22a, which are alternately and repeatedly arranged along the y direction, from below.

As shown in FIGS. 1 to 5, a low-concentration body region 22b is provided in each trench range 18. The low concentration body region 22b has a lower p-type impurity concentration than the body contact region 22a. Therefore, the resistance of the low concentration body region 22b is higher than the resistance of the body contact region 22a. As shown in FIGS. 1 and 3, the low-concentration body region 22b is exposed on the upper surface 12a of the semiconductor substrate 12 in a range where the emitter region 20 and the body contact region 22a do not exist. The low-concentration body region 22b is exposed on the upper surface 12a of the semiconductor substrate 12 in a range adjacent to the trench 40. The low-concentration body region 22b is in contact with the emitter electrode 60. As shown in FIG. 2, the low-concentration body region 22b is distributed below the emitter region 20 and the high-concentration body region 22c. The low-concentration body region 22b is in contact with the emitter region 20 and the high-concentration body region 22c from below. The low-concentration body region 22b is below the emitter region 20 and is in contact with the gate insulating films 42 on both sides of the inter-trench range 18. Further, as shown in FIG. 3, the low-concentration body region 22b is in contact with the gate insulating film 42 in the entire depth range of the low-concentration body region 22b at a position where the emitter region 20 does not exist.

The drift region 26 is an n-type region having a lower n-type impurity concentration than the emitter region 20. As shown in FIGS. 2-5, the drift region 26 is arranged below the low concentration body region 22b. The drift region 26 is distributed over the lower part of the plurality of inter-trench ranges 18. The drift region 26 is in contact with each gate insulating film 42 below each low-concentration body region 22b. The drift region 26 is separated from the emitter region 20, the body contact region 22a, and the high density body region 22c by the low density body region 22b.

The buffer region 30 is an n-type region having a higher n-type impurity concentration than the drift region 26. As shown in FIGS. 2 to 5, the buffer area 30 is arranged below the drift area 26.

The collector area 32 is a p-type area. As shown in FIGS. 2 to 5, the collector area 32 is arranged below the buffer area 30. The collector region 32 is exposed on the lower surface 12b of the semiconductor substrate 12 and is in ohmic contact with the collector electrode 62.

When the IGBT 10 is used, a potential higher than that of the emitter electrode 60 is applied to the collector electrode 62. When a potential equal to or higher than the threshold value is applied to the gate electrode 44, a channel is formed in the low-concentration body region 22b in the range in contact with the gate insulating film 42, and the emitter region 20 and the drift region 26 are connected by the channel. Then, electrons flow from the emitter electrode 60 to the collector electrode 62 via the emitter region 20, the channel, the drift region 26, the buffer region 30, and the collector region 32. Further, a hole flows from the collector electrode 62 into the drift region 26 via the collector region 32 and the buffer region 30. The hole that has flowed into the drift region 26 flows to the emitter electrode 60 via the body region 22. As the holes flow from the collector region 32 into the drift region 26, the density of the holes in the drift region 26 increases and the resistance of the drift region 26 decreases. Therefore, the electrons can pass through the drift region 26 with low loss. In this way, the IGBT 10 is turned on.

When the potential of the gate electrode 44 is lowered to a potential lower than the threshold value, the channel disappears and the flow of electrons is stopped. That is, the IGBT 10 is turned off. At this time, the holes existing in the drift region 26 are discharged to the emitter electrode 60 via the low-concentration body region 22b, the high-concentration body region 22c, and the body contact region 22a, as shown by the arrows in FIG.

FIG. 6 shows a state in which the foreign matter 90 is attached to the upper surface 12a of the semiconductor substrate 12 in the IGBT 10 of the embodiment. The foreign matter 90 adheres to the upper surface 12a of the semiconductor substrate 12 during the manufacturing process of the IGBT 10. The surface of the foreign matter 90 is covered with the emitter electrode 60. In the example of FIG. 6, one area surrounded by the trench 40 and the emitter area 20 (one area in which the body contact area 22a and the low-concentration body area 22b are exposed on the upper surface 12a) is covered with the foreign matter 90. ..

When the foreign matter 90 is attached as shown in FIG. 6, the body contact region 22a is insulated from the emitter electrode 60 in the range covered with the foreign matter 90. Therefore, when the IGBT 10 is turned off, the hole that has flowed into the body region 22 directly below the foreign matter 90 cannot flow from the body contact region 22a above the foreign matter 90 to the emitter electrode 60. Therefore, as shown by the arrow in FIG. 6, the hole flows in the body region 22 along the y direction and is discharged from the adjacent body contact region 22a to the emitter electrode 60. At this time, the resistance of the high-concentration body region 22c is low, and the high-concentration body region 22c extends from the lower part of the body contact region 22a covered with the foreign matter 90 to the lower part of the adjacent body contact region 22a. The holes flow through the high concentration body region 22c along the y direction. Since the resistance of the high-concentration body region 22c is low, when the hole flows in the high-concentration body region 22c, almost no potential difference occurs in the high-concentration body region 22c. Therefore, the potential of the lower body region 22 of the foreign matter 90 hardly rises, and the forward voltage applied to the pn junction at the interface where the lower body region 22 of the foreign matter 90 is in contact with the emitter region 20 is extremely small. Therefore, it is difficult for holes to flow into the emitter region 20 from the body region 22 below the foreign matter 90. Therefore, in the IGBT 10, latch-up is unlikely to occur.

The suppression of the latch-up described above will be described with reference to the circuit diagrams of FIGS. 7 and 15. FIG. 7 shows an equivalent circuit of the IGBT 10 of the embodiment, and FIG. 15 shows an equivalent circuit of the IGBT (IGBT of the comparative example) of FIG. In FIG. 7, the MOSFET (metal oxide semiconductor field effect transistor) 202 represents a MOSFET composed of an emitter region 20, a body region 22, a drift region 26, and a gate electrode 44. That is, the MOSFET 202 corresponds to the gate structure of the IGBT 10. In FIG. 7, transistor 204 represents an npn-type transistor composed of an emitter region 20, a body region 22, and a drift region 26. The source of the MOSFET 202 and the emitter of the transistor 204 are composed of a common emitter region 20, and the emitter region 20 is connected to the emitter electrode 60. The drain of the MOSFET 202 and the collector of the transistor 204 are configured in a common drift region 26. In FIG. 7, the transistor 206 represents a pnp type transistor composed of a body region 22, a drift region 26, and a collector region 32. The base of the transistor 204 and the collector of the transistor 206 are composed of a common body region 22. The collector of transistor 204 and the base of transistor 206 are configured by a common drift region 26. The emitter of the transistor 206 is composed of a collector region 32, and the collector region 32 is connected to the collector electrode 62. In FIG. 7, the resistance element 208 represents the resistance of the path through which the hole flows when the IGBT is turned off (see the arrows in FIGS. 4 and 6). The resistance of the resistance element 208 corresponds to the resistance of the body region 22. Further, the equivalent circuit of FIG. 15 also represents the IGBT of FIG. 14 in substantially the same manner as that of FIG. 7. In FIG. 15, the gate electrode G represents the gate electrode of the MOSFET 202 (that is, the gate electrode of the IGBT).

In the IGBTs of FIGS. 14 and 15, the body region 104 does not have a high concentration body region, and the body region 104 has a high resistance. Therefore, in the IGBTs of FIGS. 14 and 15, the resistance of the resistance element 208 increases as the path (see the arrow in FIG. 14) when the hole flows due to the adhesion of the foreign matter 120 becomes longer. Therefore, the potential of the body region 104 (base of the transistor 204) becomes high immediately under the foreign matter 120, and the base current easily flows through the transistor 204. When the base current flows through the transistor 204, the transistor 204 is turned on. Then, the base current also flows through the transistor 206, and the transistor 206 is turned on. When the transistors 204 and 206 are turned on, they continue to flow through the transistors 204 and 206 until the potential difference between the collector electrode 112 and the emitter electrode 110 becomes small. That is, the current cannot be controlled by the potential of the gate electrode G. That is, latch-up occurs. As described above, in the IGBTs of FIGS. 14 and 15, latch-up is likely to occur.

On the other hand, in the IGBT 10 of the embodiment, when the foreign matter 90 adheres as shown in FIG. 6, the hole flows in the high concentration body region 22c. Since the resistance of the high-concentration body region 22c is low, the resistance of the resistance element 208 of FIG. 7 does not increase so much even when the foreign matter 90 adheres. Therefore, it is difficult for the base current to flow through the transistor 204, and latch-up is unlikely to occur. As described above, according to the IGBT 10 of the present embodiment, latch-up can be suppressed.

8 to 13 show a step of forming a body contact region 22a and a high-concentration body region 22c in the manufacturing process of the IGBT 10 of the embodiment. 8, 10 and 12 show a cross section corresponding to FIG. 4, and FIGS. 9, 11 and 13 show a cross section corresponding to FIG. First, as shown in FIGS. 8 and 9, after forming the emitter region 20 and the low-concentration body region 22b, a mask 300 having an opening 302 is formed in a range where the body contact region 22a should be formed. Next, the p-type impurity is injected into the upper surface 12a of the semiconductor substrate 12 via the mask 300. Here, the p-type impurities are injected into the depth range near the upper surface 12a of the semiconductor substrate 12 (the depth range in which the body contact region 22a should be formed). Next, the mask 300 is removed. Next, the p-type impurities shown in FIGS. 10 and 11 are injected. Here, as shown in FIG. 11, the mask 310 is formed. The mask 310 has an opening 312 in a range where the high concentration body region 22c should be formed. The cross section shown in FIG. 10 is located in the opening 312 and is not covered by the mask 310. Next, the p-type impurity is injected into the upper surface 12a of the semiconductor substrate 12 via the mask 310. Here, the p-type impurities are injected into a range deeper than the depth range in which the p-type impurities are injected in FIGS. 8 and 9 (the depth range in which the high-concentration body region 22c should be formed). Further, here, the p-type impurities are injected at a higher concentration than the p-type impurity injection steps of FIGS. 8 and 9. Next, the mask 310 is removed and the semiconductor substrate 12 is heated. As a result, the p-type impurities injected into the semiconductor substrate 12 are activated. As a result, as shown in FIGS. 12 and 13, a body contact region 22a and a high-concentration body region 22c are formed.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in this specification or drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

10: Semiconductor device 12: Semiconductor substrate 18: Inter-trench range 20: Emitter region 22: Body region 22a: Body contact region 22b: Low-concentration body region 22c: High-concentration body region 26: Drift region 30: Buffer region 32: Collector region 40: Trench 42: Gate insulating film 44: Gate electrode 46: Interlayer insulating film 60: Emitter electrode 62: Collector electrode

Claims (1)

It is a manufacturing method of an insulated gate bipolar transistor.
The insulated gate bipolar transistor
With a semiconductor substrate
The first trench provided on the surface of the semiconductor substrate and
The first gate electrode, which is arranged in the first trench and is insulated from the semiconductor substrate by the first gate insulating film,
A second trench provided on the surface of the semiconductor substrate along the first trench and arranged at intervals from the first trench, and
A second gate electrode arranged in the second trench and insulated from the semiconductor substrate by the second gate insulating film,
An emitter electrode that is arranged on the surface and is insulated from the first gate electrode and the second gate electrode.
Have,
The semiconductor substrate
It is arranged between the first trench and the second trench, and extends from a position in contact with the first gate insulating film to a position in contact with the second gate insulating film in a range in contact with the emitter electrode. A plurality of n-type emitter regions arranged at intervals in the longitudinal direction of one trench,
A plurality of p-shaped body contact regions in contact with the emitter electrode in each range between the emitter regions adjacent to each other at intervals.
A p-type high-concentration body region that extends along the longitudinal direction so as to be in contact with the plurality of emitter regions and the plurality of body contact regions from below, and has a higher p-type impurity concentration than the body contact regions. When,
A p-type low-concentration body region that is in contact with the first gate insulating film and the second gate insulating film under the plurality of emitter regions and has a lower p-type impurity concentration than the body contact region.
An n-type drift region that is in contact with the first gate insulating film and the second gate insulating film below the low-concentration body region.
Have a,
The first step of injecting p-type impurities into the surface of the semiconductor substrate and
A second step of injecting p-type impurities into the surface of the semiconductor substrate at a concentration higher than that of the first step in a range deeper than the range in which the p-type impurities were injected in the first step.
By heating the semiconductor substrate, the high-concentration body region is formed in the range where the p-type impurity concentration is increased in the second step, and the p-type impurity is injected in the first step. The third step of forming the body contact region in a range shallower than the range in which the p-type impurity concentration increased in the second step,
Manufacturing method having.

Images