JP6810931B2 - A / D converter - Google Patents

Description

The present invention relates to an A / D converter.

An analog-to-digital converter (hereinafter referred to as an A / D converter) that converts an analog signal into a digital signal is widely used.

In addition, as a high-precision A / D converter with less malfunction due to manufacturing variations, a cyclic A / D converter that uses β conversion that encodes in non-binary (= β-ary, 1 <β <2). Alternatively, a β-conversion pipeline A / D converter in which a plurality of β-conversion cyclic A / D converters are connected in cascade is known (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2013-70255

FIG. 39 shows an example of the configuration of the β conversion pipeline A / D converter. In the example of FIG. 39, the β-conversion pipeline ADC (Analog to Digital Converter) 1 is digitally synthesized with a plurality of β-conversion cyclic ADCs 10-1 to 10-n (n is a natural number of 2 or more) connected in cascade. It has a + β value estimation unit 20.

The plurality of β-converted cyclic ADCs 10-1 to 10-n sample the input voltage Vin, and in order from the most significant bit, β-converted cyclic ADC10-1, β-converted cyclic ADC10-2, ..., β-converted cyclic ADC10-2. A / D conversion is performed using the click ADC 10-n.

The digital synthesis + β value estimation unit 20 estimates the value of β (1 <β <2) indicating the amplification factor of the operational amplifier included in each of the plurality of β-conversion cyclic ADCs 10-1 to 10-n. Further, the digital synthesis + β value estimation unit 20 synthesizes the A / D conversion results output from a plurality of β conversion cyclic ADCs 10-1 to 10-n using the estimated β values, and the β conversion pipeline. The digital output Dout, which is the result of A / D conversion of ADC1, is output.

In such a β-conversion pipeline ADC1, each of the plurality of β-conversion cyclic ADCs 10-1 to 10-n includes an operational amplifier. Generally, the current consumption of the operational amplifier is large, and it is necessary to keep the current flowing while the signal is amplified (calculated), which hinders the reduction of the power consumption of the β conversion pipeline ADC1.

The embodiment of the present invention has been made in view of the above problems, and a plurality of A / D conversion circuits including a β conversion cyclic type A / D conversion circuit are combined to cause a malfunction due to manufacturing variation. An object of the present invention is to provide an A / D converter having low power consumption.

The A / D converter (100) according to one embodiment of the present invention is an A / D converter (100) in which a plurality of A / D conversion methods are combined, and is a non-binary β-conversion cyclic type A /. The β is added to the A / D conversion circuit which is configured to include both the D conversion circuit (110) and the binary or lower sequential comparison type A / D conversion circuit (120) and is in charge of the A / D conversion in a predetermined bit range. The sequential comparison type A / D conversion circuit (110) is applied to the conversion cyclic type A / D conversion circuit (110), and the A / D conversion circuit is in charge of A / D conversion in a bit range lower than the predetermined bit range. 120) is applied, and the successive approximation type A / D conversion circuit (120) uses a capacitance array (1300) including a plurality of capacitance elements (C _{0 to} CN _-1 ) to obtain A in the lower bit range. The / D conversion is executed, and the β conversion cyclic type A / D conversion circuit (110) uses the capacitance array as an integrated capacitance to perform the A / D conversion in the predetermined bit range, and the β conversion. The sequential comparison type A / D conversion circuit converts the A / D conversion result of the predetermined bit range by the cyclic A / D conversion circuit (110) and the residual signal after the A / D conversion of the predetermined bit range. The A / D conversion result of the lower bit range obtained by A / D conversion in (120) is synthesized by the digital synthesizer (230), and the A / D converter (100) outputs the result. It is characterized by obtaining an A / D conversion result.

Preferably, the A / D converter (100) has a plurality of the capacitive arrays (1300), and the first capacitive array (1300-1) is used to perform the β-conversion cyclic A / D conversion. After the circuit (110) executes the A / D conversion of the predetermined bit range, the successive approximation type A / D conversion circuit (120) executes the A / D conversion of the lower bit range, and the first A second capacitive array (1300-2) different from the first capacitive array (1300-1) before the A / D conversion of the lower bit range using the capacitive array (1300-1) is completed. ) Is used to perform an interleave operation in which the β-conversion cyclic A / D conversion circuit (110) starts A / D conversion in the predetermined bit range.

Preferably, the A / D converter (100) is an A / D converter (100) that combines a plurality of A / D conversion methods, and is a non-binary β-conversion cyclic A / D conversion circuit. The β conversion cyclic to the A / D conversion circuit which is configured to include both (110) and a binary or lower sequential comparison type A / D conversion circuit (120) and is in charge of A / D conversion in a predetermined bit range. A type A / D conversion circuit (110) is applied, and the sequential comparison type A / D conversion circuit (120) is applied to the A / D conversion circuit in charge of A / D conversion in a bit range lower than the predetermined bit range. applied, the successive approximation a / D converter circuit (120) includes a plurality of capacitor array (1300) including a plurality of capacitive elements, with the first capacitor array (1300-1), the β transformation After the cyclic A / D conversion circuit (110) executes the A / D conversion of the predetermined bit range, the successive approximation type A / D conversion circuit (120) performs the A / D conversion of the lower bit range. Is executed, and before the A / D conversion of the lower bit range using the first capacitance array (1300-1) is completed, a second different from the first capacitance array (1300-1) is completed. using the capacitor array (1300-2), said had row interleaving operation β converting cyclic a / D converter circuit (110) starts the a / D conversion of the predetermined bit range, the β transformation Sai The sequential comparison type A / D conversion circuit (110) converts the A / D conversion result of the predetermined bit range and the residual signal after the A / D conversion of the predetermined bit range by the click type A / D conversion circuit (110). The A / D conversion result of the lower bit range obtained by A / D conversion in 120) is synthesized by the digital synthesizer (230), and the A output by the A / D converter (100) is output. It is characterized by obtaining a / D conversion result.

Preferably, one or more of the β-conversion cyclic A / D conversion circuits (110) included in the A / D converter (100) is the β-conversion cyclic A / D conversion circuit (110). It has an input circuit (SW7) that inputs a predetermined voltage to the input node.

Preferably, the A / D converter (100) includes a reference voltage Vref1 used in the β transformation cyclic A / D converter circuit (110), the successive approximation A / D converter circuit (120) the reference voltage Vref2 to be used, Vref2 ≧ Vref1 + Voff between the offset voltage Voff, between the β transformation cyclic a / D converter circuit (110) and the successive approximation a / D converter (120) It is a feature that Vref1 and Vref2 are set so that the relationship of is established.

Preferably, the A / D converter is connected to a signal comparison node Vx that is an input to the comparator (240) that compares the magnitude of the sequential comparison type A / D converter (120) with the reference voltage. It has a D / A conversion circuit (3301), and uses the output signal of the D / A conversion circuit (3301) to cancel the offset voltage of the sequential comparison type A / D conversion circuit (120). ..

Preferably, the A / D converter (100) has a signal generator (3501) for inputting a dither signal to the signal comparison node Vx of the sequential comparison type A / D converter (120).

Preferably, the A / D converter (100) averages a plurality of A / D conversion results by the successive approximation type A / D conversion circuit (120), and the sequential comparison type A / D conversion circuit (120). ) Has an average processing unit (3503) that improves the effective resolution.

Preferably, the A / D converter (100) has a bit length control unit (3402) that changes the bit length of the A / D conversion executed by the successive approximation type A / D conversion circuit (120).

Preferably, the β-conversion cyclic A / D conversion circuit (110) compares the comparison voltage to be compared with the threshold value, and outputs a digital value indicating the comparison result, and β. An arithmetic amplification unit (111) having an amplification factor of (1 <β <2) times and performing a predetermined calculation according to the comparison result of the comparator to generate the residual signal, and an input signal At the time of sampling, the switching unit (SW3) that outputs the input signal as the comparison voltage and outputs the residual signal as the comparison voltage after the sampling is completed, and the A / D converter that outputs a predetermined voltage. It has a β value estimation control unit (222) that estimates the β value using the result of A / D conversion in (100), and the digital synthesis unit (230) is the β conversion cyclic type. The β-ary A / D conversion result of the predetermined bit range by the A / D conversion circuit (110) is converted into binary by using the estimation result of the β value estimated by the β value estimation control unit (222). It is characterized in that the converted result and the A / D conversion result of the lower bit range by the sequential comparison type A / D conversion circuit (120) are combined and the binary A / D conversion result is output. ..

According to the present invention, it is possible to provide an A / D converter with less malfunction due to manufacturing variation and low power consumption by combining a plurality of A / D conversion circuits including a β conversion cyclic type A / D conversion circuit. it can.

It is a figure which shows the structural example of the A / D converter which concerns on one Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 1st Embodiment. It is a figure for demonstrating an example of operation of β conversion cyclic ADC. It is a figure (1) which shows the setting example of the switch of the β conversion cyclic ADC. It is a figure (2) which shows the setting example of the switch of the β conversion cyclic ADC. It is a flowchart which shows the example of the processing of the A / D converter which concerns on 1st Embodiment. It is a figure which shows the example of the processing timing of the A / D converter which concerns on 1st Embodiment. It is a figure (1) which shows the setting example of the switch of the A / D converter which concerns on 1st Embodiment. It is a figure (2) which shows the setting example of the switch of the A / D converter which concerns on 1st Embodiment. It is a figure (3) which shows the setting example of the switch of the A / D converter which concerns on 1st Embodiment. It is a figure (4) which shows the setting example of the switch of the A / D converter which concerns on 1st Embodiment. It is a figure (5) which shows the setting example of the switch of the A / D converter which concerns on 1st Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 2nd Embodiment. It is a figure which shows the example of the circuit structure of the capacitance array which concerns on 2nd Embodiment. It is a flowchart which shows the example of the processing of the A / D converter which concerns on 2nd Embodiment. It is a figure which shows the example of the processing timing of the A / D converter which concerns on 2nd Embodiment. It is a figure (1) which shows the setting example of the switch of the A / D converter which concerns on 2nd Embodiment. It is a figure (2) which shows the setting example of the switch of the A / D converter which concerns on 2nd Embodiment. It is a figure (3) which shows the setting example of the switch of the A / D converter which concerns on 2nd Embodiment. It is a figure (4) which shows the setting example of the switch of the A / D converter which concerns on 2nd Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 3rd Embodiment. It is a flowchart which shows the example of the processing of the A / D converter which concerns on 3rd Embodiment. It is a figure which shows the example of the processing timing of the A / D converter which concerns on 2nd Embodiment. It is a figure (1) which shows the setting example of the switch of the A / D converter which concerns on 3rd Embodiment. It is a figure (2) which shows the setting example of the switch of the A / D converter which concerns on 3rd Embodiment. It is a figure (3) which shows the setting example of the switch of the A / D converter which concerns on 3rd Embodiment. It is a figure (4) which shows the setting example of the switch of the A / D converter which concerns on 3rd Embodiment. It is a figure (5) which shows the setting example of the switch of the A / D converter which concerns on 3rd Embodiment. It is a figure (6) which shows the setting example of the switch of the A / D converter which concerns on 3rd Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 4th Embodiment. It is a figure which shows the example of the β conversion pipeline A / D converter which concerns on 4th Embodiment. It is a figure for demonstrating the reference voltage which concerns on 4th Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 5th Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 6th Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 7th Embodiment. It is a figure which shows the image of A / D conversion when the circuit has low noise. It is a figure which shows the image of A / D conversion when the circuit has high noise. It is a figure which shows the image of the A / D conversion when the circuit applies the dither signal with low noise. It is a figure which shows an example of the structure of the β conversion pipeline ADC.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

<A / D converter configuration>
FIG. 1 is a diagram showing a configuration example of an A / D converter according to an embodiment. The A / D converter (analog-digital converter) 100 is a device (or circuit) that converts an analog signal into a digital signal, and converts an analog input signal Vin into a digital signal Dout having a predetermined number of bits and outputs the signal. To do.

FIG. 1A shows an example of the A / D converter 100 according to the embodiment. The A / D converter 100 includes a β-conversion cyclic ADC (Analog to Digital Converter) 110, a sequential comparison ADC 120, and a digital synthesis + β value estimation unit 130. The A / D converter 100 is a β (1 <β <2) -ary β conversion cyclic ADC 110 (β conversion) as an A / D conversion circuit in charge of A / D conversion of the high-order bits that require circuit accuracy. Cyclic type A / D conversion circuit) is applied. Further, as an A / D conversion circuit in charge of A / D conversion of the lower bits for which the requirement for circuit accuracy is relaxed, for example, a binary sequential comparison ADC 120 (sequential comparison type A / D conversion circuit) is applied. The sequential comparison ADC 120 is not limited to the binary sequential comparison ADC, and may use any binary or lower sequential comparison ADC.

The A / D converter 100, which is a combination of these two A / D conversion methods, has a digital compositing unit that synthesizes a digital bit output from the β-conversion cyclic ADC 110 and a digital bit output from the sequential comparison ADC 120. You will need it. Further, the A / D converter 100 requires a β value estimation operation for estimating the β value actually realized on the chip, and a β estimation control unit for executing the β value estimation algorithm. In the example of FIG. 1, the digital composition + β value estimation unit 130 includes the digital composition unit and the β estimation control unit.

FIG. 1B shows another example of the A / D converter 100 according to the embodiment. As shown in FIG. 1 (b), the β-conversion cyclic ADC that realizes the A / D conversion of the high-order bit is composed of a plurality of β-conversion cyclic ADCs 110-1, 110-2, ... It may be. Further, the sequential comparison ADC 120 that realizes the A / D conversion of the lower bits may be one or more stages of the sequential comparison ADC 120.

That is, the A / D converter 100 applies the β conversion cyclic ADC 110 to the A / D conversion circuit in charge of A / D conversion in a predetermined bit range, and A / D in a bit range lower than the predetermined bit range. Anything that applies the sequential comparison ADC 120 to the conversion circuit may be used. In this case, the A / D converter 100 sequentially compares the A / D conversion result of the predetermined bit range by the β-conversion cyclic ADC 110 and the residual signal after the A / D conversion of the predetermined bit range with the ADC 120. The A / D conversion result of the lower bit range D-converted is combined to obtain the A / D conversion result output by the A / D converter 100.

Subsequently, a specific configuration of the A / D converter 100 will be described by exemplifying a plurality of embodiments.

[First Embodiment]
<A / D converter configuration>
FIG. 2 is a diagram showing an example of a circuit configuration of the A / D converter according to the first embodiment. In FIG. 2, the A / D converter 100 corresponds to the A / D converter 100 shown in FIG. 1 (a), and is a β-conversion cyclic ADC 110, a sequential comparison ADC 120, a reference voltage generation circuit 210, and an overall control unit. 220, digital compositing unit 230 and the like are included.

(Structure of β-conversion cyclic ADC)
The β-conversion cyclic ADC 110 (hereinafter referred to as the first ADC) is a β-ary (non-binary) A / D conversion circuit. For example, as shown in FIG. 2, the comparator 11, the DAC unit 12, It includes an operational amplifier 13, capacitive elements 14a and 14b, and a plurality of switches SW1 to SW7.

The first ADC 110 does not encode a digital signal by binary coding, and uses, for example, a value of β that is greater than 1 and less than 2 as shown in Patent Document 1. A digital signal is encoded by linear coding.

The comparator (Sub-ADC) 11 compares a predetermined threshold voltage (VCM in the example of FIG. 2) with a sampling voltage Vs output from the switch SW3 (switching unit), and compares the comparison result. The indicated 1-bit digital signal is output. The comparator 11 is realized by, for example, a comparator or the like.

For example, the comparator 11 outputs "1" when the sampling voltage Vs to be compared is higher than VCM, and outputs "0" when the sampling voltage Vs is VCM or less. The VCM is, for example, the median value (for example, 0V) of the full-scale voltage Vfs (reference voltage + Vref to −Vref) in the first ADC 110.

The DAC unit 12 is a circuit that selectively outputs a reference voltage + Vref or −Vref according to the comparison result of the comparator 11, and is realized by, for example, a multiplexer or the like. The DAC unit 12 outputs + Vref when it is determined by the comparator 11 that the sampling voltage Vs is higher than VCM, and outputs −Vref when it is determined that the sampling voltage Vs is lower than VCM.

The operational amplifier 111 has an amplification factor (gain) of β (1 <β <2) times, executes a predetermined operation according to the comparison result of the comparator 11, and generates a residual signal Vres. For example, it is realized by an operational amplifier or the like. The value of β representing the amplification factor of the arithmetic amplification unit 111 is preset so that 1 <β <2 by the ratio of the capacitance value Ca of the capacitance element 14a and the capacitance value Cb of the capacitance element 14b. It is assumed that there is.

The capacitance element 14a is a capacitance element having a capacitance value Ca, and the capacitance element 14b is a capacitance element having a capacitance value Cb. The capacitive elements 14a and 14b are realized by, for example, a capacitor or the like.

The switches SW1 to SW7 are switch elements that switch between connecting and disconnecting signals under the control of the overall control unit 220. The β-conversion cyclic ADC has three operating states, and the overall control unit 220 switches switches SW1 to SW7 so as to be in a connected state according to each operating state.

(Operation of β-conversion cyclic ADC)
Here, the operation of the first ADC 110 will be described with reference to FIGS. 3 to 5. FIG. 3 is a diagram for explaining an example of the operation of the β-conversion cyclic ADC. Further, FIGS. 4 and 5 are diagrams showing a setting example of each switch of the first ADC 110.

FIG. 3A is a flowchart showing the flow of the A / D conversion process of the first ADC 110.

In step S301, the overall control unit 220 switches the switches SW1 to SW6 of the first ADC 110, for example, as shown in FIG. 4A, to convert the input signal Vin of the first ADC 110 into the capacitance element 14a (Ca). ), And the capacitive element 14b (Cb) is sampled. In the following description, this state is referred to as an operating state (A).

In the operating state (A), the overall control unit 220 controls the switch SW1 so that the capacitance element 14b is connected to the Vin, so that the capacitance element 14a is connected to the Vin, as shown in FIG. 4A. Controls the switch SW2. Further, the overall control unit 220 controls the switch SW3 so that Vin is input to the comparator 11 as the sample voltage Vs (comparison voltage). Further, the overall control unit 220 controls to disconnect the switch SW4 and connect the switches SW5 and SW6.

The overall control unit 220 controls the switch SW7 so as to input VCM to the first ADC 110 only when performing the β value estimation operation for estimating the β value. Here, the first ADC 110 is used. It is assumed that SW7 is fixedly set so that Vin is input.

FIG. 3B is a diagram showing the timing of the A / D conversion process of the first ADC 110. As shown in FIG. 3B, at the end of the first operating state (A), the comparison result of the comparator 11 is updated, and the first output bit (most significant bit) b ₀ is output.

After that, in step S302, the overall control unit 220 amplifies the signal according to the comparison result of the comparator 11 by switching the switches SW1 to SW6 of the first ADC 110, for example, as shown in FIG. 4B. Perform a signal amplification operation. In the following description, this state is referred to as an operating state (B).

In the operating state (B), the overall control unit 220 controls the switch SW1 so that the capacitive element 14b is connected to the residual signal Vres output from the arithmetic amplification unit 111, as shown in FIG. 4B. .. Further, the overall control unit 220 controls the switch SW2 so that the capacitance element 14a is connected to the output of the DAC unit 12. Further, the overall control unit 220 controls the switch SW3 so as to input Vres as the sample voltage Vs to the comparator 11. Furthermore, the overall control unit 220 controls to disconnect the switches SW4 and SW5 and connect the switches SW6.

In this operating state (B), when the comparator 11 determines that the sample voltage Vs is higher than the VCM, the arithmetic amplification unit 111 assumes that the voltage sampled by the capacitive element 14a is Vres', and the output voltage Vres = Outputs Vres'× β + (1-β) Vref. On the other hand, when the comparator 11 determines that the sample voltage Vs is lower than the VCM, the arithmetic amplification unit 111 outputs the output voltage Vres = Vres' × β + (β-1) Vref.

In step S303, the overall control unit 220 executes the cyclic sampling operation by switching the switches SW1 to SW6 of the first ADC 110, for example, as shown in FIG. In the following description, this state is referred to as an operating state (C).

In the operating state (C), the overall control unit 220 controls the switch SW1 so that the capacitance element 14b is connected to the residual signal Vres, and the capacitance element 14a is connected to the residual signal Vres, as shown in FIG. The switch SW2 is controlled so as to be operated. Further, the overall control unit 220 controls the switch SW3 so as to output the residual signal Vres as the sample voltage Vs to the comparator 11. Further, the overall control unit 220 connects the switch SW4 and controls the switches SW5 and SW6 to be disconnected.

In this operating state (C), the first ADC 110 samples the residual signal Vres stored in the capacitive element 14b created by the signal amplification operation in step S302 to the capacitive element 14a on the input side.

At this time, as shown in FIG. 3 (b), at the end of the first operating state (C), the comparison result of the comparator 11 is updated and the second output bit b ₁ is output.

In step S304, the overall control unit 220 determines whether or not a predetermined number of bits X (for example, 5 bits) has been obtained.

When a predetermined number of output bits B _x (= b ₀ , b ₁ , ..., b _x-1 ) are obtained, the overall control unit 220 ends one A / D conversion process. On the other hand, when the predetermined number of bits is not obtained, the overall control unit 220 returns the process to step S302 and executes the same process again.

(Sequential comparison ADC)
Sequential comparison ADC 120 (hereinafter referred to as the second ADC) consists of N capacitive elements C _{0 to} C _N-1 with binary (binary) weighted values (N is an integer of 2 or more) and one dummy. It has a capacitance array including a capacitance element C _d , a comparator 240, SAR250, a switch SW10, a switch array SW_SAR, SW_Vres, and the like.

For the sake of simplicity, the configuration using a capacitive element having a binary weighted value has been described, but the capacitive elements C _{0 to} CN _-1 and C _d are composed of a combination of capacitive elements having a unit capacitance. You may.

In the second ADC 120, according to the output logic of the SAR (sequential comparison register) 250, the outputs of the switches connected to + Vref and -Vref have the same logic ( _DN-1 , ..., D ₀ , D _d ). Toggle the switch as in. The SAR 250 changes the output voltage Vx by sequentially switching the switch from the high-order bit ( _DN-1 ) side, and performs sequential comparison A / D conversion for specifying the A / D conversion value by the dichotomy.

The comparator 240 includes a predetermined threshold voltage (V _CM as an _example), the output voltage Vx (hereinafter, referred to as terminal for the voltage Vx is input to the voltage comparator node) by comparing the comparison result The indicated 1-bit digital value d _Y is output. The comparator 240 obtains output bits Dy (= d ₀ , d ₁ , ..., d _Y-1 ) having a predetermined number of bits Y according to the output of the SAR (sequential comparison register) 250.

Further, the overall control unit 220 connects the switches included in the switch array SW_Vres to the residual signal Vres after executing the A / D conversion of the high-order bits in the first ADC 110 to the second ADC 120. Input as an input signal. As a result, the second ADC 120 performs A / D conversion of the input residual signal Vres and identifies the lower bits.

(Reference voltage generation circuit)
The reference voltage generation circuit 210 generates a median VCM (for example, 0V) of the reference voltages + Vref, −Vref, and + Vref to −Vref.

(Overall control unit)
The overall control unit 220 includes a switch control unit 221, a β value estimation control unit 222, and an AD conversion control unit 223.

The switch control unit 221 outputs a control signal for controlling the connection / disconnection of the switches SW1 to SW7, SW10, the switch array SW_Vres, etc., according to the control of the β value estimation control unit 222 or the AD conversion control unit 223.

The β value estimation control unit 222 estimates the value of the amplification factor β of the arithmetic amplification unit 111 actually realized on the chip. For example, the β value estimation control unit 222 controls the switch SW7 to input the median VCM of the reference voltage + Vref and −Vref to the input of the A / D converter 100 to execute the A / D conversion. Further, the β value estimation control unit 222 obtains an A / D conversion result in which the first bit starts from zero and an A / D conversion result in which the first bit starts from 1, obtained as a result of executing the A / D conversion. Estimate the value of β, focusing on equality.

The AD conversion control unit 223 controls the connection and disconnection of the switches SW1 to SW7, SW10, and the switch array SW_Vres by using the switch control unit 221 to control the A / D conversion in the A / D converter 100.

(Digital compositing department)
The digital compositing unit 230 includes a Radix conversion unit 231 and an adder 232.

Radix conversion unit 231, a β advance digital bit _{B x} output from the β transformation cyclic ADC 110, using the estimated results of the β value by β value estimation control unit 222, and converts the Radix from β proceeds to binary 2 Generates an advanced digital bit DB _x .

The adder 232 adds binary digital bit DB _x the Radix conversion unit 231 to generate a digital bit _{D y} output from the successive approximation ADC 120, generates a binary digital output signal Dout.

<Processing flow>
Subsequently, the flow of processing for A / D conversion by the A / D converter 100 will be described.

FIG. 6 is a flowchart showing an example of processing of the A / D converter according to the first embodiment. In FIG. 6, the process 610 of steps S601 to S605 shows the process by the first ADC 110, and the process 620 shown in steps S606 and S607 shows the process by the second ADC 120. Since the processes of steps S601 to S604 of FIG. 6 correspond to the processes of steps S301 to S304 of FIG. 3A, detailed description thereof will be omitted here.

In step S601, the AD conversion control unit 223 of the overall control unit 220 executes a sampling operation of sampling the input signal Vin to the capacitance element 14a (Ca) and the capacitance element 14b (Cb). For example, the AD conversion control unit 223 uses the switch control unit 221 to switch the switches SW1 to SW6 and SW10 of the A / D converter 100, and the switch array SW_Vres as shown in FIG. In the following description, this state is referred to as an operating state (A).

In the operating state (A), the AD conversion control unit 223 of the overall control unit 220 sets the switches SW1 to SW6 of the first ADC 110 as described above in FIG. 4A. Further, the AD conversion control unit 223 controls the SW10 and the switch array SW_Vres in the disconnected state. As a result, the input signal Vin is sampled in the capacitive elements 14a and 14b of the first ADC 110.

The AD conversion control unit 223 controls the switch SW7 so that the first ADC 110 inputs Vin during the A / D conversion operation, and does not switch.

FIG. 7 is a diagram showing an example of processing timing of the A / D converter 100. As shown in FIG. 7, when the sampling of the input signal Vin1 is completed in the operating state (A) at the time t1, the comparison result of the comparator 11 is updated and the most significant bit bit _n-1 is output.

In step S602, the AD conversion control unit 223 of the overall control unit 220 executes a signal amplification operation that amplifies the signal according to the comparison result of the comparator 11. For example, the AD conversion control unit 223 uses the switch control unit 221 to switch the switches SW1 to SW6 and SW10 of the A / D converter 100, and the switch array SW_Vres as shown in FIG. In the following description, this state is referred to as an operating state (B).

In the operating state (B), the AD conversion control unit 223 of the overall control unit 220 sets the switches SW1 to SW6 of the first ADC 110 as described above in FIG. 4B. Further, the AD conversion control unit 223 maintains the disconnected state of the SW10 and the switch array SW_Vres. As a result, the first ADC 110 amplifies the signal according to the comparison result of the comparator 11, and stores the residual signal Vres in the capacitive element 14b.

In step S603, the AD conversion control unit 223 of the overall control unit 220 executes the cyclic sampling operation. For example, the AD conversion control unit 223 uses the switch control unit 221 to switch the switches SW1 to SW6 and SW10 of the A / D converter 100, and the switch array SW_Vres as shown in FIG. In the following description, this state is referred to as an operating state (C).

In the operating state (C), the AD conversion control unit 223 of the overall control unit 220 sets the switches SW1 to SW6 of the first ADC 110 as described above in FIG. Further, the AD conversion control unit 223 maintains the disconnected state of the SW10 and the switch array SW_Vres. As a result, the residual signal Vres stored in the capacitance element 14b in step S602 is sampled by the capacitance element 14a on the input side.

As shown in FIG. 7, at the end of the first operating state (C), the comparison result of the comparator 11 is updated, and bit _n-2 is output.

In step S604, the AD conversion control unit 223 of the overall control unit 220 determines whether or not a predetermined number of bits (n−k bits in the example of FIG. 7) has been obtained.

When the predetermined number of bits has not been obtained, the AD conversion control unit 223 repeatedly executes the processes of steps S602 to S604 until the predetermined number of bits is obtained. On the other hand, when a predetermined number of bits is obtained, the AD conversion control unit 223 shifts the process to step S605.

When the process proceeds to step S605, the AD conversion control unit 223 of the overall control unit 220 causes the first ADC 110 to hold the residual signal Vres for a predetermined period of time. For example, the AD conversion control unit 223 controls the switches SW1 to SW6 of the first ADC 110 as shown in FIG. As a result, the residual signal Vres is held in the first ADC 110. In the following description, this state is referred to as an operating state (D).

At this time, the second ADC 120 samples the residual signal Vres (step S606). For example, the residual signal Vres is sampled in each of the capacitive elements C _{0 to} C _N-1, C _d included in the capacitive array of the second ADC 120. In the following description, this state is referred to as an operating state (E).

As shown in FIG. 7, at time t2, after the first ADC 110 outputs a bit, the first ADC 110 is set to the state (D) and the second ADC 120 is set to the state (E). To. Further, when the sampling of the residual signal Vres by the second ADC 120 is completed at the time t3, the first ADC 110 can perform the sampling of the next input signal Vin2.

In step S607 of FIG. 6, the SAR 250 of the second ADC 120 controls the switch array SW_SAR to perform sequential comparison A / D conversion to obtain the lower bits. In the following description, this state is referred to as an operating state (F).

In the operating state (F), the AD conversion control unit 223 controls the switches SW1 to SW6 of the first ADC 110 as shown in FIG. 11, for example, and thereby, for example, the following input as shown in FIG. Sampling of the signal Vin2 can be started.

In step S608, the digital compositing unit 230 synthesizes the upper digital bit output from the first ADC 110 in steps S601 to S604 and the lower digital bit output from the second ADC 120 in step S607. Output the conversion result.

By the above processing, the A / D converter 100 executes the A / D conversion of the upper bit, which requires the accuracy of the circuit, with the β-conversion cyclic ADC 110, and the A / D of the lower bit, which requires the accuracy of the circuit, is relaxed. The / D conversion can be realized by the sequential comparison ADC 120. This eliminates the need for an operational amplifier for A / D conversion of the lower bits, so that a plurality of A / D conversion circuits including a β-conversion cyclic A / D conversion circuit can be combined to reduce malfunctions due to manufacturing variations and consume. It becomes possible to provide an A / D converter with less power.

[Second Embodiment]
In the second embodiment, as another suitable example, the capacitance array (C _{0 to} CN _-1, C _d) of the second ADC 120 is combined with the integrated capacitance Cb of the first ADC (β-converted cyclic ADC 110). An example of the configuration used as is described.

The A / D converter 100 according to the second embodiment A / D-converts the residual signal Vres after the A / D conversion of the high-order bit by the first ADC 110 as it is by the second ADC 120. Will be able to. Thereby, for example, the processing of steps S605 and S606 in FIG. 6 can be omitted. Further, in the A / D converter 100 according to the present embodiment, the sampling error in the A / D converter 100 can be reduced by eliminating the error due to sampling in the sequential comparison ADC 120.

<A / D converter configuration>
FIG. 13 is a diagram showing an example of a circuit configuration of the A / D converter according to the second embodiment. The A / D converter 100 shown in FIG. 13 has a capacitance array 1300 instead of the capacitance element 14b and the switch SW1 of the A / D converter 100 according to the first embodiment shown in FIG.

FIG. 14 is a diagram showing an example of the circuit configuration of the capacitance array according to the second embodiment. The capacitance array 1300 includes N capacitive elements C _{0 to} C _N-1 having binary weighted values and one dummy capacitive element C _d included in the second ADC 120 according to the first embodiment. And include. Further, the capacitance array 1300 has a switch array SW_Vin in addition to the switch arrays SW_SAR and SW_Vres included in the second ADC 120 according to the first embodiment. Note that, in FIGS. 13 and 14, the same reference numbers are given to the components described by the A / D converter 100 according to the first embodiment shown in FIG. 2, and detailed description thereof will be omitted here.

The overall control unit 220 of the A / D converter 100 controls the switch array SW_Vin and connects the Vin to the capacitive elements C _{0 to} C _N-1 and C _d , whereby the capacitive elements C _{0 to} C _N-1. it can be employed including synthetic capacity _{C d} as an integral capacitance Cb of the first ADC 110.

<Processing flow>
Subsequently, the flow of the A / D conversion process by the A / D converter 100 according to the second embodiment will be described.

FIG. 15 is a flowchart showing an example of processing of the A / D converter according to the second embodiment.

In step S1501, the AD conversion control unit 223 of the overall control unit 220 executes a sampling operation of sampling the input signal Vin to the capacitance element 14a (Ca) and the capacitance array 1300 (Cb). For example, the AD conversion control unit 223 uses the switch control unit 221 to display the switches SW2 to SW7 of the A / D converter 100 and the switch arrays SW_Vres and SW_Vin of the capacitance array 1300 in FIGS. 17A and 17B. Set as shown in. In the following description, this state is referred to as an operating state (A).

In the operating state (A), as shown in FIGS. 17A and 17B, the settings of the switches SW2 to SW7 and the switch array SW_Vres of the capacitance array 1300 are the operations according to the first embodiment shown in FIG. It is the same as the setting of the state (A). Further, as shown in FIG. 17B, the AD conversion control unit 223 sets each switch included in the switch array SW_Vin of the capacitance array 1300 in the connected state. As a result, the A / D converter 100 functions as a β-conversion cyclic ADC, and the input signal Vin is sampled in the capacitive array 1300 (Cb).

FIG. 16 is a diagram showing an example of processing timing of the A / D converter according to the second embodiment. As shown in FIG. 16, when the sampling of the input signal Vin1 is completed in the operating state (A) at the time t1, the comparison result of the comparator 11 is updated and the most significant bit bit _n-1 is output.

In step S1502, the AD conversion control unit 223 of the overall control unit 220 executes a signal amplification operation that amplifies the signal according to the comparison result of the comparator 11. For example, the AD conversion control unit 223 uses the switch control unit 221 to display the switches SW2 to SW7 of the A / D converter 100 and the switch arrays SW_Vres and SW_Vin of the capacitance array 1300 in FIGS. 18A and 18B. Set as shown in. In the following description, this state is referred to as an operating state (B).

In the operating state (B), as shown in FIGS. 18A and 18B, the settings of the switches SW2 to SW7 are the same as the settings of the operating state (B) according to the first embodiment shown in FIG. .. Further, as shown in FIG. 18B, the AD conversion control unit 223 puts each switch included in the switch array SW_Vin in the disconnected state and puts each switch included in the switch array SW_Vres in the connected state. As a result, the A / D converter 100 amplifies the signal according to the comparison result of the comparator 11, and stores the residual signal Vres in the capacitive array 1300 (Cb).

In step S1503, the AD conversion control unit 223 of the overall control unit 220 executes the cyclic sampling operation. For example, the AD conversion control unit 223 uses the switch control unit 221 to display the switches SW2 to SW7 of the A / D converter 100 and the switch arrays SW_Vres and SW_Vin of the capacitance array 1300 in FIGS. 19A and 19B. Set as shown in. In the following description, this state is referred to as an operating state (C).

In the operating state (C), as shown in FIGS. 19A and 19B, the settings of the switches SW2 to SW7 are the same as the settings of the operating state (C) according to the first embodiment shown in FIG. .. Further, as shown in FIG. 19B, the AD conversion control unit 223 maintains each switch included in the switch array SW_Vin in the disconnected state and each switch included in the switch array SW_Vres in the connected state. As a result, the residual signal Vres stored in the capacitance array 1300 (Cb) in step S1502 is sampled by the capacitance element 14a on the input side.

As shown in FIG. 16, at the end of the first operating state (C), the comparison result of the comparator 11 is updated, and bit _n-2 is output.

In step S1504, the AD conversion control unit 223 of the overall control unit 220 determines whether a predetermined number of bits (for example, 5 bits) has been obtained.

If the predetermined number of bits has not been obtained, the AD conversion control unit 223 repeatedly executes the processes of steps S1502 to S1504 until the predetermined number of bits is obtained. On the other hand, when a predetermined number of bits is obtained, the AD conversion control unit 223 shifts the process to step S1505.

In FIG. 16, in the A / D converter 100 according to the second embodiment, the residual signal Vres is already stored in the capacitance array 1300 when the β-conversion cyclic ADC 110 outputs a bit at time t2. Therefore, the A / D converter 100 according to the present embodiment omits the processing of the operating states (D) and (E) of the first embodiment shown in FIG. 7, and immediately performs sequential comparison A / D conversion at time t2. Can be started.

When the process proceeds to step S1505, the AD conversion control unit 223 of the overall control unit 220 uses the switch control unit 221 to perform the switches SW2 to SW7 of the A / D converter 100 and the switch arrays SW_Vres and SW_Vin of the capacitance array 1300. The settings are made as shown in FIGS. 20A and 20B. In the following description, this state is referred to as an operating state (F).

In the operating state (F), the settings of the switches SW2 to SW7 maintain the state of the operating state (C). Further, as shown in FIG. 20B, the AD conversion control unit 223 sets each switch included in the switch arrays SW_Vres and SW_Vin in the disconnected state. As a result, the A / D converter 100 functions as a sequential comparison ADC, and the capacitive array 1300 can be used to perform sequential comparison A / D conversion.

In this state, in steps S1501 to S1504, the A / D converter 100 A / D-converts the residual signal Vres after A / D conversion of the high-order bit as a sequential comparison ADC to obtain the low-order bit. For example, the A / D converter 100 changes the output voltage Vx by sequentially switching the switches connected to + Vref and −Vref from the upper bit ( _DN-1 ) side according to the output of the SAR 250, and the dichotomy method. Performs sequential comparison A / D conversion to specify the A / D conversion value in.

In step S1506, the digital compositing unit 230 synthesizes the upper digital bits output in steps S1501 to S1504 and the lower digital bits output in step S1505 to generate an output signal Dout, and outputs the output signal Dout.

By the above processing, the A / D converter 100 converts the A / D conversion of the upper bit, which requires the accuracy of the circuit, into β-conversion cyclic A / D, and the lower bit, which relaxes the requirement for the accuracy of the circuit. A / D conversion can be sequentially compared A / D conversion. As a result, the circuit can be configured by one operational amplifier, so that a plurality of A / D conversion circuits including a β-conversion cyclic A / D conversion circuit can be combined to reduce malfunctions due to manufacturing variations and reduce power consumption. It becomes possible to provide a small number of A / D converters.

Further, in the A / D converter 100 according to the present embodiment, the process of sampling the residual signal Vres after the β-conversion cyclic A / D conversion of the high-order bit by the sequential comparison A / D conversion is omitted. be able to. Further, in the A / D converter 100 according to the present embodiment, the sampling error in the A / D converter 100 can be reduced by eliminating the error due to sampling in the sequential comparison ADC 120.

[Third Embodiment]
In the second embodiment, an example of the A / D converter 100 in which the capacitance array 1300 used in the sequential comparison A / D conversion is used as the integrated capacitance Cb of the β-conversion cyclic A / D conversion has been described. In this case, the sampling of the next input signal Vin cannot be started until the A / D converter 100 finishes the sequential comparison A / D conversion.

In a third embodiment, a plurality of capacitive arrays 1300 are used, and the next input signal Vin is used using the second capacitive array before the sequential comparison A / D conversion using the first capacitive array is completed. An example of a configuration in which an interleave operation for starting sampling of is performed will be described.

<A / D converter configuration>
FIG. 21 is a diagram showing an example of a circuit configuration of the A / D converter according to the third embodiment. The A / D converter 100 shown in FIG. 13 has a first capacitance array 1300-1 and a second capacitance instead of the capacitance array 1300 of the A / D converter 100 according to the second embodiment shown in FIG. It has an array 1300-2 and switches SW21 and SW22. The configurations of the first capacitive array 1300-1 and the second capacitive array 1300-2 are the same as those of the capacitive array 1300 according to the first embodiment shown in FIG.

The A / D converter 100 according to the present embodiment uses the second capacitive array 1300-2 to perform β-conversion when the sequential comparison A / D conversion is performed using the first capacitive array 1300-1. It is configured so that cyclic A / D conversion can be executed in parallel.

The switch SW21 connects the Vout of the first capacitance array 1300-1 to the input terminal of the operational amplifier 13 or the input terminal of the comparator 240 under the control of the overall control unit 220. The switch SW22 connects the Vout of the second capacitive array 1300-2 to the input terminal of the operational amplifier 13 or the input terminal of the comparator 240 under the control of the overall control unit 220.

The first capacitive array 1300-1 is a β-conversion cyclic ADC by connecting each switch included in the switch array SW_Vin shown in FIG. 14 to a connected state and connecting Vout to the input terminal of the operational amplifier 13 by the switch SW21. It functions as an integrated capacitance Cb.

Further, in the first capacitance array 1300-1, each switch included in the switch arrays SW_Vin and SW_Vres is disconnected, and Vout is connected to the input terminal of the comparator 240 by the switch SW21, so that the capacitance array of the sequential conversion ADC is used. Functions as. The same applies to the second capacitive array 1300-2.

<Processing flow>
Subsequently, the flow of the A / D conversion process by the A / D converter 100 according to the third embodiment will be described.

FIG. 22 is a flowchart showing an example of processing of the A / D converter according to the third embodiment.

In step S2211, the AD conversion control unit 223 of the overall control unit 220 samples the input signal Vin1 into the capacitance element 14a (Ca) and the first capacitance array 1300-1 (Cb1). For example, the AD conversion control unit 223 sets the switches SW2 to SW7, SW21, and SW22 of the A / D converter 100 as shown in FIG. 24 by using the switch control unit 221. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the first capacitance array 1300-1 as shown in FIG. 17B. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the second capacitance array 1300-2 as shown in FIG. 20 (b). In the following description, this state is referred to as an operating state (A).

As a result, the A / D converter 100 can sample the input signal Vin1 in the first capacitive array 1300-1 (Cb1) as a β-converting cyclic ADC. At this time, the A / D converter 100 can execute the sequential comparison A / D conversion using the second capacitance array 1300-2 as the sequential comparison ADC.

FIG. 23 is a diagram showing an example of processing timing of the A / D converter according to the third embodiment. As shown in FIG. 23, when the sampling of the input signal Vin1 is completed in the operating state (A) at the time t1, the comparison result of the comparator 11 is updated and the most significant bit bit _n-1 is output. Further, in FIG. 23, since the A / D conversion of the upper bits has not been completed during the period of time t1 to t2, the A / D conversion of the lower bits (sequential comparison A / D conversion) is not executed.

In step S2212, the AD conversion control unit 223 of the overall control unit 220 executes a signal amplification operation of amplifying a signal according to the comparison result of the comparator 11 by using the first capacitance array 1300-1 (Cb1). .. For example, the AD conversion control unit 223 sets the switches SW2 to SW7, SW21, and SW22 of the A / D converter 100 as shown in FIG. 25 by using the switch control unit 221. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the first capacitance array 1300-1 as shown in FIG. 18B. Further, the AD conversion control unit 223 maintains the states of the switch arrays SW_Vres and SW_Vin of the second capacitance array 1300-2 in the states shown in FIG. 20B. In the following description, this state is referred to as an operating state (B).

As a result, the A / D converter 100 amplifies the signal as a β-converting cyclic ADC according to the comparison result of the comparator 11, and stores the residual signal Vres in the first capacitive array 1300-1 (Cb1). .. At this time, the A / D converter 100 can continuously execute the sequential comparison A / D conversion by using the second capacitance array 1300-2 as the sequential comparison ADC.

In step S2213, the AD conversion control unit 223 of the overall control unit 220 executes a cyclic sampling operation using the first capacitive array 1300-1 (Cb1). For example, the AD conversion control unit 223 sets the switches SW2 to SW7, SW21, and 22 of the A / D converter 100 as shown in FIG. 26 by using the switch control unit 221. Further, the AD conversion control unit 223 maintains the switch arrays SW_Vres and SW_Vin of the first capacitance array 1300-1 in the state shown in FIG. 18B. Further, the AD conversion control unit 223 maintains the states of the switch arrays SW_Vres and SW_Vin of the second capacitance array 1300-2 in the states shown in FIG. 20B. In the following description, this state is referred to as an operating state (C).

As a result, the A / D converter 100 samples the residual signal Vres stored in the first capacitance array 1300-1 (Cb1) in the first capacitance array 1300-1 (Cb1) in the input side capacitance element 14a as a β-conversion cyclic ADC in step S2212. .. At this time, the A / D converter 100 can continuously execute the sequential comparison A / D conversion by using the second capacitance array 1300-2 as the sequential comparison ADC.

As shown in FIG. 23, at the end of the first operating state (C), the comparison result of the comparator 11 is updated, and bit _n-2 is output.

In step S2214, the AD conversion control unit 223 of the overall control unit 220 has a predetermined number of bits (for example, 5 bits) by β-conversion cyclic A / D conversion using the first capacitance array 1300-1 (Cb1). Determine if it was obtained.

If the predetermined number of bits has not been obtained, the AD conversion control unit 223 repeatedly executes the processes of steps S2212 to S2214 until the predetermined number of bits is obtained. On the other hand, when a predetermined number of bits is obtained, the AD conversion control unit 223 shifts the processing to steps S2215 and S2221.

Here, the A / D converter 100 executes the processes shown in steps S2215 and S2216 and the processes shown in steps S2221 to S2224 in parallel.

When the process shifts to step S2215, the AD conversion control unit 223 of the overall control unit 220 uses the switch control unit 221 to display the switches SW2 to SW7, SW21, and SW22 of the A / D converter 100, for example, as shown in FIG. 27. Set to. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the first capacitance array 1300-1 as shown in FIG. 20 (b). Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the second capacitance array 1300-2 as shown in FIG. 17 (b). In the following description, this state is referred to as an operating state (F).

As a result, the A / D converter 100 uses the first capacitive array 1300-1 (Cb1) as the sequential comparison ADC to perform the A / D conversion of the upper bits in steps S2211 to S2214, and then the residual signal. Vres can be subjected to sequential comparison A / D conversion.

In step S2216, the digital compositing unit 230 synthesizes the upper digital bits output in steps S2211 to S2214 and the lower digital bits output in step S2215 to generate an output signal Dout, and outputs the output signal Dout.

In step S2215, the A / D converter 100 performs the processes of steps S2221 to S2224 in parallel when the sequential comparison A / D conversion is performed using the first capacitive array 1300-1 (Cb1). To execute.

For example, as shown in FIG. 23, the A / D converter 100 has a first capacitance when the A / D conversion of the upper bits using the first capacitance array 1300-1 (Cb1) is completed at time t2. The array 1300-1 (Cb1) is used to start the A / D conversion of the lower bits. Further, the A / D converter 100 uses the second capacitive array 1300-2 after the time t2 and before the A / D conversion of the lower bits using the first capacitive array 1300-1 (Cb1) is completed. (Cb2) can be used to start sampling the next input signal Vin2.

In FIG. 22, when the process proceeds to step S2221, the AD conversion control unit 223 of the overall control unit 220 samples the input signal Vin2 into the capacitance element 14a (Ca) and the second capacitance array 1300-2 (Cb2). In the following description, this state is referred to as an operating state (A'). In the operating state (A') and the above-mentioned operating state (F), the switches SW2 to SW7, SW21, SW22 of the A / D converter 100, and the switch arrays SW_Vres and SW_Vin of the first and second capacitance arrays The settings are similar.

As a result, the A / D converter 100 can sample the input signal Vin2 in the second capacitive array 1300-2 (Cb2) as a β-converting cyclic ADC. At this time, the A / D converter 100 can execute the sequential comparison A / D conversion using the first capacitance array 1300-1 as the sequential comparison ADC.

In step S2222, the AD conversion control unit 223 of the overall control unit 220 executes a signal amplification operation of amplifying the signal according to the comparison result of the comparator 11 by using the second capacitance array 1300-2 (Cb2). .. For example, the AD conversion control unit 223 sets the switches SW2 to SW7, SW21, and SW22 of the A / D converter 100 as shown in FIG. 28 by using the switch control unit 221. Further, the AD conversion control unit 223 sets the states of the switch arrays SW_Vres and SW_Vin of the second capacitance array 1300-2 to the states shown in FIG. 18B. Further, the AD conversion control unit 223 maintains the switch arrays SW_Vres and SW_Vin of the first capacitance array 1300-1 in the state shown in FIG. 20 (b). In the following description, this state is referred to as an operating state (B').

In the operating state (B'), the A / D converter 100 serves as a β-converting cyclic ADC, amplifies the signal according to the comparison result of the comparator 11, and sets the residual signal Vres as the second capacitive array 1300-2. Store in (Cb2). At this time, the A / D converter 100 can continuously execute the sequential comparison A / D conversion by using the first capacitance array 1300-1 as the sequential comparison ADC.

In step S2223, the AD conversion control unit 223 of the overall control unit 220 executes the cyclic sampling operation using the second capacitive array 1300-2 (Cb2). For example, the AD conversion control unit 223 sets the switches SW2 to SW7, SW21, and 22 of the A / D converter 100 as shown in FIG. 29 by using the switch control unit 221. Further, the AD conversion control unit 223 maintains the states of the switch arrays SW_Vres and SW_Vin of the second capacitance array 1300-2 in the states shown in FIG. 18B. Further, the AD conversion control unit 223 maintains the switch arrays SW_Vres and SW_Vin of the first capacitance array 1300-1 in the state shown in FIG. 20 (b). In the following description, this state is referred to as an operating state (C').

In the operating state (C'), the A / D converter 100 uses the residual signal Vres stored in the second capacitance array 1300-2 (Cb2) in step S2222 as the β-converting cyclic ADC to the capacitance of the input side. Sampling is performed on the element 14a. At this time, the A / D converter 100 can continuously execute the sequential comparison A / D conversion by using the first capacitance array 1300-1 as the sequential comparison ADC.

In step S2224, the AD conversion control unit 223 of the overall control unit 220 has a predetermined number of bits (for example, 5 bits) by β-conversion cyclic A / D conversion using the second capacitance array 1300-2 (Cb2). Determine if it was obtained.

If the predetermined number of bits has not been obtained, the AD conversion control unit 223 repeatedly executes the processes of steps S2222 to S2224 until the predetermined number of bits is obtained. On the other hand, when a predetermined number of bits is obtained, the AD conversion control unit 223 shifts the processing to steps S2225 and S2227.

When the process proceeds to step S2225, the AD conversion control unit 223 of the overall control unit 220 uses the switch control unit 221 to switch the switches SW2 to SW7, SW21, and SW22 of the A / D converter 100 again as shown in FIG. 24. Set to. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the first capacitance array 1300-1 as shown in FIG. 17B. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the second capacitance array 1300-2 as shown in FIG. 20 (b). In the following description, this state is referred to as an operating state (F').

As a result, the A / D converter 100 uses the second capacitive array 1300-2 (Cb2) as the sequential comparison ADC to perform the A / D conversion of the high-order bits in steps S2221 to S2224, and then the residual signal. Vres can be subjected to sequential comparison A / D conversion. For example, the A / D converter 100 changes the output voltage Vx by sequentially switching the switches connected to + Vref and −Vref from the upper bit ( _DN-1 ) side according to the output of the SAR 250, and the dichotomy method. Performs sequential comparison A / D conversion to specify the A / D conversion value in.

In step S2226, the digital compositing unit 230 synthesizes the upper digital bits output in steps S2221 to S2224 and the lower digital bits output in step S2225 to generate an output signal Dout and outputs the output signal Dout.

In step S2227, the AD conversion control unit 223 of the overall control unit 220 determines, for example, whether or not to end the process, and if the process is not terminated, shifts the process to step S2211. Alternatively, the AD conversion control unit 223 may shift the process to step S2211 without determining whether or not to end the process.

By the above processing, the A / D converter 100 can perform the interleaving operation by alternately using the two capacitance arrays 1300-1 and 1300-2, for example, as shown in FIG.

Thereby, for example, while performing the sequential comparison A / D conversion of the lower bits using the first capacitance array 1300-1, the next input signal Vin is used by using the second capacitance array 1300-2. Beta conversion of high-order bits Cyclic A / D conversion can be executed.

Further, in the A / D converter 100 according to the present embodiment, as in the second embodiment, the residual signal Vres after the β-conversion cyclic A / D conversion of the high-order bit is sequentially compared A /. The process of sampling by D conversion can be omitted. Therefore, according to the third embodiment, the processing speed of the A / D conversion can be increased in the A / D converter 100 that combines the β conversion cyclic ADC and the successive approximation ADC.

[Fourth Embodiment]
In the fourth and subsequent embodiments, a more preferable configuration example of the A / D converter 100 in which the β-converting cyclic ADC and the sequential comparison ADC are combined will be described.

FIG. 30 is a diagram showing an example of a circuit configuration of the A / D converter according to the fourth embodiment. In FIG. 30, the reference voltage generation circuit 210 includes reference voltages + Vref1 and −Vref1 for the first ADC 110 (β-conversion cyclic ADC) and reference voltages + Vref2 and −Vref2 for the second ADC 120 (sequential conversion ADC). Is configured to generate separately. The other configuration of the A / D converter 100 shown in FIG. 30 is the same as that of the A / D converter 100 according to the first embodiment shown in FIG.

The β value estimation control unit 222 of the overall control unit 220 receives the input of the first ADC 110 when estimating the amplification factor β (1 <β <2) of the arithmetic amplification unit 111 actually realized on the chip. Input VCM and execute A / D conversion. The VCM is the median (for example, 0V) of the full-scale voltage FS1 (+ Vref1 to −Vref1) of the first ADC 110.

Therefore, the A / D converter 100 has a switch SW7 (input circuit) for inputting VCM (an example of a predetermined voltage) to the input node of the first ADC 110 so that the β value can be estimated. )have.

Further, as shown in FIG. 31, when the A / D converter 100 includes a plurality of first ADC 110-1, 110-2, ..., The VCM is input to the input node of each first ADC 110. Input circuit is provided.

As a result, the β value estimation control unit 222 of the overall control unit 220 can input the VCM to the input node of each first ADC 110 and estimate the β value.

FIG. 32 is a diagram for explaining the reference voltage according to the fourth embodiment. FIG. 32 (a) shows the input / output characteristics of the first ADC 110 (β-converted cyclic ADC) by the arithmetic amplification unit 111.

In FIG. 32 (a), when the input voltage VIN (Input) is −Vref ≦ VIN <0, the arithmetic amplification unit 111 outputs the output voltage Vres = VIN × β + (β-1) Vref. When the input voltage VIN is 0 ≦ VIN ≦ + Vref, the arithmetic amplification unit 111 outputs the output voltage Vres = VIN × β + (1-β) Vref. The value of β representing the slope of input / output (amplification rate or gain) is 1 <β <2.

FIG. 32 (b) shows the input / output characteristics of the first ADC 110 (β-conversion cyclic ADC) according to the fourth embodiment by the arithmetic amplification unit 111 and the input range (-) of the second ADC 120 (sequential conversion ADC). Vref2 to + Vref2) are shown.

In FIG. 32 (b), when Vref1 = Vref2, when an interstage offset voltage Voff between the first ADC 110 and the second ADC 120 occurs, a problem arises in the linearity of the A / D converter 100. For example, the output voltage of the first ADC 110 exceeds the input range of the second ADC 120, a signal clip is generated in the A / D conversion result, and a problem appears in linearity.

Therefore, in the A / D converter according to the fourth embodiment, the values of Vref2 and Vref1 are set so that the relationship of Vref2 ≧ Vref1 + Voff is established. For the interstage offset voltage Voff, for example, the worst value of the interstage offset voltage obtained in advance by calculation, experiment, or the like can be applied.

With the above configuration, in the A / D converter 100 in which the first ADC 110 and the second ADC 120 are combined, it is possible to reduce the deterioration of the accuracy of the A / D conversion due to the interstage offset voltage.

At this time, the digital compositing unit 230 of the A / D converter 100 uses, for example, the following equation (1) to obtain the A / D conversion result of the upper bits by the first ADC 110 and the second ADC 120. The A / D conversion result of the lower bit can be combined.

式（１）は、第１のＡＤＣ１１０により、上位５ビットのＡ／Ｄ変換を行い、第２のＡＤＣ１２０により下位Ｎビット（Ｎは２以上の整数）のＡ／Ｄ変換を行う場合の例を示している。

Equation (1) is an example in which the first ADC 110 performs A / D conversion of the upper 5 bits and the second ADC 120 performs A / D conversion of the lower N bits (N is an integer of 2 or more). Shown.

In the equation (1), β _a represents the value of β estimated by the β value estimation control unit 222. b _{1 to} b ₅ indicate the values of the first bit to the fifth bit output from the first ADC 110. The FS1 is a full-scale voltage of the first ADC 110, for example, a voltage twice the reference voltage Vref1 of the first ADC 110. The FS2 is the full-scale voltage of the second ADC 120, for example, twice the reference voltage Vref2 of the second ADC 120. E _q indicates the quantization noise (quantization error).

Further, the β value estimation control unit 222 of the A / D converter 100 inputs the median value (VCM) of FS1 (-Vref1 to + Vref1) to the input of the first ADC 110, and the A / D converter 100 performs A. The value of β is estimated using the conversion result obtained by the / D conversion. For example, in FIG. 32 (b), when a median value of 0 V is input to the input of the first ADC 110, the A / D conversion result corresponding to P0 in which the first bit starts from zero and P1 in which the first bit starts from 1 are displayed. The corresponding A / D conversion result is obtained. The β value estimation control unit 222 can estimate the β value by paying attention to the fact that the two A / D conversion results obtained when the median value of 0 V is input show the same voltage.

[Fifth Embodiment]
In the fourth embodiment, in the A / D converter 100 in which the first ADC 110 and the second ADC 120 are combined, the accuracy of the A / D conversion due to the interstage offset voltage is deteriorated by increasing the value of Vref2. The method of reducing the problem was explained. However, when the value of Vref2 becomes large, the quantization noise of the second ADC 120 becomes large, and there is a problem that the SNDR (Signal to Noise and Distortion Ratio) deteriorates.

In the fifth embodiment, a digital-analog converter (hereinafter referred to as a D / A converter or DAC) is provided in the signal comparison node Vx of the second ADC 120 to positively cancel the offset voltage between the stages. An example of the configuration to be performed will be described.

FIG. 33 is a diagram showing an example of the circuit configuration of the A / D converter according to the fifth embodiment. The A / D converter 100 shown in FIG. 33 has a DAC (Digital to Analog Converter) 3301, a switch 3302, and a capacitive element 3303, in addition to the configuration of the A / D converter 100 according to the first embodiment shown in FIG. Etc. The switch 3302 and the capacitance element 3303 are examples of a circuit for applying the output voltage of the DAC 3301 to the signal comparison node Vx of the second ADC 120. For example, the output terminal of the DAC 3301 may be directly connected to the input terminal (signal comparison node Vx) of the comparator 240.

It is assumed that the DAC 3301 is preset or adjusted so as to output a voltage for canceling the interstage offset voltage between the first ADC 110 and the second ADC 120.

With the above configuration, in the A / D converter 100 in which the first ADC 110 and the second ADC 120 are combined, it is possible to reduce the deterioration of the accuracy of the A / D conversion due to the interstage offset voltage. Further, in the present embodiment, since it is not necessary to increase the value of Vref2, it is possible to reduce the problem that the quantization noise of the second ADC 120 becomes large and the SNDR deteriorates.

[Sixth Embodiment]
In the A / D converter 100 according to each of the above embodiments, in order for the β value estimation control unit 222 to accurately estimate the β value, when estimating the β value, the second ADC 120 (sequential conversion) It is desirable to increase the resolution of the ADC) by 1 to 2 bits. On the other hand, in the A / D converter 100, when performing normal A / D conversion, it is desirable not to increase the resolution by 1 to 2 bits in order to improve the conversion speed.

In the sixth embodiment, an example of the A / D converter 100 capable of improving the resolution of the second ADC 120 when estimating the value of β will be described.

FIG. 34 is a diagram showing an example of the circuit configuration of the A / D converter according to the sixth embodiment. The A / D converter 100 shown in FIG. 34 has a bit length control unit 3402 in addition to the configuration of the A / D converter 100 according to the first embodiment shown in FIG.

For example, when the β value estimation control unit 222 estimates the β value, the bit length control unit 3402 instructs the SAR250 of the second ADC 120 to increase the number of bits for sequential conversion A / D conversion (BIT_CNT). Is output.

Further, when the SAR 250 of the second ADC 120 receives a signal instructing an increase in the number of bits of the sequential conversion A / D conversion, the SAR250 has a predetermined number of bits (for example, 2 bits) more than that of the normal A / D conversion. Perform A / D conversion.

For example, in the second ADC 120, it is assumed that the plurality of capacitive elements CN-1 to C0 and the switch arrays SW_SAR and SW_Vres are provided with elements corresponding to redundant bits in advance. When performing a normal A / D conversion, the SAR250 of the second ADC 120 executes the sequential comparison A / D conversion without using the element corresponding to the redundant bit. On the other hand, when estimating the value of β, the SAR250 of the second ADC 120 executes sequential comparison A / D conversion using an element corresponding to the redundant bit.

With the above configuration, in the A / D converter 100 in which the first ADC 110 and the second ADC 120 are combined, the estimation accuracy of the β value is improved without affecting the conversion speed of the normal A / D conversion. You will be able to make it.

The bit length control unit 3402 is not limited to the case where the β value estimation control unit 222 estimates the β value, and increases the number of bits for sequential conversion A / D conversion when improving the accuracy of A / D conversion. It may be the one that instructs.

[7th Embodiment]
In the sixth embodiment, an example in which the bit length of the second ADC 120 (sequential comparison ADC) is changed when estimating the value of β has been described.

In the fifth embodiment, A / D conversion is performed by adding a dither signal such as a pseudo-random sequence to the signal comparison node Vx of the second ADC 120 and averaging the results of A / D conversion a plurality of times. An example of improving the substantial resolution (effective resolution) of the above will be described.

FIG. 35 is a diagram showing an example of the circuit configuration of the A / D converter according to the seventh embodiment. The A / D converter 100 shown in FIG. 35 has a dither signal generation unit 3501, a signal control unit 3502, and an average processing unit 3503, in addition to the configuration of the A / D converter 100 according to the first embodiment shown in FIG. Has.

The dither signal generation unit 3501 generates a dither signal such as a pseudo-random sequence according to the control of the signal control unit 3502, and inputs the dither signal generated to the signal comparison node Vx of the second ADC 120 (sequential comparison ADC). ..

For example, when the β value estimation control unit 222 estimates the β value, the signal control unit 3502 instructs the dither signal generation unit 3501 to generate a dither signal.

The averaging unit 3503 averages the residual signal Vres after the first ADC 110 performs A / D conversion of the high-order bit, and the result of the second ADC 120 performing A / D conversion a plurality of times. .. When the second ADC 120 samples the residual signal Vres once, it keeps holding the residual signal Vres according to the charge conservation law, so that the A / D conversion can be executed a plurality of times. By averaging the results of a plurality of A / D conversions, the substantial resolution of the A / D conversion can be improved.

Here, the effect of the dither signal will be described.

FIG. 36 is a diagram showing an image of A / D conversion when the circuit has low noise. For example, in FIG. 36, it is assumed that the value of the input voltage Vin is 10.25 and the value of n is 10. In the example of FIG. 36, since the circuit noise is small, the Vin value has a code transition noise range 3601 in which the A / D conversion result changes between 9 and 10, and the A / D conversion result is between 10 and 11. It shows a state not included in the code transition noise range 3602 that changes with. In this case, no matter how many times Vin is A / D converted and averaged, the A / D conversion result is 10, indicating that the effect of improving the substantial resolution of the A / D conversion cannot be obtained. ..

FIG. 37 is a diagram showing an image of A / D conversion when the circuit has high noise. In the example of FIG. 37, the circuit is noisy, the Vin value is in the code transition noise range 3701 in which the A / D conversion result changes between 9 and 10, and the A / D conversion result is between 10 and 11. It shows the state included in the changing code transition noise range 3702. In this case, the Vin conversion result changes between 9, 10, or 11, so that the A / D conversion result approaches 10.25 by performing and averaging the A / D conversion a plurality of times. Can be expected.

FIG. 38 is a diagram showing an image of A / D conversion when the circuit applies a dither signal with low noise. In FIG. 36, it is assumed that the dither signal generation unit 3501 generates uniform noise of, for example, ± 0.5 LSB.

In this case, Vin changes from 9.75 to 10.75, so the A / D conversion result is 10 or 11, and 11 appears at a ratio of 3: 1. Therefore, by executing the A / D conversion a plurality of times and averaging, the A / D conversion result approaches 10.25, that is, the effect of averaging can be obtained.

With the above configuration, in the A / D converter 100 in which the first ADC 110 and the second ADC 120 are combined, the β value is estimated without increasing the bit length of the second ADC 120 (sequential comparison ADC). The accuracy can be improved.

11 Comparator 13 Operational amplifier 100 A / D converter 110 β-conversion cyclic ADC (β-conversion cyclic A / D conversion circuit)
111 Arithmetic amplification unit 120 Sequential comparison ADC (sequential comparison type A / D conversion circuit)
222 β value estimation control unit 1300 Capacitive array 1300-1 First capacitive array 1300-2 Second capacitive array 3301 DAC (D / A conversion circuit)
3402 Bit length control unit 3501 Dither signal generator (signal generator)
3503 Average processing unit C _{0 to} C _N-1 , C _d Multiple capacitance elements Cb Integral capacitance SW3 switch (switching unit)
SW7 switch (input circuit)

Claims (10)

An A / D converter that combines multiple A / D conversion methods.
It is configured to include both a non-binary β-conversion cyclic A / D conversion circuit and a binary or lower sequential comparison type A / D conversion circuit.
The β conversion cyclic type A / D conversion circuit is applied to the A / D conversion circuit in charge of A / D conversion in a predetermined bit range.
The sequential comparison type A / D conversion circuit is applied to the A / D conversion circuit in charge of A / D conversion in a bit range lower than the predetermined bit range.
The successive approximation type A / D conversion circuit performs A / D conversion in the lower bit range using a capacitance array including a plurality of capacitance elements.
The β-conversion cyclic A / D conversion circuit uses the capacitance array as an integral capacitance to perform A / D conversion in the predetermined bit range.
The A / D conversion result of the predetermined bit range by the β conversion cyclic A / D conversion circuit and
Digitally, and the A / D conversion result of the lower bit range obtained by A / D conversion by the successive approximation A / D converter circuit a residual signal after A / D conversion of the predetermined bit range An A / D converter characterized by synthesizing in a synthesizing unit and obtaining an A / D conversion result output by the A / D converter. Having a plurality of said capacitive arrays
After the β-conversion cyclic A / D conversion circuit performs A / D conversion in the predetermined bit range using the first capacitive array, the successive approximation type A / D conversion circuit performs the lower bits. Perform A / D conversion of the range and
Before the A / D conversion of the lower bit range using the first capacitance array is completed, the β conversion cyclic type A is used by using a second capacitance array different from the first capacitance array. The A / D converter according to claim 1, wherein the / D conversion circuit performs an interleave operation to start A / D conversion in the predetermined bit range. An A / D converter that combines multiple A / D conversion methods.
It is configured to include both a non-binary β-conversion cyclic A / D conversion circuit and a binary or lower sequential comparison type A / D conversion circuit.
The β conversion cyclic type A / D conversion circuit is applied to the A / D conversion circuit in charge of A / D conversion in a predetermined bit range.
The sequential comparison type A / D conversion circuit is applied to the A / D conversion circuit in charge of A / D conversion in a bit range lower than the predetermined bit range.
The sequential comparison type A / D conversion circuit has a plurality of capacitive arrays including a plurality of capacitive elements, and has a plurality of capacitive arrays.
After the β-conversion cyclic A / D conversion circuit performs A / D conversion in the predetermined bit range using the first capacitive array, the successive approximation type A / D conversion circuit performs the lower bits. Perform A / D conversion of the range and
Before the A / D conversion of the lower bit range using the first capacitance array is completed, the β conversion cyclic type A is used using a second capacitance array different from the first capacitance array. / D converting circuit have rows interleave operation to start the a / D conversion of the predetermined bit range,
The A / D conversion result of the predetermined bit range by the β conversion cyclic A / D conversion circuit and
The A / D conversion result of the lower bit range obtained by A / D converting the residual signal after the A / D conversion of the predetermined bit range with the successive approximation type A / D conversion circuit is digitally obtained. An A / D converter characterized by synthesizing in a synthesizing unit and obtaining an A / D conversion result output by the A / D converter . One or more of the β-conversion cyclic A / D conversion circuits included in the A / D converter is an input for inputting a predetermined voltage to the input node of the β-conversion cyclic A / D conversion circuit. The A / D converter according to any one of claims 1 to 3, which has a circuit. A reference voltage Vref1 used in the β transformation cyclic A / D converter circuit,
The reference voltage Vref2 used in the successive approximation type A / D conversion circuit and
And the offset voltage Voff between the the β transformation cyclic A / D converter circuit and the successive approximation A / D converter circuit,
The A / D converter according to any one of claims 1 to 4, wherein Vref1 and Vref2 are set so that the relationship of Vref2 ≧ Vref1 + Voff is established between the two. It has a D / A conversion circuit connected to the signal comparison node of the sequential comparison type A / D conversion circuit.
The A / D converter according to any one of claims 1 to 5, wherein the output signal of the D / A conversion circuit is used to cancel the offset voltage of the sequential comparison type A / D conversion circuit. .. The A / D converter according to any one of claims 1 to 6, further comprising a signal generator for inputting a dither signal to the signal comparison node of the sequential comparison type A / D conversion circuit. Any of claims 1 to 7 having an averaging unit for averaging a plurality of A / D conversion results by the successive approximation type A / D conversion circuit to improve the effective resolution of the sequential comparison type A / D conversion circuit. The A / D converter according to item 1. The A / D converter according to any one of claims 1 to 8, further comprising a bit length control unit for changing the bit length of the A / D conversion executed by the successive approximation type A / D conversion circuit. The β-conversion cyclic A / D conversion circuit is
A comparator that compares the comparison voltage to be compared with the threshold value and outputs a digital value indicating the comparison result,
An arithmetic amplification unit having an amplification factor of β (1 <β <2) times and executing a predetermined operation according to the comparison result of the comparator to generate the residual signal.
When sampling the input signal, a switching unit that outputs the input signal as the comparison voltage and outputs the residual signal as the comparison voltage after the sampling is completed.
A β value estimation control unit that estimates the β value using the result of A / D conversion of a predetermined input voltage by the A / D converter.
Have,
The digital compositing unit
The β-ary A / D conversion result of the predetermined bit range by the β-conversion cyclic A / D conversion circuit is converted into binary using the estimation result of the β value estimated by the β value estimation control unit. Claim 1 is characterized in that the converted result is combined with the A / D conversion result of the lower bit range by the successive approximation type A / D conversion circuit, and the binary A / D conversion result is output. The A / D converter according to any one of 9 to 9.

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