JP2018064157A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter that is hardly made to operate erroneously by manufacturing dispersion and consumes reduced power, by assembling a plurality of A/D conversion circuits including a β conversion cyclic type A/D conversion circuit.SOLUTION: An A/D converter is configured to include both of a non-2-ary β conversion cyclic type A/D conversion circuit and a 2 or less-ary successive comparison type A/D conversion circuit. The β conversion cyclic type A/D conversion circuit is applied for an A/D conversion circuit in charge of A/D conversion in a predetermined bit range; the successive comparison type A/D conversion circuit is applied for an A/D conversion circuit in charge of A/D conversion in a bit range whose order is lower than that of the predetermined bit range. An A/D conversion result to be output by the A/D converter is obtained by a digital synthesis unit synthesizing a result of the A/D conversion in the predetermined bit range by the β conversion cyclic type A/D conversion circuit and a result of the A/D conversion in the lower order bit range obtained by the successive comparison type A/D conversion circuit performing A/D conversion on a residual signal after the A/D conversion in the predetermined bit range.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an A / D converter.

  An analog-digital converter (hereinafter referred to as an A / D converter) that converts an analog signal into a digital signal is widely used.

  Further, as a high-precision A / D converter with few malfunctions due to manufacturing variations, a cyclic A / D converter using β conversion that performs non-binary (= β-ary, 1 <β <2) encoding A β conversion pipeline A / D converter in which a plurality of β conversion cyclic A / D converters are connected in cascade is known (for example, see Patent Document 1).

JP 2013-70255 A

  FIG. 39 shows an example of the configuration of a β conversion pipeline A / D converter. In the example of FIG. 39, a β conversion pipeline ADC (Analog to Digital Converter) 1 includes a plurality of β conversion cyclic ADCs 10-1 to 10-n (n is a natural number of 2 or more) connected in cascade, and digital synthesis. + Β value estimation unit 20.

  The plurality of β conversion cyclic ADCs 10-1 to 10-n sample the input voltage Vin, and in order from the upper bit, the β conversion cyclic ADC 10-1, the β conversion cyclic ADC 10-2,. A / D conversion is performed using the click ADC 10-n.

  The digital synthesis + β value estimation unit 20 estimates the value of β (1 <β <2) indicating the amplification factor of the operational amplifier included in each of the plurality of β conversion cyclic ADCs 10-1 to 10-n. In addition, the digital synthesis + β value estimation unit 20 synthesizes A / D conversion results output from the plurality of β conversion cyclic ADCs 10-1 to 10-n using the estimated β value, and generates a β conversion pipeline. A digital output Dout that is an A / D conversion result of the ADC 1 is output.

  In such a β conversion pipeline ADC1, each of the plurality of β conversion cyclic ADCs 10-1 to 10-n includes an operational amplifier. In general, the operational amplifier consumes a large amount of current, and it is necessary to keep the current flowing while the signal is amplified (computed), which hinders the low power consumption of the β conversion pipeline ADC1.

  The embodiments of the present invention have been made in view of the above-described problems. A plurality of A / D conversion circuits including a β conversion cyclic A / D conversion circuit are combined to cause malfunction due to manufacturing variations. An object of the present invention is to provide an A / D converter that has low power consumption.

  An A / D converter (100) according to an embodiment of the present invention is an A / D converter (100) that combines a plurality of A / D conversion methods, and is a non-binary β conversion cyclic A / D converter. A D conversion circuit (110) and a successive approximation type A / D conversion circuit (120) of binary or less are included, and the A / D conversion circuit in charge of A / D conversion of a predetermined bit range is provided with the β A conversion cyclic A / D converter circuit (110) is applied, and the successive approximation A / D converter circuit (the A / D converter circuit in charge of A / D conversion in a bit range lower than the predetermined bit range) 120), the A / D conversion result of the predetermined bit range by the β conversion cyclic A / D conversion circuit (110) and the residual signal after A / D conversion of the predetermined bit range Obtained by A / D conversion by the successive approximation A / D converter circuit (120). The A / D conversion result in the lower bit range is synthesized by a digital synthesis unit (230), and an A / D conversion result output from the A / D converter (100) is obtained. To do.

Preferably, the successive approximation type A / D conversion circuit (120) uses an A / D of the lower bit range by using a capacitance array including a plurality of capacitance elements (C _{0 to} C _N-1 ) having different capacitance values. The conversion is performed, and the β conversion cyclic A / D conversion circuit (110) performs A / D conversion of the predetermined bit range using the capacitor array as an integration capacitor.

  Preferably, the A / D converter (100) includes a plurality of the capacitance arrays (1300), and the β conversion cyclic A / D conversion is performed using the first capacitance array (1300-1). After the circuit (110) performs A / D conversion of the predetermined bit range, the successive approximation A / D conversion circuit (120) performs A / D conversion of the lower bit range, and the first Before the A / D conversion of the lower bit range using the first capacitor array (1300-1), the second capacitor array (1300-2) different from the first capacitor array (1300-1) is completed. ), The β conversion cyclic A / D conversion circuit (110) performs an interleaving operation for starting A / D conversion of the predetermined bit range.

  Preferably, the one or more β conversion cyclic A / D conversion circuits (110) included in the A / D converter (100) are the β conversion cyclic A / D conversion circuits (110). An input circuit (SW7) for inputting a predetermined voltage to the input node is provided.

  Preferably, the A / D converter (100) is used in the reference voltage Vref1 used in the β conversion cyclic A / D conversion circuit (110) and in the successive approximation type A / D conversion circuit (120). Vref2 ≧ Vref1 + Voff between the reference voltage Vref2 and the offset voltage Voff between the β conversion cyclic A / D conversion circuit (110) and the successive approximation A / D conversion circuit (120). Vref1 and Vref2 are set so that the following holds.

  Preferably, the A / D converter is connected to a signal comparison node Vx serving as an input to a comparator (240) that performs a magnitude comparison with a reference voltage of the successive approximation A / D conversion circuit (120). A D / A conversion circuit (3301) is included, and the offset voltage of the successive approximation type A / D conversion circuit (120) is canceled using the output signal of the D / A conversion circuit (3301). .

  Preferably, the A / D converter (100) includes a signal generator (3501) that inputs a dither signal to the signal comparison node Vx of the successive approximation A / D converter circuit (120).

  Preferably, the A / D converter (100) averages a plurality of A / D conversion results by the successive approximation A / D converter circuit (120), and the successive approximation A / D converter circuit (120). ) Has an average processing unit (3503) for improving the effective resolution.

  Preferably, the A / D converter (100) includes a bit length control unit (3402) that changes a bit length of A / D conversion executed by the successive approximation A / D conversion circuit (120).

  Preferably, the β conversion cyclic A / D conversion circuit (110) compares a comparison voltage to be compared with a threshold value and outputs a digital value indicating a comparison result, and β An operational amplification unit (111) having an amplification factor of (1 <β <2), performing a predetermined calculation according to the comparison result of the comparator to generate the residual signal, and an input signal When sampling, the input signal is output as the comparison voltage, and after the sampling is completed, the switching unit (SW3) that outputs the residual signal as the comparison voltage, and a predetermined voltage is output to the A / D converter A β value estimation control unit (222) that estimates the value of β using the result of A / D conversion in (100), and the digital synthesis unit (230) is configured to perform the β conversion cyclic type. The predetermined by the A / D conversion circuit (110) The result of converting the β range A / D conversion result of the bit range into binary using the estimation result of the β value estimated by the β value estimation control unit (222), and the successive approximation type A / D The A / D conversion result of the lower bit range by the conversion circuit (120) is synthesized, and a binary A / D conversion result is output.

  According to the present invention, it is possible to provide an A / D converter that combines a plurality of A / D conversion circuits including a β-conversion cyclic A / D conversion circuit, reduces malfunction due to manufacturing variations, and consumes less power. it can.

It is a figure which shows the structural example of the A / D converter which concerns on one Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 1st Embodiment. It is a figure for demonstrating the example of operation | movement of (beta) conversion cyclic ADC. It is a figure (1) which shows the example of a setting of the switch of beta conversion cyclic ADC. It is a figure (2) which shows the example of a setting of the switch of beta conversion cyclic ADC. It is a flowchart which shows the example of a process of the A / D converter which concerns on 1st Embodiment. It is a figure which shows the example of the process timing of the A / D converter which concerns on 1st Embodiment. It is a figure (1) which shows the example of a setting of the switch of the A / D converter concerning a 1st embodiment. It is FIG. (2) which shows the example of a setting of the switch of the A / D converter which concerns on 1st Embodiment. It is a figure (3) which shows the example of a setting of the switch of the A / D converter concerning a 1st embodiment. It is a figure (4) which shows the example of a setting of the switch of the A / D converter concerning a 1st embodiment. It is FIG. (5) which shows the example of a setting of the switch of the A / D converter which concerns on 1st Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 2nd Embodiment. It is a figure which shows the example of the circuit structure of the capacity | capacitance array which concerns on 2nd Embodiment. It is a flowchart which shows the example of a process of the A / D converter which concerns on 2nd Embodiment. It is a figure which shows the example of the process timing of the A / D converter which concerns on 2nd Embodiment. It is a figure (1) which shows the example of a setting of the switch of the A / D converter concerning a 2nd embodiment. It is FIG. (2) which shows the example of a setting of the switch of the A / D converter which concerns on 2nd Embodiment. It is FIG. (3) which shows the example of a setting of the switch of the A / D converter which concerns on 2nd Embodiment. It is FIG. (4) which shows the example of a setting of the switch of the A / D converter which concerns on 2nd Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 3rd Embodiment. It is a flowchart which shows the example of a process of the A / D converter which concerns on 3rd Embodiment. It is a figure which shows the example of the process timing of the A / D converter which concerns on 2nd Embodiment. It is FIG. (1) which shows the example of a setting of the switch of the A / D converter which concerns on 3rd Embodiment. It is FIG. (2) which shows the example of a setting of the switch of the A / D converter which concerns on 3rd Embodiment. It is FIG. (3) which shows the example of a setting of the switch of the A / D converter which concerns on 3rd Embodiment. It is FIG. (4) which shows the example of a setting of the switch of the A / D converter which concerns on 3rd Embodiment. It is a figure (5) which shows the example of a setting of the switch of the A / D converter which concerns on 3rd Embodiment. It is a figure (6) which shows the example of a setting of the switch of the A / D converter which concerns on 3rd Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 4th Embodiment. It is a figure which shows the example of the beta conversion pipeline A / D converter which concerns on 4th Embodiment. It is a figure for demonstrating the reference voltage which concerns on 4th Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 5th Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 6th Embodiment. It is a figure which shows the example of the circuit structure of the A / D converter which concerns on 7th Embodiment. It is a figure which shows the image of A / D conversion in case a circuit is low noise. It is a figure which shows the image of A / D conversion in case a circuit is high noise. It is a figure which shows the image of A / D conversion when a circuit applies a dither signal with low noise. It is a figure which shows an example of a structure of (beta) conversion pipeline ADC.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

<Configuration of A / D converter>
FIG. 1 is a diagram illustrating a configuration example of an A / D converter according to an embodiment. The A / D converter (analog-to-digital converter) 100 is a device (or circuit) that converts an analog signal into a digital signal, converts the analog input signal Vin into a digital signal Dout having a predetermined number of bits, and outputs it. To do.

  FIG. 1A shows an example of an A / D converter 100 according to an embodiment. The A / D converter 100 includes a β conversion cyclic ADC (Analog to Digital Converter) 110, a successive approximation ADC 120, and a digital synthesis + β value estimation unit 130. The A / D converter 100 is a β (1 <β <2) base β conversion cyclic ADC 110 (β conversion) as an A / D conversion circuit in charge of A / D conversion of upper bits that require circuit accuracy. A cyclic A / D converter circuit) is applied. In addition, as an A / D conversion circuit in charge of A / D conversion of lower-order bits that reduces the accuracy requirement of the circuit, for example, a binary successive approximation ADC 120 (successive comparison type A / D conversion circuit) is applied. Note that the successive approximation ADC 120 is not limited to a binary successive approximation ADC, and may be any one that uses a binary or lower successive approximation ADC.

  The A / D converter 100 that combines these two A / D conversion methods includes a digital synthesis unit that synthesizes the digital bits output from the β conversion cyclic ADC 110 and the digital bits output from the successive approximation ADC 120. I need it. Further, the A / D converter 100 requires a β value estimation operation for estimating the value of β actually realized on the chip and a β estimation control unit for executing the β value estimation algorithm. In the example of FIG. 1, the digital synthesis + β value estimation unit 130 includes the digital synthesis unit and the β estimation control unit.

  FIG. 1B shows another example of the A / D converter 100 according to an embodiment. As shown in FIG. 1B, the β conversion cyclic ADC that realizes A / D conversion of the upper bits is composed of a plurality of stages of β conversion cyclic ADCs 110-1, 110-2,. It may be. Further, the successive approximation ADC 120 that realizes A / D conversion of the lower bits may be a one or more successive approximation ADC 120.

  That is, the A / D converter 100 applies the β conversion cyclic ADC 110 to the A / D conversion circuit in charge of A / D conversion of a predetermined bit range, and the A / D of a bit range lower than the predetermined bit range. What is necessary is just to apply the successive approximation ADC 120 to the conversion circuit. In this case, the A / D converter 100 uses the successive approximation ADC 120 to convert the A / D conversion result of the predetermined bit range by the β conversion cyclic ADC 110 and the A / D converted residual signal of the predetermined bit range by the successive approximation ADC 120. The A / D conversion result of the lower bit range obtained by D conversion is synthesized, and the A / D conversion result output from the A / D converter 100 is obtained.

  Next, a specific configuration of the A / D converter 100 will be described by exemplifying a plurality of embodiments.

[First Embodiment]
<Configuration of A / D converter>
FIG. 2 is a diagram illustrating an example of a circuit configuration of the A / D converter according to the first embodiment. 2, an A / D converter 100 corresponds to the A / D converter 100 shown in FIG. 1A, and includes a β conversion cyclic ADC 110, a successive approximation ADC 120, a reference voltage generation circuit 210, and an overall control unit. 220, a digital synthesis unit 230, and the like.

(Configuration of β conversion cyclic ADC)
A β conversion cyclic ADC 110 (hereinafter referred to as a first ADC) is a β-ary (non-binary) A / D conversion circuit. For example, as shown in FIG. 2, a comparator 11, a DAC unit 12, It includes an operational amplifier 13, capacitive elements 14a and 14b, and a plurality of switches SW1 to SW7.

  The first ADC 110 does not encode a digital signal by binary encoding. For example, as shown in Patent Document 1, β that uses a value of β that is a number larger than 1 and smaller than 2 is used. A digital signal is encoded by hexadecimal encoding.

  The comparator (Sub-ADC) 11 compares a predetermined threshold voltage (VCM in the example of FIG. 2) with the sampling voltage Vs output from the switch SW3 (switching unit), and compares the comparison result. A 1-bit digital signal is output. The comparator 11 is realized by, for example, a comparator.

  For example, the comparator 11 outputs “1” when the sampling voltage Vs to be compared is higher than VCM, and outputs “0” when the sampling voltage Vs is equal to or lower than VCM. Note that VCM is, for example, the median value (for example, 0 V) of the full-scale voltage Vfs (reference voltage + Vref to −Vref) in the first ADC 110.

  The DAC unit 12 is a circuit that selectively outputs the reference voltage + Vref or −Vref according to the comparison result of the comparator 11, and is realized by, for example, a multiplexer. The DAC unit 12 outputs + Vref when the comparator 11 determines that the sampling voltage Vs is higher than VCM, and outputs −Vref when it is determined that the sampling voltage Vs is lower than VCM.

  The operational amplifier 111 has a gain (gain) that is β (1 <β <2) times, and performs a predetermined calculation according to the comparison result of the comparator 11 to generate a residual signal Vres. For example, it is realized by an operational amplifier or the like. Note that the value of β representing the amplification factor of the operational amplifier 111 is set in advance so that 1 <β <2 by the ratio of the capacitance value Ca of the capacitive element 14a and the capacitance value Cb of the capacitive element 14b. It shall be.

  The capacitive element 14a is a capacitive element having a capacitance value Ca, and the capacitive element 14b is a capacitive element having a capacitance value Cb. The capacitive elements 14a and 14b are realized by, for example, capacitors.

  The switches SW <b> 1 to SW <b> 7 are switch elements that switch connection and disconnection of signals under the control of the overall control unit 220. The β conversion cyclic ADC has three operation states, and the overall control unit 220 switches the switches SW1 to SW7 so as to be in a connection state corresponding to each operation state.

(Operation of β conversion cyclic ADC)
Here, the operation of the first ADC 110 will be described with reference to FIGS. FIG. 3 is a diagram for explaining an example of the operation of the β conversion cyclic ADC. 4 and 5 are diagrams illustrating setting examples of the switches of the first ADC 110. FIG.

  FIG. 3A is a flowchart showing a flow of A / D conversion processing of the first ADC 110.

  In step S301, the overall control unit 220 switches the switches SW1 to SW6 of the first ADC 110 as shown in FIG. 4A, for example, thereby changing the input signal Vin of the first ADC 110 to the capacitive element 14a (Ca ) And the capacitor element 14b (Cb). In the following description, this state is referred to as an operation state (A).

  In the operation state (A), as shown in FIG. 4A, the overall control unit 220 controls the switch SW1 so that the capacitive element 14b is connected to Vin, so that the capacitive element 14a is connected to Vin. The switch SW2 is controlled. Further, the overall control unit 220 controls the switch SW3 so that Vin is input to the comparator 11 as the sample voltage Vs (comparison voltage). Further, the overall control unit 220 controls to disconnect the switch SW4 and connect the switches SW5 and SW6.

  Note that the overall control unit 220 controls the switch SW7 so that the VCM is input to the first ADC 110 only when performing the β value estimation operation for estimating the value of β. It is assumed that SW7 is fixedly set so that Vin is input.

FIG. 3B is a diagram illustrating the timing of the A / D conversion process of the first ADC 110. As shown in FIG. 3B, at the end of the first operation state (A), the comparison result of the comparator 11 is updated and the first output bit (most significant bit) b ₀ is output.

  Thereafter, in step S302, the overall control unit 220 amplifies the signal according to the comparison result of the comparator 11 by switching the switches SW1 to SW6 of the first ADC 110 as shown in FIG. 4B, for example. A signal amplification operation is performed. In the following description, this state is referred to as an operation state (B).

  In the operating state (B), the overall control unit 220 controls the switch SW1 so that the capacitive element 14b is connected to the residual signal Vres output from the operational amplification unit 111, as shown in FIG. 4B. . Further, the overall control unit 220 controls the switch SW2 so that the capacitive element 14a is connected to the output of the DAC unit 12. Further, the overall control unit 220 controls the switch SW3 so as to input Vres as the sample voltage Vs to the comparator 11. Furthermore, the overall control unit 220 controls to disconnect the switches SW4 and SW5 and connect the switch SW6.

  In this operating state (B), when the comparator 11 determines that the sample voltage Vs is higher than VCM, the operational amplifier 111 assumes that the voltage sampled in the capacitive element 14a is Vres ′, and the output voltage Vres = Vres ′ × β + (1−β) Vref is output. On the other hand, when the comparator 11 determines that the sample voltage Vs is lower than VCM, the operational amplifier 111 outputs the output voltage Vres = Vres ′ × β + (β−1) Vref.

  In step S303, the overall control unit 220 performs a cyclic sampling operation by switching the switches SW1 to SW6 of the first ADC 110, for example, as shown in FIG. In the following description, this state is referred to as an operation state (C).

  In the operation state (C), as shown in FIG. 5, the overall control unit 220 controls the switch SW1 so that the capacitive element 14b is connected to the residual signal Vres, and the capacitive element 14a is connected to the residual signal Vres. The switch SW2 is controlled as described above. Further, the overall control unit 220 controls the switch SW3 so as to output a residual signal Vres as the sample voltage Vs to the comparator 11. Further, the overall control unit 220 controls the switch SW4 to be connected and the switches SW5 and SW6 to be disconnected.

  In this operation state (C), the first ADC 110 samples the residual signal Vres stored in the capacitive element 14b created by the signal amplification operation in step S302 in the capacitive element 14a on the input side.

At this time, as shown in FIG. 3B, at the end of the first operation state (C), the comparison result of the comparator 11 is updated, and the second output bit b ₁ is output.

  In step S304, the overall control unit 220 determines whether a predetermined number of bits X (for example, 5 bits) has been obtained.

When the output bits B _x (= b ₀ , b ₁ ,..., B _x−1 ) having a predetermined number of bits are obtained, the overall control unit 220 ends one A / D conversion process. On the other hand, if the predetermined number of bits is not obtained, the overall control unit 220 returns the process to step S302 and executes the same process again.

(Successive comparison ADC)
The successive approximation ADC 120 (hereinafter referred to as a second ADC) includes N capacitive elements C _{0 to} C _N−1 having a binary (binary) weighted value and an dummy. capacitor array including a capacitor _{C d,} the comparator 240, SAR250, a switch SW10, switch array SW_SAR, SW_Vres like.

For the sake of simplicity, the description has been made with the configuration using the capacitive element having the binary weighted value. However, the capacitive elements C _{0 to} C _N−1 and C _d are configured by a combination of capacitive elements of unit capacitance. You may do it.

According to the output logic of the SAR (successive approximation register) 250, the second ADC 120 has the same logic (D _N−1 ,..., D ₀ , D _d ) as the outputs of the switches connected to + Vref and −Vref. Switch the switch as follows. The SAR 250 changes the output voltage Vx by sequentially switching the switches from the upper bit (D _N-1 ) side, and performs successive approximation A / D conversion that specifies an A / D conversion value by a bisection method.

The comparator 240 compares a predetermined threshold voltage (for example, V _CM ) with an output voltage Vx (hereinafter, a terminal to which the voltage Vx is input is referred to as a voltage comparison node), and compares the comparison result. and outputs a 1-bit digital values d _Y shown. The comparator 240 obtains output bits Dy (= d ₀ , d ₁ ,..., D _Y−1 ) having a predetermined number of bits Y according to the output of the SAR (successive approximation register) 250.

  In addition, the overall control unit 220 connects the switches included in the switch array SW_Vres, so that the residual signal Vres after the A / D conversion of the upper bits in the first ADC 110 is performed by the second ADC 120. Input as an input signal. As a result, the second ADC 120 performs A / D conversion of the input residual signal Vres to identify the lower bits.

(Reference voltage generation circuit)
The reference voltage generation circuit 210 generates a reference value + Vref, −Vref, and a median value VCM (for example, 0 V) of + Vref to −Vref.

(Overall control unit)
The overall control unit 220 includes a switch control unit 221, a β value estimation control unit 222, and an AD conversion control unit 223.

  The switch control unit 221 outputs a control signal for controlling connection / disconnection of the switches SW1 to SW7, SW10, the switch array SW_Vres, and the like according to the control of the β value estimation control unit 222 or the AD conversion control unit 223.

  The β value estimation control unit 222 estimates the value of the amplification factor β of the operational amplification unit 111 actually realized on the chip. For example, the β value estimation control unit 222 controls the switch SW7 to input the median value VCM of the reference voltages + Vref and −Vref to the input of the A / D converter 100, and executes A / D conversion. Further, the β value estimation control unit 222 obtains an A / D conversion result starting from zero and an A / D conversion result starting from 1 as the first bit obtained as a result of executing the A / D conversion. Focusing on the equality, the value of β is estimated.

  The AD conversion control unit 223 uses the switch control unit 221 to control connection / disconnection of the switches SW1 to SW7, SW10 and the switch array SW_Vres, and controls A / D conversion in the A / D converter 100.

(Digital synthesis part)
The digital synthesis unit 230 includes a Radix conversion unit 231 and an adder 232.

Radix conversion unit 231, a β advance digital bit _{B x} output from the β transformation cyclic ADC 110, using the estimated results of the β value by β value estimation control unit 222, and converts the Radix from β proceeds to binary 2 The base digital bit DB _x is generated.

The adder 232 adds the binary digital bit DB _x generated by the Radix conversion unit 231 and the digital bit D _y output from the successive approximation ADC 120 to generate a binary digital output signal Dout.

<Process flow>
Next, the flow of A / D conversion processing by the A / D converter 100 will be described.

  FIG. 6 is a flowchart illustrating an example of processing of the A / D converter according to the first embodiment. In FIG. 6, processing 610 in steps S601 to S605 indicates processing by the first ADC 110, and processing 620 illustrated in steps S606 and S607 indicates processing by the second ADC 120. Note that the processing in steps S601 to S604 in FIG. 6 corresponds to the processing in steps S301 to S304 in FIG.

  In step S601, the AD conversion control unit 223 of the overall control unit 220 performs a sampling operation for sampling the input signal Vin into the capacitive element 14a (Ca) and the capacitive element 14b (Cb). For example, the AD conversion control unit 223 uses the switch control unit 221 to switch the switches SW1 to SW6 and SW10 and the switch array SW_Vres of the A / D converter 100 as illustrated in FIG. In the following description, this state is referred to as an operation state (A).

  In the operation state (A), the AD conversion control unit 223 of the overall control unit 220 sets the switches SW1 to SW6 of the first ADC 110 as described above with reference to FIG. The AD conversion control unit 223 controls the SW 10 and the switch array SW_Vres to be in a disconnected state. As a result, the input signal Vin is sampled in the capacitive elements 14 a and 14 b of the first ADC 110.

  Note that the AD conversion control unit 223 controls the switch SW7 to input Vin to the first ADC 110 during the A / D conversion operation, and does not perform switching.

FIG. 7 is a diagram illustrating an example of processing timing of the A / D converter 100. As shown in FIG. 7, when the sampling of the input signal Vin1 is completed in the operation state (A) at time t1, the comparison result of the comparator 11 is updated, and bit _n-1 which is the most significant bit is output.

  In step S <b> 602, the AD conversion control unit 223 of the overall control unit 220 performs a signal amplification operation for amplifying a signal according to the comparison result of the comparator 11. For example, the AD conversion control unit 223 uses the switch control unit 221 to switch the switches SW1 to SW6 and SW10 and the switch array SW_Vres of the A / D converter 100 as illustrated in FIG. In the following description, this state is referred to as an operation state (B).

  In the operation state (B), the AD conversion control unit 223 of the overall control unit 220 sets the switches SW1 to SW6 of the first ADC 110 as described above with reference to FIG. In addition, the AD conversion control unit 223 maintains the disconnected state of the SW 10 and the switch array SW_Vres. Thereby, the first ADC 110 amplifies the signal according to the comparison result of the comparator 11, and stores the residual signal Vres in the capacitive element 14b.

  In step S603, the AD conversion control unit 223 of the overall control unit 220 performs a cyclic sampling operation. For example, the AD conversion control unit 223 uses the switch control unit 221 to switch the switches SW1 to SW6 and SW10 and the switch array SW_Vres of the A / D converter 100 as illustrated in FIG. In the following description, this state is referred to as an operation state (C).

  In the operation state (C), the AD conversion control unit 223 of the overall control unit 220 sets the switches SW1 to SW6 of the first ADC 110 as described above with reference to FIG. In addition, the AD conversion control unit 223 maintains the disconnected state of the SW 10 and the switch array SW_Vres. As a result, the residual signal Vres stored in the capacitive element 14b in step S602 is sampled in the capacitive element 14a on the input side.

As shown in FIG. 7, at the end of the first operation state (C), the comparison result of the comparator 11 is updated and bit _n-2 is output.

  In step S604, the AD conversion control unit 223 of the overall control unit 220 determines whether a predetermined number of bits (n−k bits in the example of FIG. 7) has been obtained.

  When the predetermined number of bits is not obtained, the AD conversion control unit 223 repeatedly executes the processes of steps S602 to S604 until the predetermined number of bits is obtained. On the other hand, when the predetermined number of bits is obtained, the AD conversion control unit 223 shifts the processing to step S605.

  In step S605, the AD conversion control unit 223 of the overall control unit 220 causes the first ADC 110 to hold the residual signal Vres for a predetermined period. For example, the AD conversion control unit 223 controls the switches SW1 to SW6 of the first ADC 110 as illustrated in FIG. Thereby, the first ADC 110 holds the residual signal Vres. In the following description, this state is referred to as an operation state (D).

At this time, the second ADC 120 samples the residual signal Vres (step S606). For example, the residual signal Vres is sampled in each of the capacitive elements C _{0 to} C _{N−1 and} C _d included in the capacitive array of the second ADC 120. In the following description, this state is referred to as an operation state (E).

  As shown in FIG. 7, at time t2, after the first ADC 110 outputs bit k, the first ADC 110 is set to the state (D) and the second ADC 120 is set to the state (E). The At time t3, when the sampling of the residual signal Vres by the second ADC 120 is completed, the first ADC 110 can sample the next input signal Vin2.

  In step S607 of FIG. 6, the SAR 250 of the second ADC 120 controls the switch array SW_SAR to execute successive approximation A / D conversion to obtain lower bits. In the following description, this state is referred to as an operation state (F).

  In the operation state (F), the AD conversion control unit 223 controls the switches SW1 to SW6 of the first ADC 110, for example, as shown in FIG. Sampling of the signal Vin2 can be started.

  In step S608, the digital synthesis unit 230 synthesizes the upper digital bits output from the first ADC 110 in steps S601 to S604 and the lower digital bits output from the second ADC 120 in step S607. Output the conversion result.

  With the above processing, the A / D converter 100 executes the A / D conversion of the upper bits, which require circuit accuracy, by the β conversion cyclic ADC 110, and the lower bit A, which reduces circuit accuracy requirements. / D conversion can be realized by the successive approximation ADC 120. This eliminates the need for an operational amplifier for A / D conversion of the lower bits, so that a plurality of A / D conversion circuits including a β conversion cyclic A / D conversion circuit can be combined to reduce malfunctions due to manufacturing variations and consumption. An A / D converter with low power can be provided.

[Second Embodiment]
In the second embodiment, as another preferable example, the capacitor array (C _{0 to} C _N−1, C _d) of the second ADC 120 is used as the integration capacitor Cb of the first ADC (β conversion cyclic ADC 110). An example of a configuration used as will be described.

  The A / D converter 100 according to the second embodiment A / D-converts the residual signal Vres after the A / D conversion of the upper bits by the first ADC 110 as it is by the second ADC 120. Will be able to. Thereby, for example, the processing of steps S605 and S606 in FIG. 6 can be omitted. In the A / D converter 100 according to the present embodiment, the sampling error in the A / D converter 100 can be reduced by eliminating the error due to the sampling in the successive approximation ADC 120.

<Configuration of A / D converter>
FIG. 13 is a diagram illustrating an example of a circuit configuration of the A / D converter according to the second embodiment. An A / D converter 100 illustrated in FIG. 13 includes a capacitor array 1300 instead of the capacitor 14b and the switch SW1 of the A / D converter 100 according to the first embodiment illustrated in FIG.

FIG. 14 is a diagram illustrating an example of a circuit configuration of the capacitor array according to the second embodiment. The capacitive array 1300 includes N capacitive elements C _{0 to} C _N−1 having a binary weighted value and one dummy capacitive element C _d included in the second ADC 120 according to the first embodiment. Including. The capacitor array 1300 includes a switch array SW_Vin in addition to the switch arrays SW_SAR and SW_Vres included in the second ADC 120 according to the first embodiment. 13 and 14, the same reference numerals are assigned to the components described in the A / D converter 100 according to the first embodiment shown in FIG. 2, and detailed description thereof is omitted here.

The overall control unit 220 of the A / D converter 100 controls the switch array SW_Vin and connects Vin to the capacitive elements C _{0 to} C _N−1 and C _d , thereby causing the capacitive elements C _{0 to} C _N−1. it can be employed including synthetic capacity _{C d} as an integral capacitance Cb of the first ADC 110.

<Process flow>
Next, the flow of A / D conversion processing by the A / D converter 100 according to the second embodiment will be described.

  FIG. 15 is a flowchart illustrating an example of processing of the A / D converter according to the second embodiment.

  In step S1501, the AD conversion control unit 223 of the overall control unit 220 performs a sampling operation for sampling the input signal Vin into the capacitive element 14a (Ca) and the capacitive array 1300 (Cb). For example, the AD conversion control unit 223 uses the switch control unit 221 to change the switches SW2 to SW7 of the A / D converter 100 and the switch arrays SW_Vres and SW_Vin of the capacitor array 1300 into FIGS. 17A and 17B. Set as shown in. In the following description, this state is referred to as an operation state (A).

  In the operation state (A), as shown in FIGS. 17A and 17B, the switches SW2 to SW7 and the switch array SW_Vres of the capacitor array 1300 are set according to the operation according to the first embodiment shown in FIG. This is the same as setting the state (A). In addition, as illustrated in FIG. 17B, the AD conversion control unit 223 places each switch included in the switch array SW_Vin of the capacitor array 1300 in a connected state. As a result, the A / D converter 100 functions as a β conversion cyclic ADC, and the input signal Vin is sampled in the capacitor array 1300 (Cb).

FIG. 16 is a diagram illustrating an example of processing timing of the A / D converter according to the second embodiment. As shown in FIG. 16, when the sampling of the input signal Vin1 is completed in the operation state (A) at time t1, the comparison result of the comparator 11 is updated, and bit _n-1 which is the most significant bit is output.

  In step S <b> 1502, the AD conversion control unit 223 of the overall control unit 220 performs a signal amplification operation that amplifies the signal according to the comparison result of the comparator 11. For example, the AD conversion control unit 223 uses the switch control unit 221 to change the switches SW2 to SW7 of the A / D converter 100 and the switch arrays SW_Vres and SW_Vin of the capacitor array 1300 into FIGS. 18A and 18B. Set as shown in. In the following description, this state is referred to as an operation state (B).

  In the operating state (B), as shown in FIGS. 18A and 18B, the settings of the switches SW2 to SW7 are the same as the setting of the operating state (B) according to the first embodiment shown in FIG. . Further, as illustrated in FIG. 18B, the AD conversion control unit 223 sets each switch included in the switch array SW_Vin to a disconnected state and sets each switch included in the switch array SW_Vres to a connected state. As a result, the A / D converter 100 amplifies the signal according to the comparison result of the comparator 11, and stores the residual signal Vres in the capacitor array 1300 (Cb).

  In step S1503, the AD conversion control unit 223 of the overall control unit 220 performs a cyclic sampling operation. For example, the AD conversion control unit 223 uses the switch control unit 221 to change the switches SW2 to SW7 of the A / D converter 100 and the switch arrays SW_Vres and SW_Vin of the capacitor array 1300 into FIGS. 19A and 19B. Set as shown in. In the following description, this state is referred to as an operation state (C).

  In the operating state (C), as shown in FIGS. 19A and 19B, the settings of the switches SW2 to SW7 are the same as the setting of the operating state (C) according to the first embodiment shown in FIG. . Further, as illustrated in FIG. 19B, the AD conversion control unit 223 maintains each switch included in the switch array SW_Vin in a disconnected state and each switch included in the switch array SW_Vres in a connected state. As a result, the residual signal Vres stored in the capacitor array 1300 (Cb) in step S1502 is sampled in the input-side capacitor element 14a.

As shown in FIG. 16, at the end of the first operation state (C), the comparison result of the comparator 11 is updated and bit _n-2 is output.

  In step S1504, the AD conversion control unit 223 of the overall control unit 220 determines whether a predetermined number of bits (for example, 5 bits) has been obtained.

  When the predetermined number of bits is not obtained, the AD conversion control unit 223 repeatedly executes the processes of steps S1502 to S1504 until the predetermined number of bits is obtained. On the other hand, when the predetermined number of bits is obtained, the AD conversion control unit 223 shifts the processing to step S1505.

  In FIG. 16, in the A / D converter 100 according to the second embodiment, when the β conversion cyclic ADC 110 outputs bit k at time t2, the residual signal Vres is already stored in the capacitor array 1300. Therefore, the A / D converter 100 according to the present embodiment omits the processing of the operating states (D) and (E) of the first embodiment shown in FIG. 7, and immediately performs successive approximation A / D conversion at time t2. Can start.

  In step S1505, the AD conversion control unit 223 of the overall control unit 220 uses the switch control unit 221 to switch the switches SW2 to SW7 of the A / D converter 100 and the switch arrays SW_Vres and SW_Vin of the capacitance array 1300. Settings are made as shown in FIGS. 20 (a) and 20 (b). In the following description, this state is referred to as an operation state (F).

  In the operating state (F), the settings of the switches SW2 to SW7 maintain the operating state (C). Further, as shown in FIG. 20B, the AD conversion control unit 223 turns off the switches included in the switch arrays SW_Vres and SW_Vin. As a result, the A / D converter 100 functions as a successive approximation ADC and can perform successive approximation A / D conversion using the capacitor array 1300.

In this state, in steps S1501 to S1504, the A / D converter 100 performs A / D conversion on the residual signal Vres after A / D conversion of the upper bits as a successive approximation ADC, and obtains lower bits. For example, the A / D converter 100 changes the output voltage Vx by sequentially switching the switch connected to + Vref and −Vref from the upper bit (D _N−1 ) side according to the output of the SAR 250, and bisects The successive approximation A / D conversion for specifying the A / D conversion value is performed.

  In step S1506, the digital synthesizing unit 230 generates the output signal Dout by synthesizing the upper digital bits output in steps S1501 to S1504 and the lower digital bits output in step S1505.

  As a result of the above processing, the A / D converter 100 performs β conversion cyclic A / D conversion on the A / D conversion of the upper bits for which the circuit accuracy is required, and lower bits for which the circuit accuracy requirement is relaxed. These A / D conversions can be subjected to successive approximation A / D conversion. As a result, since a circuit can be configured with one operational amplifier, a plurality of A / D conversion circuits including a β conversion cyclic A / D conversion circuit are combined to reduce malfunction due to manufacturing variations and reduce power consumption. A small number of A / D converters can be provided.

  Further, in the A / D converter 100 according to the present embodiment, the process of sampling the residual signal Vres after performing the β conversion cyclic A / D conversion of the upper bits by the successive approximation A / D conversion is omitted. be able to. In the A / D converter 100 according to the present embodiment, the sampling error in the A / D converter 100 can be reduced by eliminating the error due to the sampling in the successive approximation ADC 120.

[Third Embodiment]
In the second embodiment, the example of the A / D converter 100 using the capacitor array 1300 used in the successive approximation A / D conversion as the integration capacitor Cb of the β conversion cyclic A / D conversion has been described. In this case, sampling of the next input signal Vin cannot be started until the A / D converter 100 finishes the successive approximation A / D conversion.

  In the third embodiment, before the successive approximation A / D conversion using the first capacitor array is completed using the plurality of capacitor arrays 1300, the second input signal Vin is input using the second capacitor array. A configuration example for performing an interleaving operation for starting sampling will be described.

<Configuration of A / D converter>
FIG. 21 is a diagram illustrating an example of a circuit configuration of an A / D converter according to the third embodiment. An A / D converter 100 illustrated in FIG. 13 includes a first capacitor array 1300-1 and a second capacitor instead of the capacitor array 1300 of the A / D converter 100 according to the second embodiment illustrated in FIG. It has an array 1300-2 and switches SW21 and SW22. The configurations of the first capacitor array 1300-1 and the second capacitor array 1300-2 are the same as those of the capacitor array 1300 according to the first embodiment shown in FIG.

  The A / D converter 100 according to the present embodiment uses the second capacitor array 1300-2 to perform β conversion when performing the successive approximation A / D conversion using the first capacitor array 1300-1. Cyclic A / D conversion can be executed in parallel.

  The switch SW21 connects Vout of the first capacitor array 1300-1 to the input terminal of the operational amplifier 13 or the input terminal of the comparator 240 under the control of the overall control unit 220. The switch SW22 connects Vout of the second capacitor array 1300-2 to the input terminal of the operational amplifier 13 or the input terminal of the comparator 240 under the control of the overall control unit 220.

  In the first capacitor array 1300-1, the switches included in the switch array SW_Vin shown in FIG. 14 are connected, and Vout is connected to the input terminal of the operational amplifier 13 by the switch SW21. It functions as an integration capacitor Cb.

  Further, the first capacitor array 1300-1 is configured so that each switch included in the switch arrays SW_Vin and SW_Vres is in a disconnected state, and Vout is connected to the input terminal of the comparator 240 by the switch SW <b> 21, thereby Function as. The same applies to the second capacitor array 1300-2.

<Process flow>
Next, the flow of A / D conversion processing by the A / D converter 100 according to the third embodiment will be described.

  FIG. 22 is a flowchart illustrating an example of processing of the A / D converter according to the third embodiment.

  In step S2211, the AD conversion control unit 223 of the overall control unit 220 samples the input signal Vin1 into the capacitive element 14a (Ca) and the first capacitive array 1300-1 (Cb1). For example, the AD conversion control unit 223 uses the switch control unit 221 to set the switches SW2 to SW7, SW21, and SW22 of the A / D converter 100 as illustrated in FIG. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the first capacitor array 1300-1 as shown in FIG. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the second capacitor array 1300-2 as shown in FIG. In the following description, this state is referred to as an operation state (A).

  Thereby, the A / D converter 100 can sample the input signal Vin1 to the first capacitor array 1300-1 (Cb1) as a β conversion cyclic ADC. At this time, the A / D converter 100 can perform the successive approximation A / D conversion using the second capacitor array 1300-2 as the successive approximation ADC.

FIG. 23 is a diagram illustrating an example of processing timing of the A / D converter according to the third embodiment. As shown in FIG. 23, when the sampling of the input signal Vin1 is completed in the operation state (A) at time t1, the comparison result of the comparator 11 is updated, and bit _n-1 which is the most significant bit is output. In FIG. 23, since the A / D conversion of the upper bits has not been completed yet during the period from time t1 to t2, the A / D conversion (sequential comparison A / D conversion) of the lower bits is not executed.

  In step S2212, the AD conversion control unit 223 of the overall control unit 220 uses the first capacitor array 1300-1 (Cb1) to execute a signal amplification operation for amplifying a signal according to the comparison result of the comparator 11. . For example, the AD conversion control unit 223 uses the switch control unit 221 to set the switches SW2 to SW7, SW21, and SW22 of the A / D converter 100 as illustrated in FIG. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the first capacitor array 1300-1 as shown in FIG. Furthermore, the AD conversion control unit 223 maintains the state of the switch arrays SW_Vres and SW_Vin of the second capacitor array 1300-2 in the state illustrated in FIG. In the following description, this state is referred to as an operation state (B).

  As a result, the A / D converter 100 is a β-converted cyclic ADC, amplifies the signal according to the comparison result of the comparator 11, and stores the residual signal Vres in the first capacitor array 1300-1 (Cb1). . At this time, the A / D converter 100 can continuously execute the successive approximation A / D conversion using the second capacitor array 1300-2 as the successive approximation ADC.

  In step S2213, the AD conversion control unit 223 of the overall control unit 220 performs a cyclic sampling operation using the first capacitor array 1300-1 (Cb1). For example, the AD conversion control unit 223 uses the switch control unit 221 to set the switches SW2 to SW7, SW21, and 22 of the A / D converter 100 as illustrated in FIG. Further, the AD conversion control unit 223 maintains the switch arrays SW_Vres and SW_Vin of the first capacitor array 1300-1 in the state illustrated in FIG. Furthermore, the AD conversion control unit 223 maintains the state of the switch arrays SW_Vres and SW_Vin of the second capacitor array 1300-2 in the state illustrated in FIG. In the following description, this state is referred to as an operation state (C).

  As a result, the A / D converter 100 samples the residual signal Vres stored in the first capacitor array 1300-1 (Cb1) in step S2212 as the β-converted cyclic ADC in the input-side capacitive element 14a. . At this time, the A / D converter 100 can continuously execute the successive approximation A / D conversion using the second capacitor array 1300-2 as the successive approximation ADC.

As shown in FIG. 23, at the end of the first operation state (C), the comparison result of the comparator 11 is updated and bit _n-2 is output.

  In step S2214, the AD conversion control unit 223 of the overall control unit 220 has a predetermined number of bits (for example, 5 bits) by β conversion cyclic A / D conversion using the first capacitor array 1300-1 (Cb1). Judge whether it was obtained.

  When the predetermined number of bits is not obtained, the AD conversion control unit 223 repeatedly executes the processes of steps S2212 to S2214 until the predetermined number of bits is obtained. On the other hand, when the predetermined number of bits is obtained, the AD conversion control unit 223 shifts the processing to steps S2215 and S2221.

  Here, the A / D converter 100 executes the processes shown in steps S2215 and S2216 and the processes shown in steps S2221 to S2224 in parallel.

  In step S2215, the AD conversion control unit 223 of the overall control unit 220 uses the switch control unit 221 to switch the switches SW2 to SW7, SW21, and SW22 of the A / D converter 100, for example, as illustrated in FIG. Set to. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the first capacitor array 1300-1 as shown in FIG. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the second capacitor array 1300-2 as shown in FIG. In the following description, this state is referred to as an operation state (F).

  Thereby, the A / D converter 100 uses the first capacitor array 1300-1 (Cb1) as the successive approximation ADC, and the residual signal after the A / D conversion of the upper bits is performed in steps S2211 to S2214. Vres can be subjected to successive approximation A / D conversion.

  In step S2216, the digital synthesis unit 230 generates the output signal Dout by synthesizing the upper digital bits output in steps S2211 to S2214 and the lower digital bits output in step S2215.

  In addition, when the A / D converter 100 performs the successive approximation A / D conversion using the first capacitor array 1300-1 (Cb1) in step S2215, the processes of step S2221 to step S2224 are performed in parallel. And execute.

  For example, as shown in FIG. 23, when the A / D conversion of the upper bits using the first capacitor array 1300-1 (Cb1) is completed at time t2, the A / D converter 100 completes the first capacitor. The lower bit A / D conversion is started using the array 1300-1 (Cb1). In addition, the A / D converter 100, after the time t2, before the A / D conversion of the lower bits using the first capacitor array 1300-1 (Cb1) is completed, the second capacitor array 1300-2 Using (Cb2), sampling of the next input signal Vin2 can be started.

  In FIG. 22, when the process proceeds to step S2221, the AD conversion control unit 223 of the overall control unit 220 samples the input signal Vin2 into the capacitive element 14a (Ca) and the second capacitive array 1300-2 (Cb2). In the following description, this state is referred to as an operation state (A ′). In the operation state (A ′) and the operation state (F) described above, the switches SW2 to SW7, SW21 and SW22 of the A / D converter 100 and the switch arrays SW_Vres and SW_Vin of the first and second capacitor arrays The setting is the same.

  Thereby, the A / D converter 100 can sample the input signal Vin2 to the second capacitor array 1300-2 (Cb2) as a β conversion cyclic ADC. At this time, the A / D converter 100 can perform successive approximation A / D conversion using the first capacitor array 1300-1 as the successive approximation ADC.

  In step S <b> 2222, the AD conversion control unit 223 of the overall control unit 220 uses the second capacitance array 1300-2 (Cb <b> 2) to execute a signal amplification operation that amplifies the signal according to the comparison result of the comparator 11. . For example, the AD conversion control unit 223 uses the switch control unit 221 to set the switches SW2 to SW7, SW21, and SW22 of the A / D converter 100 as illustrated in FIG. Further, the AD conversion control unit 223 sets the state of the switch arrays SW_Vres and SW_Vin of the second capacitor array 1300-2 to the state shown in FIG. Furthermore, the AD conversion control unit 223 maintains the switch arrays SW_Vres and SW_Vin of the first capacitor array 1300-1 in the state illustrated in FIG. In the following description, this state is referred to as an operation state (B ′).

  In the operation state (B ′), the A / D converter 100 is a β conversion cyclic ADC, amplifies the signal according to the comparison result of the comparator 11, and converts the residual signal Vres into the second capacitor array 1300-2. Store in (Cb2). At this time, the A / D converter 100 can continuously execute the successive approximation A / D conversion using the first capacitor array 1300-1 as the successive approximation ADC.

  In step S2223, the AD conversion control unit 223 of the overall control unit 220 performs a cyclic sampling operation using the second capacitor array 1300-2 (Cb2). For example, the AD conversion control unit 223 uses the switch control unit 221 to set the switches SW2 to SW7, SW21, and 22 of the A / D converter 100 as shown in FIG. Further, the AD conversion control unit 223 maintains the state of the switch arrays SW_Vres and SW_Vin of the second capacitor array 1300-2 in the state illustrated in FIG. Furthermore, the AD conversion control unit 223 maintains the switch arrays SW_Vres and SW_Vin of the first capacitor array 1300-1 in the state illustrated in FIG. In the following description, this state is referred to as an operation state (C ′).

  In the operation state (C ′), the A / D converter 100 operates as the β conversion cyclic ADC by using the residual signal Vres stored in the second capacitor array 1300-2 (Cb2) in step S2222 as the input side capacitor. Sampling is performed on the element 14a. At this time, the A / D converter 100 can continuously execute the successive approximation A / D conversion using the first capacitor array 1300-1 as the successive approximation ADC.

  In step S2224, the AD conversion control unit 223 of the overall control unit 220 has a predetermined number of bits (for example, 5 bits) by β conversion cyclic A / D conversion using the second capacitor array 1300-2 (Cb2). Judge whether it was obtained.

  When the predetermined number of bits is not obtained, the AD conversion control unit 223 repeatedly executes the processes of steps S2222 to S2224 until the predetermined number of bits is obtained. On the other hand, when the predetermined number of bits is obtained, the AD conversion control unit 223 shifts the processing to steps S2225 and S2227.

  In step S2225, the AD conversion control unit 223 of the overall control unit 220 uses the switch control unit 221 to switch the switches SW2 to SW7, SW21, and SW22 of the A / D converter 100 again as shown in FIG. Set to. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the first capacitor array 1300-1 as shown in FIG. Further, the AD conversion control unit 223 sets the switch arrays SW_Vres and SW_Vin of the second capacitor array 1300-2 as shown in FIG. In the following description, this state is referred to as an operation state (F ′).

Thereby, the A / D converter 100 uses the second capacitor array 1300-2 (Cb2) as the successive approximation ADC, and the residual signal after the A / D conversion of the upper bits is performed in steps S2221 to S2224. Vres can be subjected to successive approximation A / D conversion. For example, the A / D converter 100 changes the output voltage Vx by sequentially switching the switch connected to + Vref and −Vref from the upper bit (D _N−1 ) side according to the output of the SAR 250, and bisects The successive approximation A / D conversion for specifying the A / D conversion value is performed.

  In step S2226, the digital synthesizing unit 230 generates the output signal Dout by synthesizing the upper digital bits output in steps S2221 to S2224 and the lower digital bits output in step S2225.

  In step S2227, the AD conversion control unit 223 of the overall control unit 220 determines, for example, whether to end the process. If the process is not ended, the process proceeds to step S2211. Alternatively, the AD conversion control unit 223 may shift the process to step S2211 without determining whether to end the process.

  With the above processing, the A / D converter 100 can perform an interleave operation as shown in FIG. 23, for example, by alternately using the two capacitance arrays 1300-1 and 1300-2.

  Thus, for example, while the successive comparison A / D conversion of the lower bits is performed using the first capacitor array 1300-1, the next input signal Vin is transmitted using the second capacitor array 1300-2. It becomes possible to execute β conversion cyclic A / D conversion of the upper bits.

  Further, in the A / D converter 100 according to the present embodiment, as in the second embodiment, the residual signal Vres after the β conversion cyclic A / D conversion of the upper bits is used as the successive approximation A / D. The process of sampling by D conversion can be omitted. Therefore, according to the third embodiment, in the A / D converter 100 in which the β conversion cyclic ADC and the successive approximation ADC are combined, the processing speed of the A / D conversion can be increased.

[Fourth Embodiment]
In the fourth and subsequent embodiments, a more preferable configuration example of the A / D converter 100 in which the β conversion cyclic ADC and the successive approximation ADC are combined will be described.

  FIG. 30 is a diagram illustrating an example of a circuit configuration of an A / D converter according to the fourth embodiment. In FIG. 30, the reference voltage generation circuit 210 includes reference voltages + Vref1 and −Vref1 for the first ADC 110 (β conversion cyclic ADC), reference voltages + Vref2 and −Vref2 for the second ADC 120 (successive conversion ADC), and Are generated separately. Other configurations of the A / D converter 100 illustrated in FIG. 30 are the same as those of the A / D converter 100 according to the first embodiment illustrated in FIG.

  When estimating the amplification factor β (1 <β <2) of the operational amplification unit 111 actually realized on the chip, the β value estimation control unit 222 of the overall control unit 220 is input to the first ADC 110. Input VCM and execute A / D conversion. VCM is a median value (for example, 0 V) of the full-scale voltage FS1 (+ Vref1 to −Vref1) of the first ADC 110.

  Therefore, the A / D converter 100 can switch the switch SW7 (input circuit) for inputting VCM (an example of a predetermined voltage) to the input node of the first ADC 110 so that the β value can be estimated. )have.

  Further, as shown in FIG. 31, when the A / D converter 100 includes a plurality of first ADCs 110-1, 110-2,..., The VCM is input to the input node of each first ADC 110. The input circuit is provided.

  Accordingly, the β value estimation control unit 222 of the overall control unit 220 can input the VCM to the input node of each first ADC 110 and can estimate the value of β.

  FIG. 32 is a diagram for explaining the reference voltage according to the fourth embodiment. FIG. 32A shows the input / output characteristics of the operational amplifier 111 of the first ADC 110 (β conversion cyclic ADC).

  In FIG. 32A, when the input voltage VIN (Input) is −Vref ≦ VIN <0, the operational amplifier 111 outputs the output voltage Vres = VIN × β + (β−1) Vref. When the input voltage VIN is 0 ≦ VIN ≦ + Vref, the operational amplifier 111 outputs the output voltage Vres = VIN × β + (1−β) Vref. Note that the value of β representing the input / output slope (amplification factor or gain) is 1 <β <2.

  FIG. 32B shows the input / output characteristics of the first ADC 110 (β conversion cyclic ADC) according to the fourth embodiment by the operational amplifier 111 and the input range (− of the second ADC 120 (sequential conversion ADC)). Vref2 to + Vref2).

  In FIG. 32B, when Vref1 = Vref2, if the interstage offset voltage Voff between the first ADC 110 and the second ADC 120 is generated, a problem occurs in the linearity of the A / D converter 100. For example, the output voltage of the first ADC 110 exceeds the input range of the second ADC 120, signal clipping occurs in the A / D conversion result, and a problem appears in linearity.

  Therefore, in the A / D converter according to the fourth embodiment, the values of Vref2 and Vref1 are set so that the relationship of Vref2 ≧ Vref1 + Voff is established. As the interstage offset voltage Voff, for example, a worst value of the interstage offset voltage obtained in advance by calculation or experiment can be applied.

  With the above configuration, in the A / D converter 100 in which the first ADC 110 and the second ADC 120 are combined, it is possible to reduce deterioration in A / D conversion accuracy due to the interstage offset voltage.

  At this time, the digital synthesizing unit 230 of the A / D converter 100 uses, for example, the following equation (1), and the A / D conversion result of the upper bits by the first ADC 110 and the second ADC 120: The A / D conversion result of the lower bits can be synthesized.

式（１）は、第１のＡＤＣ１１０により、上位５ビットのＡ／Ｄ変換を行い、第２のＡＤＣ１２０により下位Ｎビット（Ｎは２以上の整数）のＡ／Ｄ変換を行う場合の例を示している。

Formula (1) is an example in which the first ADC 110 performs upper 5 bits of A / D conversion, and the second ADC 120 performs lower N bits (N is an integer of 2 or more). Show.

In equation (1), β _a represents the value of β estimated by the β value estimation control unit 222. b _{1 to} b ₅ represent values of the first to fifth bits output from the first ADC 110. FS1 is a full-scale voltage of the first ADC 110, and is, for example, a voltage that is twice the reference voltage Vref1 of the first ADC 110. FS2 is a full-scale voltage of the second ADC 120, and is, for example, a voltage twice the reference voltage Vref2 of the second ADC 120. E _q represents quantization noise (quantization error).

  Further, the β value estimation control unit 222 of the A / D converter 100 inputs the median value (VCM) of FS1 (−Vref1 to + Vref1) to the input of the first ADC 110, and the A / D converter 100 performs A The value of β is estimated using the conversion result obtained by performing the / D conversion. For example, in FIG. 32B, when a median value of 0 V is input to the input of the first ADC 110, the A / D conversion result corresponding to P0 where the first bit starts from zero and P1 where the first bit starts from 1 are set to P1. A corresponding A / D conversion result is obtained. The β value estimation control unit 222 can estimate the value of β by paying attention to the fact that the two A / D conversion results obtained when the median value 0 V is input indicate equal voltages.

[Fifth Embodiment]
In the fourth embodiment, in the A / D converter 100 in which the first ADC 110 and the second ADC 120 are combined, the accuracy of A / D conversion due to the interstage offset voltage is reduced by increasing the value of Vref2. A method for reducing the above has been described. However, when the value of Vref2 increases, there is a problem that the quantization noise of the second ADC 120 increases and SNDR (Signal to Noise and Distortion Ratio) deteriorates.

  In the fifth embodiment, a digital-analog converter (hereinafter referred to as a D / A converter or DAC) is provided in the signal comparison node Vx of the second ADC 120 to actively cancel the offset voltage between stages. An example of the configuration to be performed will be described.

  FIG. 33 is a diagram illustrating an example of a circuit configuration of an A / D converter according to the fifth embodiment. 33, in addition to the configuration of the A / D converter 100 according to the first embodiment shown in FIG. 2, the A / D converter 100 includes a DAC (Digital to Analog Converter) 3301, a switch 3302, and a capacitive element 3303. Etc. Note that the switch 3302 and the capacitor 3303 are an example of a circuit for applying the output voltage of the DAC 3301 to the signal comparison node Vx of the second ADC 120. For example, the output terminal of the DAC 3301 may be directly connected to the input terminal (signal comparison node Vx) of the comparator 240.

  The DAC 3301 is set or adjusted in advance so as to output a voltage for canceling the interstage offset voltage between the first ADC 110 and the second ADC 120.

  With the above configuration, in the A / D converter 100 in which the first ADC 110 and the second ADC 120 are combined, it is possible to reduce deterioration in A / D conversion accuracy due to the interstage offset voltage. Further, in the present embodiment, since it is not necessary to increase the value of Vref2, it is possible to reduce the problem that the quantization noise of the second ADC 120 increases and SNDR deteriorates.

[Sixth Embodiment]
In the A / D converter 100 according to each of the above embodiments, in order for the β value estimation control unit 222 to estimate the value of β accurately, the second ADC 120 (sequential conversion) is used when estimating the value of β. It is desirable to increase the resolution of the ADC) by 1-2 bits. On the other hand, in the A / D converter 100, when performing normal A / D conversion, it is desirable not to increase the resolution of 1 to 2 bits in order to improve the conversion speed.

  In the sixth embodiment, an example of the A / D converter 100 that can improve the resolution of the second ADC 120 when estimating the value of β will be described.

  FIG. 34 is a diagram illustrating an example of a circuit configuration of the A / D converter according to the sixth embodiment. The A / D converter 100 shown in FIG. 34 includes a bit length control unit 3402 in addition to the configuration of the A / D converter 100 according to the first embodiment shown in FIG.

  For example, when the β value estimation control unit 222 estimates the value of β, the bit length control unit 3402 instructs the SAR 250 of the second ADC 120 to increase the number of bits for successive conversion A / D conversion (BIT_CNT). Is output.

  Further, when the SAR 250 of the second ADC 120 receives a signal instructing an increase in the number of bits of the successive conversion A / D conversion, the SAR 250 of the second ADC 120 has a predetermined number of bits (for example, 2 bits) larger than that in the normal A / D conversion, A / D conversion is executed.

  For example, in the second ADC 120, it is assumed that elements corresponding to redundant bits are provided in advance in the plurality of capacitive elements CN-1 to C0 and the switch arrays SW_SAR and SW_Vres. When normal A / D conversion is performed, the SAR 250 of the second ADC 120 performs successive approximation A / D conversion without using an element corresponding to a redundant bit. On the other hand, when estimating the value of β, the SAR 250 of the second ADC 120 performs successive approximation A / D conversion using elements corresponding to redundant bits.

  With the above configuration, in the A / D converter 100 in which the first ADC 110 and the second ADC 120 are combined, the estimation accuracy of the β value is improved without affecting the conversion speed of normal A / D conversion. To be able to.

  Note that the bit length control unit 3402 is not limited to the case where the β value estimation control unit 222 estimates the value of β, but when the accuracy of A / D conversion is improved, the bit number of the successive conversion A / D conversion is increased. May be used.

[Seventh Embodiment]
In the sixth embodiment, an example in which the bit length of the second ADC 120 (successive comparison ADC) is changed when the value of β is estimated has been described.

  In the fifth embodiment, the A / D conversion is performed by adding a dither signal such as a pseudo-random sequence to the signal comparison node Vx of the second ADC 120 and averaging a plurality of A / D conversion results. An example in the case where the substantial resolution (effective resolution) is improved will be described.

  FIG. 35 is a diagram illustrating an example of a circuit configuration of an A / D converter according to the seventh embodiment. 35, in addition to the configuration of the A / D converter 100 according to the first embodiment shown in FIG. 2, the A / D converter 100 includes a dither signal generator 3501, a signal controller 3502, and an average processor 3503. Have

  The dither signal generator 3501 generates a dither signal such as a pseudo-random sequence under the control of the signal controller 3502, and inputs the generated dither signal to the signal comparison node Vx of the second ADC 120 (successive comparison ADC). .

  For example, when the β value estimation control unit 222 estimates the value of β, the signal control unit 3502 instructs the dither signal generation unit 3501 to generate a dither signal.

  The average processing unit 3503 averages the residual signal Vres after the first ADC 110 performs the A / D conversion of the upper bits, and the result of the second ADC 120 performing the A / D conversion a plurality of times. . When the second ADC 120 samples the residual signal Vres once, the second ADC 120 continues to hold the residual signal Vres according to the charge conservation law, and thus can execute A / D conversion multiple times. The average resolution of A / D conversion can be improved by averaging a plurality of A / D conversion results.

  Here, the effect of the dither signal will be described.

  FIG. 36 is a diagram showing an image of A / D conversion when the circuit has low noise. For example, in FIG. 36, it is assumed that the value of the input voltage Vin is 10.25 and the value of n is 10. In the example of FIG. 36, since the circuit noise is small, the value of Vin is a code transition noise range 3601 in which the A / D conversion result changes between 9 and 10, and the A / D conversion result is between 10 and 11. A state that is not included in the code transition noise range 3602 that changes in FIG. In this case, no matter how many times A / D conversion is performed on Vin, the A / D conversion result is 10, indicating that the effect of improving the substantial resolution of A / D conversion cannot be obtained. .

  FIG. 37 is a diagram showing an image of A / D conversion when the circuit has high noise. In the example of FIG. 37, there is a lot of circuit noise, and the value of Vin is between the code transition noise range 3701 in which the A / D conversion result changes between 9 and 10, and the A / D conversion result is between 10 and 11. The state included in the changing code transition noise range 3702 is shown. In this case, since the conversion result of Vin changes between 9, 10, or 11, the A / D conversion result approaches 10.25 by performing A / D conversion multiple times and averaging. Can be expected.

  FIG. 38 is a diagram showing an image of A / D conversion when the circuit applies low-noise and a dither signal. In FIG. 36, it is assumed that the dither signal generator 3501 generates a uniform noise of ± 0.5 LSB, for example.

  In this case, since Vin changes from 9.75 to 10.75, the A / D conversion result is 10 or 11, and 11 appears at a ratio of 3: 1. Therefore, by executing A / D conversion a plurality of times and averaging, the A / D conversion result approaches 10.25, that is, the effect of averaging can be obtained.

  With the above configuration, in the A / D converter 100 in which the first ADC 110 and the second ADC 120 are combined, the value of β is estimated without increasing the bit length of the second ADC 120 (successive comparison ADC). The accuracy can be improved.

11 Comparator 13 Operational Amplifier 100 A / D Converter 110 β Conversion Cyclic ADC (β Conversion Cyclic A / D Conversion Circuit)
111 operational amplifier 120 successive approximation ADC (successive comparison type A / D conversion circuit)
222 β value estimation control unit 1300 Capacitance array 1300-1 First capacitor array 1300-2 Second capacitor array 3301 DAC (D / A conversion circuit)
3402 Bit length controller 3501 Dither signal generator (signal generator)
3503 Average processing unit C _{0 to} C _N−1 , C _{d A} plurality of capacitive elements Cb integral capacitance SW 3 switch (switching unit)
SW7 switch (input circuit)

Claims (10)

An A / D converter combining a plurality of A / D conversion methods,
A non-binary β conversion cyclic A / D conversion circuit and a binary or less successive approximation A / D conversion circuit are included.
Applying the β conversion cyclic A / D conversion circuit to an A / D conversion circuit in charge of A / D conversion of a predetermined bit range;
Applying the successive approximation A / D conversion circuit to an A / D conversion circuit in charge of A / D conversion of a bit range lower than the predetermined bit range;
A / D conversion result of the predetermined bit range by the β conversion cyclic A / D conversion circuit;
An A / D conversion result of the lower bit range obtained by A / D converting the residual signal after A / D conversion of the predetermined bit range by the successive approximation A / D conversion circuit;
A / D converter characterized in that an A / D conversion result output from the A / D converter is obtained by synthesizing with a digital synthesis unit. The successive approximation A / D converter circuit performs A / D conversion of the lower bit range using a capacitor array including a plurality of capacitors.
The A / D conversion according to claim 1, wherein the β conversion cyclic A / D conversion circuit performs A / D conversion of the predetermined bit range using the capacitor array as an integration capacitor. converter. Having a plurality of said capacitance arrays;
After the β conversion cyclic A / D conversion circuit performs A / D conversion of the predetermined bit range using the first capacitor array, the successive approximation A / D conversion circuit performs the lower order bit conversion. Perform A / D conversion of the range,
Before the A / D conversion of the lower-order bit range using the first capacitor array is completed, the β-converting cyclic A using the second capacitor array different from the first capacitor array is used. 3. The A / D converter according to claim 2, wherein an / D conversion circuit performs an interleaving operation for starting A / D conversion of the predetermined bit range.   The one or more β conversion cyclic A / D conversion circuits included in the A / D converter have inputs that input a predetermined voltage to an input node of the β conversion cyclic A / D conversion circuit. The A / D converter according to any one of claims 1 to 3, further comprising a circuit. A reference voltage Vref1 used in the β conversion cyclic A / D conversion circuit;
A reference voltage Vref2 used in the successive approximation A / D converter circuit;
An offset voltage Voff between the β conversion cyclic A / D conversion circuit and the successive approximation A / D conversion circuit;
5. The A / D converter according to claim 1, wherein Vref <b> 1 and Vref <b> 2 are set such that a relationship of Vref <b> 2 ≧ Vref <b> 1 + Voff is established between the two. A D / A converter circuit connected to a signal comparison node of the successive approximation A / D converter circuit;
6. The A / D converter according to claim 1, wherein an offset voltage of the successive approximation type A / D converter circuit is canceled using an output signal of the D / A converter circuit. .   The A / D converter according to claim 1, further comprising: a signal generation unit that inputs a dither signal to a signal comparison node of the successive approximation A / D converter circuit.   The average processing unit that averages a plurality of A / D conversion results by the successive approximation A / D converter circuit and improves the effective resolution of the successive approximation A / D converter circuit. The A / D converter according to one item.   The A / D converter according to claim 1, further comprising a bit length control unit that changes a bit length of A / D conversion executed by the successive approximation A / D conversion circuit. The β conversion cyclic A / D conversion circuit is:
A comparator that compares a comparison voltage to be compared with a threshold value and outputs a digital value indicating a comparison result;
an operational amplification unit that has an amplification factor of β (1 <β <2), performs a predetermined calculation according to the comparison result of the comparator, and generates the residual signal;
When sampling the input signal, the input signal is output as the comparison voltage, and after the sampling is completed, the switching unit that outputs the residual signal as the comparison voltage;
A β value estimation control unit that estimates the value of β using a result of A / D conversion of a predetermined input voltage by the A / D converter;
Have
The digital synthesis unit
The β-adic A / D conversion result of the predetermined bit range by the β-converting cyclic A / D conversion circuit is binarized using the β value estimation result estimated by the β-value estimation control unit. 2. The result of conversion and the A / D conversion result of the lower bit range by the successive approximation A / D conversion circuit are combined to output a binary A / D conversion result. The A / D converter as described in any one of thru | or 9.

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