JP6810319B2 - Charge storage device - Google Patents

Description

The present invention relates to a charge storage element, and particularly relates to a charge storage element suitable for application to a photoelectric conversion element or a solid-state image pickup device.

The present inventors have already proposed a 4-tap lateral electric field control type charge modulation device capable of acquiring continuous time-resolved components with low noise in four short-time time windows (see Patent Document 1). According to the technique of Patent Document 1, one time window is set to sub-nanoseconds, and at the same time, 3 to 4 time windows are measured with a single shot, and then the 3 to 4 time windows are delayed as a whole for the first time. It is possible to measure the measurement time range immediately after the time window and connect these several times to realize the sub-nanosecond time resolution and several nanosecond measurement time range required for fluorescence lifetime measurement.

However, the charge modulation element (charge storage element) of Patent Document 1 has a one-stage charge transfer, and both the gate electrode for the drain and the gate electrode for the transfer gate have only an ON / OFF function. Further, in the measurement of the fluorescence lifetime of intracellular molecules, the intensity of the excitation light cannot be increased indefinitely in order to suppress damage to the cells due to the excitation light, and the fluorescence is generally weaker than that of the excitation light. Is required to have low noise in addition to high speed and high sensitivity. As a technique for meeting such a demand for low noise, a charge storage element in which a charge storage region is provided via a transfer electrode in the charge reading region has been proposed (see Patent Document 2).

By using two-stage transfer as in Patent Document 2, the difference between the potential when the charge storage region is reset and the charge storage potential is read out by correlated double sampling, so that low noise with the reset noise canceled is read out. Can be done. Therefore, by combining Patent Documents 1 and 2, reading is possible with low noise in addition to high speed and high sensitivity, and a sensor more suitable for fluorescence lifetime measurement can be provided. However, as it is, the accumulated charge capacity in the charge storage region is increased. There is a problem that it is not enough.

International Publication No. 2015/118884 Pamphlet International Publication No. 2014/021417 Pamphlet

In view of the above problems, it is an object of the present invention to provide a charge storage device having a charge transfer structure capable of increasing the stored charge capacity in the charge transfer channel.

In order to achieve the above object, the first aspect of the present invention is provided in (a) a first conductive type element arrangement layer and (b) a part of the upper part of the element arrangement layer to form a charge supply region. The second conductive type surface embedding region and (c) the input side are connected to the surface embedding region, and the second conductive type charge storage region and (d) charge accumulation have a higher impurity density than the surface embedding region. The second conductive type target region, which is connected to the output side of the region and has a higher impurity density than the charge storage region, and (e) face each other in pairs on both sides of the charge transfer channel defined on the input side of the charge storage region. Adjacent to the input control electrode, which is arranged and controls the depletion potential of the charge transfer channel by the lateral electrostatic induction effect to introduce the signal charge from the surface-embedded region into the charge storage region, and (f) the input control electrode. , Charge storage with capacitance expansion electrodes located on the output side of the charge transfer channel, paired on both sides of the charge storage region, and controlling the depletion potential of the charge storage region with a lateral electrostatic induction effect. The gist is that it is an element. In the charge storage device according to the first aspect of the present invention, the amount of signal charge stored in the charge storage region is expanded by the voltage applied to the capacitance expansion electrode.

A second aspect of the present invention is to (a) a first conductive type element arrangement layer and (b) a second conductive type surface embedding provided in a part of the upper part of the element arrangement layer and forming a charge supply region. The input side is connected to the region and (c) the surface-embedded region, and the second conductive type charge storage region with a higher impurity density than the surface-embedded region and (d) the output side of the charge storage region are connected. It is divided into a second conductive type target region with a higher impurity density than the charge storage region, and (e) a region composed of a first conductive type polycrystalline silicon film and a region composed of a second conductive type polycrystalline silicon film. The gist is that the charge storage element is symmetrically arranged on both sides of the charge storage region and includes an input control electrode that controls the depletion potential of the charge storage region by a lateral electrostatic induction effect. In the charge storage element according to the second aspect of the present invention, regions made of a first conductive type polycrystalline silicon film are arranged in pairs on both sides of a charge transfer channel defined on the input side of the charge storage region. , The depletion potential of the charge transfer channel is controlled by the lateral electrostatic induction effect, and functions as an input control electrode that introduces signal charge from the surface-embedded region into the charge storage region. Further, a region made of a second conductive type polycrystalline silicon film is arranged at a position close to the charge storage region on the output side of the charge storage region, and the depletion potential of the charge storage region is controlled by the lateral electrostatic induction effect. By doing so, the amount of signal charge accumulated in the charge storage region is increased.

According to the present invention, it is possible to provide a charge storage device having a charge transfer structure capable of increasing the stored charge capacity in the charge transfer channel.

It is a schematic plan view (top view) explaining the outline of the photoelectric conversion element using the charge storage element which concerns on embodiment. It is a schematic cross-sectional view explaining the schematic structure of the photoelectric conversion element using the charge storage element which concerns on embodiment seen from the AA direction of FIG. It is a schematic plan view (top view) which shows the charge storage element which concerns on embodiment. The figure which shows the potential distribution with respect to the electron of the lower end (bottom part) of the conduction band of the charge storage element which concerns on embodiment in the cross section seen from the Y1-Y1 direction of FIG. 3, the cross section seen in the Y2-Y2 direction and the Y3-Y3 direction. Is. It is a figure which shows the potential distribution with respect to the electron of the lower end (bottom part) of the conduction band of the charge storage element which concerns on embodiment in the state of FIG. It is a figure which shows the potential distribution with respect to the electron of the lower end (bottom part) of the conduction band of the charge storage element which concerns on embodiment in the cross section seen from each of the Y1-Y1 direction, the Y2-Y2 direction and the Y3-Y3 direction of FIG. is there. It is a figure which shows the potential distribution with respect to the electron of the lower end (bottom part) of the conduction band of the charge storage element which concerns on embodiment in the state of FIG. It is a figure which shows the potential distribution with respect to the electron of the lower end (bottom part) of the conduction band of the charge storage element which concerns on embodiment in the cross section seen from each of the Y1-Y1 direction, the Y2-Y2 direction and the Y3-Y3 direction of FIG. is there. It is a figure which shows the potential distribution with respect to the electron of the lower end (bottom part) of the conduction band of the charge storage element which concerns on embodiment in the state of FIG. 8 by a three-dimensional mesh structure. It is a figure which shows the potential distribution with respect to the electron of the lower end (bottom part) of the conduction band of the charge storage element which concerns on embodiment in the cross section seen from each of the Y1-Y1 direction, the Y2-Y2 direction and the Y3-Y3 direction of FIG. is there. It is a figure which shows the potential distribution with respect to the electron of the lower end (bottom part) of the conduction band of the charge storage element which concerns on embodiment in the state of FIG. 10 by a three-dimensional mesh structure. It is a schematic plan view (top view) explaining the operation of the photoelectric conversion element using the charge storage element which concerns on embodiment. It is a figure which shows the potential distribution with respect to the electron of the lower end part (bottom part) of the conduction band of the charge storage element which concerns on the 1st modification of embodiment with a 3D mesh structure. The potential distribution of the lower end (bottom) of the conduction band of the charge accumulating element according to the embodiment viewed from the X1-X1 direction of FIG. 3 with respect to electrons will be described separately for the case where the capacitance expansion electrode is provided and the case where it is not provided. is there. The potential distribution for electrons at the lower end (bottom) of the conduction band of the charge accumulating element according to the embodiment viewed from the X1-X1 direction of FIG. 3 is described separately according to the level of the control voltage applied to the output control electrode. is there. It is a schematic plan view (top view) of the charge storage element which concerns on 1st modification of embodiment. The potential distribution for electrons at the lower end (bottom) of the conduction band of the charge storage device according to the first modification of the embodiment viewed from the X2-X2 direction of FIG. 15 is determined by the magnitude of the control voltage applied to the capacitance expansion electrode. It is a figure which explains separately. The potential distribution for electrons at the lower end (bottom) of the conduction band of the charge storage device according to the first modification of the embodiment viewed from the Y4-Y4 direction in FIG. 15 is determined by the magnitude of the control voltage applied to the capacitance expansion electrode. It is a figure which explains separately. It is a schematic plan view (top view) of the charge storage element which concerns on 2nd modification. The potential distribution for electrons at the lower end (bottom) of the conduction band of the charge storage element according to the second modification in the cross section seen from the X3-X3 direction of FIG. 19 is determined by the magnitude of the control voltage applied to the output control electrode. It is a figure which explains separately. The potential distribution for electrons at the lower end (bottom) of the conduction band of the charge storage device according to the second modification in the cross section seen from the Y5-Y5 direction in FIG. 19 is determined by the magnitude of the control voltage applied to the output control electrode. It is a figure which explains separately. It is a figure explaining the potential distribution with respect to the electron of the lower end (bottom part) of the conduction band of the charge storage element which concerns on a comparative example, divided by the magnitude of the control voltage applied to an output control electrode. It is a schematic plan view (top view) which shows the charge transfer structure of the charge storage element which concerns on a comparative example. It is a schematic plan view (top view) which shows the charge transfer structure of the charge storage element which concerns on 3rd modification. It is a schematic plan view (top view) which shows the charge transfer structure of the charge storage element which concerns on 4th modification of embodiment. 26 (a) is a schematic cross-sectional view for explaining the schematic structure of the charge storage element according to the fourth modification of the embodiment in the cross section seen from the Y6-Y6 direction of FIG. 25, and FIG. 26 (b). ) Is a diagram showing the potential distribution for electrons at the lower end (bottom) of the conduction band in the region shown in FIG. 26 (a). It is a figure which shows the potential distribution with respect to the electron of the lower end (bottom part) of the conduction band in the cross section seen at the level of the ZZ direction of FIG. 26A.

Next, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other.

Further, the embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention describes the material, shape, structure, and arrangement of constituent parts. Etc. are not specified as the following. The technical idea of the present invention may be modified in various ways within the technical scope specified by the claims stated in the claims. Further, the directions of "left and right" and "up and down" in the following description are merely definitions for convenience of explanation, and do not limit the technical idea of the present invention. Therefore, for example, if the paper surface is rotated 90 degrees, "left and right" and "up and down" are read interchangeably, and if the paper surface is rotated 180 degrees, "left" becomes "right" and "right" becomes "left". Of course it will be.

Further, in the drawings, it is obvious to those skilled in the art that the region or layer labeled n or p means a member or component made of a semiconductor such as a semiconductor region or a semiconductor layer. Further, the + superscript attached to n or p in the drawing means that the impurity density is relatively high in the semiconductor region as compared with the semiconductor region not marked with +, and n or p. The-superscript attached to the upper right of is a semiconductor region having a relatively low impurity density as compared with the semiconductor region not marked with-. Further, even if the same notation such as n ⁺ and n ⁺ is used, it does not necessarily indicate that the impurity densities are the same.

(Structure of charge storage element)
As shown in the plan view of FIG. 3 and the cross-sectional view of FIG. 2, the charge storage element according to the embodiment of the present invention includes the first conductive type (p type) element arrangement layer 2 and the upper part of the element arrangement layer 2. A second conductive type (n-type) surface-embedded region 3 provided in a part of the surface and forming a charge supply region, and an input side connected to the surface-embedded region 3 to have higher impurities than the surface-embedded region 3. It is connected to the output side of the n-type charge storage region SD7 and the charge storage region SD7 in terms of density, and is defined on the input side of the n-type target region FD7 and the charge storage region SD7 with a higher impurity density than the charge storage region SD7. The charge transfer channels R7 are arranged in pairs on both sides, and the depletion potential of the charge transfer channel R7 is controlled by the lateral electrostatic induction effect, and the signal charge is transferred from the surface embedded region 3 to the charge storage region SD7. The input control electrodes G6 and G7 to be introduced are adjacent to the input control electrodes G6 and G7, are located on the output side of the charge transfer channel R7, are arranged in pairs on both sides of the charge storage area SD7, and are arranged to face each other. The capacitance expansion electrodes CA71 and CA72 that control the depletion potential of SD7 by the lateral electrostatic induction effect are provided. The charge storage element according to the embodiment of the present invention expands the amount of signal charge stored in the charge storage region SD7 by the voltage applied to the capacitance expansion electrodes CA71 and CA72. The charge storage element according to the embodiment of the present invention is provided on the output side of the charge storage region SD7, and further includes output control electrodes TX71 and TX72 that transfer the signal charge stored in the charge storage region SD7 to the target region FD7.

(Structure of application example of charge storage device)
As shown in the plan view of FIG. 1 and the cross-sectional view of FIG. 2, the photoelectric conversion element using the charge storage element according to the embodiment is provided on a part of the p-type element arrangement layer 2 and the upper part of the element arrangement layer 2. It is provided in contact with the surface of the n-type surface embedding region 3, the p-type high impurity density potential hill forming portion 7 provided in the center of the surface embedding region 3, and the surface embedding region 3. In addition, a signal processing region (2,3,5,7) including a p-type pinning layer 5, an insulating film 9 provided on the signal processing region (2,3,5,7), and a signal processing region (2,3,5,7) The n-type first charge storage region SD1 and second charge having a higher impurity density than the element arrangement layer 2 provided so as to surround the charge supply region PD defined in the central portion of 2, 3, 5, 7). It includes a storage area SD2, a third charge storage area SD3, ..., And an eighth charge storage area SD8. The first charge storage region SD1, the second charge storage region SD2, the third charge storage region SD3, ..., And the eighth charge storage region SD8 are symmetrical with respect to the center position of the charge supply region PD so as to surround the charge supply region PD, respectively. They are arranged apart from each other at each of the eight positions.

In the photoelectric conversion element using the charge storage element according to the embodiment, at a position surrounding the charge supply region PD, the first charge storage region SD1, the second charge storage region SD2, and the third charge are located from the center position of the charge supply region PD. First input control electrode G1, second input control electrode G2, third input control electrode G3, on both sides of each of the eight charge transfer channels leading to each of the storage regions SD3, ..., 8th charge storage region SD8. ..., The eighth input control electrodes G8 are arranged in pairs on the insulating film 9.

The eight charge transfer channels are two adjacent input controls of the eight first input control electrodes G1, the second input control electrode G2, the third input control electrode G3, ..., And the eighth input control electrode G8. It is formed by being sandwiched between electrodes. For example, the first charge transfer channel R1 located at the uppermost part in FIG. 1 is a region sandwiched between the eighth input control electrode G8 and the first input control electrode G1. The second charge transfer channel R2 appearing on the left side of the first charge transfer channel R1 in FIG. 1 is a region sandwiched between the first input control electrode G1 and the second input control electrode G2. In FIG. 2, a third charge transfer channel R3 and a seventh charge transfer channel R7 appearing horizontally on the same straight line in the left-right direction in FIG. 1 are exemplified.

The photoelectric conversion element using the charge storage element according to the embodiment is used with respect to the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., And the eighth input control electrode G8, respectively. By periodically applying electric field control pulses having different phases and sequentially changing the depletion potential of the surface-embedded region 3, a potential gradient in which charges are transported is sequentially formed in one of the charge transfer channels. The destinations of the multiple carriers generated in the surface embedded region 3 are sequentially moved to one of the first charge storage region SD1, the second charge storage region SD2, the third charge storage region SD3, ..., And the eighth charge storage region SD8. Control to set. That is, the photoelectric conversion element using the charge storage element according to the embodiment is the first input control electrode G1 and the second, which are eight gates that control the electric field in the lateral direction by the electrostatic induction effect in the direction across the charge transfer channel. The input control electrodes G2, the third input control electrodes G3, ..., and the eighth input control electrode G8 cause the photoelectrons generated in the almost regular octagonal charge supply region PD in the plane pattern to be centered on the charge supply region PD. Charge modulation is performed by moving at high speed by lateral electric field control along eight charge transfer channels radiating outward from the charge.

As can be seen from the plan view of FIG. 1, the arrangement topology of the first charge storage region SD1, the second charge storage region SD2, the third charge storage region SD3, ..., The eighth charge storage region SD8 is that of the charge supply region PD. It is rotationally symmetric 8 times with respect to the center position. Each of the first charge storage region SD1, the second charge storage region SD2, the third charge storage region SD3, ..., And the eighth charge storage region SD8 shown in FIG. 1 is a large number of carriers generated in the surface embedded region 3. Functions as a target area for accumulating and reading out as a signal charge.

At the outer ends of the first charge storage region SD1, the second charge storage region SD2, the third charge storage region SD3, ..., and the eighth charge storage region SD8, an n-type primary purpose having a high impurity density is used. Regions FD1, second destination region FD2, third destination region FD3, ..., Eighth destination region FD8 are provided. Inside the insulating films 9 on both sides of the first charge storage region SD1, the second charge storage region SD2, the third charge storage region SD3, ..., and the eighth charge storage region SD8, the first charge storage region SD1, 2nd charge storage region SD2, 3rd charge storage region SD3, ..., Capacity expansion electrodes CA11, CA21, CA31, ..., to which a lateral electric field that promotes charge accumulation in the 8th charge storage region SD8 is applied. CA81; CA12, CA22, CA32, ..., CA82 are provided. On the outside of the capacitance expansion electrodes CA11, CA21, CA31, ..., CA81; CA12, CA22, CA32, ..., CA82, the first target area FD1, the second target area FD2, the third target area FD3, ..., Output control electrodes TX11, TX21, TX31, ..., TX81; TX12, TX22, TX32, ..., TX82 are provided, to which a lateral electric field is applied to promote the transfer of electric charges to the eighth target region FD8.

As shown in FIGS. 1 and 2, a shielding plate 11 is further provided above the insulating film 9. A planar pattern of the charge supply region PD is defined in the central portion of the signal processing region (2, 3, 5, 7) through the opening of the shielding plate 11, and light is selectively emitted to the charge supply region PD. Be irradiated. In the plan view of FIG. 1, a charge supply region PD as an opening of the shielding plate 11 is defined in the central portion of the signal processing region (2, 3, 5, 7), but in the charge supply region PD. The third charge transfer channel R3 and the seventh charge transfer channel R7 are set in the horizontal direction (X direction). The first charge transfer channel R1 and the fifth charge transfer channel R5 are set in the vertical direction (Y direction) orthogonal to the charge transfer channel in the horizontal direction.

The fourth charge transfer channel R4 and the eighth charge transfer channel R8 are set at positions on the straight line of y = x when the X and Y directions are in the Cartesian coordinate system, and the fourth charge transfer channel R8 is set on the straight line of y = −x. A second charge transfer channel R2 and a sixth charge transfer channel R6 are set at the positions. Therefore, in the plan view of FIG. 1, eight charge transfer channels are defined from the charge supply region PD so that the adjacent charge transfer channels and the central axes form an angle of 45 ° and extend radially outward. Then, at the four ends of the first charge transfer channel R1 to the eighth charge transfer channel R8, the first charge storage region SD1, the second charge storage region SD2, the third charge storage region SD3, ..., The eighth charge, respectively. The storage area SD8 is connected.

In the description at the beginning of the embodiment of the present invention, a pair of capacitance expanding electrodes CA11, CA21, CA31, ..., CA81; CA12, CA22, CA32, ..., CA82 are provided on both sides of the seventh charge storage region SD7. Focusing on the magnifying electrode pairs (CA71, CA72), the structure around the 7th charge storage region SD7 was explained. That is, the charge storage element according to the embodiment includes a pair of magnifying electrode pairs (CA71, CA72), and each of the capacitance expanding electrodes CA71 and CA72 constituting the pair of magnifying electrodes (CA71, CA72) is shown in FIG. As shown in, the plane pattern is almost rectangular. Each of the capacitance expansion electrodes CA71 and CA72 extends in parallel with the rectangular seventh charge storage region SD7 and extends toward the seventh target region FD7 with a slight gap from the seventh charge storage region SD7. Further, the capacitance expansion electrodes CA71 and CA72 are arranged with a slight gap between the sixth input control electrode G6 and the seventh input control electrode G7. That is, the pair of magnifying electrodes (CA71, CA72) are arranged side by side in the direction orthogonal to the moving direction of the electric charge.

The seventh charge storage region SD7 constituting the charge storage element according to the embodiment extends from the seventh charge transfer channel R7 to the continuous first rectangular region and the first rectangular region to the seventh target region FD7. , A stepped polygon having a second rectangular region narrower than the first rectangular region. The length of the long side of the capacitance expansion electrodes CA71 and CA72 is substantially the same as the length of the long side of the first rectangular region of the seventh charge storage region SD7.

A pair of output electrode pairs (TX71, TX72) are provided on both sides of the second rectangular region of the seventh charge storage region SD7 so as to be separated from the seventh charge storage region SD7 and the capacitance expansion electrodes CA71 and CA72. Has been done. The capacitance expansion electrodes CA71 and CA72 and the output control electrodes TX71 and TX72 are provided on the upper portion of the insulating film 9. The pair of magnifying electrode pairs (CA71, CA72) is applied along the charge transfer path (accumulation transfer path) sandwiched between the pair of magnifying electrode pairs (CA71, CA72) by applying a set control voltage. Increases the stored charge capacity in the defined seventh charge storage region SD7.

As shown in FIGS. 4 and 5, a pair of input control electrodes (G6, G7) is in an on state, a pair of magnifying electrode pairs (CA71, CA72) are in an on state, and a pair of output electrode pairs (TX71, TX72) are in an on state. In the off state, the potential for electrons at the position in the cross section seen from the Y2-Y2 direction in the center of the horizontal direction in FIG. 3 along the charge movement path is the deepest as a whole. Next, the position in the cross section seen from the Y1-Y1 direction in FIG. 3, which is closer to the pair of input control electrodes (G6, G7) in the charge transfer path, is deep, and the pair of output electrode pairs (TX71, TX72) in the charge transfer path. ) The potential at the position in the cross section seen from the Y3-Y3 direction of FIG.

Further, as shown in FIGS. 6 and 7, a pair of input control electrodes (G6, G7) are in an off state, a pair of magnifying electrode pairs (CA71, CA72) are in an on state, and a pair of output electrode pairs (TX71, TX72). When is off, the potential for electrons at the position in the cross section seen from the Y2-Y2 direction in the center of FIG. 3 is the deepest as a whole. The potential at the position in the cross section seen from the Y3-Y3 direction in FIG. 3 is the second deepest at the center position in the Y direction, but at the positions at both ends in the Y direction, in the cross section seen from the Y1-Y1 direction in FIG. It becomes shallower than the potential at the position.

Further, as shown in FIGS. 8 and 9, a pair of input control electrodes (G6, G7) are in an off state, a pair of magnifying electrode pairs (CA71, CA72) are in an on state, and a pair of output electrode pairs (TX71, TX72). When is on, the potential for electrons at the position in the cross section seen from the Y1-Y1 direction in FIG. 3 is the shallowest as a whole. The potential at the position in the cross section seen from the Y3-Y3 direction in FIG. 3 is the deepest at the center position in the Y direction, but at the positions at both ends in the Y direction, the potential at the position in the cross section seen from the Y2-Y2 direction in FIG. It becomes shallower than the potential of.

Further, as shown in FIGS. 10 and 11, a pair of input control electrodes (G6, G7) are in an off state, a pair of magnifying electrode pairs (CA71, CA72) are in an off state, and a pair of output electrode pairs (TX71, TX72). When is on, at the center position in the Y direction in FIG. 3, the potential for electrons at the position in the cross section seen from the Y3-Y3 direction is the deepest overall, and then from the Y2-Y2 direction in FIG. The potential at the position in the viewed cross section is deeper, and finally the potential at the position in the cross section seen from the Y1-Y1 direction in FIG. 3 is deeper. On the other hand, the positions at both ends in the Y direction in FIG. 3 are the deepest, but the positions in the cross section seen from the Y1-Y1 direction in FIG. 3, the positions in the cross section seen from the Y2-Y2 direction in FIG. 3, and Y3-Y3 in FIG. The potential for electrons increases in the order of position in the cross section viewed from the direction.

The shape of the capacitance expansion electrode is not limited to the rectangle shown in FIG. 3, and is elliptical as long as it has a region extending along the seventh charge storage region SD7 and the stored charge capacity in the sandwiched region is increased. It may be another shape such as a shape or a polygon. The structures of the other capacitance expansion electrodes are also equivalent to those of the capacitance expansion electrodes CA71 and CA72.

(Operation of charge storage element)
The first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., The eighth input control electrode G8 are inputs located symmetrically with respect to the axis of symmetry passing through the central axis of the desired charge transfer channel. The control electrodes form a pair of control electrodes, and a gate signal of the same magnitude is applied to the pair of control electrodes. As shown in FIG. 12, focusing on the seventh charge transfer channel R7, the operation of the charge storage element according to the embodiment by moving the charge to the seventh charge storage region SD7 and the seventh target region FD7 will be described. In the photoelectric conversion element using the charge storage element according to the embodiment, the first control electrode pair (G2, G3) and the second control electrode are along the BB line forming the central axis of the seventh charge transfer channel R7. Pairs (G1, G4), third control electrode pairs (G8, G5) and fourth control electrode pairs (G7, G6) are formed, respectively. The maximum width of the regular octagon of the charge supply region PD that supplies the signal charge to the charge storage element according to the embodiment is about 4.5 μm.

A gate signal of the first potential level L (-1V) is applied to the first control electrode pair (G2, G3). A gate signal of a second potential level M (0.5 V) higher than the first potential level L is applied to the second control electrode pair (G1, G4). A gate signal of a third potential level H (1.0 V) higher than the second potential level M is applied to the third control electrode pair (G8, G5). A gate signal of a fourth potential level V (2.3 V) higher than the third potential level H is applied to the fourth control electrode pair (G7, G6).

That is, it is the end point side of charge transfer from the first control electrode pair (G2, G3) on both sides of the axis of symmetry passing through the central axis of the seventh charge transfer channel R7 constituting the charge storage element according to the embodiment. Four control electrode pairs consisting of eight input control electrodes are configured so that the applied potential increases in sequence toward the fourth control electrode pair (G7, G6), and the four control electrode pairs of the four control electrode pairs. The voltage applied to each is controlled.

When the seventh charge transfer channel R7 constituting the charge storage element according to the embodiment is used, the first control electrode pair (G2, G3), the second control electrode pair (G1, G4), and the third control electrode pair (G8) are used. , G5) and the fourth control electrode pair (G7, G6), different electric field control voltages are applied by the first control pulse, the second control pulse, the third control pulse, ..., The eighth control pulse, respectively. , Change the depletion potential of each charge transfer channel. As a result, different potential gradients are formed depending on the position of interest in the charge storage element according to the embodiment as shown in FIGS. 5 and 6, and the moving directions of the signal charges supplied from the charge supply region PD are sequentially changed. Be controlled.

The signal charge travels around the potential hill forming portion 7, and finally via the seventh charge transfer channel R7 between the fourth control electrode pair (G7, G6), the charge accumulation according to the embodiment. It moves to the seventh charge storage region SD7 constituting the element. At this time, the potential of the third charge transfer channel R3 for electrons is shallow, and the potential of the seventh charge transfer channel R7 for electrons is deep. As shown in FIG. 13, from the seventh charge transfer channel R7 to the seventh charge storage region SD7, Further, a potential gradient that continuously descends to the seventh target region FD7 is formed. That is, the gate to the 7th charge storage region SD7 is open, but all the gates other than the 7th charge storage region SD7 are closed. The potentials of the charge transfer channels other than the seventh charge storage region SD7 for electrons are shallow, and potential gradients that hinder the movement of charges are formed.

On the other hand, for example, when it is desired to transfer the charge to the fifth charge storage region SD5 and the fifth target region FD5 using the lowermost fifth charge transfer channel R5 in FIG. 1, the central axis of the fifth charge transfer channel R5. The first control electrode pair (G8, G1), the second control electrode pair (G2, G7), the third control electrode pair (G3, G6), and the fourth control electrode pair (G4, G5) are formed along the above. Will be done.

Then, eight control electrode pairs (G8, G1) are sequentially applied from the first control electrode pair (G8, G1) toward the fourth control electrode pair (G4, G5), which is the end point side of the charge transfer, so that the applied potential increases. By controlling the voltage applied to the pair of input control electrodes, the signal charge can be moved to the fifth target region FD5. Although not shown, in order to efficiently change the depletion potential, the portion directly below the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., The eighth input control electrode G8. The thickness of the insulating film 9 is thinner than that of other parts, and functions as a so-called "gate insulating film". Actually, the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., the eighth input control electrode G8, etc. are embedded inside the insulating film 9, and the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., The area directly below the eighth input control electrode G8 is thinner than the other parts.

As shown in FIG. 2, the signal processing region (2, 3, 5, 7) shown in FIG. 1 is provided with a p-type element arrangement layer 2 and an n-type provided in a part of the upper part of the element arrangement layer 2. The electron, which is a large number of carriers in the surface-embedded region 3, is transported in the surface-embedded region 3 as a signal charge. A p-type pinning layer 5 is provided in contact with the surface of the surface-embedded region 3 that functions as a charge transfer channel. As shown in FIG. 2, the cross-sectional structure of the photoelectric conversion element using the charge storage element according to the embodiment has a three-layered signal processing region (2, 3, 5, 7) on the p-type semiconductor substrate 1. Since it is formed in, it actually has a four-layer structure.

FIG. 2 illustrates a structure in which the element arrangement layer 2 is deposited on the p-type semiconductor substrate 1 by epitaxial growth or the like, but the element arrangement layer 2 may be provided on the n-type semiconductor substrate 1. I do not care. Further, another layer may be included between the element arrangement layer 2 and the semiconductor substrate 1 to form a structure having five or more layers. In the pinning layer 5, the depletion potential of the charge transfer channel is controlled by the voltage applied to the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., The eighth input control electrode G8. By doing so, the density of holes, which are carriers of the opposite conductivity type to the signal charge, changes.

Although the insulating film 9 is not shown in the plan view of FIG. 1, the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., And the eighth input control electrode G8 are insulating films. It is arranged on the signal processing region (2, 3, 5, 7) via 9. A first charge transfer channel R1 is defined between the adjacent eighth input control electrode G8 and the first input control electrode G1, and a second charge transfer is performed between the adjacent first input control electrode G1 and the second input control electrode G2. Channel R2 is defined. Further, a third charge transfer channel R3 is defined between the adjacent second input control electrode G2 and the third input control electrode G3, and a fourth charge transfer channel R3 is defined between the adjacent third input control electrode G3 and the fourth input control electrode G4. The charge transfer channel R4 is defined. Further, a fifth charge transfer channel R5 is provided between the fourth input control electrode G4 and the fifth input control electrode G5, and a sixth charge transfer channel R6 is provided between the fifth input control electrode G5 and the sixth input control electrode G6. A seventh charge transfer channel R7 is defined between the sixth input control electrode G6 and the seventh input control electrode G7, and an eighth charge transfer channel R8 is defined between the seventh input control electrode G7 and the eighth input control electrode G8. ..

The eighth input control electrode G8 and the first input control electrode G1 are arranged along a direction orthogonal to the signal charge transfer direction so as to sandwich the surface embedded region 3 functioning as the first charge transfer channel R1. .. Similarly, the first input control electrode G1 and the second input control electrode G2 are arranged along a direction orthogonal to the signal charge transfer direction so as to sandwich the surface embedded region 3 functioning as the second charge transfer channel R2. ing. Further, the third input control electrode G3 and the fourth input control electrode G4 are arranged so that the second input control electrode G2 and the third input control electrode G3 sandwich the surface embedded region 3 that functions as the third charge transfer channel R3. 4 The fourth input control electrode G4 and the fifth input control electrode G5 sandwich the surface embedded region 3 functioning as the fifth charge transfer channel R5 so as to sandwich the surface embedded region 3 functioning as the fourth charge transfer channel R4. The sixth input control electrode G6 and the seventh input control electrode G7 are arranged so that the fifth input control electrode G5 and the sixth input control electrode G6 sandwich the surface embedded region 3 that functions as the sixth charge transfer channel R6. 7 The 7th input control electrode G7 and the 8th input control electrode G8 sandwich the surface embedded region 3 functioning as the 8th charge transfer channel R8 so as to sandwich the surface embedded region 3 functioning as the 7 charge transfer channel R7. It is arranged along a direction orthogonal to the transfer direction of the signal charge.

In the plan view of FIG. 1, the outer edge portion and the opening portion of the shielding plate 11 are shown by an octagonal broken line. In the plan view of FIG. 1, a part of the p-type element arrangement layer 2 located directly below the inside of the aperture and a part of the n-type surface embedded region 3 form an embedded photodiode region. There is. In FIG. 1, the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., No. 1 so as to surround the embedded photodiode region that functions as the charge supply region PD directly under the aperture. The 8-input control electrode G8 is arranged. Therefore, the potential applied to the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., And the eighth input control electrode G8 is changed to be located around the charge supply region PD. The depletion potential of the surface-embedded region 3 and the depletion potential of the charge transfer channel can be controlled and changed by the electrostatic induction effect.

Although not shown, the gate electrode of the first read transistor (amplification transistor) is connected to the first target region FD1 via a contact window provided in the insulating film 9. The drain electrode of the first read transistor is connected to the power supply VDD, and the source electrode is connected to the drain electrode of the first switching transistor SEL1 for pixel selection. The source electrode of the first switching transistor SEL1 is connected to a vertical signal line, and a horizontal line selection control signal SL (i) is given to the gate electrode from a vertical shift register (not shown).

By raising the selection control signal SL (i) to a high level, the first switching transistor SEL1 becomes conductive, and the current corresponding to the potential of the first target region FD1 amplified by the first read transistor flows in the vertical signal line. .. Further, the source electrode of the first reset transistor RT1 is connected to the first target region FD1. The drain electrode of the first reset transistor RT1 is connected to the power supply VDD, and the reset signal RT ₁ (i) is given to the gate electrode of the first reset transistor RT1 from the vertical shift register. The reset signal RT ₁ (i) is set to a high level, and the first reset transistor RT1 discharges the electric charge accumulated in the first target region FD1 to reset the first target region FD1.

On the other hand, the second target area FD2, the third target area FD3, the fourth target area FD4, ..., The seventh target area FD7 are also equivalent to the first read transistor, as in the first target area FD1. The second read transistor, the third read transistor, the fourth read transistor, ..., The seventh read transistor are connected. Further, in the second target area FD2, the third target area FD3, the fourth target area FD4, ..., And the seventh target area FD7, the second switching transistor SEL2 and the third switching transistor equivalent to the first switching transistor SEL1 are all included. SEL3, 4th switching transistor SEL4, ..., 7th switching transistor SEL7, 2nd reset transistor RT2, 3rd reset transistor RT3, 4th reset transistor RT4, ..., which are equivalent to the 1st reset transistor RT1. 7 The reset transistor RT7 is connected.

The movement of electrons generated in the charge supply region PD can be freely controlled by the voltage applied to the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., And the eighth input control electrode G8. In order to do so, the depletion potential of the charge transfer channel sandwiched between the control electrode pairs and the depletion potential in the embedded diode may be configured to vary greatly depending on the voltage applied to the control electrode pair. This can be done by setting the impurity density of the substrate low and selecting the p ⁺ pinning layer 5 for surface hole pinning to a relatively low impurity density. In principle, changes in the concentration of carriers inside the input control electrode and the pinning layer of the charge storage element are typically described using "input control electrode pairs 41a and 41b" in Patent Document 1. Since they are equivalent, duplicate explanations will be omitted.

In a normal solid-state imaging device, the pinning layer is a layer that suppresses carrier generation and signal carrier capture on the surface during darkness, and has been conventionally used as a preferable layer for reducing dark current and signal carrier capture. Although used, the pinning layer 5 of the photoelectric conversion element using the charge storage element according to the embodiment is not limited to these conventionally known functions, and the depletion potential of the surface embedded region 3 and the depletion of the charge transfer channel are depleted. It functions as an important layer that greatly changes the conversion potential with the voltage of the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., And the eighth input control electrode G8. ..

By applying gate voltages of different voltage levels to each of the four control electrode pairs as illustrated in FIG. 12, light incident on the opening (aperture) of the shielding plate 11 is generated in the embedded photodiode region. It is possible to realize a charge modulation element or the like that moves the carriers (electrons) at high speed so as to distribute them to a desired movement path in eight directions extending from the charge supply region PD.

That is, in the photoelectric conversion element using the charge storage element according to the embodiment, as shown in FIG. 12, at the ends of the eight charge transfer channels provided with the central axes at an angle of 45 ° each, Since the first target area FD1 to the eighth target area FD8 are provided, the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., The eighth input control electrode G8 By applying different gate voltages of the first to fourth potential levels, the signal charges of carriers (electrons) generated in the embedded photodiode region located on the starting point side of the eight charge transfer channels are input to the first input. Control electrode G1, 2nd input control electrode G2, 3rd input control electrode G3, ..., Optical flight time (TOF) type distance sensor that is distributed and moved at high speed by the electric charge control voltage applied to the 8th input control electrode G8. The operation can be realized.

Since the gate electrode of the first read transistor is connected to the first target region FD1, the output amplified by the first read transistor is generated by the voltage corresponding to the amount of electric charge transported to the first target region FD1. , It is output to the outside via the first switching transistor SEL1. Similarly, since the gate electrode of the second read transistor is connected to the second target region FD2, it is amplified by the second read transistor by the voltage corresponding to the amount of electric charge transported to the second target region FD2. The output is output to the outside via the second switching transistor.

For example, in application to a TOF type distance sensor, light is repeatedly irradiated to an object as a pulse signal from a light source provided in the TOF distance sensor, and the delay time T _d required for the reciprocation of the light reflected by the object is measured. do it. That is, in the application to the TOF distance sensor, as described above, the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., And the eighth input control electrode G8 are in phase with each other. The operation of applying the first control pulse, the second control pulse, the third control pulse, ..., The eighth control pulse, which are different from each other, is periodically repeated in synchronization with the repetition period of the optical pulse of the output light, and the delay time. Measure T _d . For the measurement of the delay time T _d, it can be used the same principle as "measurement of the delay time T _d" in Patent Document 1.

The photoelectric conversion element using the charge storage element according to the embodiment is operated by using pulsed light having a relatively narrow duty. During the period in which the light pulse of the incoming light is received and the charge modulated by the charge storage element is stored, the first control pulse, the second control pulse, the third control pulse, ..., The eighth control pulse are generated by a shaping circuit. It is shaped to generate four output levels of first potential level L, second potential level M, third potential level H, and fourth potential level V, respectively, and eight gate signals are periodically applied for operation. .. The four-stage output level signal may be realized, for example, by appropriately combining a plurality of logic circuits.

The charge transferred to the desired charge transfer channel by the control voltage applied to the first input control electrode G1, the second input control electrode G2, the third input control electrode G3, ..., The eighth input control electrode G8 is a capacitance. The first charge storage region SD1, the second charge storage region SD2, and the third charge storage region depend on the control voltage applied to the magnifying electrodes CA11, CA21, CA31, ..., CA81; CA12, CA22, CA32, ..., CA82. It is stored in each of SD3, ..., And the eighth charge storage region SD8. Then, when a high level potential is applied to the pair of magnifying electrode pairs CA11, CA21, CA31, ..., CA81; CA12, CA22, CA32, ..., CA82 provided on both sides of each charge storage region, the built-in potential is applied. A potential depending on the (diffusion potential) or the lateral electric field is generated, and as shown by the solid line trajectory in FIG. 14, the potentials of the desired charge storage regions SD1, SD2, SD3, ..., SD8 can be deepened. At this time, the number of electrons that can be stored in each of the charge storage regions SD1, SD2, SD3, ..., SD8 having a constant volume was 1912 when calculated by simulation.

On the other hand, in the case of a charge storage element without a pair of magnifying electrodes, the potential of the charge storage regions SD1, SD2, SD3, ..., SD8 with respect to electrons is not deep, and as shown by the broken line locus in FIG. The maximum thickness is about 0.56 V shallower than that of the photoelectric conversion element using the charge storage element according to the embodiment. The number of electrons that can be stored in the charge storage regions SD1, SD2, SD3, ..., SD8 having the same volume as that of the embodiment of the present invention was 820 when calculated by simulation. That is, the charge storage element provided with the capacitance expansion electrodes CA11, CA21, CA31, ..., CA81; CA12, CA22, CA32, ..., CA82 can store 1092 more electrons.

Further, as shown in FIG. 15, the voltage applied to the input control electrodes G1, G2, G3, ..., G8 is set to a low level, and the capacitance expansion electrodes CA11, CA21, CA31, ..., CA81; CA12, CA22, CA32 , ..., with the voltage applied to CA82 at a low level of, for example, about 2.58V, the output control electrodes TX11, TX21, TX31, ..., TX81; TX12, TX22, TX32, ..., TX82 are at a low level. From SD1, SD2, SD3, ..., SD8 to the target region, the slope of the potential with respect to the electrons can be changed sharply. In this way, by strengthening the slope of the potential for electrons from the charge storage regions SD1, SD2, SD3, ..., SD8 to the target regions FD1, FD2, FD3, ..., FD8, the target regions FD1, FD2, FD3, ... ..., can assist in facilitating the transfer of charge to the FD8.

The photoelectric conversion element using the charge storage element according to the embodiment has capacitance expansion electrodes CA11, CA21, CA31, ..., CA81 that assist the transfer of charges in the vicinity of the charge storage regions SD1, SD2, SD3, ..., SD8. ; CA12, CA22, CA32, ..., CA82 are provided. Then, by applying a high level potential to the capacitance expansion electrodes CA11, CA21, CA31, ..., CA81; CA12, CA22, CA32, ..., CA82, a built-in potential (diffusion potential) or a potential dependent on the lateral electric field is applied. The number of electrons that can be stored can be increased. Therefore, according to the photoelectric conversion element using the charge storage element according to the embodiment, by increasing the accumulated charge capacity in the charge movement path, the respective charge storage regions SD1, SD2, SD3, ..., SD8 are sufficient. Accumulated charge capacity can be realized.

Further, according to the photoelectric conversion element using the charge storage element according to the embodiment, when the charge is transferred from the charge storage region SD1, SD2, SD3, ..., SD8 to the target region FD1, FD2, FD3, ..., FD8. By setting the capacitance expansion electrodes CA11, CA21, CA31, ..., CA81; CA12, CA22, CA32, ..., CA82 to low-level potentials, the inclination to the target region FD1, FD2, FD3, ..., FD8 Can be strengthened to assist the transfer of electric charge to the target regions FD1, FD2, FD3, ..., FD8.

(First modification)
The output control electrodes TX11, TX21, TX31, ..., TX81; TX12, TX22, TX32, ..., TX82 of the charge storage elements shown in FIGS. 1 to 15 all have charge storage regions SD1, SD2, SD3, ... ..., SD8 was provided in pairs so as to sandwich the second rectangular region of each. However, as illustrated in the enlarged view of the region centered on the seventh charge storage region SD7 in FIG. 16, above the first rectangular region and the narrow second rectangular region of the seventh charge storage region SD7. The output control electrode TX70 having a normal insulated gate structure composed of one sheet may be provided so as to overlap with each other at the same time.

17 and 18 show a pair of magnifying electrodes with a voltage of -1V applied to the sixth input control electrode G6 and the seventh input control electrode G7 and a voltage of -1V applied to the output control electrode TX70 having a normal insulated gate structure. The cross section of the potential state for electrons obtained when the voltage applied to (CA71, CA72) is changed between about -1.0 V and about 2.3 V, as viewed from the X2-X2 direction of FIG. The position of and the position of the cross section seen from the Y4-Y4 direction are shown. As shown in FIGS. 17 and 18, the greater the voltage applied to the pair of magnifying electrode pairs (CA71, CA72), the deeper the depth of the deepest potential for electrons. As can be seen from FIGS. 17 and 18, when the voltage applied to the pair of magnifying electrode pairs (CA71, CA72) varies between about -1.0V and about 2.3V, it is about 2.58V to about 3. A modulation effect of 12V could be obtained.

Similarly to the charge storage element shown in FIGS. 1 to 15, the charge storage element according to the first modification of the embodiment provided with the single output control electrode TX70 also accumulates the charge in the movement path. It is possible to increase the charge capacity and assist the transfer of charge to the target regions FD1, FD2, FD3, ..., FD8.

(Second modification)
Further, as illustrated in the enlarged view of the region centered on the seventh charge storage region SD7 in FIG. 19, in the charge storage element according to the second modification of the embodiment, the seventh charge storage region SD7 has a substantially rectangular shape. An n-type (n ⁺⁺ ) charge storage auxiliary region XD7 having a higher impurity density than the seventh charge storage region SD7, which is composed of only regions and extends from this rectangular region toward the seventh target region FD7, is provided for electrons. The potential may be deepened.

As shown in FIG. 19, the charge storage auxiliary region XD7 has a substantially crucifix shape in a planar pattern, and the region corresponding to the lower side of the horizontal bar of the vertical bar of the cross partially overlaps with the seventh charge storage area SD7. The potential for electrons becomes deeper. The region corresponding to the upper side of the horizontal bar of the vertical bar of the cross of the charge storage auxiliary region XD7 is in contact with the seventh target region FD7 on the output side. The region corresponding to the left and right protruding portions of the horizontal bar of the cross of the charge storage auxiliary region XD7 is arranged so that the pair of output electrode pairs (TX71, TX72) and the end portions partially overlap each other.

20 and 21 show a pair of output electrode pairs with the voltage applied to the sixth input control electrode G6, the seventh input control electrode G7, and the pair of magnifying electrode pairs (CA71, CA72) at low levels. The position of the cross section and the Y5-Y5 direction as seen from the X3-X3 direction of FIG. 19 obtained when the voltage applied to (TX71, TX72) was changed between about -2.0V and about 3.0V. The state of the potential for each electron at the position of the cross section seen from is shown. As shown in FIGS. 20 and 21, the larger the voltage applied to the pair of output electrode pairs (TX71, TX72), the stronger the inclination of the potential for electrons to the seventh target region FD7 on the output side.

On the other hand, as shown in FIG. 22, in the case of a charge storage element in which a pair of magnifying electrode pairs (CA71, CA72) is not provided, for example, the voltage applied to the pair of output electrode pairs (TX71, TX72) is about 3. In the case of .3V, a substantially flat potential region is generated at the boundary between the 7th charge storage region SD7 and the 7th target region FD7. Since a relatively large amount of electric charge stays in this flat potential region, as shown in FIG. 22, when the voltage applied to the pair of output electrode pairs (TX71, TX72) changes to, for example, about −1.0 V, The potential of this flat potential region becomes shallow, and a part of the accumulated charge falls to the 7th target region FD7, but a part of it falls to the 7th charge storage region SD7 side, that is, the so-called "return charge" from the output side. Will occur a lot. The return charge leads to increased noise.

In this regard, in the case of the charge storage element according to the second modification, the voltage applied to the pair of output electrode pairs (TX71, TX72) changes with the pair of magnifying electrode pairs (CA71, CA72) provided. Even if the voltage of the pair of output electrode pairs (TX71, TX72) is low, the potential gradient with respect to the electron to the 7th target region FD7 is strong, and the flat potential region as shown in FIG. 22 is on the output side. Does not occur. Therefore, according to the charge storage element according to the second modification, in addition to the effects of the charge storage elements shown in FIGS. 1 to 15, it is possible to further suppress the generation of return charge and reduce the noise of the charge storage element. ..

(Comparison example)
Further, FIG. 23 shows a structure in which the seventh charge storage region SD7 is connected to the n-type seventh charge transfer channel R7 connected to the charge supply region PD on the input side without independently providing a pair of magnifying electrodes. A charge storage element according to a comparative example is shown in which a one-stage charge transfer structure is formed long along a charge transfer channel by a pair of control electrode pairs (G6A, G7A). In the charge storage element according to the comparative example, the signal charge is transferred from the charge supply region PD on the input side to the seventh charge transfer channel R7, and the stored charge capacity in the seventh charge transfer channel R7 is increased to increase the charge capacity on the output side. A structure is shown that includes a pair of control electrode pairs (G6A, G7A) that assist in the transfer of signal charges to the seventh objective region FD7.

The input control electrodes G6A and G7A constituting the pair of control electrode pairs (G6A, G7A) are slightly separated from the seventh charge transfer channel R7 on both sides of the seventh charge transfer channel R7 and the seventh charge storage region SD7. It is provided. Each of the input control electrodes G6A and G7A has a rectangular pattern as a plan view, and the output-side region near the seventh target region FD7 of each rectangular pattern and close to the seventh charge storage region SD7 is n. It constitutes a composite structure composed of polycrystalline silicon (doped polysilicon) to which ⁺ -type impurities are added. n ⁺ -type potential at zero bias of the seventh charge storage region SD7 of the seventh object region FD7 Towards sandwiched on both sides by doped polysilicon region deeper rely on surface potential by the n ⁺ type doped polysilicon region ing. Input control electrode G6A, in each of the composite structure of G7A, except n ⁺ -type doped polysilicon region is composed of p ⁺ type doped polysilicon region. p ⁺ -type doped poly surface potential level by a p ⁺ -type doped polysilicon region at zero bias of the silicon region on both sides of the sandwiched left side of the input side of the seventh charge storage region SD7 and seventh charge transfer channel R7 It is shallow depending on.

(Third modification example)
FIG. 24 shows a charge storage element according to a third modification in which a seventh charge storage region SD7 is provided for the charge storage element having the one-stage charge transfer structure shown in FIG. 23. As shown in FIG. 24, a pair of control electrode pairs (G6A, G7A) having a region of n ⁺ type doped polysilicon, together with a pair of magnifying electrode pairs (CA71, CA72), are partially provided in the seventh target region FD7. It may be placed close to. The input control electrodes G6A and G7A constituting the pair of control electrode pairs (G6A and G7A) shown on the left side of FIG. 24 have a stepped seventh charge transfer channel R7 and a narrow portion on the left side of the seventh charge storage region SD7. The seventh charge storage region SD7 is provided on both sides of the connection portion with a slight distance from the left side portion. Each of the input control electrodes G6A and G7A has a rectangular pattern as a plan view, but has a smaller area than the structure shown in FIG. 23, and a part of the region close to the left side portion of the seventh charge storage region SD7 is , N ⁺ -type doped polysilicon constitutes a composite structure. potential at zero bias on the left side portion of the seventh charge storage region SD7 sandwiched on both sides by n ⁺ -type doped polysilicon region is deeper rely on surface potential by the n ⁺ type doped polysilicon region. Input control electrode G6A, in each of the composite structure of G7A, except n ⁺ -type doped polysilicon region is composed of p ⁺ type doped polysilicon region. potential at zero bias of the seventh charge transfer channel R7 sandwiched on both sides by p ⁺ -type doped polysilicon region is shallower rely on surface potential by the p ⁺ -type doped polysilicon region.

Similar to those already shown in FIGS. 17 and 18, the larger the voltage applied to the pair of enlarged electrode pairs CA71 and CA72 close to the thick portion on the right side of the seventh charge storage region SD7, the larger the seventh charge storage region. The depth of potential for electrons in the thick portion on the right side of SD7 can be deeply controlled, and the amount of charge stored in the seventh charge storage region SD7 can be increased. As shown in FIG. 24, a pair of magnifying electrodes pairs CA11, CA21, CA31, ..., CA81; CA12, CA22, CA32, ..., CA82 in the vicinity of the charge storage regions SD1, SD2, SD3, ..., SD8. And the charge storage element according to the third modification in which the input control electrodes G6A and G7A constituting the pair of magnifying electrodes are arranged so as to face each other also has a charge transfer path similar to the charge storage element shown in FIGS. While increasing the accumulated charge capacity inside, it is possible to assist the transfer of signal charge to the target regions FD1, FD2, FD3, ..., FD8.

(Fourth modification)
Further, as shown in FIGS. 25 and 26 (a), n ⁺ type charge accumulation promoting regions SD71 and SD72 are surface-embedded regions on the upper part of the element arrangement layer 2 under the pair of enlarged electrode pairs (CA71 and CA72). A pair of magnifying electrode pairs (CA71, CA72) of the charge storage element according to the comparative example illustrated in FIGS. 25 and 26 (a) may be provided in contact with the third charge transfer channel R7. A part of the rectangular region to be formed is composed of n ⁺ type doped polysilicon.

The capacitance expansion electrodes CA71 and CA72 constituting the pair of expansion electrode pairs (CA71, CA72) shown on the right side of FIG. 25 sandwich the right portion of the seventh charge storage region SD7 on both sides of the seventh charge storage region SD7. It is provided slightly away from the right side of the. Each of the capacitance expansion electrodes CA71 and CA72 has a rectangular pattern as a plan view. A part of the output side region close to the right side portion of the seventh charge storage region SD7 of the capacitance expansion electrodes CA71 and CA72 constitutes a composite structure composed of n ⁺ type doped polysilicon. potential at zero bias of the right portion of the seventh charge storage region SD7 sandwiched on both sides by n ⁺ -type doped polysilicon region is deeper rely on surface potential by the n ⁺ type doped polysilicon region. In each of the composite structure of capacity expansion electrodes CA71, CA72, except ^{n +} -type doped polysilicon region is composed of ^{p +} type doped polysilicon region. potential at zero bias of the seventh charge storage region SD7 sandwiched on both sides by p ⁺ -type doped polysilicon region is shallower rely on surface potential by the p ⁺ -type doped polysilicon region.

As shown by the shaded areas in FIGS. 26 (b) and 27, in the charge storage element according to the comparative example, electrons for charge storage are also under the pair of magnifying electrode pairs (CA71, CA72). A potential well can be formed. FIG. 27 illustrates a state in which a deep potential for electrons of Φ1 is formed between the insulating film 9 and the upper portion of the charge accumulation promoting region SD72. According to the charge storage element according to the fourth modification, in addition to the effect of the charge storage element shown in FIGS. 1 to 15, the charge storage amount can be further increased.

(Other embodiments)
Although the present invention has been described by the embodiments described above, the statements and drawings that form part of this disclosure should not be understood to limit the invention. Various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art from this disclosure. For example, in FIGS. 1 to 27, a case where the light receiving region of the 8-tap lateral electric field control type photoelectric conversion element is the charge supply region PD of the charge storage element has been described as an example, but the input side of the charge storage element The connected charge supply region PD is not limited to the 8-tap lateral electric field control type photoelectric conversion element, and the number of taps can be arbitrarily changed such as 1-tap type and 5-tap type. The charge supply region PD connected to the input side does not have to be the light receiving region of the photoelectric conversion element, and may be another semiconductor region as long as it can supply signal charges.

Further, the shape of the charge supply region PD connected to the input side has been described as a regular octagon, but the shape is not limited to this, and may be appropriately changed according to the specifications of the charge storage element such as the number of taps. Further, the charge storage element according to the present invention can be realized by combining the partial structures included in the charge storage elements shown in FIGS. 1 to 27 with each other.

In the description of the embodiment of the present invention described above, the first conductive type is defined as p type and the second conductive type is defined as n type. However, the first conductive type may be defined as n type and the second conductive type may be defined as p type. It is easy to understand that the same effect can be obtained by reversing the electrical polarity.

In the description of the embodiment of the present invention described above, the signal charge to be transported, stored, etc. is an electron, and in the potential diagram, the downward direction (depth direction) of the figure is the positive direction of the potential (potential). However, when the electrical polarity is reversed, the electric charge to be processed becomes holes, so the potential shape indicating the potential barrier, potential valley, potential well, etc. in the photoelectric conversion element is shown below the figure. The direction (depth direction) is expressed as the negative direction of the potential.

As described above, the present invention includes various embodiments not described above, and the technical scope of the present invention is defined only by the matters specifying the invention relating to the reasonable claims from the above description. It is a thing.

1 Semiconductor substrate 2 Element placement layer 3 Surface embedded region 5 Pinning layer 7 Potential hill forming portion 9 Insulation film 11 Shielding plate CA11 to CA81, CA12 to CA82, G6A, G7A Capacity expansion electrodes TX11 to TX81, TX12 to TX82, TX70 Output Control electrodes FD1 to FD8 1st target area to 8th target area G1 to G8 1st input control electrode to 8th input control electrode SD1 to SD8 1st charge storage area to 8th charge storage area SD71, SD72 Charge storage promotion area XD7 Charge storage auxiliary area

Claims (9)

The first conductive type element arrangement layer and
A second conductive type surface-embedded region provided in a part of the upper part of the element arrangement layer and forming a charge supply region,
An input side is connected to the surface-embedded region, and a second conductive type charge storage region having a higher impurity density than the surface-embedded region and
A second conductive type target region connected to the output side of the charge storage region and having a higher impurity density than the charge storage region.
The charge transfer channels are arranged in pairs on both sides of the charge transfer channel defined on the input side of the charge storage region, and the depletion potential of the charge transfer channels is controlled by the lateral electrostatic induction effect to control the surface-embedded region. The input control electrode that introduces the signal charge into the charge storage region from
Adjacent to the input control electrode, located on the output side of the charge transfer channel and arranged in pairs on both sides of the charge storage region, the depletion potential of the charge storage region is laterally electrostatically induced. With the capacitance expansion electrode controlled by
A charge storage element comprising the above, wherein the amount of signal charge accumulated in the charge storage region is expanded by a voltage applied to the capacity expansion electrode. The charge storage element according to claim 1, wherein the capacitance expanding electrode is divided into a region made of a first conductive type polycrystalline silicon film and a region made of a second conductive type polycrystalline silicon film. .. The charge storage device according to claim 2, wherein the region made of the second conductive type polycrystalline silicon film is arranged at a position close to the charge storage region on the output side of the charge storage region. .. The charge storage element according to claim 1, wherein the input control electrode is divided into a region made of a first conductive type polycrystalline silicon film and a region made of a second conductive type polycrystalline silicon film. .. The charge storage device according to claim 4, wherein the region made of the second conductive type polycrystalline silicon film is arranged at a position in a direction away from the input side of the charge transfer channel. In the second conductive type, the charge accumulation promoting region having a higher impurity density than the charge accumulation region is insulated on the output side of the charge storage region by a part of the upper part of the element arrangement layer below the capacitance expansion electrode. The charge accumulating element according to any one of claims 1 to 5, wherein the charge accumulating element is arranged via a film. The first conductive type element arrangement layer and
A second conductive type surface-embedded region provided in a part of the upper part of the element arrangement layer and forming a charge supply region,
An input side is connected to the surface-embedded region, and a second conductive type charge storage region having a higher impurity density than the surface-embedded region and
A second conductive type target region connected to the output side of the charge storage region and having a higher impurity density than the charge storage region.
It is divided into a region composed of a first conductive type polycrystalline silicon film and a region composed of a second conductive type polycrystalline silicon film, which are symmetrically arranged on both sides of the charge storage region and have a depletion potential of the charge storage region. With an input control electrode that controls the lateral electrostatic induction effect,
The region made of the first conductive type polycrystalline silicon film is arranged in pairs on both sides of the charge transfer channel defined on the input side of the charge storage region, and the charge transfer channel is depleted. The region formed of the second conductive type polycrystalline silicon film functions as an input control electrode that controls the potential by the lateral electrostatic induction effect and introduces the signal charge from the surface-embedded region into the charge storage region. , It is arranged at a position close to the charge storage region on the output side of the charge storage region, and is accumulated in the charge storage region by controlling the depletion potential of the charge storage region by the lateral electrostatic induction effect. A charge storage element characterized by increasing the amount of signal charge. The present invention according to any one of claims 1 to 7, further comprising an output control electrode provided on the output side of the charge storage region and transferring the signal charge accumulated in the charge storage region to the target region. The charge storage element according to the description. On the plane pattern, the charge storage region is provided so as to include the output side region of the charge storage region, and a second conductive type charge storage auxiliary region having a higher impurity density than the charge storage region is further provided. The charge storage device according to any one of claims 1 to 8.

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