JP6795734B2 - DC / AC inverter - Google Patents

Description

The present invention relates to a DC / AC inverter that connects a low-voltage direct current to a system, such as a power conditioner for photovoltaic power generation.

Patent Document 1 uses two inverters to adjust the output voltage of the inverters according to the pulsation of alternating current, and switches the operation of the two inverters to convert direct current to alternating current.

However, in Patent Document 1, since an AC ripple current flows through the smoothing capacitor of the inverter, the capacity of the smoothing capacitor cannot be reduced. Therefore, the inverter device described in Patent Document 2 shown in FIG. 11 is used. This inverter device is an active filter circuit 211 having a full bridge circuit composed of switch elements 51S to 54S, an isolated DC / DC converter 213 composed of diodes D11 to D14, a reactor L3, a capacitor C12, a switch element 3S and a capacitor Cdc. The inverter circuit 221 has a full bridge circuit including switch elements 41S to 44S.

This inverter device uses the active filter circuit 211 to generate an alternating pulsation component in the capacitor Ccd, and inputs the combined voltage of the capacitor Ccd and the DC voltage Vdc into the inverter circuit 221 to convert the direct current into an alternating current. As a result, the ripple content of the current flowing through the capacitor C12 can be suppressed.

Japanese Unexamined Patent Publication No. 61-251480 International Publication No. 2013/146340

However, since switch elements are used for each of the rectifier circuits D11 to D14 and the active filter circuit 211 of the isolated DC / DC converter (switching power supply circuit) 213, the number of parts is large and the conduction loss due to the switch elements is large. , The efficiency was reduced.

An object of the present invention is to provide a DC / AC inverter capable of simplifying a circuit and improving efficiency.

The present invention is a DC / AC inverter that converts a DC voltage into an AC voltage, includes a half-bridge circuit including a first switch element and a second switch element, and switches the first switch element and the second switch element. A DC / DC converter that converts the DC voltage into an AC voltage and outputs it to the secondary winding via the primary winding of the transformer, and the third switch element to the third switch element connected to the secondary winding. A first full bridge circuit consisting of 6 switch elements, an active buffer circuit having buffer capacitors connected to both ends of the output of the first full bridge circuit, and a second full bridge circuit consisting of 7th switch elements to 10th switch elements. the a, comprising a current inverter for supplying to a load to convert the voltage from the buffer capacitor into an AC voltage, and a control circuit for turning on and off the respective switching elements of the first switching element to tenth switching element, wherein The control circuit has a first mode in which the output of the DC / DC converter is supplied to the load, a second mode in which the buffer capacitor is charged by the output of the DC / DC converter, the output of the DC / DC converter and the buffer capacitor. The processing of the third mode in which the DC / DC converters are connected in series and discharged to the load, and the fourth mode in which the output of the DC / DC converter does not act on the buffer capacitor is performed from the first mode to the fourth mode in order. Each switch element is controlled on and off, and the secondary winding is composed of a series circuit of a first secondary winding and a second secondary winding, and the first secondary winding is connected to one end of the first secondary winding. The 3 switch element and the 4th switch element are connected, the 5th switch element and the 6th switch element are connected to one end of the 2nd secondary winding, and the control circuit is the first in the 1st mode. The 3 switch element or the 5th switch element is turned on, the two switch elements diagonal to the 2nd full bridge circuit are turned on, and in the 2nd mode, the 3rd switch element or the 5th switch element is turned on. Turn on, turn off all switch elements of the second full bridge circuit, turn on the fourth switch element or the sixth switch element in the third mode, and make a diagonal of the second full bridge circuit 2 It is characterized in that one switch element is turned on, the fourth switch element or the sixth switch element is turned on, and all the switch elements of the second full bridge circuit are turned off in the fourth mode .

According to the present invention, in contrast to the conventional DC / AC inverter, the DC / DC converter is composed of a half-bridge circuit composed of first and second switch elements, the diode is eliminated, and high-frequency rectification is performed in the active buffer circuit. By adding the operation, the number of passing elements in the secondary side circuit of the transformer is reduced, so that the circuit configuration can be simplified and the efficiency can be improved by reducing the conduction loss.

It is a figure which shows the circuit structure of the DC / AC inverter which concerns on Example 1 of this invention. It is a figure for demonstrating the operation of each mode of the DC / AC inverter which concerns on Example 1 of this invention. It is a figure for demonstrating the operation of each mode of the DC / AC inverter which concerns on Example 1 of this invention. It is a figure which shows the structure of the control circuit of the DC / AC inverter which concerns on Example 1 of this invention. It is a figure which shows the detailed structure of the Δ-ΣPDM part shown in FIG. It is a figure which shows the voltage waveform and the current waveform of the half-bridge circuit in the DC / AC inverter which concerns on Example 1 of this invention. It is a figure which shows the voltage waveform and the current waveform of the active buffer circuit and the current inverter in the DC / AC inverter which concerns on Example 1 of this invention. It is a figure which shows the waveform of the input voltage, the input current, the capacitor voltage, the system voltage, and the inverter output current of the DC / AC inverter which concerns on Example 1 of this invention. It is a figure which shows the efficiency of the output power of the DC / AC inverter which concerns on Example 1 of this invention. It is a figure which shows the loss analysis result at the time of output power of 300W of the DC / AC inverter which concerns on Example 1 of this invention. It is a figure which shows the circuit structure of the conventional DC / AC inverter.

Hereinafter, the DC / AC inverter according to the embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of a DC / AC inverter according to a first embodiment of the present invention. The DC / AC inverter shown in FIG. 1 adds a high-frequency rectification operation to the active buffer circuit to reduce the number of elements passing through the transformer secondary circuit, simplify the circuit configuration, and reduce conduction loss. It is a feature.

In the DC / AC inverter shown in FIG. 1, a series circuit of the capacitor C1 and the capacitor C2 and a series circuit of the first switch element S1 and the second switch element S2 are connected to both ends of the DC power supply Vin. .. A series circuit of the reactor Ls and the primary winding P of the transformer T is connected between the connection point between the capacitor C1 and the capacitor C2 and the connection point between the first switch element S1 and the second switch element S2. There is. The first switch element S1 and the second switch element S2 form a half-bridge circuit. The reactor Ls may be the leakage inductance between the primary winding P and the secondary winding of the transformer T.

The capacitor C1, the capacitor C2, the first switch element S1, the second switch element S2, the reactor Ls, and the primary winding P of the transformer T form an isolated DC / DC converter. This DC / DC converter reduces switching loss by performing zero current switching (ZCS) between the first switch element S1 and the second switch element S2 by resonance between the reactor Ls and the capacitors C1 and C2.

On the secondary side of the transformer T, the first secondary winding SA1 and the second secondary winding SA2 are connected in series. The first secondary winding SA1 and the second secondary winding SA2 are connected to both ends of a first full bridge circuit including a third switch element S3 to a sixth switch element S6 and a first full bridge circuit. A capacitor C3 (corresponding to a buffer capacitor) and an active buffer circuit 2 including diodes D1 to D3 are connected. The diode D1 corresponds to the first rectifying element, the diode D2 corresponds to the second rectifying element, and the diode D3 corresponds to the third rectifying element.

The source of the third switch element S3 and the anode of the diode D1 are connected to one end of the first secondary winding SA1, and the drain of the fourth switch element S4 is connected to the cathode of the diode D1. The source of the fifth switch element S5 and the anode of the diode D2 are connected to one end of the second secondary winding SA2, and the drain of the sixth switch element S6 is connected to the cathode of the diode D2.

The drain of the third switch element S3 and the drain of the fifth switch element S5 are connected to one end of the capacitor C3, and the source of the fourth switch element S4 and the source of the sixth switch element S6 are the other end of the capacitor C3 and the diode D3. It is connected to the anode of. The connection point between the first secondary winding SA1 and the second secondary winding SA2 is connected to the cathode of the diode D3.

A current inverter 3 including a second full bridge circuit including the seventh switch element S7 to the tenth switch element S10 is connected to both ends of the series circuit of the capacitor C3 and the diode D3. The drain of the 7th switch element S7 and the drain of the 9th switch element S9 are connected to one end of the capacitor C3, and the source of the 8th switch element S8 and the source of the 10th switch element S10 are connected to the cathode of the diode D3. There is.

The drain of the eighth switch element S8 is connected to the source of the seventh switch element S7, and the drain of the tenth switch element S10 is connected to the source of the ninth switch element S9. Both ends of the capacitor C4 are connected to the connection point between the source of the 7th switch element S7 and the drain of the 8th switch element S8 and the connection point between the source of the 9th switch element S9 and the drain of the 10th switch element S10. At the same time, a series circuit of the reactor Lo and the AC power supply 4 is connected. The capacitor C4 and the reactor Lo form an output filter.

The first switch element S1 to the tenth switch element S10 are composed of MOSFETs, and a diode is connected between the drain and the source of the MOSFET. This diode may be a parasitic diode of the MOSFET or a separate diode.

The control circuit 10 controls on / off of the first switch element S1 to the tenth switch element S10. Details of on / off control of each switch element of the control circuit 10 will be described later.

Next, the operation of each operation mode will be described in detail with reference to FIGS. 1 to 3 for the DC / AC inverter of the first embodiment configured in this way. The operation modes are direct delivery mode (corresponding to FIGS. 2 (a), 2 (b), and first mode), charging mode (corresponding to FIG. 2 (c), FIG. 2 (d), and second mode), and discharging mode. It is composed of four modes (FIG. 3 (a), FIG. 3 (b), corresponding to the third mode) and a reflux mode (FIG. 3 (c), FIG. 3 (d), corresponding to the fourth mode). Here, only the operation mode when the system voltage is positive will be described. The switching frequency of the half-bridge circuit is set with a duty of 50% according to the resonance frequency.

First, the direct delivery mode will be described with reference to FIGS. 1 and 2 (a) and 2 (b). The control circuit 10 turns off the first switch element S1 and turns on the second switch element S2, the third switch element S3, the seventh switch element S7, and the tenth switch element S10 in a half cycle of the gate signal. Then, the current ircc flows in the route of Vin → C1 → Ls → P → S2 → Vin. On the secondary side of the transformer T, the current idc flows through the path of one end of the first secondary winding SA1 → S3 → S7 → 4 → S10 → the other end of the first secondary winding SA1.

Next, the control circuit 10 turns off the second switch element S2 in the next half cycle of the gate signal, and causes the first switch element S1, the fifth switch element S5, the seventh switch element S7, and the tenth switch element S10. Turn on. Then, the current ircc flows in the route of Vin → S1 → P → Ls → C2 → Vin. On the secondary side of the transformer T, the current idc flows through the path of one end of the second secondary winding SA2 → S5 → S7 → 4 → S10 → the other end of the second secondary winding SA2. Therefore, the power of the DC power supply 1 can be directly sent to the load 4 (system).

Next, a charging mode for charging the capacitor C3 will be described with reference to FIGS. 1 and 2 (c) and 2 (d).

The control circuit 10 turns on the second switch element S2 and the third switch element S3, and turns off the seventh switch element S7 to the tenth switch element S10 in a half cycle of the gate signal. Then, the current ircc flows in the route of Vin → C1 → Ls → P → S2 → Vin. On the secondary side of the transformer T, the current idc flows in the path of one end of the first secondary winding SA1 → C3 → D3 → the other end of the first secondary winding SA1.

Next, the control circuit 10 turns on the first switch element S1 and the fifth switch element S5, and turns off the seventh switch element S7 to the tenth switch element S10 in the next half cycle of the gate signal. Then, the current ircc flows in the route of Vin → S1 → P → Ls → C2 → Vin. On the secondary side of the transformer T, the current idc flows in the path of one end of the second secondary winding SA2 → S5 → C3 → D3 → the other end of the second secondary winding SA2. Therefore, the power of the DC power supply 1 can be charged to the capacitor C3.

Next, a discharge mode for discharging the capacitor C3 will be described with reference to FIGS. 1 and 3 (a) and 3 (b).

The control circuit 10 turns off the first switch element S1 and turns on the second switch element S2, the fourth switch element S4, the seventh switch element S7, and the tenth switch element S10 in a half cycle of the gate signal. Then, the current ircc flows in the route of Vin → C1 → Ls → P → S2 → Vin. On the secondary side of the transformer T, the current idc flows in the path of one end of the first secondary winding SA1 → D1 → S4 → D3 → the other end of the first secondary winding SA1. Further, the capacitor C3 is discharged to the load 4 (system) in the path of C3 → S7 → 4 → S10.

Next, the control circuit 10 turns off the second switch element S2 in the next half cycle of the gate signal, and turns the first switch element S1, the sixth switch element S6, the seventh switch element S7, and the tenth switch element S10. Turn it on. Then, the current ircc flows in the route of Vin → S1 → P → Ls → C2 → Vin. On the secondary side of the transformer T, the current idc flows in the path of one end of the second secondary winding SA2 → D2 → S6 → D3 → the other end of the second secondary winding SA2. Further, the capacitor C3 is discharged to the load 4 (system) in the path of C3 → S7 → 4 → S10.

Next, the reflux mode will be described with reference to FIGS. 1, 3 (c), and 3 (d).

The control circuit 10 turns on the second switch element S2 and the fourth switch element S4, and turns off the first switch element S1 and the seventh switch element S7 to the tenth switch element S10 in a half cycle of the gate signal. Then, the current ircc flows in the route of Vin → C1 → Ls → P → S2 → Vin. On the secondary side of the transformer T, the current idc flows in the path of one end of the first secondary winding SA1 → D1 → S4 → D3 → the other end of the first secondary winding SA1.

Next, the control circuit 10 turns on the first switch element S1 and the sixth switch element S6 in the next half cycle of the gate signal, and turns on the second switch element S2 and the seventh switch element S7 to the tenth switch element S10. Turn off. Then, the current ircc flows in the route of Vin → S1 → P → Ls → C2 → Vin. On the secondary side of the transformer T, the current idc flows in the path of one end of the second secondary winding SA2 → D2 → S6 → D3 → the other end of the second secondary winding SA2. That is, it becomes a return path of the current idc, and no current flows through the load 4 (system) and the capacitor C3.

Although only the operation mode when the system voltage is positive has been described, when the system voltage is negative, FIGS. 2 (a), 2 (b), 3 (a), and 3 (b) show. , The control circuit 10 turns off the 7th switch element S7 and the 10th switch element S10, and turns on the 8th switch element S8 and the 9th switch element S9. Other operations are the same as those when the system voltage is positive.

As described above, according to the DC / AC inverter according to the first embodiment, the DC / DC converter is composed of a half bridge circuit composed of switch elements S1 and S2 with respect to the conventional DC / AC inverter shown in FIG. Moreover, by deleting the diodes D11 to D14 and adding a high-frequency rectification operation to the active buffer circuit 2, the number of passing elements in the secondary circuit of the inverter is reduced, so that the circuit configuration can be simplified and the conduction loss is reduced. can do.

Further, by switching the secondary side rectifier circuit of the transformer, the direct delivery mode, the charge mode, the discharge mode, and the reflux mode can be realized, so that the capacity of the capacitor C3 can be reduced. Therefore, it is not necessary to use an electrolytic capacitor. Further, the power pulsation compensation can be realized by further adding the charge / discharge mode of the capacitor C3 to the direct delivery mode and the reflux mode to control the ratio of the charge / discharge operation.

Next, a detailed configuration of the control circuit 10 shown in FIG. 4 will be described. The control circuit 10 includes a Δ-ΣPDM unit 11, an active buffer switching table 12, and an inverter switching table 13.

The Δ-ΣPDM unit 11 contains a first converter gate signal for controlling the on / off of the first switch element S1 and the second switch element S2 of the DC / DC converter, and a first duty command value dmode1 for the direct delivery mode and the return mode. And the second duty command value dmode2 for the charge mode and the third duty command value dmode3 for the discharge mode are quantized using Δ-Σ conversion to generate three mode selection information Selmode1, Selmode2, and Selmode3. ..

FIG. 5 is a detailed configuration diagram of the Δ-ΣPDM unit 11. The Δ-ΣPDM unit 11 includes a ΔΣ modulator including subtractors 111a to 111c, integrators 112a to 112c, quantizers 113a to 113c, multipliers 114a to 114c, and delayers 115a to 115c. Further, the Δ-ΣPDM unit 11 has comparators 116 and 118 and inverters 117 and 119. ZOH is a zero-order hold.

The subtractor 111a obtains the difference between the second duty command value dmode2 and the output of the quantizer 113a from the delayer 115a, and the adder 112a integrates the output from the subtractor 111a and accumulates the quantization error. .. Next, the quantizer 113a outputs a quantization pulse whose output is switched to 1 or 0 based on the accumulation error to the multiplier 114a.

The subtractor 111b obtains the difference between the first duty command value dmode1 and the output of the quantizer 113b from the delayer 115b, and the adder 112b integrates the output from the subtractor 111b and accumulates the quantization error. .. Next, the quantizer 113b outputs a quantization pulse whose output is switched to 1 or 0 based on the accumulation error to the multiplier 114b.

The subtractor 111c obtains the difference between the third duty command value dmode3 and the output of the quantizer 113c from the delayer 115c, and the adder 112c integrates the output from the subtractor 111c and accumulates the quantization error. .. Next, the quantizer 113c outputs a quantization pulse whose output is switched to 1 or 0 based on the accumulation error to the multiplier 114c.

The accumulation error increases in proportion to the magnitude of the duty. The quantization interval corresponds to one cycle of the pulse current. Since the Δ-Σ conversion is only quantized, a switching pattern for turning each switch element on and off according to the original duty command value is generated.

Further, a mode selection unit that compares the quantization errors of the three integrators 112a to 112c, selects the integrator having the largest quantization error, and outputs mode selection information from the modulator having the selected integrator. It has. The mode selection unit includes comparators 116 and 118, inverters 117 and 119, and multipliers 114a to 114c.

Each mode is selectively output using the comparators 116 and 118. Specifically, the comparator 116 outputs 1 to the integrator 117 and the multiplier 114a when the output of the integrator 112a is equal to or greater than the output of the integrator 112b, and the output of the integrator 112a is less than the output of the integrator 112b. In the case, 0 is output to the integrator 117 and the multiplier 114a. The multiplier 114a multiplies the output of the comparator 116 and the output of the quantizer 113a and outputs the multiplication output as the mode selection information Sermode2. The inverter 117 inverts the output of the comparator 116 and outputs it to the multiplier 114b.

The comparator 118 outputs 1 to the integrator 119 and the multiplier 114b when the output of the integrator 112b is equal to or greater than the output of the integrator 112c, and 0 when the output of the integrator 112b is less than the output of the integrator 112c. Output to integrator 119 and multiplier 114b. The multiplier 114b multiplies the output of the comparator 118, the output of the quantizer 113b, and the output of the inverter 117, and outputs the multiplication output as the mode selection information Selfmode1. The inverter 119 inverts the output of the comparator 118 and outputs it to the multiplier 114c.

That is, since the accumulation error and the duty command value are proportional to each other, the output in the mode having the largest accumulation error is prioritized, and the other outputs are set to zero, so that the modulator can be made non-interfering. The mode not selected this time is accumulated as a quantization error and reflected in the next mode selection.

The active buffer switching table 12 has the first converter gate signal and the mode selection information from the Δ-Σ PDM unit 11 in the active buffer circuit 2 in synchronization with the polarity of the first converter gate signal based on the mode selection information Selmode1, Selmode2, and Selmode3. A gate signal composed of switching pulses for the three switch elements S3 to the sixth switch element S6 is generated.

The inverter switching table 13 sets the current inverter 3 in synchronization with the grid voltage polarity signal based on the grid voltage polarity signal from the load 4 (system) and the mode selection information Cellmode1, Celmode2, and Celmode3 from the Δ-ΣPDM unit 11. A gate signal composed of switching pulses for the 7th switch element S7 to the 10th switch element S10 to have is generated.

Further, the control circuit 10 determines the polarity of the high-frequency current using the control signal of the DC / DC converter, and selects two switch elements diagonal to the first full bridge circuit according to the determined polarity. Specifically, the active buffer switching table 12 of the third switch element S3 to the sixth switch element S6 of the active buffer circuit 2 according to the polarity of the first converter gate signal (corresponding to the control signal of the DC / DC converter). Since the gate signal for this is generated, the active buffer circuit 2 can perform high-frequency rectification operation by switching between two diagonal switch elements that operate according to the polarity of the primary current of the transformer T.

Further, since the current inverter 3 switches the leg (two diagonal switch elements of the second full bridge circuits S7 to S10) that operate according to the polarity of the system voltage with reference to the inverter switching table 13, it is commercially available. A sinusoidal current of frequency can be output to the system side.

Further, in the first embodiment, the zero currents of the first switch element S1 and the second switch element S2 of the half bridge circuit are resonated by resonating the capacitors C1 and C2 connected to the primary side with the reactor Ls which is the leakage inductance of the transformer. Since switching (ZCS) is performed, switching loss can be reduced. Therefore, the size of the device can be reduced and the efficiency can be improved.

FIG. 6 shows the drain-source voltage waveform Vs1 and the current waveform is1 of the first switch element S1 of the half-bridge circuit. FIG. 7 shows the drain-source voltage waveform Vs3 and the current waveform is3 of the third switch element S3 of the active buffer circuit 2, and the drain-source voltage waveform Vs7 and the current waveform is7 of the seventh switch element S7 of the current inverter 3. Shown.

From FIGS. 6 and 7, it can be seen that the ZCS operation is performed in each switch element because the drain-source voltage rises or falls near zero of the drain current. The ZCS operation is performed because the leakage inductance Ls of the transformer T and the series resonance of the capacitors C1 and C2 are applied to the primary side circuit, and Δ-ΣPDM is applied to the secondary side circuit.

FIG. 8 shows the waveforms of the input voltage Vin, the input current Iin, the capacitor voltage Vc, the system voltage Vac, and the inverter output current iac. By controlling the capacitor voltage Vc at twice the frequency of the system voltage Vac, the input voltage Vin does not generate a voltage ripple at a frequency twice the power supply frequency, and the single-phase power pulsation can be satisfactorily compensated.

FIG. 9 shows the efficiency of the output power of the DC / AC inverter. In the first embodiment, since ZCS is achieved in all the switch elements, the switching loss is not considered. Further, the loss of the transformer T and the output filters Lo and C4 is ignored. From FIG. 9, it can be seen that in the first embodiment, the efficiency can be improved as compared with the conventional circuit in all the output power regions. This is because the conduction loss is reduced as the number of passing elements in the secondary circuit is reduced. The efficiency at a rated output of 300 W was 96.9%, an improvement of 1.1%.

FIG. 10 shows the loss analysis result when the output power of the DC / AC inverter is 300 W. FIG. 10A is the circuit of the first embodiment, and FIG. 10B is the loss data of the conventional circuit. The circuit of the first embodiment can reduce the conduction loss by 25% as compared with the conventional circuit. It was also confirmed that the conduction loss of the DC / DC converter is dominant. This is because the primary side circuit operates at a low voltage and a large current. In particular, a low on-resistance element may be used for the MOSFET used in the primary circuit.

1 DC power supply 2 Active buffer circuit 3 Current inverter 4 AC power supply 10 Control circuit 11 Δ-Σ PDM unit 12 Active buffer switching table 13 Inverter switching table 111a to 111c Subtractors 112a to 112c Inverter 113a to 113c Quantizer 114a to 114c Multiplying Inverter 116, 118 Capacitors C1 to C4 Capacitors S1 to S10 1st switch element to 10th switch element T Transformer P Primary winding SA1 1st secondary winding SA2 2nd secondary winding Ls, L0 Reactor

Claims (6)

A DC / AC inverter that converts DC voltage to AC voltage.
A half-bridge circuit including a first switch element and a second switch element is provided, and the DC voltage is converted into an AC voltage by switching the first switch element and the second switch element, and the DC voltage is converted into an AC voltage via the primary winding of the transformer. DC / DC converter that outputs to the secondary winding
A first full-bridge circuit composed of a third switch element to a sixth switch element connected to the secondary winding, an active buffer circuit having buffer capacitors connected to both ends of the output of the first full-bridge circuit, and an active buffer circuit.
A current inverter having a second full bridge circuit composed of 7th switch elements to 10th switch elements, converting the voltage from the buffer capacitor into AC voltage and supplying it to the load.
A control circuit that controls on / off of each switch element of the first switch element to the tenth switch element, and
Equipped with a,
The control circuit has a first mode of supplying the output of the DC / DC converter to the load, a second mode of charging the buffer capacitor by the output of the DC / DC converter, an output of the DC / DC converter and the buffer. The third mode in which capacitors are connected in series and discharged to the load, and the fourth mode in which the output of the DC / DC converter does not act on the buffer capacitor are processed from the first mode to the fourth mode in order. On / off control of each switch element is performed.
The secondary winding consists of a series circuit of a first secondary winding and a second secondary winding.
The third switch element and the fourth switch element are connected to one end of the first secondary winding, and the fifth switch element and the sixth switch element are connected to one end of the second secondary winding.
In the first mode, the control circuit turns on the third switch element or the fifth switch element, and turns on two diagonal switch elements of the second full bridge circuit.
In the second mode, the third switch element or the fifth switch element is turned on, and all the switch elements of the second full bridge circuit are turned off.
In the third mode, the fourth switch element or the sixth switch element is turned on, and the two diagonal switch elements of the second full bridge circuit are turned on.
A DC / AC inverter characterized in that, in the fourth mode, the fourth switch element or the sixth switch element is turned on and all switch elements of the second full bridge circuit are turned off . The turn ratio between the first secondary winding and the second secondary winding, 1: DC / AC inverter according to claim 1, wherein the 1. A first rectifying element connected between one end of the first secondary winding and the fourth switch element,
A second rectifying element connected between one end of the second secondary winding and the sixth switch element,
The DC / AC inverter according to claim 1 or 2 , wherein the DC / AC inverter is provided. A connection point between the first secondary winding and a second secondary winding, according to claim 1 to claim 3, characterized in that it comprises a third rectifying element connected to the one end of the buffer capacitor The DC / AC inverter according to any one of the above. The control circuit has a first duty command value for the first mode and the fourth mode, a second duty command value for the second mode, and a third duty command value for the third mode. It is equipped with a Δ-Σ PDM unit that generates mode selection information by quantization using Δ-Σ conversion.
The Δ-ΣPDM unit is a modulation having a subtractor, an integrator, a quantizer, and a delay device connected to the output of the quantizer corresponding to the first duty command value to the third duty command value. Equipped with 3 sets of vessels,
In each modulator, the subtractor obtains the difference between the duty command value and the output of the quantizer from the delayer, and the integrator integrates the output from the subtractor to obtain a quantization error. 1 to claim 1 , wherein the quantization device outputs a quantization pulse whose output is switched to 1 or 0 based on an accumulation error from the integrator as the mode selection information. The DC / AC integrator according to any one of 4 . Mode selection in which the quantization errors of the three integrators are compared, the integrator having the largest quantization error is selected, and the mode selection information is output from the modulator having the selected integrator. The DC / AC inverter according to claim 5, further comprising a unit.

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