JP6772542B2 - Circuits, oscillators, electronics and mobiles - Google Patents

Description

The present invention relates to circuit devices, oscillators, electronic devices, mobile objects, and the like.

Conventionally, a temperature compensated crystal oscillator (TCXO) called a temperature compensated crystal oscillator has been known. This TCXO is used as a reference signal source in, for example, a mobile communication terminal, a GPS-related device, a wearable device, an in-vehicle device, or the like.

The TCXO includes an analog type temperature compensation type oscillator, ATCXO, and a digital type temperature compensation type oscillator, DTCXO. As a conventional technique of ATCXO, a technique disclosed in Patent Document 1 is known. As a conventional technique of DTCXO, a technique disclosed in Patent Document 2 is known.

Japanese Unexamined Patent Publication No. 2012-199631 Japanese Unexamined Patent Publication No. 64-82809

A digital oscillator such as DTCXO has an advantage in reducing power consumption and the like as compared with an analog oscillator such as ATCXO. For example, in ATCXO, a large amount of current is consumed in the analog circuit of the circuit device. Especially in ATCXO, in order to improve the frequency accuracy, if the order of the approximate function in the temperature compensation circuit (approximate function generation circuit) which is an analog circuit is increased, or the current flowing through the transistor of the analog circuit is increased to reduce the noise, Power consumption will increase significantly. Therefore, there is a problem that it is difficult to achieve both improvement of frequency accuracy and reduction of power consumption.

According to some aspects of the present invention, it is possible to provide a circuit device, an oscillator, an electronic device, a mobile body, or the like that can realize both improvement in frequency accuracy and low power consumption.

One aspect of the present invention is an A / D conversion unit that performs A / D conversion of the temperature detection voltage from the temperature sensor unit and outputs the temperature detection data, and a temperature compensation process of the oscillation frequency based on the temperature detection data. Oscillation that generates an oscillation signal of the oscillation frequency set by the frequency control data using the processing unit that outputs the frequency control data of the oscillation frequency and the frequency control data and the oscillator from the processing unit. The oscillation signal generation circuit includes a signal generation circuit, and the oscillation signal generation circuit includes a D / A conversion unit that performs D / A conversion of the frequency control data from the processing unit, and an output voltage and vibration of the D / A conversion unit. The D / A conversion unit receives the frequency control data of i = (n + m) bits from the processing unit, and includes an oscillation circuit that generates the oscillation signal using a child, and the m of the frequency control data. A modulation circuit that modulates the n-bit data of the frequency control data based on the bit data, a D / A converter that performs D / A conversion of the modulated n-bit data, and the D / A conversion. It relates to a circuit device including a filter circuit that smoothes the output voltage of the device.

According to one aspect of the present invention, simply by providing a modulation circuit or a filter circuit in the D / A conversion unit, a high resolution of i = (n + m) bits can be obtained while using a D / A converter having a resolution of, for example, n bits. A D / A conversion unit can be realized. By increasing the resolution of the D / A conversion unit that D / A-converts the frequency control data in this way, it is possible to improve the frequency accuracy of the oscillation signal generated based on the frequency control data. Further, the increase in power consumption due to the provision of such a modulation circuit or filter circuit is not so large. Further, it is not so difficult to supply, for example, i-bit frequency control data from the processing unit to the D / A conversion unit. Therefore, according to one aspect of the present invention, it is possible to provide a circuit device or the like that can realize both improvement in frequency accuracy and low power consumption.

Further, in one aspect of the present invention, when the sampling frequency of the D / A conversion unit is fs and the change in the oscillation frequency due to one D / A conversion of the D / A conversion unit is Δf, Δf / fs <1/10 ⁶ may be set.

In one aspect of the present invention, the sampling frequency fs of the D / A converter, the change Delta] f of the oscillation frequency by one of the D / A conversion of the D / A converter, satisfy Δf / fs <1/10 ^6. This makes it possible to suppress deterioration of C / N characteristics due to spurious caused by fluctuations in frequency control data.

Further, in one aspect of the present invention, when fs ≧ 1 kHz, Δf / fs <1/10 ⁶ may be set, and when fs <1 kHz, Δf <1 MHz may be set.

This makes it possible to use appropriate conditions according to fs in order to suppress deterioration of the C / N characteristics.

Further, in one aspect of the present invention, when the sampling frequency of the D / A conversion unit is fs and the change in the oscillation frequency due to one D / A conversion of the D / A conversion unit is Δf, fs <. In the case of 1 kHz, Δf <1 MHz may be used.

In one aspect of the present invention, the sampling frequency fs of the D / A conversion unit and the change Δf of the oscillation frequency due to one D / A conversion of the D / A conversion unit satisfy Δf <1 MHz when fs <1 kHz. .. This makes it possible to suppress deterioration of C / N characteristics due to spurious caused by fluctuations in frequency control data.

Further, in one aspect of the present invention, the oscillator may be a crystal oscillator.

This makes it possible to use a crystal oscillator as the oscillator.

Further, in one aspect of the present invention, the crystal oscillator may be an AT-cut oscillator, an SC-cut oscillator, or a SAW (Surface Acoustic Wave) resonator.

This makes it possible to use at least one of a plurality of oscillators (resonators) having different characteristics as the crystal oscillator.

Further, in one aspect of the present invention, the processing unit corresponds to the second temperature from the first data corresponding to the first temperature when the temperature changes from the first temperature to the second temperature. The frequency control data changing in units of k × LSB (k ≧ 1) may be output to the second data.

As a result, even when the temperature changes from the first temperature to the second temperature, the frequency control data that changes in k × LSB units is input from the processing unit to the D / A conversion unit. Become. Therefore, when the temperature changes from the first temperature to the second temperature, a large voltage change occurs in the output voltage of the D / A converter, and a problem caused by the voltage change occurs, which is an effect. Can be suppressed.

Further, in one aspect of the present invention, the processing unit uses the first data, which is the calculation result data of the previous temperature compensation process, and the second data, which is the calculation result data of the temperature compensation process this time. When the second data is larger than the first data, the process of adding a predetermined value to the first data is performed, and the addition result data is added to the second data. While performing until it reaches, the addition result data is output as the frequency control data, and when the second data is smaller than the first data, a predetermined value is subtracted from the first data. The subtraction result data may be output as the frequency control data while the subtraction result data reaches the second data.

As a result, the frequency control data can be changed in units of k × LSB by performing a process of adding a predetermined value to the first data or a process of subtracting a predetermined value from the first data. become.

Further, in one aspect of the present invention, the processing unit performs the calculation of the temperature compensation processing of the oscillation frequency based on the temperature detection data, and outputs the calculation result data of the temperature compensation processing, and the calculation unit. The output unit includes an output unit that receives the calculation result data from the unit and outputs the frequency control data, and the output unit is the first from the first data in which the calculation result data corresponds to the first temperature. When the data changes to the second data corresponding to the temperature of 2, the frequency control data that changes from the first data to the second data may be output in k × LSB units.

As a result, the temperature compensation processing of the oscillation frequency is realized by the arithmetic processing in the arithmetic unit. Then, when the calculation result data from the calculation unit changes from the first data to the second data, the output unit changes from the first data to the second data in k × LSB units. Is output. By doing so, when the temperature changes from the first temperature to the second temperature, the first data corresponding to the first temperature is changed to the second data corresponding to the second temperature. The frequency control data that changes in LSB units can be output from the processing unit.

Further, in one aspect of the present invention, the processing unit may output the frequency control data at an output rate faster than the output rate of the temperature detection data from the A / D conversion unit.

As a result, for example, within the A / D conversion period of the A / D conversion unit, the frequency control data can be sequentially changed in units of k × LSB.

Further, in one aspect of the present invention, the D / A conversion unit changes in the step width of the voltage corresponding to k × LSB (k ≧ 1) when the minimum resolution of the data in the D / A conversion is LSB. The output voltage may be output.

As a result, the change in the output voltage of the D / A conversion unit is limited to the step width of the voltage corresponding to k × LSB, so that the occurrence of a problem caused by a large voltage change in the output voltage is suppressed. become able to.

Further, in one aspect of the present invention, k = 1 may be set.

As a result, the output voltage of the D / A conversion unit can be changed by the step width of the voltage corresponding to 1 LSB.

Further, another aspect of the present invention relates to an oscillator including the circuit device according to any one of the above and the oscillator.

Further, another aspect of the present invention relates to an electronic device including the circuit device according to any one of the above.

Further, another aspect of the present invention relates to a mobile body including the circuit device according to any one of the above.

Relationship diagram between frequency accuracy and chip size. The figure which shows the frequency drift of ATCXO The figure which shows the frequency drift of the conventional DTCXO. A basic configuration example of the circuit device of this embodiment. A detailed configuration example of the circuit device of this embodiment. The figure which shows the temperature characteristic of an oscillator and an example of the variation. The explanatory view of the temperature compensation process of this embodiment. Explanatory drawing of communication error caused by frequency drift. The explanatory view about the change of the frequency control voltage when changing from the 1st temperature to the 2nd temperature. The explanatory view about the change of the frequency control voltage when changing from the 1st temperature to the 2nd temperature. Explanatory drawing of the method of this embodiment. Explanatory drawing of the method of this embodiment. Explanatory drawing of the method of this embodiment. Explanatory drawing about frequency hopping. Explanatory drawing of improvement of frequency drift when the method of this embodiment is adopted. The explanatory view of the relationship between the C / N characteristic of an oscillator and the spurious which deteriorates the C / N characteristic. The figure which shows the characteristic example of spurious according to Δf and fs. The figure which shows the setting example of Δf and fs which does not deteriorate the C / N characteristic. Explanatory drawing of the method of changing the setting of Δf and fs in time series. Detailed configuration example of the processing unit. The explanatory view of the method of changing the frequency control data in k × LSB units. The explanatory view of the method of changing the frequency control data in k × LSB units. A detailed configuration example of the D / A conversion unit. A more detailed configuration example of the D / A conversion unit. Explanatory drawing of PWM modulation. Explanatory drawing of PWM modulation. Explanatory drawing of PWM modulation. Detailed configuration example of the temperature sensor unit. Detailed configuration example of the temperature sensor unit. Explanatory drawing of the temperature sensor part. Detailed configuration example of the oscillation circuit. The explanatory view of the modification of this embodiment. The explanatory view of the modification of this embodiment. The explanatory view of the modification of this embodiment. The figure which shows the frequency drift in the modification. The figure which shows the frequency drift in the modification. The figure which shows the frequency drift in the modification. A detailed configuration example of the A / D conversion unit. Oscillator configuration example. Configuration example of electronic equipment. Configuration example of a moving body.

Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all of the configurations described in the present embodiment are indispensable as a means for solving the present invention. Not necessarily.

1. 1. Frequency drift In TCXO, which is a temperature-compensated oscillator, there is a demand for improved frequency accuracy and lower power consumption. For example, in a wearable device such as a clock with a built-in GPS or a device for measuring biological information such as a pulse wave, it is necessary to lengthen the operation duration by the battery. Therefore, the TCXO, which is the reference signal source, is required to have lower power consumption while ensuring frequency accuracy.

Further, various methods have been proposed as communication methods between the communication terminal and the base station. For example, in the TDD (Time Division Duplex) system, each device transmits data in an assigned time slot. Then, by setting a guard time between the time slots (up line slot, down line slot), it is possible to prevent the time slots from overlapping. In next-generation communication systems, it has been proposed to carry out data communication in a TDD manner, for example, using one frequency band (for example, 50 GHz).

However, when such a TDD method is adopted, it is necessary to synchronize the time in each device, and accurate absolute time timing is required. In order to meet such demands, for example, a method of providing an atomic clock (atomic oscillator) as a reference signal source in each device can be considered, but there are problems such as an increase in the cost of the device and an increase in the size of the device. Occurs.

Further, TCXO includes ATCXO which is an analog type temperature compensation type oscillator and DTCXO which is a digital type temperature compensation type oscillator.

When ATCXO is used as the reference signal source, if an attempt is made to improve the frequency accuracy, the chip size of the circuit device increases as shown in FIG. 1, and cost reduction and power consumption reduction can be realized. It gets harder.

On the other hand, DTCXO has an advantage that high frequency accuracy can be realized without increasing the chip size of the circuit device so much, as shown in FIG.

However, in a digital oscillator such as DTCXO, there is a problem that a communication error or the like occurs in a communication device incorporating the oscillator due to frequency drift of the oscillation frequency. For example, in a digital oscillator, the temperature detection voltage from the temperature sensor unit is A / D converted, the temperature compensation processing of the frequency control data is performed based on the obtained temperature detection data, and the oscillation signal is based on the frequency control data. To generate. In this case, it has been found that if the value of the frequency control data changes significantly due to the temperature change, the problem of frequency hopping occurs due to this. When such frequency hopping occurs, in the case of a GPS-related communication device as an example, a problem such as unlocking of GPS occurs.

For this reason, although various circuit methods have been proposed for digital oscillators such as DTCXO, most digital oscillators are used as reference signal sources for actual products in which such communication errors pose a problem. However, the current situation is that analog oscillators such as ATCXO are used.

For example, FIG. 2 is a diagram showing the frequency drift of ATCXO. In ATCXO, even when the temperature changes with the passage of time as shown in FIG. 2, the frequency drift is within the range (± FD) of the allowable frequency drift (allowable frequency error). In FIG. 2, the frequency drift (frequency error) is shown as a ratio (frequency accuracy. Pppb) to the nominal oscillation frequency (for example, about 16 MHz). For example, in order to prevent a communication error from occurring, it is necessary to keep the frequency drift within the allowable frequency drift range (± FD) within a predetermined period TP (for example, 20 msec). Here, the FD is, for example, about several ppb.

On the other hand, FIG. 3 is a diagram showing a frequency drift when a conventional DTCXO is used. As shown in FIG. 3, in the conventional DTCXO, the frequency drift does not fall within the allowable frequency drift range, and frequency hopping occurs in which the frequency drift exceeds the allowable frequency drift range. For this reason, a communication error (GPS unlocked, etc.) caused by this frequency hopping occurs, which hinders the adoption of DTCXO as a reference signal source for an actual product.

Further, it is known that the oscillator generates phase noise according to the characteristics of the oscillator. D1 of FIG. 16 described later is an example of general C / N characteristics of a crystal oscillator, and the intensity of phase noise (vertical axis, unit dBc / Hz) is the detuning frequency (horizontal axis, unit Hz) with respect to the oscillation frequency. ) Is low, it is inversely proportional to the cube of the detuning frequency f, and in the range of about 1k to 10kHz, it is inversely proportional to the square of f. In the frequency range of 10 kHz or less, the influence of so-called 1 / f noise is large. On the other hand, at frequencies higher than 10 kHz, the influence of thermal noise is large, and the characteristics are flat and do not depend on f. That is, it is inevitable that a signal having a frequency other than the desired oscillation frequency is generated due to the characteristics of the oscillator, and an oscillator such as DTCXO (and a circuit device including the oscillator) has a C / N characteristic such as D1. The design is such that there is no problem even if phase noise occurs.

However, in DTCXO, spurious intensity is generated according to the output frequency fs of the data for controlling the oscillation frequency (frequency control data DDS) and the change Δf of the oscillation frequency. The details will be described later using the following equation (10) and the like, but the generated spurious has a detuning frequency of fs with respect to the fundamental wave (oscillation frequency) and a value corresponding to (Δf / fs) ² of the intensity. Then, depending on the values of fs and Δf, there is a possibility that spurious emissions having a higher intensity than the original phase noise of the oscillator shown in D1 may occur. D2 in FIG. 16 is an example of spurious when Δf = 0.1 Hz and fs = 100 kHz, and D3 is an example of spurious when Δf = 0.1 Hz and fs = 600 kHz. Both the spurious of D2 and D3 have higher intensity than the original phase noise (D1) of the oscillator.

When spurious as shown in D2 and D3 is generated, the signal strength at a frequency different from the desired oscillation frequency becomes relatively large, and the C / N characteristic of the oscillator 400 deteriorates. Deterioration of C / N characteristics leads to deterioration of accuracy of data acquired by using an oscillation signal. For example, in the case of the above GPS example, the accuracy of the GPS received signal is lowered, and specifically, the accuracy of the position information obtained from the GPS received signal is lowered. As described above, the generation of spurious in response to the frequency fluctuation also hinders the adoption of DTCXO as the reference signal source of the actual product. The spurious shown in D2 and D3 of FIG. 16 deteriorates the C / N characteristics when the strength is not reduced. Therefore, if noise reduction processing that reduces the spurious intensity, such as smoothing by a filter circuit, is performed, it is prevented from adopting the values of Δf and fs corresponding to D2 and D3 in the method of the present embodiment. Absent. Details will be described later.

2. Configuration Figure 4 shows a basic configuration example of the circuit device of this embodiment. This circuit device is a circuit device (semiconductor chip) that realizes a digital oscillator such as DTCXO or OCXO. For example, by housing this circuit device and the oscillator XTAL in a package, a digital oscillator can be realized.

The circuit device of FIG. 4 includes an A / D conversion unit 20, a processing unit 50, and an oscillation signal generation circuit 140. Further, the circuit device can include a temperature sensor unit 10 and a buffer circuit 160. The configuration of the circuit device is not limited to the configuration shown in FIG. 4, and some components (for example, temperature sensor unit, buffer circuit, A / D conversion unit, etc.) may be omitted or other components may be added. It is possible to carry out various modifications such as.

The oscillator XTAL is a piezoelectric oscillator such as a crystal oscillator. The oscillator XTAL may be an oven-type oscillator (OCXO) provided in a constant temperature bath. The oscillator XTAL may be a resonator (electromechanical resonator or electrical resonance circuit). As the oscillator XTAL, a piezoelectric oscillator, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) oscillator, or the like can be adopted. As the substrate material of the transducer XTAL, a piezoelectric single crystal such as crystal, lithium tantalate, lithium niobate or the like, a piezoelectric material such as piezoelectric ceramics such as lead zirconate titanate, or a silicon semiconductor material can be used. As the exciting means of the oscillator XTAL, one by a piezoelectric effect may be used, or electrostatic drive by a Coulomb force may be used.

The temperature sensor unit 10 outputs the temperature detection voltage VTD. Specifically, a temperature-dependent voltage that changes according to the temperature of the environment (circuit device) is output as the temperature detection voltage VTD. A specific configuration example of the temperature sensor unit 10 will be described later.

The A / D conversion unit 20 performs A / D conversion of the temperature detection voltage VTD from the temperature sensor unit 10 and outputs the temperature detection data DTD. For example, the digital temperature detection data DTD (A / D result data) corresponding to the A / D conversion result of the temperature detection voltage VTD is output. As the A / D conversion method of the A / D conversion unit 20, for example, a sequential comparison method or a method similar to the sequential comparison method can be adopted. The A / D conversion method is not limited to such a method, and various methods (counting type, parallel comparison type, series-parallel type, etc.) can be adopted.

The processing unit 50 (DSP unit: digital signal processing unit) performs various signal processing. For example, the processing unit 50 (temperature compensation unit) performs temperature compensation processing for the oscillation frequency (frequency of the oscillation signal) based on the temperature detection data DTD. Then, the frequency control data DDS of the oscillation frequency is output. Specifically, the processing unit 50 has a temperature change based on the temperature detection data DTD (temperature-dependent data) that changes according to the temperature and the coefficient data (data of the coefficient of the approximation function) for the temperature compensation processing. Even in such a case, temperature compensation processing is performed to keep the oscillation frequency constant. The processing unit 50 may be realized by an ASIC circuit such as a gate array, or may be realized by a processor and a program operating on the processor.

The oscillation signal generation circuit 140 generates an oscillation signal SSC. For example, the oscillation signal generation circuit 140 uses the frequency control data DDS from the processing unit 50 and the oscillator XTAL to generate an oscillation signal SSC having an oscillation frequency set by the frequency control data DDS. As an example, the oscillation signal generation circuit 140 oscillates the oscillator XTAL at the oscillation frequency set by the frequency control data DDS to generate the oscillation signal SSC.

The oscillation signal generation circuit 140 may be a circuit that generates an oscillation signal SSC by a direct digital synthesizer method. For example, the oscillation signal SSC of the oscillation frequency set in the frequency control data DDS may be digitally generated by using the oscillation signal of the oscillator XTAL (oscillation source of the fixed oscillation frequency) as a reference signal.

The oscillation signal generation circuit 140 can include a D / A conversion unit 80 and an oscillation circuit 150. However, the oscillation signal generation circuit 140 is not limited to such a configuration, and various modifications such as omitting some of the components or adding other components can be performed.

The D / A conversion unit 80 performs D / A conversion of the frequency control data DDS (output data of the processing unit) from the processing unit 50. The frequency control data DDS input to the D / A conversion unit 80 is frequency control data (frequency control code) after the temperature compensation processing by the processing unit 50. As the D / A conversion method of the D / A conversion unit 80, for example, a resistance string type (resistor division type) can be adopted. However, the D / A conversion method is not limited to this, and various methods such as a resistance ladder type (R-2R ladder type, etc.), a capacitance array type, and a pulse width modulation type can be adopted. Further, the D / A conversion unit 80 can include a control circuit, a modulation circuit, a filter circuit, and the like in addition to the D / A converter.

The oscillation circuit 150 generates an oscillation signal SSC by using the output voltage VQ of the D / A conversion unit 80 and the oscillator XTAL. The oscillation circuit 150 is connected to the oscillator XTAL via the first and second oscillator terminals (oscillator pads). For example, the oscillation circuit 150 generates an oscillation signal SSC by oscillating an oscillator XTAL (piezoelectric oscillator, resonator, etc.). Specifically, the oscillation circuit 150 oscillates the oscillator XTAL at an oscillation frequency in which the output voltage VQ of the D / A conversion unit 80 is a frequency control voltage (oscillation control voltage). For example, when the oscillation circuit 150 is a circuit (VCO) that controls the oscillation of the oscillator XTAL by voltage control, the oscillation circuit 150 is a variable capacitance capacitor (varicap or the like) whose capacitance value changes according to the frequency control voltage. ) Can be included.

As described above, the oscillation circuit 150 may be realized by the direct digital synthesizer method. In this case, the oscillation frequency of the oscillator XTAL becomes the reference frequency, which is different from the oscillation frequency of the oscillation signal SSC. ..

The buffer circuit 160 buffers the oscillation signal SSC generated by the oscillation signal generation circuit 140 (oscillation circuit 150), and outputs the buffered signal SQ. That is, buffering is performed so that the external load can be sufficiently driven. The signal SQ is, for example, a clipped sine wave signal. However, the signal SQ may be a rectangular wave signal. Alternatively, the buffer circuit 160 may be a circuit capable of outputting both a clipped sine wave signal and a square wave signal as the signal SQ.

FIG. 5 shows a detailed configuration example of the circuit device of the present embodiment. In FIG. 5, the D / A conversion unit 80 includes a modulation circuit 90, a D / A converter 100, and a filter circuit 120.

The modulation circuit 90 of the D / A conversion unit 80 receives i = (n + m) bit frequency control data DDS from the processing unit 50 (i, n, m are integers of 1 or more). As an example, i = 20, n = 16, m = 4. Then, the modulation circuit 90 modulates the n-bit (for example, 16-bit) data of the frequency control data DDS based on the m-bit (for example, 4 bits) data of the frequency control data DDS. Specifically, the modulation circuit 90 performs PWM modulation of the frequency control data DDS. The modulation method of the modulation circuit 90 is not limited to PWM modulation (pulse width modulation), and may be pulse modulation such as PDM modulation (pulse density modulation) or a modulation method other than pulse modulation. .. For example, bit expansion (bit expansion from n bits to i bits) may be realized by performing m-bit dither processing (dithering processing) on n-bit data of frequency control data DDS.

The D / A converter 100 performs D / A conversion of n-bit data modulated by the modulation circuit 90. For example, D / A conversion of n = 16-bit data is performed. As the D / A conversion method of the D / A converter 100, for example, a resistance string type or a resistance ladder type can be adopted.

The filter circuit 120 smoothes the output voltage VDA of the D / A converter 100. For example, a low-pass filter process is performed to smooth the output voltage VDA. By providing such a filter circuit 120, for example, PWM demodulation of a PWM-modulated signal becomes possible. The cutoff frequency of the filter circuit 120 can be set according to the PWM modulation frequency of the modulation circuit 90. That is, since the signal of the output voltage VDA from the D / A converter 100 includes the fundamental frequency of PWM modulation and the ripple of the harmonic component, the filter circuit 120 attenuates this ripple. As the filter circuit 120, for example, a passive filter using a passive element such as a resistor or a capacitor can be adopted. However, it is also possible to use an active filter such as SCF as the filter circuit 120.

As will be described later, in order to suppress the occurrence of communication errors caused by the frequency hopping described in FIG. 3 and improve the frequency accuracy, it is necessary to increase the resolution of the D / A conversion unit 80 as much as possible. ..

However, it is difficult to realize high-resolution D / A conversion such as i = 20 bits only with a D / A converter 100 such as a resistance string type. Further, if the output noise of the D / A conversion unit 80 is large, it becomes difficult to improve the frequency accuracy due to the noise.

Therefore, in FIG. 5, a modulation circuit 90 is provided in the D / A conversion unit 80. Further, the processing unit 50 outputs the frequency control data DDS of i = m + n bits, which has a larger number of bits than the n bits (for example, 16 bits) which is the resolution of the D / A converter 100. Since the processing unit 50 performs floating-point arithmetic or the like in order to realize digital signal processing such as temperature compensation processing, i = has a larger number of bits than such n bits (for example, n = 16 bits). It is easy to output m + n-bit frequency control data DDS.

Then, the modulation circuit 90 modulates the n-bit data of i = m + n (PWM modulation or the like) based on the m-bit data of i = m + n, and D the modulated n-bit data DM. Output to / A converter 100. Then, the D / A converter 100 performs D / A conversion of the data DM, and the filter circuit 120 performs the smoothing process of the obtained output voltage VDA, so that the high i = m + n bits (for example, 20 bits) is obtained. It becomes possible to realize D / A conversion with resolution.

According to this configuration, for example, a resistance string type having less output noise can be adopted as the D / A converter 100, so that the output noise of the D / A converter 80 can be reduced and the deterioration of frequency accuracy can be easily suppressed. .. For example, noise is generated by modulation in the modulation circuit 90, but the noise can also be sufficiently attenuated by setting the cutoff frequency of the filter circuit 120, and deterioration of frequency accuracy caused by the noise can be suppressed. ..

The resolution of the D / A conversion unit 80 is not limited to i = 20 bits, and may be higher than 20 bits or lower. Further, the number of modulation bits of the modulation circuit 90 is not limited to m = 4 bits, and may be larger than 4 bits (for example, m = 8 bits) or smaller.

Further, in FIG. 5, it is effectively utilized that the processing unit 50 that performs digital signal processing such as temperature compensation processing is provided in front of the D / A conversion unit 80. That is, the processing unit 50 executes digital signal processing such as temperature compensation processing with high accuracy by, for example, floating-point arithmetic. Therefore, for example, if the lower bits of the mantissa part of the result of floating-point arithmetic are treated as valid data and converted to binary data, the frequency control data DDS with a high bit number such as i = m + n = 20 bits can also be obtained. It can be output easily. Focusing on this point in FIG. 5, the frequency control data DDS of i = m + n bits having such a high number of bits is supplied to the D / A conversion unit 80, and the m-bit modulation circuit 90 and the n-bit D / Using the A converter 100, we have succeeded in realizing high-resolution D / A conversion such as i = m + n bits.

By increasing the resolution of the D / A conversion unit 80 to a high resolution in this way, the occurrence of the frequency hopping described above can be suppressed. This makes it possible to suppress the occurrence of communication errors and the like caused by frequency hopping.

In addition to the problem of frequency hopping, digital oscillators such as DTCXO and OCXO are required to have extremely high frequency accuracy with respect to the oscillation frequency. For example, in the above-mentioned TDD system, data is transmitted and received in time division using the same frequency for uplink and downlink, and a guard time is set between the time slots assigned to each device. Therefore, in order to realize proper communication, it is necessary to synchronize the time in each device, and accurate absolute time timing is required. For example, when a reference signal (GPS signal or signal via the Internet) disappears or an abnormal holdover occurs, it is necessary for the oscillator side to accurately time the absolute time in the absence of the reference signal. Therefore, oscillators used in such devices (GPS-related devices, base stations, etc.) are required to have extremely high oscillation frequency accuracy.

If, for example, a method of providing an atomic clock or the like in each device is adopted in order to realize such a requirement, the cost and scale of the device will be increased. Further, even if an oscillator having high frequency accuracy is realized, it is not desirable that the circuit device used for the oscillator becomes large-scale or the power consumption becomes very large.

In this regard, according to the configuration of the circuit device of FIG. 5, the D / A conversion unit 80 has a very high resolution of D /, for example, i ≧ 20 bits, simply by providing the modulation circuit 90 and the filter circuit 120. The A conversion unit 80 can be realized, and by increasing the resolution in this way, it is possible to realize high accuracy of the oscillation frequency. The increase in the chip size and the increase in power consumption of the circuit device due to the provision of the modulation circuit 90 and the filter circuit 120 are not so large. Further, since the processing unit 50 executes the temperature compensation processing by floating point arithmetic or the like, it is easy to output the frequency control data DDS such that i ≧ 20 bits to the D / A conversion unit 80. Therefore, the configuration of the circuit device of FIG. 5 has an advantage that high accuracy of the oscillation frequency and suppression of an increase in the scale and power consumption of the circuit device can be realized at the same time.

The circuit devices of FIGS. 4 and 5 can also be used as an oscillation IC in a PLL circuit having a phase comparison circuit for comparing an input signal based on a reference signal (GPS signal or a signal via the Internet) and an oscillation signal. it can. In this case, for example, the processing unit 50 may perform temperature compensation processing, aging correction processing, or the like on the frequency control data from the phase comparison circuit, and the oscillation signal generation circuit 140 may generate an oscillation signal.

Further, when the temperature changes from the first temperature to the second temperature, the processing unit 50 starts with the second temperature (second temperature) from the first data corresponding to the first temperature (first temperature detection data). The frequency control data DDS that changes in k × LSB units (changes in k × LSB increments) is output to the second data corresponding to (2) temperature detection data). Here, k ≧ 1, and k is an integer of 1 or more. For example, when the number of bits of the frequency control data DDS (resolution of the D / A conversion unit) is i, k <2 ⁱ , and k is an integer sufficiently smaller than 2 ⁱ (for example, k = 1 to 8). ). More specifically, k <2 ^m . For example, when k = 1, the processing unit 50 outputs the frequency control data DDS that changes from the first data to the second data in 1LSB units (1 bit units). That is, the frequency control data DDS that changes while shifting by 1 LSB (1 bit) from the first data to the second data is output. The change step width of the frequency control data DDS is not limited to 1LSB, and may be a change step width of 2 × LSB or more, for example, 2 × LSB, 3 × LSB, 4 × LSB, and so on.

For example, the processing unit 50 includes a calculation unit 60 and an output unit 70. The calculation unit 60 calculates the temperature compensation processing of the oscillation frequency based on the temperature detection data DTD. For example, temperature compensation processing is realized by digital signal processing such as floating point arithmetic. The output unit 70 receives the calculation result data CQ from the calculation unit 60 and outputs the frequency control data DDS. Then, when the calculation result data CQ changes from the first data corresponding to the first temperature to the second data corresponding to the second temperature, the output unit 70 makes the first in k × LSB units. The output processing of the frequency control data DDS that changes from the above data to the second data is performed.

In this way, if the frequency control data DDS output from the processing unit 50 changes by k × LSB, for example, when the temperature changes from the first temperature to the second temperature, D / A conversion is performed. It is possible to suppress a situation in which a large voltage change occurs in the output voltage VQ of the unit 80 and the frequency hopping of FIG. 3 occurs due to this voltage change. This makes it possible to prevent a communication error or the like from occurring due to the frequency hopping.

More specifically, the processing unit 50 uses the first data, which is the calculation result data (CQ) of the previous (previous timing) temperature compensation process, and the calculation result data of the temperature compensation process of this time (current timing). Compare some second data.

Then, when the second data is larger than the first data, the processing unit 50 (output unit 70) performs a process of adding a predetermined value to the first data. For example, a process of adding k × LSB as a predetermined value is performed. For example, when k = 1, a process of adding 1 LSB as a predetermined value is performed. The predetermined value to be added is not limited to 1LSB, and may be 2 × LSB or more. Then, the processing unit 50 outputs the addition result data as frequency control data DDS while performing the addition processing until the addition result data reaches the second data, for example.

On the other hand, when the second data corresponding to the second temperature is smaller than the first data corresponding to the first temperature, the processing unit 50 (output unit 70) starts from the first data. Performs a process of subtracting a predetermined value. For example, a process of subtracting k × LSB as a predetermined value is performed. For example, when k = 1, a process of subtracting 1 LSB as a predetermined value is performed. The predetermined value to be subtracted is not limited to 1LSB, and may be 2 × LSB or more. Then, the processing unit 50 outputs the subtraction result data as frequency control data DDS while performing this subtraction processing until the subtraction result data reaches the second data, for example.

In this way, if the process of adding a predetermined value to the first data or subtracting the predetermined value from the first data is performed, if the frequency control data DDS is output, the calculation result data of the temperature compensation process will be obtained. When the first data corresponding to the first temperature is changed to the second data corresponding to the second temperature, for example, from the first data to the second data in k × LSB units corresponding to a predetermined value. It becomes possible to output the changing frequency control data DDS.

Further, the processing unit 50 (output unit 70) performs output processing of frequency control data DDS that changes in units of k × LSB in the first mode (normal mode). As a result, it is possible to suppress the occurrence of communication errors and the like caused by frequency hopping.

On the other hand, in the second mode (high-speed mode), the processing unit 50 outputs the calculation result data of the temperature compensation processing as the frequency control data DDS without performing the output processing of the frequency control data DDS that changes in units of k × LSB. To do. Specifically, the calculation result data CQ from the calculation unit 60 is output as frequency control data DDS. By doing so, the frequency control data DDS that changes at a higher speed than the first mode can be supplied to the D / A conversion unit 80, and the high-speed mode can be realized.

The first mode is set during normal operation (normal operation period) of the circuit device. On the other hand, the second mode is set, for example, at the time of starting (starting period) or inspection (testing period) of the circuit device. That is, the circuit device is set to the second mode during operations other than normal operation.

For example, in the normal operation of the circuit device, the processing unit 50 outputs the frequency control data DDS that changes in units of k × LSB by being set to the first mode. As a result, problems such as frequency hopping can be prevented, and the accuracy of the oscillation frequency can be improved.

On the other hand, at the time of starting up or inspecting the circuit device, by setting to the second mode, the process of changing the frequency control data DDS in units of k × LSB is not performed, and the calculation result data from the calculation unit 60 is not performed. CQ will be output as frequency control data DDS as it is. As a result, the start-up time of the circuit device can be shortened, and the circuit device can be started at high speed. In addition, the inspection period (test period) at the time of manufacturing a circuit device or an oscillator can be shortened, and the manufacturing period can be shortened.

Further, in the present embodiment, the processing unit 50 outputs the frequency control data DDS at an output rate faster than the output rate of the temperature detection data DTD from the A / D conversion unit 20. By doing so, it becomes possible to output the frequency control data DDS that changes from the first data to the second data in units of k × LSB. For example, within the period corresponding to the A / D conversion period, the frequency control data DDS can be changed stepwise by k × LSB.

FIG. 6 is a diagram showing an example of the frequency deviation of the oscillation frequency due to the temperature of the oscillator XTAL (AT oscillator or the like). The processing unit 50 performs temperature compensation processing for making the oscillation frequency of the vibrator XTAL having the temperature characteristics as shown in FIG. 6 constant regardless of the temperature.

Specifically, in the processing unit 50, the output data (temperature detection data) of the A / D conversion unit 20 and the input data (frequency control data) of the D / A conversion unit 80 have a correspondence relationship as shown in FIG. Such temperature compensation processing is performed. The correspondence (frequency correction table) in FIG. 7 shows, for example, that an oscillator incorporating a circuit device is placed in a constant temperature bath, and the input data (DDS) of the D / A conversion unit 80 and the A / D conversion unit 20 at each temperature. It can be acquired by a method such as monitoring the output data (DTD).

Then, the coefficient data of the approximate function for temperature compensation for realizing the correspondence relationship in FIG. 7 is stored in the memory unit (nonvolatile memory) of the circuit device. Then, the processing unit 50 performs arithmetic processing based on the coefficient data read from the memory unit and the temperature detection data DTD from the A / D conversion unit 20, so that the oscillation frequency of the oscillator XTAL is set to the temperature. Realize temperature compensation processing to make it constant regardless.

The temperature detection voltage VTD of the temperature sensor unit 10 has, for example, a negative temperature characteristic as described later. Therefore, with the temperature compensation characteristics as shown in FIG. 7, the temperature dependence of the oscillation frequency of the oscillator XTAL of FIG. 6 can be offset and compensated.

3. 3. Method of this embodiment Next, the details of the method of this embodiment will be described. First, a GPS (Global Positioning System) communication error caused by frequency hopping will be described with reference to FIG. Further, the C / N characteristics and spurious of the oscillator 400 will be described with reference to FIGS. 16 to 19.

3.1 Frequency hopping GPS satellites include information on satellite orbits, time, etc. in the navigation message shown in FIG. 8 and transmit them as GPS satellite signals at a data rate of 50 bps. Therefore, the length of one bit is 20 msec (20 cycles of the PN code). One navigation message is composed of one master frame, and one master frame is composed of 25 frames consisting of 1500 bits.

As shown in FIG. 8, the GPS satellite signal is modulated by the BPSK modulation method according to the bit value of the navigation message. Specifically, the navigation message is multiplied by a PN code (pseudo-random code) to perform spread spectrum, and the signal after spread spectrum is multiplied by a carrier wave (1575.42 MHz) to perform BPSK modulation. Will be. In FIG. 8, the PN code of the B1 part of the navigation message is shown, and the carrier wave of the B2 part of the PN code is shown. At the timing when the logic level of the PN code changes, the carrier wave is phase-inverted as shown in B3. The period of one wavelength of the carrier wave is about 0.635 ns. The GPS receiver receives the carrier wave of the navigation message modulated by the BPSK modulation method, and acquires the navigation message by performing demodulation processing of the received signal of the carrier wave.

If the residual frequency with the carrier frequency (1575.42 MHz) is not kept within 4 Hz / 20 msec during the demodulation process of such a received signal, an erroneous determination will occur in the demodulation process. That is, in TP = 20 msec, which is a period of 1 bit length of the GPS navigation message (cycle of the GPS navigation message), if the residual frequency with the frequency of the carrier wave is not kept within 4 Hz, a communication error due to frequency hopping will occur. ..

Since the ratio of the above 4 Hz to the carrier frequency of 1575.42 MHz is about several ppb, the FD which is the allowable drift frequency shown in FIGS. 2 and 3 is also about several ppb.

For example, in a GPS receiver, the frequency of the carrier wave in the demodulation process is set by the oscillation signal generated by the circuit device (oscillator) of the present embodiment. Therefore, it is necessary to keep the frequency drift of the oscillation frequency of the oscillation signal within ± FD at TP = 20 msec. By doing so, it is possible to prevent the occurrence of erroneous determination in the demodulation process of the received signal of the GPS satellite signal, and it is possible to avoid the occurrence of a communication error (reception error).

However, in the conventional digital oscillator such as DTCXO, the frequency drift is not suppressed within ± FD (about several ppb) in the period TP (20 msec). Therefore, there is a problem that a communication error occurs due to an erroneous determination of the demodulation process due to the frequency hopping as shown in FIG.

Therefore, in the present embodiment, the problem of frequency hopping is solved by adopting the methods described in FIGS. 9 to 13 and the like.

In FIG. 9, the frequency control voltage corresponding to the first temperature T1 is defined as the first control voltage VC1. Further, the frequency control voltage corresponding to the second temperature T2 is defined as the second control voltage VC2. This frequency control voltage (oscillation control voltage) is the frequency control voltage of the oscillation circuit 150 of FIGS. 4 and 5, and corresponds to, for example, the output voltage VQ of the D / A conversion unit 80. The first and second temperatures T1 and T2 are the temperatures detected by the temperature sensor unit 10, and correspond to the temperature detection data DTD from the A / D conversion unit 20.

For example, the temperature detection data DTD of the A / D conversion unit 20 when the temperature is the first temperature T1 is referred to as the first temperature detection data DTD1. The temperature detection data DTD of the A / D conversion unit 20 when the temperature is the second temperature T2 is referred to as the second temperature detection data DTD2.

In this case, the first control voltage VC1 in FIG. 9 is the frequency control voltage corresponding to the first temperature detection data DTD1 in the temperature compensation characteristics described in FIG. 7. Further, the second control voltage VC2 becomes a frequency control voltage corresponding to the second temperature detection data DTD2 in the above temperature compensation characteristics.

Note that, for convenience, FIG. 9 assumes a case where the frequency control voltage increases as the temperature increases. That is, as is clear from FIGS. 6 and 7, there is a temperature range in which the frequency control voltage increases and a temperature range in which the frequency control voltage decreases when the temperature rises, but here, in the former case. Will be explained.

As shown in FIG. 10, when the temperature changes from the first temperature T1 to the second temperature T2, the difference voltage between the first control voltage VC1 and the second control voltage VC2 becomes VDF. Therefore, if no measures are taken, the output voltage VQ of the D / A conversion unit 80 changes from VC1 to VC2 when the temperature changes from the first temperature T1 to the second temperature T2. That is, the output voltage VQ of the D / A conversion unit 80 changes depending on the step width of the differential voltage VDF.

That is, as described above, the first control voltage VC1 is the frequency control voltage corresponding to the first temperature detection data DTD1 in the temperature compensation characteristic of FIG. 7, and the second control voltage VC2 is the second temperature. It is a frequency control voltage corresponding to the detection data DTD2. Therefore, normally, the D / A conversion unit 80 outputs the first control voltage VC1, which is the frequency control voltage corresponding to the first temperature detection data DTD1, at the first temperature T1, and the second. At the temperature T2, the second control voltage VC2, which is the frequency control voltage corresponding to the second temperature detection data DTD2, is output. Therefore, the output voltage VQ of the D / A conversion unit 80 changes significantly from the first control voltage VC1 to the second control voltage VC2 in the step width of the difference voltage VDF.

If the output voltage VQ of the D / A conversion unit 80 changes significantly with the step width of the differential voltage VDF in this way, frequency hopping as shown in FIG. 3 occurs. That is, the oscillation circuit 150 of FIGS. 4 and 5 oscillates the oscillator XTAL using the output voltage VQ of the D / A conversion unit 80 as the frequency control voltage. Therefore, if the output voltage VQ of the D / A conversion unit 80 changes with the step width of the difference voltage VDF, the oscillation frequency of the oscillator XTAL also changes with the step width corresponding to this difference voltage VDF. As a result, frequency hopping as shown in FIG. 3 occurs, and a communication error as described in FIG. 8 occurs.

Therefore, in the present embodiment, as shown in FIG. 11, when the temperature changes from the first temperature T1 to the second temperature T2, the difference voltage VDF between the first control voltage VC1 and the second control voltage VC2 The output voltage VQ, which changes in a voltage width smaller than the absolute value, is output from the D / A conversion unit 80 to the oscillation circuit 150.

The absolute value of the differential voltage VDF is, for example, | VC1-VC2 |. In this case, VC1> VC2 may be used, or VC1 <VC2 may be used. Further, when VC1 = VC2 (DTD1 = DTD2) because there is no temperature change, the change voltage width of the output voltage VQ naturally becomes 0V, and the absolute value of the difference voltage VDF and the change of the output voltage VQ The voltage widths match. That is, this case is an exception to the method of the present embodiment.

For example, when the method of the present embodiment is not adopted, when the temperature changes from T1 to T2, the output voltage VQ of the D / A conversion unit 80 is the difference voltage VDF as shown in C1 of FIG. It changes with the step width.

On the other hand, in the method of the present embodiment, as shown in C2 of FIG. 11, the output voltage VQ of the D / A conversion unit 80 is changed by a voltage width VA smaller than the absolute value of the difference voltage VDF. The voltage width VA is, for example, a voltage change of the output voltage VQ within the period TDAC.

As shown in C2 of FIG. 11, if the output voltage VQ of the D / A conversion unit 80 is changed so that VA <VDF, the change in the oscillation frequency of the oscillation circuit 150 is very large as compared with the case of C1. It becomes smaller. Therefore, the occurrence of frequency hopping as shown in FIG. 3 is suppressed, and the occurrence of the communication error described in FIG. 8 can also be prevented.

More specifically, in the present embodiment, the D / A conversion unit 80 has a voltage step width corresponding to k × LSB (k ≧ 1) when the minimum resolution of the data in the D / A conversion is LSB. Outputs the output voltage VQ that changes with. For example, as shown in C2 of FIG. 11, the output voltage VQ of the D / A conversion unit 80 changes stepwise (stepwise) with a step width of the voltage corresponding to k × LSB. That is, the voltage width VA described above is, for example, the step width of the voltage corresponding to k × LSB of the D / A conversion unit 80. It is sufficient that the voltage width VA is equal to or less than the step width of the voltage corresponding to k × LSB, and the VA is larger than the step width of the voltage corresponding to k × LSB by using, for example, the method of the modification described later. It may be made smaller.

Here, the LSB is the minimum resolution of the data (frequency control data DDS output by the processing unit 50) input to the D / A conversion unit 80. The voltage corresponding to the LSB is the minimum resolution voltage, which is the voltage per the minimum resolution of the D / A conversion. Therefore, the voltage corresponding to k × LSB corresponds to a voltage k times this minimum resolution voltage.

Further, for example, when the resolution of the D / A conversion unit 80 is i-bit, k <2 ⁱ , and k is an integer sufficiently smaller than 2 ⁱ (for example, k = 1 to 8). More specifically, when the resolution of the D / A conversion unit 80 is extended from n bits to i = n + m bits by providing a modulation circuit 90 or the like, k <2 ^m can be set.

For example, when k = 1, the output voltage VQ of the D / A conversion unit 80 changes with the step width of the voltage corresponding to 1 LSB (1 bit). For example, the output voltage VQ of the D / A conversion unit 80 changes (increases or decreases) stepwise (stepwise) with a step width of a voltage corresponding to 1 LSB.

That is, the output voltage VQ of the D / A conversion unit 80 changes with the step width of the voltage corresponding to 1LSB (broadly defined as k × LSB) without depending on the input data DDS to the D / A conversion unit 80. .. This is because, for example, when the processing unit 50 (output unit 70) of FIG. 5 changes the temperature from the first temperature to the second temperature, the second temperature from the first data corresponding to the first temperature. It can be realized by outputting the frequency control data DDS that changes in 1LSB unit (k × LSB unit) to the second data corresponding to.

Further, the stepwise change in the step width of the voltage corresponding to k × LSB as shown in C2 of FIG. 11 is faster than the output rate of the temperature detection data DTD (DTD1, DTD2) from the A / D conversion unit 20. This is realized by the processing unit 50 outputting the frequency control data DDS (the D / A conversion unit 80 performs D / A conversion) at the output rate.

For example, the A / D conversion unit 20 outputs the temperature detection data DTD for each period TAD as shown in FIG. For example, the A / D converter 20 outputs the first temperature detection data DTD1 corresponding to the first temperature T1, and then, after the lapse of the period TAD, the second temperature detection data corresponding to the second temperature T2. Outputs DTD2. The period TAD corresponds to the A / D conversion interval (sampling interval of the temperature detection voltage) of the A / D conversion unit 20, and 1 / TAD corresponds to the output rate of the A / D conversion unit 20.

Then, when the A / D conversion unit 20 outputs the second temperature detection data DTD2, the processing unit 50 that receives the output performs digital signal processing such as temperature compensation processing, and the frequency corresponding to the second temperature detection data DTD2. Output the control data DDS. At this time, the processing unit 50 changes the frequency control data DDS in steps of k × LSB, as shown in FIGS. 21 and 22 described later. Therefore, as shown in C2 of FIG. 11, the output voltage VQ of the D / A conversion unit 80 that receives the frequency control data DDS that changes in k × LSB units and performs D / A conversion is also k × LSB for each period TDAC. It will change with the step width of the voltage corresponding to.

Here, the period TDAC corresponds to the D / A conversion interval of the D / A conversion unit 80 (the output interval of the frequency control data DDS of the processing unit 50), and 1 / TDAC corresponds to the processing unit 50 and the D / A conversion unit. It corresponds to an output rate of 80.

Then, as shown in FIG. 11, TAD> TDAC, and 1 / TDAC which is the output rate of the processing unit 50 and the D / A conversion unit 80 as compared with 1 / TAD which is the output rate of the A / D conversion unit 20. Is getting faster. Therefore, even if the change width of the output voltage VQ for each period TDAC (output rate 1 / TDAC) is as small as the voltage of VA = k × LSB, the output voltage VQ is within the period TAD. The control voltage VC1 can be changed to the control voltage VC2. That is, when the temperature changes from T1 to T2 and the temperature detection data changes from DTD1 to DTD2, the temperature is detected from the control voltage VC1 corresponding to the temperature detection data DTD1 within the period TAD which is the A / D conversion interval. The output voltage VQ can be changed to the control voltage VC2 corresponding to the data DTD2. Since the voltage width VA of the voltage change in this case is small, the occurrence of frequency hopping can be suppressed.

FIG. 12 is a diagram illustrating the method of the present embodiment in the frequency domain. For example, let FR be the frequency variable range of the oscillation frequency by the oscillation signal generation circuit 140 (D / A conversion unit 80 and the oscillation circuit 150). For example, the oscillation signal generation circuit 140 adjusts the frequency as shown in FIG. 13 with respect to the temperature change, and the frequency variable range in this frequency adjustment becomes FR. That is, if the temperature change falls within the frequency variable range FR, the frequency can be adjusted by the oscillation signal generation circuit 140.

Further, the allowable frequency drift of the oscillation frequency within the predetermined period TP is defined as FD. For example, in order to prevent the occurrence of the communication error described with reference to FIG. 8, it is necessary to keep the frequency drift of the oscillation frequency within the predetermined period TP within the allowable frequency drift FD. If the frequency drift of the oscillation frequency does not fall within the allowable frequency drift FD due to frequency hopping as shown in FIG. 3, an erroneous determination occurs in the demodulation process of a received signal such as a GPS satellite signal, and a communication error occurs. It ends up.

Further, the full-scale voltage of the D / A conversion unit 80 is defined as VFS. The D / A conversion unit 80 can change the output voltage VQ within the range of this full-scale voltage VFS. This full-scale voltage VFS corresponds to, for example, a voltage range when the frequency control data DDS input to the D / A conversion unit 80 changes in the full range such as 0 to 2 ⁱ .

Then, the voltage width of the voltage change of the output voltage VQ at the D / A conversion interval (TDAC) of the D / A conversion unit 80 described with reference to FIG. 11 is defined as VA. In this case, in the method of the present embodiment, the following equation (1) is established as shown in FIG.

VA <(FD / FR) x VFS (1)
Specifically, the following equation (2) holds when the resolution of the D / A conversion unit 80 is i-bit.

1/2 ⁱ <(FD / FR) (2)
By adopting the method of the present embodiment shown in the above equations (1) and (2), as shown in FIG. 12, oscillation with respect to the nominal oscillation frequency fos (for example, about 16 MHz) in a predetermined period TP (for example, 20 msec). The frequency drift of the frequency can be kept within the permissible frequency drift FD (for example, about several ppb). This makes it possible to suppress the occurrence of communication errors and the like caused by the frequency hopping described with reference to FIG.

For example, (FD / FR) × VFS on the right side of the above equation (1) is the ratio of the allowable frequency drift FD to the frequency variable range FR (FD / FR), which is the full-scale voltage VFS of the D / A conversion unit 80. Is multiplied by.

Then, if the voltage width VA of the change in the output voltage VQ at the D / A conversion interval (TDAC) of the D / A conversion unit 80 is made smaller than this (FD / FR) × VFS, in the frequency domain, FIG. As shown in, the frequency drift with respect to the nominal oscillation frequency fos can be contained within the allowable frequency drift FD. That is, the voltage width VA of the change in the output voltage VQ of the D / A conversion unit 80 can be reduced as shown in C2 of FIG. 11, and the occurrence of frequency hopping can be suppressed.

For example, if the above equation (1) does not hold, as shown in FIG. 14, frequency hopping occurs in which the frequency drift with respect to the nominal oscillation frequency fos does not fall within the allowable frequency drift FD, and the communication error or the like described in FIG. 8 occurs. Will end up. In the present embodiment, by changing the output voltage VQ of the D / A conversion unit 80 so that the above equation (1) holds, the occurrence of such frequency hopping can be suppressed and communication errors and the like can be prevented. ..

That is, the D / A conversion unit 80 changes the output voltage VQ in the range of the full-scale voltage VFS and adjusts the oscillation frequency of the oscillation circuit 150 in the frequency variable range FR as shown in FIG. , The temperature compensation process of the oscillation frequency described with reference to FIGS. 6 and 7 is realized.

However, when the voltage width VA of the change in the output voltage VQ of the D / A conversion unit 80 becomes large and, for example, VA ≧ (FD / FR) × VFS, the frequency drift of the oscillation frequency becomes the allowable frequency drift FD. However, frequency hopping as shown in FIG. 14 occurs.

On the other hand, in the present embodiment, the output voltage VQ of the D / A conversion unit 80 is changed with a small voltage width VA such that the relationship of VA <(FD / FR) × VFS is established. It becomes possible to suppress the occurrence of such frequency hopping.

Then, when the resolution of the D / A conversion unit 80 is i-bit, in the present embodiment, 1/2 ⁱ <(FD / FR) is established as in the above equation (2).

For example, when both sides of the above equation (2) are multiplied by the full-scale voltage VFS of the D / A conversion unit 80, the following equation (3) is obtained.

VFS x 1/2 ⁱ <(FD / FR) x VFS (3)
The VFS × 1/2 ^{i on} the left side of the above equation (3) corresponds to the voltage (minimum resolution voltage) of 1 LSB of the D / A conversion unit 80. The above equations (2) and (3) mean that the VFS × 1/2 ⁱ corresponding to the voltage of 1 LSB is made smaller than (FD / FR) × VFS. Assuming that VFS × 1/2 ⁱ <(FD / FR) × VFS in this way, when the output voltage VQ of the D / A conversion unit 80 is changed by the step width of the voltage of 1 LSB as shown in C2 of FIG. In addition, the frequency drift of the oscillation frequency does not exceed the allowable frequency drift FD, and the occurrence of frequency hopping can be suppressed.

In other words, the i-bit, which is the resolution of the D / A conversion unit 80, is set so that the above equations (2) and (3) hold.

In this case, in consideration of various variations such as manufacturing variations, in order to secure a sufficient margin, the D / A conversion is performed so that 1/2 ⁱ is sufficiently smaller than (FD / FR). It is desirable to set the resolution of unit 80. Specifically, the resolution of the D / A conversion unit 80 is set to, for example, i = 20 bits or more.

By doing so, for example, even when the permissible frequency drift within the TP for a predetermined period is about several ppb as described with reference to FIG. 8, the above equations (2) and (3) have a margin. It will be established. Therefore, the occurrence of communication errors due to frequency hopping can be effectively suppressed.

For example, FIG. 15 is a diagram illustrating improvement in frequency drift when the method of the present embodiment described with reference to FIGS. 11 to 13 is adopted. As is clear from comparing FIGS. 2, 3 and 15, according to the method of the present embodiment, even when a circuit configuration such as DTCXO is used, the frequency drift thereof is about the same as that of ATCXO in FIG. Can be stored in.

That is, in a conventional circuit device such as DTCXO, a frequency drift as shown in FIG. 3 occurs, which causes a communication error or the like.

On the other hand, if the method of the present embodiment is adopted, as shown in FIG. 15, the frequency drift can be made comparable to that of ATCXO in FIG. Therefore, for example, by using a circuit configuration such as DTCXO, it is possible to suppress frequency hopping and prevent the occurrence of communication errors, etc., while reducing the chip size of the circuit device and improving the frequency accuracy. Play.

3.2 C / N characteristics of spurious and oscillator Spurious is generated by fluctuation of frequency control data DDS (bit change in D / A conversion unit 80 in a narrow sense). First, the characteristics of the spurious will be described. The main signal amplitude voltage of the oscillator 400 is Vo, and the main signal frequency (oscillation frequency) of the oscillator 400 is f0. With respect to Vo and f0, the phase noise (spurious) when the minimum bit fluctuates in small steps in the D / A conversion unit 80 to cause a phase fluctuation satisfies the following equations (4) to (10).

Each equation will be described in detail. When the frequency of the phase fluctuation is fs, fs corresponds to the output frequency of the frequency control data DDS. Here, as shown in FIG. 4, when the oscillation signal generation circuit 140 includes the D / A conversion unit 80 and the oscillation circuit 150, fs, which is the output frequency of the frequency control data DDS, is the D / A conversion unit 80. Δf, which is the sampling frequency (1 / TDAC) and the change in the oscillation frequency, is the amount of change in the oscillation frequency due to one D / A conversion.

Since the minimum frequency resolution is Δf, when the phase fluctuation amplitude of the phase fluctuation is φs, φs fluctuates with a frequency change of 0, + Δf, or −Δf at every sampling frequency fs. Since it is considered that the frequency fluctuates with the amplitude ± Δf, φs is expressed by the following equation (4).
φs = 2π (Δf) t / 2π (fs) t = Δf / fs (4)

Using these variables, the signal obtained by adding the phase fluctuation to the main signal can be expressed by the following equation (5).
Vo (t) = Vo · sin {2π (f0) t + φs · sin (2π (fs) t)} (5)

From the sum product formula of trigonometric functions, the above equation (5) can be transformed as the following equation (6).
Vo (t) = Vo {sin (2π (f0) t) ・ cos (φs ・ sin (2π (fs) t)) +
cos (2π (f0) t) ・ sin (φs ・ sin (2π (fs) t))} (6)

Further, by simplifying the above equation (6) on the premise that φs is sufficiently smaller than 1, the upper equation (6) can be modified as in the lower equation (7).
Vo (t) = Vo {sin (2π (f0) t) + φs ・ cos (2π (f0) t) ・ sin (2π (fs) t)} (7)

Furthermore, from the product-sum formula of trigonometric functions, the above equation (7) can be transformed as the following equation (8).

As can be seen from the above equation (8), the signal component is the sum of the first term of the main signal and the second and third terms located vertically symmetrical to the main signal frequency in the sideband of the phase fluctuation component. Observed as. The power ratio P_ratio (fs) of this main signal and the sideband is calculated by the following equation (9) according to the amplitude levels of each other. Further, when the intensity L (fs) with respect to the main signal of spurious is expressed in dBc / Hz as a unit, the following equation (10) is obtained.

D1 of FIG. 16 is a graph showing a general C / N characteristic (phase noise characteristic) of the oscillator 400. The horizontal axis of FIG. 16 represents the detuning frequency with respect to the fundamental wave (oscillation frequency) in a logarithm, and the vertical axis represents the signal strength. As can be seen from D1, the oscillator 400 inevitably generates phase noise, and the design is performed on the premise that the phase noise is generated. That is, even if the spurious of the intensity shown in the above equation (10) is generated, if the intensity is smaller than the phase noise inherent in the oscillator, the influence of the spurious on the circuit device 500 is sufficiently small, and the accuracy of the acquired data is lowered. Can be suppressed. On the contrary, as shown in D2 and D3 of FIG. 16, when the spurious intensity is excessively large compared to the phase noise inherent in the oscillator, the C / N characteristic of the oscillator 400 deteriorates due to the spurious and is acquired. The accuracy of the data to be generated is reduced. For example, the accuracy of the position information obtained from the GPS received signal may be reduced.

In the circuit device 500 of the present embodiment, as described above, the fluctuation of the frequency control data DDS is set to k × LSB or less in order to suppress a defect due to frequency drift. Therefore, it is expected that the value of Δf will be small to some extent, but there is no guarantee that the deterioration of C / N characteristics due to spurious can be suppressed under the conditions. That is, it is necessary to specify the relationship between Δf and fs so that the fluctuation of the frequency control data DDS is k × LSB or less and the spurious intensity is such that it is buried in the phase noise inherent in the oscillator.

A specific example of the relationship will be described with reference to FIG. E1 in FIG. 17 is similar to D1 in FIG. 16 and represents the general C / N characteristics of the crystal unit. E1 is, for example, the C / N characteristic of an AT-cut crystal unit, and corresponds to the case where the characteristic of the Q value is the worst in the required range (the C / N characteristic is bad). That is, in the actual circuit device 500, it is designed so that there is no problem even if the phase noise of the intensity shown in E1 is generated. Therefore, if the spurious can be made strong enough to be buried in E1, the data accuracy is lowered. Can be suppressed.

E2 in FIG. 17 represents the intensity of the spurious in the case of ^{Δf / fs = 1/10 6} , E3 represents the strength of the spurious in the case of ^{Δf / fs = 1/10 7} , E4 is Delta] f / fs = It represents the strength of spurious in the case of 1/10 ⁸ . As shown in the above equation (10), the intensity of spurious is determined by Δf / fs. Therefore, when Δf / fs becomes a predetermined value, the intensity of spurious becomes a constant value regardless of the detuning frequency. It becomes a straight line parallel to the horizontal axis like E2 to E4. Since the detuning frequency of spurious is fs, it may be considered that the horizontal axis is the output frequency fs of the frequency control data DDS for E2 to E4. This point is the same for E5 and E6 described later.

Here, if Δf / fs <1/10 ⁸ can be set, the spurious intensity becomes lower than the straight line shown in E4, so that it can be made smaller than the original phase noise of the oscillator shown in E1. That is, in the circuit device 500 of the present embodiment, Δf / fs <1/10 ⁸ may be satisfied. However, in order to reduce Δf / fs, fs must be increased or Δf must be decreased. Increasing fs increases the power consumption of the D / A conversion unit 80, and decreasing Δf increases the resolution of the D / A conversion unit 80 (the range of frequency change corresponding to a change of 1 LSB). Need to be smaller). That is, under the condition that Δf / fs is set to less than a predetermined value, if Δf is increased to suppress the demand for resolution, fs must be increased to increase the conversion speed in the D / A conversion unit 80. There is a trade-off relationship that if fs is reduced to suppress the demand for the D / A conversion unit 80, Δf must be reduced to ensure high resolution. Therefore, the condition that Δf / fs <1/10 ⁸ is satisfied is ideal, but it may not be easy to realize.

Therefore, in the present embodiment, it may be used loose condition as compared to Δf / fs <1/10 ^8. For example, the D / A conversion unit 80 of the present embodiment has a filter circuit 120 (or a filter circuit 130 described later) after the D / A converter 100. By smoothing the output voltage of the D / A converter 100 by the filter circuit 120, it is possible to reduce the fluctuation of the oscillation frequency. That is, the filter circuit 120 can substantially reduce Δf.

For example, if the sampling frequency fs of the D / A converter 100 is set high and the cutoff rate is set to about 1/100 by the filter circuit 120, the spurious intensity can be improved by about 1/100 (-40 dB or less). It will be possible. In this case, even if Δf / fs = 1/10 ⁶ (E2), the spurious intensity after improvement by the filter circuit 120 is E1 or less, so that the spurious can be buried in the phase noise inherent in the oscillator. That is, even if the condition Δf / fs <1/10 ⁶ is used, it is possible to suppress a decrease in accuracy due to deterioration of the C / N characteristics.

As described above, the circuit device 500 of the present embodiment has the A / D conversion unit 20 that performs A / D conversion of the temperature detection voltage from the temperature sensor unit 10 and outputs the temperature detection data DTD, and the temperature detection data DTD. The frequency control data DDS is set by the processing unit 50 that performs the temperature compensation processing of the oscillation frequency based on the above and outputs the frequency control data DDS of the oscillation frequency, and the frequency control data DDS and the transducer XTAL from the processing unit 50. It includes an oscillation signal generation circuit 140 that generates an oscillation signal having an oscillation frequency to be generated. Then, in order to suppress problems due to frequency hopping, the processing unit 50 uses the first data corresponding to the first temperature to obtain the second temperature when the temperature changes from the first temperature to the second temperature. The frequency control data DDS that changes in units of k × LSB (k ≧ 1) is output to the second data corresponding to the temperature.

Further, in the present embodiment, in order to improve the accuracy of the data acquired by using the oscillation signal, the sampling frequency of the D / A conversion unit 80 is set to fs, and one D / A conversion of the D / A conversion unit 80 is performed. When the change in the oscillation frequency due to is Δf, Δf / fs <1/10 ⁶ is satisfied.

If the change in the frequency control data DDS is in units of k × LSB, the magnitude of Δf is also limited accordingly. For example, when the circuit device 500 includes the D / A converter 100, the change width ΔVDAC of the output voltage of the D / A converter 100 becomes a value corresponding to the change width of the frequency control data DDS. The variable capacitance included in the oscillation circuit has a capacitance value that changes according to the voltage, and its coefficient of variation (C / V) is determined. Further, the oscillation circuit 150 changes the oscillation frequency according to the capacitance value of the variable capacitance, and its coefficient of variation (f / C) is also determined. That is, in this example, since the relationship is Δf = ΔVDAC × (C / V) × (f / C), the change Δf of the oscillation frequency is a value corresponding to the change width of the frequency control data DDS, k × LSB. Become.

That is, Δf is limited to a predetermined value or less by satisfying the first condition that the change of the frequency control data DDS is in k × LSB units, but in the present embodiment, Δf / fs <1/10. Satisfy the second condition that ⁶ holds. In this way, it is possible to suppress defects due to frequency hopping and to suppress accuracy deterioration due to spurious.

It should be noted that what kind of Δf value the k × LSB of the frequency control data DDS specifically corresponds to is the value of k, the full scale of the D / A converter 100, the characteristics of the variable capacitance, and the oscillation circuit 150. It is determined according to the characteristics and the like. Further, a specific value of Δf for satisfying Δf / fs <1/10 ⁶ is determined according to the output frequency fs of the frequency control data DDS. Therefore, which of the first condition and the second condition becomes the stricter condition differs depending on the situation, but in any case, in the present embodiment, if the setting is made so as to satisfy the stricter condition. Good.

Further, the condition of Δf / fs <1/10 ⁶ so that the spurious is buried in the original phase noise of the oscillator regardless of the value of the detuning frequency (output frequency fs of the frequency control data DDS). It was requested from the viewpoint of. However, as is clear from E1 in FIG. 17, in the frequency band where the influence of 1 / f noise is large, the smaller the frequency, the larger the phase noise inherent in the oscillator. That is, in the band where the detuning frequency is relatively low, even if a spurious having a higher intensity is generated, the spurious is buried in the phase noise of the oscillator 400, and the influence on the accuracy is small.

That is, the condition that Δf / fs <1/10 ⁶ is satisfied regardless of the spurious detuning frequency (fs) is a sufficient condition from the viewpoint of suppressing the deterioration of the accuracy of the data based on the oscillation signal. , It is possible that the conditions are excessively strict.

Therefore, in this embodiment, conditions different from Δf / fs <1/10 ⁶ may be used. E5 and E6 of FIG. 17 are diagrams showing the characteristics of spurious when Δf is a given fixed value. As shown in FIG. 17, when the unit of the vertical axis is dBc / Hz and the horizontal axis is the logarithm of the detuning frequency, the spurious intensity when Δf is a fixed value is represented as a straight line that monotonically decreases. Then, by changing Δf, the intercept of the straight line changes, and the larger Δf, the higher the spurious intensity at the same detuning frequency. E5 in FIG. 17 represents the characteristics of spurious when Δf = 0.1 MHz, and E6 represents the characteristics of spurious when Δf = 1 MHz.

As can be seen from FIG. 17, E5 having Δf = 0.1 MHz is located below E1 representing the C / N characteristics of the oscillator 400 regardless of the position on the horizontal axis. That is, by satisfying Δf <0.1 MHz, the spurious intensity can be made smaller than the phase noise inherent in the oscillator. However, Delta] f <is also ideal conditions in the same manner as Δf / fs = 1/10 ⁸ for 0.1 mHz, actually influence on the accuracy is less a looser condition. Specifically, in the present embodiment, the straight line shown in E6 may be used as the upper limit, and Δf <1 MHz may be a condition.

However, the condition of Δf <1 MHz is also an excessively severe condition in a situation where the detuning frequency (fs) is relatively large. As can be seen from the above equation (10), the larger the fs, the smaller the spurious intensity. That is, when fs is large, even if Δf is large, an increase in spurious intensity can be suppressed, and the influence on accuracy is small. Under the condition of Δf <1 MHz, there is a possibility that Δf is excessively reduced even when fs is large, which is a severe condition.

Therefore, in the present embodiment, Δf / fs <1/10 ⁶ and Δf <1 MHz may be switched depending on the situation. Specifically, the conditions may be switched with fs = 1 kHz, which is the intersection of E2 and E6 in FIG. 17, as a boundary. On the right side of the intersection, that is, when fs ≧ 1 kHz, E2 is higher than E6, so the condition of E2 is looser. On the other hand, on the left side of the intersection, that is, when fs <1 kHz, E6 is higher than E2, so the condition of E6 is looser. That is, in the present embodiment, the condition is that Δf / fs <1/10 ⁶ when fs ≧ 1 kHz and Δf <1 MHz when fs <1 kHz. By doing so, the conditions to be satisfied can be relaxed, so that the requirement for the resolution of the D / A converter 100 can be lowered, and the circuit device 500 can be easily realized.

Further, the method of the present embodiment is not limited to the one in which Δf / fs <1/10 ⁶ and Δf <1 MHz are used in combination. Specifically, when the sampling frequency of the D / A conversion unit 80 is fs and the change in the oscillation frequency of the D / A conversion unit 80 due to one D / A conversion is Δf, when fs <1 kHz. , Δf <1 MHz. At this time, in the case of fs ≧ 1 kHz, to the Δf / fs <1/10 ⁶ it is also possible to adopt a different condition, the first place be exempt method of this embodiment the fs ≧ 1 kHz even It is possible.

In addition, various design methods of a circuit device in which Δf and fs satisfy the above conditions can be considered. For example, the conversion speed (sampling frequency) required for the D / A conversion unit 80 differs depending on the circuit device. In a given circuit device, it is possible to set a high sampling frequency such as fs = 100 kHz, but in different circuit devices, it is conceivable that only a low sampling frequency such as fs = 100 Hz is allowed from the viewpoint of power consumption and the like. .. In a circuit device in which fs = 100 kHz is allowed, Δf / fs <1/10 ⁶ may be used as a condition as described above, and Δf <100 MHz. In this case, since Δf can be made larger than Δf <1 MHz, there is no problem even if the resolution is relatively coarse. On the other hand, in a circuit device in which fs = 100 Hz, Δf <1 MHz may be used as described above. In this case, the requirement for resolution becomes relatively large, but it becomes possible to realize a circuit device having low power consumption.

Here, the oscillator XTAL according to the present embodiment is, for example, a crystal oscillator. It is known that the crystal unit has different characteristics such as oscillation frequency depending on the cutting direction from the crystal axis. The crystal oscillator according to the present embodiment may be a widely used AT-cut oscillator, an SC-cut (Stress Compensation-cut) oscillator, or a SAW resonator.

The AT-cut oscillator has an angle of 35.15 ° with respect to the crystal axis, and is an oscillator used for SPXO, TCXO, and VCXO as an oscillation source of 10 MHz to 500 MHz. Further, the SC cut oscillator is an oscillator used in OCXO as an oscillation source of 10 MHz to 100 MHz because the temperature characteristic becomes extremely small at a high temperature. The oscillation frequency of the AT-cut oscillator and the SC-cut oscillator is determined by the thickness slip. The SAW resonator is an oscillator to which a surface acoustic wave is applied, and vibrates depending on the electrode pattern on the crystal surface. The SAW resonator is an oscillator having a high oscillation frequency of 100 MHz to 3.5 GHz and good C / N characteristics (high Q value).

Note that Δf / fs <1/10 ⁶ is a condition relating to the ratio of Δf and fs. Therefore, many pairs of Δf and fs satisfying Δf / fs <1/10 ⁶ can be considered. FIG. 18 is an example of a set of values of Δf and fs when accurate data can be acquired without deteriorating the C / N characteristics. F1 in FIG. 18 is (Δf, fs) = (0.1 Hz, 4 MHz), F2 is (Δf, fs) = (4 MHz, 100 kHz), and F3 is (Δf, fs) = (1 MHz, 10 kHz). Is.

In the present embodiment, it is not prevented to limit the pair of values of Δf and fs to one. For example, only one of F1 to F3 is set as a set of values of Δf and fs, and the circuit device 500 always operates so as to satisfy the set values. However, the method of this embodiment is not limited to this, and the set of values of Δf and fs may be variable. For example, three types of F1 to F3 may be retained as candidates for a set of values of Δf and fs, and any one of the three may be adopted depending on the situation.

For example, a set of values of Δf and fs to be used is determined according to whether or not it is within a predetermined period from the start of operation of the circuit device 500. When the temperature compensation processing for the temperature detection data DTD is not performed at the start of operation, the difference between the oscillation frequency of the output oscillation signal SSC and the desired oscillation frequency (hereinafter referred to as frequency error) is large. There is. It is possible to obtain the frequency control data DDS for reducing the frequency error (set to 0 in a narrow sense) by the temperature compensation processing in the processing unit 50, but in the present embodiment, the oscillation frequency per oscillation is There is a limitation that the fluctuation is suppressed to Δf. That is, during one output of the frequency control data DDS, the frequency error is reduced by only Δf, and it may take a long time to set the frequency error to 0.

Therefore, in the present embodiment, it is preferable that Δf is set to a relatively large value at the start of operation, and fs is also set to a relatively large value in order to satisfy Δf / fs <1/10 ⁶ . In the case of the above examples of F1 to F3, (Δf, fs) = (0.1 Hz, 4 MHz) shown in F1 is used. In this way, since Δf is relatively large, it is possible to bring the oscillation frequency of the oscillation signal closer to a desired frequency (make the frequency error closer to 0) in a short time.

However, in order to increase Δf, fs must also be increased, which leads to an increase in power consumption and the like. Therefore, when a certain amount of time has passed (or when the frequency error becomes small to some extent), it is desirable to reduce Δf and fs. In the example of FIG. 18, the set of values of Δf and fs to be used is changed from (Δf, fs) = (4 MHz, 100 kHz) shown in F1 to F2. Further, when the time elapses (when the frequency error becomes smaller), even if the set of the values of Δf and fs used is changed from F2 to F3 (Δf, fs) = (1 MHz, 10 kHz). Good.

FIG. 19 is a diagram illustrating the above control. The vertical axis of FIG. 19 represents the frequency error (Hz), and the horizontal axis represents the elapsed time from the start of operation (starting) in logarithm. As shown in t1 to t2 of FIG. 19, the parameters shown in F1 are used for a predetermined period from the time of startup. Since the sampling frequency fs is high and the amount of frequency change per time Δf is also large, it is possible to bring the frequency error of 0.2 Hz or more at the time of startup close to 0 in a short time. Further, in the period of t2 to t3, it operates with the parameter shown in F2, and in the period after t3, it operates with the parameter shown in F3.

In this way, the conditions shown in Δf / fs <1/10 ⁶ can be realized by using parameters according to the situation. Specifically, in a situation where there is a possibility that the frequency error is large, the target value is followed at high speed, and when the tracking is completed to some extent, fs is reduced to suppress an increase in power consumption.

Here, an example in which there are three sets of values of Δf and fs has been described, but it goes without saying that there may be two sets or four or more sets. Further, Δf and fs need only satisfy Δf / fs <1/10 ⁶ , and specific numerical values are not limited to F1 to F3 in FIG. Further, an example in which Δf and fs are variable under the condition that Δf / fs <1/10 ⁶ is satisfied has been shown, but under the condition that the frequency control data DDS is changed in units of k × LSB (k ≧ 1). k may be variable.

4. Detailed configuration example 4.1 Processing unit Next, a detailed configuration example of each portion of the circuit device of the present embodiment is shown. FIG. 20 is a diagram showing a detailed configuration example of the processing unit 50.

As shown in FIG. 20, the processing unit 50 (DSP unit) includes a control unit 52, a calculation unit 60, and an output unit 70. The control unit 52 controls the calculation unit 60 and the output unit 70, and performs various determination processes. The calculation unit 60 calculates the temperature compensation processing of the oscillation frequency based on the temperature detection data DTD from the A / D conversion unit 20. The output unit 70 receives the calculation result data from the calculation unit 60 and outputs the frequency control data DDS.

The control unit 52 includes a determination unit 53. The determination unit 53 has comparison units 54 and 55, and performs various determination processes based on the comparison results of the comparison units 54 and 55.

The calculation unit 60 includes type conversion units 61, 62, 68, multiplexers 63, 65, a calculation unit 64, and work registers 66, 67, 69. The arithmetic unit 64 includes a multiplier 58 and an adder 59.

The type conversion unit 61 receives the coefficient data from the memory unit 180, performs type conversion from the binary type (integer) to the floating point type (single precision), and outputs the coefficient data after the type conversion to the multiplexer 63. .. The type conversion unit 62 receives the temperature detection data DTD from the A / D conversion unit 20, performs type conversion from the binary type to the floating point type, and outputs the temperature detection data DTD after the type conversion to the multiplexer 63. .. For example, the 15-bit binary temperature detection data DTD is converted into a 32-bit floating point number (exponent part = 8 bits, mantissa part = 23 bits, code = 1 bit). Further, the constant data from the ROM 190 that stores fixed value constant data for temperature compensation processing is input to the multiplexer 63.

The multiplexer 63 selects any of the output data of the arithmetic unit 64, the output data of the work registers 66 and 67, the output data of the type conversion units 61 and 62, and the output data of the ROM 190, and outputs the output data to the arithmetic unit 64. The arithmetic unit 64 executes the temperature compensation processing by performing arithmetic processing such as a 32-bit floating-point multiply-accumulate operation by the multiplier 58 and the adder 59. The multiplexer 65 selects any of the output data of the multiplier 58 of the arithmetic unit 64 and the adder 59, and outputs the output data to any of the work registers 66 and 67 and the type conversion unit 68. The type conversion unit 68 converts the calculation result data of the calculation unit 60 (calculation unit 64) from the floating point type to the binary type. For example, 32-bit floating-point arithmetic result data is type-converted to 20-bit binary arithmetic result data. The operation result data after type conversion is held in the work register 69.

As shown in the following equation (11), the calculation unit 60 (calculator 64) performs temperature compensation processing for approximating the curve of the temperature characteristic of FIG. 6 with, for example, a fifth-order approximation function (polynomial).

Vcp = b · (T-T0) ⁵ + c · (T-T0) ⁴ + d · (T-T0) ³ + e · (T-T0)
(11)
In the above equation (11), T corresponds to the temperature represented by the temperature detection data DTD, and T0 corresponds to the reference temperature (for example, 25 ° C.). b, c, d, and e are coefficients of the approximate function, and the data of these coefficients is stored in the memory unit 180. The arithmetic unit 64 executes arithmetic processing such as the product-sum operation of the above equation (11).

The output unit 70 includes a multiplexer 71, an output register 72, an LSB adder 73, and an LSB subtractor 74. The multiplexer 71 selects any of the calculation result data, which is the output data of the calculation unit 60, the output data of the LSB adder 73, and the output data of the LSB subtractor 74, and outputs the data to the output register 72. The determination unit 53 of the control unit 52 monitors the output data of the work register 69 and the output data of the output register 72. Then, various comparison determinations are performed using the comparison units 54 and 55, and the multiplexer 71 is controlled based on the determination results.

In the present embodiment, as shown in FIGS. 21 and 22, when the temperature changes from the first temperature to the second temperature, the output unit 70 starts from the first data DAT1 corresponding to the first temperature. The frequency control data DDS that changes in k × LSB units is output to the second data DAT2 corresponding to the second temperature. For example, k = 1, and the frequency control data DDS that changes in 1LSB units is output.

For example, in the output register 72, the first data DAT1 which is the calculation result data of the calculation unit 60 of the previous time (the timing of the n-1th) is stored. The work register 69 stores the second data DAT2, which is the calculation result data of the calculation unit 60 this time (nth timing).

Then, as shown in FIG. 21, when the second data DAT2 which is the current calculation result data is larger than the first data DAT1 which is the previous calculation result, the output unit 70 is the first. The addition result data is output as frequency control data DDS while performing the process of adding 1LSB (k × LSB in a broad sense) which is a predetermined value to the data DAT1 until the addition result data reaches the second data DAT2. ..

On the other hand, as shown in FIG. 22, the output unit 70 is the first when the second data DAT2 which is the current calculation result data is smaller than the first data DAT1 which is the previous calculation result. The subtraction result data is output as frequency control data DDS while performing the process of subtracting 1 LSB (k × LSB) which is a predetermined value from the data DAT1 until the subtraction result data reaches the second data DAT2.

Specifically, the determination unit 53 of the control unit 52 compares the first data DAT1 stored in the output register 72 with the second data DAT2 stored in the work register 69. The determination of this comparison is made by the comparison unit 54.

Then, as shown in FIG. 21, when DAT2 is larger than DAT1, the process of adding 1 LSB to DAT1 of the output register 72 is performed by the LSB adder 73, and the output data of the LSB adder 73 is obtained. , Selected by the multiplexer 71. As a result, as shown in FIG. 21, the output register 72 holds the addition result data in which 1 LSB is sequentially added to the DAT1. Then, the addition result data in which 1 LSB is sequentially added and updated is output as frequency control data DDS. Then, the addition process is repeated until the addition result data reaches DAT2. The comparison process for determining the match between the addition result data and the DAT2 is performed by the comparison unit 55.

On the other hand, when DAT2 is smaller than DAT1 as shown in FIG. 22, the process of subtracting 1 LSB from DAT1 of the output register 72 is performed by the LSB subtractor 74, and the output data of the LSB subtractor 74 is displayed. Selected by the multiplexer 71. As a result, as shown in FIG. 22, the output register 72 holds the subtraction result data in which 1 LSB is sequentially subtracted from DAT1. Then, the subtraction result data in which 1 LSB is sequentially subtracted and updated is output as the frequency control data DDS. Then, the subtraction process is repeated until the subtraction result data reaches DAT2.

The maximum number of addition processes and subtraction processes by the LSB adder 73 and the LSB subtractor 74 is set to a predetermined number of times (for example, 8 times). Then, for example, the maximum temperature change of the environmental temperature can be specified (for example, 2.8 ° C./10 seconds). Therefore, for example, the temperature change corresponding to 1 LSB × a predetermined number of times (for example, the temperature change corresponding to the voltage of 1 LSB × 8 times) is set so as to sufficiently exceed the above-mentioned maximum temperature change.

Further, as described with reference to FIG. 11, the output rate (1 / TDAC) of the frequency control data DDS of the processing unit 50 is faster than the output rate (1 / TAD) of the temperature detection data DTD of the A / D conversion unit 20. Therefore, for example, in FIG. 11, the period TAD from the input of the temperature detection data DTD2 from the A / D conversion unit 20 to the processing unit 50 until the next temperature detection data DTD3 is input is shown in FIGS. 21 and 22. Such a process of adding or subtracting 1 LSB a predetermined number of times can be executed. For example, the addition process and the subtraction process of a predetermined number of times (for example, 8 times), which is the maximum number of times as described above, can be executed.

As described above, according to the processing unit 50 having the configuration of FIG. 20, as shown in FIGS. 21 and 22, for example, from the first data DAT1 corresponding to the first temperature (first temperature detection data DTD1), The frequency control data DDS that changes in k × LSB units can be output to the second data DAT2 corresponding to the second temperature (second temperature detection data DTD2). As a result, the method of the present embodiment described with reference to FIGS. 11 to 13 can be realized by output control of the frequency control data DDS of the processing unit 50.

Further, in the present embodiment, for example, the processing of the arithmetic unit 60 is realized by high-precision arithmetic processing such as 32 bits. Therefore, for example, when the type conversion unit 68 performs type conversion of 32-bit floating-point arithmetic result data, for example, a 20-bit binary frequency control data DDS (for example, based on the 23-bit improper part whose accuracy is maintained) Calculation result data) can be acquired. As a result, as described with reference to FIG. 5, for example, i = 20-bit frequency control data DDS can be input from the processing unit 50 to the D / A conversion unit 80. Then, the modulation circuit 90 modulates n = 16-bit data of the frequency control data DDS based on the data of m = 4 bits out of i = 20 bits, and the D / A converter 100 modulates n. By D / A conversion of = 16-bit data, it is possible to realize D / A conversion with a resolution of i = 20 bits.

4.2 D / A conversion unit FIGS. 23 and 24 are diagrams showing a detailed configuration example of the D / A conversion unit 80. The D / A conversion unit 80 includes a modulation circuit 90, a D / A converter 100, and a filter circuit 120.

As shown in FIG. 23, the D / A converter 100 includes an upper D / A converter DACA, a lower D / A converter DACB, and operational amplifiers (arithmetic amplifiers) OPA and OPB connected by voltage followers. , Includes OPC.

The upper q-bit data of the n-bit (n = q + p) data DM from the modulation circuit 90 is input to the upper DACA, and the lower p-bit (for example, p = q = 8) is input to the lower DACB. ) Data is input. These upper DACA and lower DACB are resistor string type D / A converters that select the voltage corresponding to the input data from, for example, a plurality of divided voltages voltage divided by a plurality of resistors connected in series. Is.

As shown in FIG. 24, the upper DACA includes a plurality of resistors RAN1 to RAN connected in series between the node of the high potential side power supply voltage VDDA and the node of the low potential side power supply voltage VSS. Further, the upper DACA turns on the switch elements SA1 to SAN + 1 based on the data of the upper q bits of the data DM and the plurality of switch elements SA1 to SAN + 1 whose one end is connected to the voltage dividing node by these resistors RA1 to RAN. It also includes a decoder 104 (switch control circuit) that produces a switch control signal to turn off.

Then, the upper DACA outputs one of the divided voltages across the resistors specified by the data of the upper q bits of the plurality of resistors RA1 to RAN to the non-inverting input terminal of the operational amplifier OPA, and the other DACA. The divided voltage is output to the non-inverting input terminal of the operational amplifier OPB. As a result, the one voltage is impedance-converted by the operational amplifier OPA connected to the voltage follower and supplied to the lower DACB as the voltage VX. Further, the other voltage is impedance-converted by the operational amplifier OPB connected to the voltage follower, and supplied to the lower DACB as a voltage VY.

For example, when the resistor RA1 is specified by the data of the upper q bits, the divided voltage on the high potential side among the divided voltages across the resistor RA1 is the voltage via the switch element SA1 and the operational amplifier OPA that are turned on. It is supplied as VX. Further, the divided voltage on the low potential side is supplied as a voltage VY via the switch element SA2 turned on and the operational amplifier OPB. When the resistor RA2 is specified by the data of the upper q bits, the divided voltage on the low potential side of the divided voltages across the resistor RA2 is the voltage via the switch element SA3 and the operational amplifier OPA that are turned on. It is supplied as VX. Further, the divided voltage on the high potential side is supplied as a voltage VY via the switch element SA2 turned on and the operational amplifier OPB.

The lower DACB includes a plurality of resistors RB1 to RBM connected in series between the node of voltage VX and the node of voltage VY. Further, the lower DACB turns on the switch elements SB1 to SBM + 1 based on the data of the lower p bits of the data DM and the plurality of switch elements SB1 to SBM + 1 whose one end is connected to the voltage dividing node by these resistors RB1 to RBM. It also includes a decoder 106 (switch control circuit) that produces a switch control signal to turn off.

Then, the lower DACB is connected to the voltage follower via the switch element turned on, using one of the divided voltages selected by the data of the lower p bits as the selected voltage among the plurality of divided voltages by the resistors RB1 to RBM. Output to the non-inverting input terminal of the operational amplifier OPC. As a result, the selected voltage is output as the output voltage VDA of the D / A converter 100.

25, 26, and 27 are explanatory views of the modulation circuit 90. As shown in FIG. 25, the modulation circuit 90 receives the i = (n + m) bit frequency control data DDS from the processing unit 50. Then, based on the lower m-bit data (bits b1 to b4) of the frequency control data DDS, PWM modulation of the upper n bits (bits b5 to b20) of the frequency control data DDS is performed. Then, as described with reference to FIGS. 23 and 24, the upper q-bit data (bits b13 to b20) of the n-bit data is input to the upper DACA, and the lower p-bit data (bit b5) is input. ~ B12) is input to the lower DACB.

FIG. 26 is an explanatory diagram of the first method of PWM modulation. DY and DZ are high-order n-bit data of the data DM, and DY = DZ + 1 holds in the n-bit representation.

When the duty ratio represented by the lower m = 4 bit data used for PWM modulation is, for example, 8: 8, as shown in FIG. 26, there are eight 16-bit data DYs and eight 16-bit data DYs. The 16-bit data DZ is time-divided and output from the modulation circuit 90 to the D / A converter 100.

When the duty ratio represented by the lower m = 4 bit data is 10: 6, 10 data DYs and 6 data DZs are time-divided from the modulation circuit 90 to the D / A converter. It is output to 100. Similarly, when the duty ratio represented by the lower m = 4 bit data is 14: 2, 14 data DYs and 2 data DZs are output in time division.

FIG. 27 is an explanatory diagram of a second method of PWM modulation. When each bit b4, b3, b2, b1 of m = 4 bits used for PWM modulation has a logic level "1", the output pattern associated with each bit in FIG. 27 (shown on the right side of each bit). Output pattern) is selected.

For example, when bit b4 = 1 and b3 = b2 = b1 = 0, only the output pattern associated with bit b4 is output in the periods P1 to P16. That is, n = 16-bit data is output from the modulation circuit 90 to the D / A converter 100 in the order of DZ, DY, DZ, DY ... As a result, the number of times the data DY and DZ are output is 8 times, and the same PWM modulation as in the case where the duty ratio is 8: 8 in FIG. 26 is realized.

When the bits b4 = b2 = 1 and b3 = b1 = 0, the output patterns associated with the bits b4 and b2 are output in the periods P1 to P16. As a result, the number of times the data DY and DZ are output becomes 10 times and 6 times, respectively, and PWM modulation similar to the case where the duty ratio is 10 to 6 is realized. Similarly, when the bits b4 = b3 = b2 = 1 and b1 = 0, the number of times the data DY and DZ are output is 14 times and 2 times, respectively, and the duty ratio is 14: 2. The same PWM modulation as above is realized.

As described above, according to the modulation circuits 90 of FIGS. 5 and 23, PWM modulation can be realized only by controlling the number of output times of data DY and DZ, for example, a D / A converter 100 having a resolution of 16 bits. While using it, for example, it becomes possible to realize a resolution of D / A conversion of 20 bits or more.

For example, in a resistance string type or resistance ladder type D / A conversion with less noise, a resolution of, for example, about 16 bits is a practical limit. In this regard, according to the configurations of FIGS. 5 and 23, the resolution of D / A conversion can be improved to, for example, 20 bits or more simply by providing the modulation circuit 90 and the filter circuit 120 having a small circuit scale. Therefore, it is possible to improve the resolution of the D / A conversion unit 80 while minimizing the increase in the circuit scale. By improving the resolution of the D / A conversion unit 80, it is possible to realize high accuracy of the oscillation frequency, suppress frequency hopping, and provide an oscillator suitable for time synchronization.

4.3 Temperature sensor unit, oscillation circuit FIG. 28 shows a first configuration example of the temperature sensor unit 10. The temperature sensor unit 10 of FIG. 28 has a current source IST and a bipolar transistor TRT in which the current from the current source IST is supplied to the collector. The bipolar transistor TRT is a diode connection to which a base is connected to the collector, and a temperature detection voltage VTD having a temperature characteristic is output to a node of the collector of the bipolar transistor TRT. The temperature characteristic of the temperature detection voltage VTD is caused by the temperature dependence of the base-emitter voltage of the bipolar transistor TRT. As shown in FIG. 30, the temperature detection voltage VTD has a negative temperature characteristic (a first-order temperature characteristic having a negative gradient).

FIG. 29 shows a second configuration example of the temperature sensor unit 10. In FIG. 29, the current source IST of FIG. 28 is realized by the resistor RT. Then, one end of the resistor RT is connected to the node of the power supply voltage, and the other end is connected to the collector of the bipolar transistor TRT1. Further, the emitter of the bipolar transistor TRT1 is connected to the collector of the bipolar transistor TRT2. The bipolar transistors TRT1 and TRT2 are both diode-connected, and the voltage VTSQ output to the collector node of the bipolar transistor TRT1 has negative temperature characteristics (primary temperature with a negative gradient) as shown in FIG. Has characteristics).

Further, in the temperature sensor unit 10 of FIG. 29, an operational amplifier OPD and resistors RD1 and RD2 are further provided. A voltage VTSQ is input to the non-inverting input terminal of the operational amplifier OPD, and one end of the resistor RD1 and one end of the resistor RD2 are connected to the inverting input terminal. A reference temperature voltage VTA0 is supplied to the other end of the resistor RD1, and the other end of the resistor RD2 is connected to the output terminal of the operational amplifier OPD.

Such an operational amplifier OPD and resistors RD1 and RD2 constitute an amplification amplifier that positively amplifies the voltage VTSQ with reference to the reference temperature voltage VAT0. As a result, the temperature detection voltage VTD = VAT0 + (1 + RD2 / RD1) × (VTSQ-VAT0) is output from the temperature sensor unit 10. Then, by adjusting the reference temperature voltage VAT0, the reference temperature T0 can be adjusted.

FIG. 31 shows a configuration example of the oscillation circuit 150. The oscillation circuit 150 includes a current source IBX, a bipolar transistor TRX, a resistor RX, a variable capacitance capacitor CX1, a capacitor CX2, and a CX3.

The current source IBX supplies a bias current to the collector of the bipolar transistor TRX. The resistor RX is provided between the collector and the base of the bipolar transistor TRX.

One end of the variable capacitance capacitor CX1 having a variable capacitance is connected to one end of the oscillator XTAL. Specifically, one end of the variable capacitance capacitor CX1 is connected to one end of the oscillator XTAL via a first oscillator terminal (oscillator pad) of the circuit device. One end of the capacitor CX2 is connected to the other end of the oscillator XTAL. Specifically, one end of the capacitor CX2 is connected to the other end of the oscillator XTAL via a second oscillator terminal (oscillator pad) of the circuit device. One end of the capacitor CX3 is connected to one end of the oscillator XTAL, and the other end is connected to the collector of the bipolar transistor TRX.

The base-emitter current generated by the oscillation of the oscillator XTAL flows through the bipolar transistor TRX. When the base-emitter current increases, the collector-emitter current of the bipolar transistor TRX increases, and the bias current branched from the current source IBX to the resistor RX decreases, so that the collector voltage VCX decreases. On the other hand, when the base-emitter current of the bipolar transistor TRX decreases, the collector-emitter current decreases and the bias current branched from the current source IBX to the resistor RX increases, so that the collector voltage VCX rises. This collector voltage VCX is fed back to the oscillator XTAL via the capacitor CX3.

The oscillation frequency of the oscillator XTAL has a temperature characteristic (for example, the temperature characteristic of FIG. 6), and this temperature characteristic is compensated by the output voltage VQ (frequency control voltage) of the D / A conversion unit 80. That is, the output voltage VQ is input to the variable capacitance capacitor CX1, and the capacitance value of the variable capacitor CX1 is controlled by the output voltage VQ. When the capacitance value of the variable capacitance capacitor CX1 changes, the resonance frequency of the oscillation loop changes, so that the fluctuation of the oscillation frequency due to the temperature characteristic of the oscillator XTAL is compensated. The variable capacitance capacitor CX1 is realized by, for example, a variable capacitance diode (varicap).

The oscillation circuit 150 of this embodiment is not limited to the configuration shown in FIG. 31, and various modifications can be made. For example, in FIG. 31, the case where CX1 is used as a variable capacitance capacitor has been described as an example, but CX2 or CX3 may be used as a variable capacitor controlled by an output voltage VQ. Further, a plurality of CX1 to CX3 may be used as variable capacitance capacitors controlled by VQ.

5. Modifications Next, various modifications of the present embodiment will be described. For example, in the above, when the processing unit 50 outputs the frequency control data DDS that changes in units of k × LSB as shown in FIGS. 21 and 22, the method of the present embodiment of FIGS. 11 to 13 is realized. However, the present embodiment is not limited to this.

In the modified example of FIG. 32, a filter circuit 130 composed of an SCF (switched capacitor filter) is provided after the D / A converters DACC and DACD. For example, the 8-bit D / A converter DACC outputs the voltage DA1 based on the data D (n) at the timing n. Further, the 8-bit D / A converter DACD outputs the voltage DA2 based on the data D (n + 1) at the next timing n + 1.

When the clock frequency fck of the SCF of the filter circuit 130 is set, the resistance of RG = 1 / (CS1 × fck) is realized by the circuit composed of the capacitor CS1, the switch elements SS1 and SS2. A resistance of RF = 1 / (CS2 × fck) is realized by a circuit composed of a capacitor CS2, a switch element SS3, and SS4.

Further, the time constant τ of this filter circuit 130 is expressed by the following equation (12).

τ = RF × CS3 = (CS3 / CS2) × (1 / fck) (12)
For example, by setting CS3 = 5pF, CS2 = 0.1pF, and fck = 5KHz, τ = 10msec can be realized. By making the time constant τ sufficiently long in this way, as shown in FIG. 34, it is possible to realize an output voltage VQ that slowly changes from the voltage DA1 to the voltage DA2 with the time constant τ.

For example, as shown in FIG. 33, SL1 = FD / TP when the period TP (for example, 20 msec) described in FIG. 8 is the horizontal axis and the allowable frequency drift FD (for example, about several ppb) is the vertical axis. .. In this case, the method of the present embodiment of FIGS. 11 to 13 can be realized by making the inclination SL2 realized by the time constant τ of FIG. 34 smaller than that of the inclination SL1. That is, a filter circuit 130 having a low-pass filter characteristic so strong that the gradient SL1 defined by the period TP and the allowable frequency drift FD cannot be formed is provided after the D / A converters DACC and DACD. As a result, as shown in C2 of FIG. 11, it becomes possible to realize a voltage waveform equivalent to a voltage waveform in which the output voltage VQ of the D / A conversion unit 80 changes in a step width of a voltage of 1 LSB, and there is a problem of frequency hopping. Can be solved.

However, if the time constant τ of the filter circuit 130 becomes longer than the period TP, the fluctuation of the temperature characteristic of the oscillator XTAL cannot be completely corrected by the output voltage VQ of the filter circuit 130, and there arises a problem that the frequency shifts.

For example, FIG. 35 is a diagram showing a frequency drift with respect to a temperature change when the time constant is τ = TP = 20 msec. By setting τ = TP as shown in FIG. 35, the problem of frequency hopping can be solved. On the other hand, FIGS. 36 and 37 are diagrams showing frequency drifts with respect to temperature changes when τ = 22 msec and 40 msec, respectively. As described above, in the modified example of FIG. 32, there is a problem that the characteristic of frequency drift deteriorates when the time constant τ becomes long, and there is a disadvantage that it is difficult to find the optimum solution.

FIG. 38 is a configuration example of the A / D conversion unit 20. As shown in FIG. 38, the A / D conversion unit 20 includes a processing unit 23, a register unit 24, a D / A converter DACF, DACF, and a comparison unit 27. Further, the amplifier 28 for the temperature sensor unit can be included. The processing unit 23 and the register unit 24 are provided as the logic unit 22, and the D / A converter DACF, DACF, the comparison unit 27, and the temperature sensor unit amplifier 28 are provided as the analog unit 26.

The register unit 24 stores result data such as an intermediate result and a final result of A / D conversion. The register unit 24 corresponds to, for example, a sequential comparison result register in the sequential comparison method. The D / A converters DACF and DACF perform D / A conversion of the result data of the register unit 24. As these DACFs and DACFs, D / A converters having the same configurations as those in FIGS. 23 and 24 can be adopted. The comparison unit 27 compares the output voltage of the D / A converters DACF and DACF with the temperature detection voltage VTD (voltage after amplification by the temperature sensor unit amplifier 28). The comparison unit 27 can be realized by, for example, a chopper type comparator or the like. The processing unit 23 performs determination processing based on the comparison result of the comparison unit 27, and updates the result data of the register unit 24. Then, the final temperature detection data DTD obtained by the update process is output from the A / D conversion unit 20 as the A / D conversion result of the temperature detection voltage VTD. With such a configuration, for example, A / D conversion of a sequential comparison method, A / D conversion of a method similar to the sequential comparison method, and the like can be realized. The method of the present embodiment described with reference to FIGS. 11 to 13 can also be realized by devising the output mode of the temperature detection data DTD of the A / D conversion unit 20 of FIG. 38.

6. Oscillator, Electronic Equipment, Mobile Figure 39 shows a configuration example of an oscillator 400 including the circuit device 500 of this embodiment. As shown in FIG. 39, the oscillator 400 includes an oscillator 420 and a circuit device 500. The oscillator 420 and the circuit device 500 are mounted in the package 410 of the oscillator 400. The terminal of the oscillator 420 and the terminal (pad) of the circuit device 500 (IC) are electrically connected by the internal wiring of the package 410.

FIG. 40 shows a configuration example of an electronic device including the circuit device 500 of the present embodiment. This electronic device includes the circuit device 500 of the present embodiment, an oscillator 420 such as a crystal oscillator, an antenna ATN, a communication unit 510, and a processing unit 520. Further, the operation unit 530, the display unit 540, and the storage unit 550 can be included. The oscillator 400 is composed of the oscillator 420 and the circuit device 500. The electronic device is not limited to the configuration shown in FIG. 40, and various modifications such as omitting some of these components or adding other components can be performed.

Examples of the electronic device of FIG. 40 include wearable devices such as GPS built-in clocks, biometric information measuring devices (pulse wave meters, pedometers, etc.) or head-mounted display devices, smartphones, mobile phones, portable game devices, notebooks, etc. Various devices such as mobile information terminals (mobile terminals) such as PCs or tablet PCs, content providing terminals that distribute contents, video devices such as digital cameras and video cameras, and network-related devices such as base stations and routers. Can be assumed.

The communication unit 510 (wireless circuit) performs a process of receiving data from the outside or transmitting data to the outside via the antenna ATN. The processing unit 520 performs control processing of the electronic device, various digital processing of data transmitted and received via the communication unit 510, and the like. The function of the processing unit 520 can be realized by a processor such as a microcomputer.

The operation unit 530 is for the user to perform an input operation, and can be realized by an operation button, a touch panel display, or the like. The display unit 540 displays various types of information, and can be realized by a display such as a liquid crystal or an organic EL. When a touch panel display is used as the operation unit 530, the touch panel display also functions as the operation unit 530 and the display unit 540. The storage unit 550 stores data, and its function can be realized by a semiconductor memory such as RAM or ROM, an HDD (hard disk drive), or the like.

FIG. 41 shows an example of a mobile body including the circuit device of the present embodiment. The circuit device (oscillator) of the present embodiment can be incorporated into various moving bodies such as a car, an airplane, a motorcycle, a bicycle, or a ship. The moving body is, for example, a device / device provided with a drive mechanism such as an engine or a motor, a steering mechanism such as a steering wheel or a rudder, and various electronic devices (vehicle-mounted devices), and moves on the ground, in the air, or on the sea. FIG. 41 schematically shows an automobile 206 as a specific example of a moving body. An oscillator (not shown) having a circuit device and an oscillator of the present embodiment is incorporated in the automobile 206. The control device 208 operates by the clock signal generated by this oscillator. The control device 208 controls the hardness of the suspension according to, for example, the posture of the vehicle body 207, and controls the brakes of the individual wheels 209. For example, the control device 208 may realize the automatic driving of the automobile 206. The device in which the circuit device and the oscillator of the present embodiment are incorporated is not limited to such a control device 208, and can be incorporated in various devices (vehicle-mounted devices) provided in a mobile body such as an automobile 206. ..

Although the present embodiment has been described in detail as described above, those skilled in the art will easily understand that many modifications that do not substantially deviate from the novel matters and effects of the present invention are possible. Therefore, all such modifications are included in the scope of the present invention. For example, a term described at least once in a specification or drawing with a different term in a broader or synonymous manner may be replaced by that different term anywhere in the specification or drawing. Further, all combinations of the present embodiment and modifications are also included in the scope of the present invention. In addition, the configuration / operation of circuit devices, oscillators, electronic devices, and moving objects, D / A conversion method, frequency control data processing method, frequency control data output method of the processing unit, and voltage output method of the D / A conversion unit. The frequency control method of the transducer is not limited to the one described in this embodiment, and various modifications can be performed.

XTAL ... oscillator, DACF-DACF ... D / A converter,
OPA-OPD, OPS ... operational amplifier, CX1-CX3 ... capacitor,
VTD ... Temperature detection voltage, DTD ... Temperature detection data, DDS ... Frequency control data,
VQ ... Output voltage (frequency control voltage), SSC ... Oscillation signal,
T1, T2 ... 1st and 2nd temperature, DTD1, DTD2 ... 1st and 2nd temperature detection data,
VC1, VC2 ... 1st and 2nd control voltage, VDF ... differential voltage, VA ... voltage width,
TAD, TDAC ... period, TP ... predetermined period, FD ... allowable frequency drift,
FR ... Variable frequency range, VFS ... Full scale voltage,
DAT1, DAT2 ... 1st and 2nd data,
10 ... Temperature sensor unit, 20 ... A / D conversion unit, 22 ... Logic unit, 23 ... Processing unit,
24 ... Register part, 26 ... Analog part, 27 ... Comparison part,
28 ... Temperature sensor unit amplifier, 50 ... Processing unit, 52 ... Control unit, 53 ... Judgment unit,
54, 55 ... comparison unit, 58 ... multiplier, 59 ... adder, 60 ... arithmetic unit,
61, 62 ... type converter, 63 ... multiplexer, 64 ... arithmetic unit,
65 ... multiplexer, 66, 67 ... work register, 68 ... type converter,
69 ... work register, 70 ... output unit, 71 ... multiplexer,
72 ... Output register, 73 ... LSB adder, 74 ... LSB subtractor,
80 ... D / A converter, 90 ... Modulation circuit, 100 ... D / A converter,
104, 106 ... Decoder, 120 ... Filter circuit, 130 ... Filter circuit,
140 ... Oscillation signal generation circuit, 150 ... Oscillation circuit, 160 ... Buffer circuit,
180 ... Memory section, 190 ... ROM, 206 ... Automobile, 207 ... Body,
208 ... Control unit, 209 ... Wheels, 400 ... Oscillator, 410 package,
420 ... Oscillator, 500 ... Circuit device, 510 ... Communication unit, 520 ... Processing unit,
530 ... Operation unit, 540 ... Display unit, 550 ... Storage unit

Claims (15)

A / D conversion unit that performs A / D conversion of the temperature detection voltage from the temperature sensor unit and outputs temperature detection data,
A processing unit that performs temperature compensation processing for the oscillation frequency based on the temperature detection data and outputs frequency control data for the oscillation frequency.
An oscillation signal generation circuit that uses the frequency control data from the processing unit and the oscillator to generate an oscillation signal of the oscillation frequency set by the frequency control data.
Including
The oscillation signal generation circuit is
A D / A conversion unit that performs D / A conversion of the frequency control data from the processing unit,
An oscillation circuit that generates the oscillation signal using the output voltage of the D / A conversion unit and the oscillator,
Including
The D / A conversion unit
A modulation circuit that receives the frequency control data of i = (n + m) bits from the processing unit and modulates the n-bit data of the frequency control data based on the m-bit data of the frequency control data.
A D / A converter that performs D / A conversion of the modulated n-bit data, and
A filter circuit that smoothes the output voltage of the D / A converter,
Including
When the values specified by the n-bit data are DY and DZ (DY and DZ are numbers that satisfy DY = DZ + 1),
The D / A conversion unit
By combining one or more output patterns specified based on the m-bit data among m output patterns in which the DY output intervals are different from each other and the DY output timings do not overlap each other , the DY and A circuit device characterized by outputting DZ in time division. In the circuit device according to claim 1,
Wherein the sampling frequency of the D / A converter and fs, a change in the oscillation frequency due to a single D / A conversion of the D / A conversion section in the case of a Delta] f, is Δf / fs <1/10 ⁶ A circuit device characterized by that. In the circuit device according to claim 2.
When fs ≧ 1 kHz, Δf / fs <1/10 ⁶
A circuit device characterized in that Δf <1 MHz when fs <1 kHz. In the circuit device according to claim 1,
When the sampling frequency of the D / A conversion unit is fs and the change in the oscillation frequency due to one D / A conversion of the D / A conversion unit is Δf,
A circuit device characterized in that Δf <1 MHz when fs <1 kHz. In the circuit device according to any one of claims 1 to 4.
The oscillator is a circuit device characterized by being a crystal oscillator. In the circuit device according to claim 5,
The crystal unit
A circuit device characterized by being an AT-cut oscillator, an SC-cut oscillator, or a SAW resonator. In the circuit device according to any one of claims 1 to 6.
The processing unit
When the temperature changes from the first temperature to the second temperature, k × LSB (k) changes from the first data corresponding to the first temperature to the second data corresponding to the second temperature. ≧ 1) A circuit device characterized by outputting the frequency control data that changes in units. In the circuit device according to claim 7.
The processing unit
The first data, which is the calculation result data of the previous temperature compensation process, and the second data, which is the calculation result data of the temperature compensation process this time, are compared.
When the second data is larger than the first data, the process of adding a predetermined value to the first data is performed until the addition result data reaches the second data. , The addition result data is output as the frequency control data,
When the second data is smaller than the first data, the process of subtracting a predetermined value from the first data is performed until the subtraction result data reaches the second data. A circuit device characterized in that the subtraction result data is output as the frequency control data. In the circuit device according to claim 8.
The processing unit
A calculation unit that calculates the temperature compensation process of the oscillation frequency based on the temperature detection data and outputs the calculation result data of the temperature compensation process.
An output unit that receives the calculation result data from the calculation unit and outputs the frequency control data,
Including
The output unit
When the calculation result data changes from the first data corresponding to the first temperature to the second data corresponding to the second temperature, the first data is described in k × LSB units. A circuit device characterized by outputting the frequency control data that changes to the second data. In the circuit device according to any one of claims 1 to 9.
The processing unit
A circuit device characterized in that the frequency control data is output at an output rate faster than the output rate of the temperature detection data from the A / D converter. In the circuit device according to any one of claims 1 to 10.
The D / A conversion unit
A circuit device characterized in that when the minimum resolution of data in D / A conversion is LSB, the output voltage that changes with the step width of the voltage corresponding to k × LSB (k ≧ 1) is output. In the circuit device according to claim 11,
A circuit device characterized in that k = 1. The circuit device according to any one of claims 1 to 12.
With the oscillator
An oscillator characterized by including. An electronic device comprising the circuit device according to any one of claims 1 to 12. A mobile body including the circuit device according to any one of claims 1 to 12.