CN107017837B - Circuit device, oscillator, electronic apparatus, and moving object - Google Patents
Circuit device, oscillator, electronic apparatus, and moving object Download PDFInfo
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- H—ELECTRICITY
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
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Abstract
The invention provides a circuit device, an oscillator, an electronic apparatus, and a mobile object, which can suppress the occurrence of defects due to frequency drift of an oscillation frequency. The circuit device has: an A/D converter for A/D converting the temperature detection voltage from the temperature sensor unit and outputting temperature detection data; a processing unit that performs temperature compensation processing of the oscillation frequency based on the temperature detection data and outputs frequency control data of the oscillation frequency; and an oscillation signal generating circuit for generating an oscillation signal using the frequency control data and the oscillator, wherein the processing unit outputs frequency control data that changes in units of k × LSB (k ≧ 1).
Description
Technical Field
The present invention relates to a circuit device, an oscillator, an electronic apparatus, a mobile object, and the like.
Background
Conventionally, a temperature compensated oscillator called tcxo (temperature compensated crystal oscillator) is known. The TCXO is used as a reference signal source in a portable communication terminal, a GPS-related device, a wearable device, an in-vehicle device, or the like, for example.
The TCXO includes an ATCXO which is an analog temperature compensation oscillator and a DTCXO which is a digital temperature compensation oscillator. As a prior art of the ATCXO, a technique disclosed in patent document 1 is known. As a prior art of DTCXO, a technique disclosed in patent document 2 is known.
[ patent document 1 ] Japanese patent laid-open No. 2012 and 199631
[ patent document 2 ] Japanese patent laid-open No. Sho 64-82809
A digital oscillator such as DTCXO is advantageous in reducing power consumption and the like as compared with an analog oscillator such as ATCXO. For example, in the ATCXO, a large amount of consumption current flows in the analog circuit of the circuit device. In particular, in the ATCXO, in order to improve frequency accuracy, when it is desired to increase the number of times of an approximation function in a temperature compensation circuit (approximation function generating circuit) which is an analog circuit or to increase a current flowing through a transistor of the analog circuit to reduce noise, power consumption is greatly increased. Therefore, there is a problem that it is difficult to achieve both improvement of frequency accuracy and reduction of power consumption.
On the other hand, in a digital oscillator such as DTCXO, it has been found that various defects occur in a device using an oscillation signal of the oscillator when a frequency drift of an oscillation frequency accompanying a temperature change exceeds a permissible frequency drift range, for example.
Further, it has been found that noise (spurious) occurs at an intensity corresponding to the fluctuation due to the fluctuation of the oscillation frequency, and the C/N characteristics (carrier-to-noise ratio, CN ratio) of the circuit device are deteriorated. The deterioration of the C/N characteristic causes a decrease in the accuracy of data acquired from a signal from an oscillator such as a DTCXO.
Disclosure of Invention
According to some aspects of the present invention, it is possible to provide a circuit device, an oscillator, an electronic apparatus, a mobile object, and the like, in which defects caused by frequency drift of an oscillation frequency and the like can be suppressed.
One aspect of the present invention relates to a circuit device including: an A/D converter for A/D converting the temperature detection voltage from the temperature sensor unit and outputting temperature detection data; a processing unit that performs temperature compensation processing of an oscillation frequency based on the temperature detection data and outputs frequency control data of the oscillation frequency;and an oscillation signal generating circuit that generates an oscillation signal of the oscillation frequency set according to the frequency control data by using the frequency control data and the oscillator from the processing unit, wherein the processing unit outputs the frequency control data changed from 1 st data corresponding to the 1 st temperature to 2 nd data corresponding to the 2 nd temperature in units of k × LSB (k ≧ 1) when the temperature is changed from 1 st temperature to 2 nd temperature, and Δ f/fs are set when the output frequency of the frequency control data changed in units of k × LSB of the processing unit is fs and the change in the oscillation frequency due to the change in units of k × LSB of the frequency control data is Δ f<1/106。
In one embodiment of the present invention, temperature compensation processing of the oscillation frequency is performed based on the temperature detection data, and the obtained frequency control data and the oscillator are used to generate the oscillation signal. In one embodiment of the present invention, when the temperature changes from the 1 st temperature to the 2 nd temperature, the frequency control data that changes from the 1 st data to the 2 nd data in units of k × LSB is output. Thus, when the temperature changes from the 1 st temperature to the 2 nd temperature, it is possible to suppress a situation in which the frequency control data changes greatly and the oscillation frequency has a large frequency drift. Therefore, a circuit device and the like can be provided, and the occurrence of defects due to frequency drift of the oscillation frequency and the like can be suppressed. In one embodiment of the present invention, the output frequency fs of the frequency control data and the change Δ f of the oscillation frequency due to the change in the frequency control data in units of k × LSB satisfy Δ f/fs<1/106. This can suppress the deterioration of the C/N characteristics due to the spurious variation caused by the frequency control data.
In one embodiment of the present invention, Δ f/fs may be set to a value of fs ≧ 1kHz<1/106At fs, in<In the case of 1kHz,. DELTA.f<1mHz。
Thus, in order to suppress the deterioration of the C/N characteristics, an appropriate condition or the like corresponding to fs can be used.
Another aspect of the present invention relates to a circuit device including: an A/D converter for A/D converting the temperature detection voltage from the temperature sensor unit and outputting temperature detection data; a processing unit that performs temperature compensation processing of an oscillation frequency based on the temperature detection data and outputs frequency control data of the oscillation frequency; and an oscillation signal generating circuit that generates an oscillation signal of the oscillation frequency set according to the frequency control data using the frequency control data and the oscillator from the processing unit, wherein the processing unit outputs the frequency control data that changes from 1 st data corresponding to the 1 st temperature to 2 nd data corresponding to the 2 nd temperature in units of k × LSB (k ≧ 1) when the temperature changes from the 1 st temperature to the 2 nd temperature, and wherein Δ f <1mHz is provided when fs <1kHz is an output frequency of the frequency control data that changes in units of k × LSB of the processing unit and Δ f is a change in the oscillation frequency due to a change in units of k × LSB of the frequency control data.
In another aspect of the present invention, the occurrence of defects due to frequency drift of the oscillation frequency or the like can be suppressed. Further, since the condition of Δ f <1mHz is satisfied when fs <1kHz, it is possible to suppress the deterioration of the C/N characteristics due to the spurious caused by the frequency control data fluctuation.
Another aspect of the present invention relates to a circuit device including: an A/D converter for A/D converting the temperature detection voltage from the temperature sensor unit and outputting temperature detection data; a processing unit that performs temperature compensation processing of an oscillation frequency based on the temperature detection data and outputs frequency control data of the oscillation frequency; and an oscillation signal generation circuit that generates an oscillation signal of the oscillation frequency set according to the frequency control data using the frequency control data and a vibrator from the processing unit, wherein DV < (FD/FR) × DFS is set when a frequency variable range of the oscillation frequency realized by the oscillation signal generation circuit is FR, an allowable frequency drift of the oscillation frequency within a predetermined period is FD, a full-scale value of the frequency control data is DFS, and a variation value of the frequency control data at an output interval of the frequency control data of the processing unit is DV.
According to another aspect of the present invention, the temperature compensation process of the oscillation frequency is performed based on the temperature detection data, and the obtained frequency control data and the oscillator are used to generate the oscillation signal. Here, the frequency variable range of the oscillation frequency is FR, the allowable frequency drift of the oscillation frequency is FD, the full-scale value of the frequency control data is DFS, and the variation value at the output interval of the frequency control data is DV. Then, according to one embodiment of the present invention, the frequency control data is changed by a change value DV of DV < (FD/FR) × DFS. The frequency control data changes according to the change value DV, and thereby, the frequency drift of the oscillation frequency within a predetermined period can be narrowed to, for example, an allowable frequency drift. Therefore, a circuit device and the like can be provided, and the occurrence of defects due to frequency drift of the oscillation frequency and the like can be suppressed.
In another aspect of the present invention, when the output frequency of the frequency control data of the processing unit is fs, and a change in the oscillation frequency due to a change in the change value DV of the frequency control data is Δ f, Δ f/fs may be set<1/106。
In another aspect of the present invention, the change Δ f of the oscillation frequency due to the change in the output frequency fs of the frequency control data and the change value DV of the frequency control data satisfies Δ f/fs<1/106. This can suppress the deterioration of the C/N characteristic due to the spurious caused by the frequency control data fluctuation.
In another embodiment of the present invention, Δ f/fs may be set to a value of fs ≧ 1kHz<1/106，fs<In the case of 1kHz,. DELTA.f<1mHz。
Thus, in order to suppress the deterioration of the C/N characteristics, an appropriate condition or the like corresponding to fs can be used.
In another aspect of the present invention, when the output frequency of the frequency control data of the processing unit is fs and the change in the oscillation frequency due to the change in the change value DV of the frequency control data is Δ f, the Δ f may be less than 1mHz when fs is less than 1 kHz.
In another aspect of the present invention, a change Δ f of the oscillation frequency due to a change in the output frequency fs of the frequency control data and the change value DV of the frequency control data satisfies Δ f <1mHz in fs <1 kHz. This can suppress the deterioration of the C/N characteristics due to the spurious variation caused by the frequency control data.
In one embodiment of the present invention, the resonator may be a quartz resonator.
Thus, a quartz resonator can be used as the resonator.
In one embodiment of the present invention, the quartz resonator may be an AT-cut resonator, an SC-cut resonator, or a SAW (Surface Acoustic Wave) resonator.
Thus, at least one of a plurality of resonators (resonators) having different characteristics can be used as the quartz resonator.
In one aspect of the present invention, the oscillation signal generation circuit may include: a D/a conversion unit that performs D/a conversion on the frequency control data from the processing unit; and an oscillation circuit that generates the oscillation signal using an output voltage of the D/a conversion unit and the oscillator, wherein the output frequency fs of the frequency control data is a sampling frequency of the D/a conversion unit, and a change Δ f of the oscillation frequency is an amount of change in the oscillation frequency due to 1 time of the D/a conversion.
Thus, when the oscillation signal generation circuit includes the D/a conversion unit and the oscillation circuit, the sampling frequency of the D/a conversion unit can be set to fs, and the amount of change in the oscillation frequency due to 1D/a conversion can be set to Δ f.
In one aspect of the present invention, the D/a converter may include: a D/A converter that performs D/A conversion of the frequency control data; and a filter circuit that smoothes an output voltage of the D/a converter.
Thus, by smoothing the output of the D/a converter by the filter circuit, substantial fluctuation of the oscillation frequency and the like can be suppressed.
In one aspect of the present invention, when a frequency control voltage that is an output voltage of the D/a converter corresponding to a1 st temperature is a1 st control voltage, and when the frequency control voltage corresponding to a2 nd temperature is a2 nd control voltage, and when a temperature changes from the 1 st temperature to the 2 nd temperature, the D/a converter may output the output voltage to the oscillator circuit, the output voltage changing with a voltage width smaller than an absolute value of a difference voltage between the 1 st control voltage and the 2 nd control voltage.
Accordingly, when the temperature changes from the 1 st temperature to the 2 nd temperature, it is possible to suppress a situation in which the frequency control voltage, which is the output voltage of the D/a converter, greatly changes, and a large frequency drift or the like occurs in the oscillation frequency.
In one embodiment of the present invention, when the minimum resolution of data in the D/a conversion is LSB, the D/a converter may output the output voltage varying in steps of voltage corresponding to k × LSB (k ≧ 1).
Thus, the change in the output voltage of the D/A converter is limited to within the voltage step corresponding to k × LSB, and therefore, the occurrence of defects and the like due to a large voltage change in the output voltage can be suppressed.
In one embodiment of the present invention, k may be 1.
This enables the output voltage of the D/a converter to be changed in steps corresponding to 1 LSB.
In one aspect of the present invention, when the temperature detection data of the a/D converter at the temperature of the 1 st temperature is 1 st temperature detection data and the temperature detection data of the a/D converter at the temperature of the 2 nd temperature is 2 nd temperature detection data, the 1 st control voltage may be the frequency control voltage corresponding to the 1 st temperature detection data in the temperature compensation characteristic of the temperature compensation process, and the 2 nd control voltage may be the frequency control voltage corresponding to the 2 nd temperature detection data in the temperature compensation characteristic of the temperature compensation process.
Thus, the A/D converter outputs the 1 st temperature detection data when the temperature is the 1 st temperature, and outputs the 2 nd temperature detection data when the temperature is the 2 nd temperature. In this case, normally, the D/a converter outputs a1 st control voltage, which is a frequency control voltage corresponding to the 1 st temperature detection data, at the 1 st temperature, and outputs a2 nd control voltage, which is a frequency control voltage corresponding to the 2 nd temperature detection data, at the 2 nd temperature. Therefore, the output voltage of the D/a conversion section is caused to vary greatly from the 1 st control voltage to the 2 nd control voltage. In this regard, according to one embodiment of the present invention, the output voltage of the D/a conversion section changes with a voltage width smaller than the absolute value of the difference voltage between the 1 st control voltage and the 2 nd control voltage. Therefore, the occurrence of defects due to frequency drift of the oscillation frequency or the like can be effectively suppressed.
In one aspect of the present invention, the processing unit may compare the 1 st data, which is the operation result data of the previous temperature compensation process, with the 2 nd data, which is the operation result data of the current temperature compensation process, and when the 2 nd data is larger than the 1 st data, the processing unit may perform a process of adding a predetermined value to the 1 st data until addition result data reaches the 2 nd data and output the addition result data as the frequency control data, and when the 2 nd data is smaller than the 1 st data, the processing unit may perform a process of subtracting a predetermined value from the 1 st data until subtraction result data reaches the 2 nd data and output the subtraction result data as the frequency control data.
Thus, by performing the processing of adding a predetermined value to the 1 st data or the processing of subtracting a predetermined value from the 1 st data, the frequency control data can be changed in units of k × LSB.
In one aspect of the present invention, the processing unit may include: a calculation unit that performs calculation of the temperature compensation processing of the oscillation frequency based on the temperature detection data and outputs the calculation result data of the temperature compensation processing; and an output unit that receives the operation result data from the operation unit and outputs the frequency control data, wherein when the operation result data changes from the 1 st data corresponding to the 1 st temperature to the 2 nd data corresponding to the 2 nd temperature, the output unit outputs the frequency control data that changes from the 1 st data to the 2 nd data in k × LSB units.
Thus, the temperature compensation process of the oscillation frequency can be realized by the calculation process in the calculation unit. When the operation result data from the operation unit changes from the 1 st data to the 2 nd data, the output unit outputs frequency control data that changes from the 1 st data to the 2 nd data in units of k × LSB. Thus, when the temperature changes from the 1 st temperature to the 2 nd temperature, the frequency control data changing from the 1 st data corresponding to the 1 st temperature to the 2 nd data corresponding to the 2 nd temperature in units of k × LSB can be output from the processing unit.
Another embodiment of the present invention relates to an oscillator including any of the above-described circuit devices and the above-described oscillator.
Another embodiment of the present invention relates to an electronic device including any of the above-described circuit devices.
Another aspect of the present invention relates to a mobile body including any of the circuit devices described above.
Drawings
Fig. 1 is a graph of frequency accuracy versus chip size.
Fig. 2 is a graph showing the frequency drift of the ATCXO.
Fig. 3 is a graph showing frequency drift of a conventional DTCXO.
Fig. 4 shows a basic configuration example of the circuit device according to the present embodiment.
Fig. 5 is a detailed configuration example of the circuit device of the present embodiment.
Fig. 6 is a diagram showing an example of temperature characteristics of the vibrator and variations thereof.
Fig. 7 is an explanatory diagram of the temperature compensation process of the present embodiment.
Fig. 8 is an explanatory diagram of a communication error due to frequency drift.
Fig. 9 is an explanatory diagram of changes in the frequency control voltage when changing from the 1 st temperature to the 2 nd temperature.
Fig. 10 is an explanatory diagram of changes in the frequency control voltage when changing from the 1 st temperature to the 2 nd temperature.
Fig. 11 is an explanatory diagram of the method of the present embodiment.
Fig. 12 is an explanatory diagram of the method of the present embodiment.
Fig. 13 is an explanatory diagram of the method of the present embodiment.
Fig. 14 is an explanatory diagram relating to frequency hopping.
Fig. 15 is an explanatory diagram of improvement in frequency drift when the method of the present embodiment is employed.
Fig. 16 is an explanatory diagram of the relationship between the C/N characteristics of the vibrator and the parasitics that deteriorate the C/N characteristics.
Fig. 17 is a diagram showing an example of parasitic characteristics corresponding to Δ f and fs.
FIG. 18 is a diagram showing an example of setting Δ f and fs that do not deteriorate C/N characteristics.
Fig. 19 is an explanatory diagram of a method of changing the settings of Δ f and fs in time series.
Fig. 20 is a detailed configuration example of the processing unit.
Fig. 21 is an explanatory diagram of a method of changing the frequency control data in units of k × LSB.
Fig. 22 is an explanatory diagram of a method of changing the frequency control data in units of k × LSB.
Fig. 23 shows a detailed configuration example of the D/a converter.
Fig. 24 shows a more detailed configuration example of the D/a converter.
Fig. 25 is an explanatory diagram of PWM modulation.
Fig. 26 is an explanatory diagram of PWM modulation.
Fig. 27 is an explanatory diagram of PWM modulation.
Fig. 28 is a detailed configuration example of the temperature sensor section.
Fig. 29 is a detailed configuration example of the temperature sensor section.
Fig. 30 is an explanatory view of the temperature sensor unit.
Fig. 31 is a detailed configuration example of the oscillation circuit.
Fig. 32 is an explanatory diagram of a modification of the present embodiment.
Fig. 33 is an explanatory diagram of a modification of the present embodiment.
Fig. 34 is an explanatory diagram of a modification of the present embodiment.
Fig. 35 is a diagram illustrating frequency drift in a modification.
Fig. 36 is a diagram illustrating frequency drift in a modification.
Fig. 37 is a diagram illustrating frequency drift in a modification.
Fig. 38 shows a detailed configuration example of the a/D conversion section.
Fig. 39 is a configuration example of a circuit device according to a modification of the present embodiment.
Fig. 40 shows an example of the structure of the oscillator.
Fig. 41 shows an example of the configuration of the electronic device.
Fig. 42 shows a configuration example of the mobile body.
PREFERRED EMBODIMENTS FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all of the configurations described in the present embodiment are not necessarily means for solving the present invention.
1. Frequency drift
In a TCXO that is a temperature compensation oscillator, improvement in frequency accuracy and reduction in power consumption are required. For example, wearable devices such as GPS-equipped timepieces and devices for measuring vital information such as pulse have been required to have a prolonged battery-operated time duration. Therefore, the TCXO as a reference signal source is required to consume less power while ensuring frequency accuracy.
Various communication schemes have been proposed as communication schemes between a communication terminal and a base station. For example, in the tdd (time Division duplex) scheme, each device transmits data in divided time slots. Further, by setting an isolation time between slots (uplink slot and downlink slot), overlapping of slots can be prevented. In the next-generation communication system, it is proposed to perform data communication in TDD using, for example, 1 frequency band (e.g., 50 GHz).
However, in the case of such a TDD scheme, time synchronization is required in each device, and a clock with accurate absolute time is required. In order to meet such a demand, for example, a method of providing an atomic clock (atomic oscillator) as a reference signal source in each device is conceivable, but this causes problems such as high cost of the device and large size of the device.
The TCXO includes an ATCXO as an analog temperature compensation oscillator and a DTCXO as a digital temperature compensation oscillator.
When the ATCXO is used as the reference signal source, if the frequency accuracy is to be improved, as shown in fig. 1, the chip size of the circuit device increases, and it is difficult to reduce the cost and power consumption.
On the other hand, the DTCXO has an advantage that the chip size of the circuit device does not become excessively large and the frequency accuracy can be improved as shown in fig. 1.
However, in a digital oscillator such as DTCXO, there is a problem that a communication error or the like occurs in a communication device incorporating the oscillator due to frequency drift of the oscillation frequency. For example, in a digital oscillator, a temperature detection voltage from a temperature sensor unit is a/D converted, temperature compensation processing of frequency control data is performed based on the obtained temperature detection data, and an oscillation signal is generated based on the frequency control data. In this case, it has been found that when the value of the frequency control data is greatly changed due to a temperature change, a problem of frequency hopping occurs. When such frequency hopping occurs, a problem such as a GPS lock falling occurs, for example, in a communication device related to a GPS.
Therefore, various circuit systems have been proposed for digital oscillators such as DTCXO, but at present, an analog oscillator such as ATCXO is used as a reference signal source for an actual product in which such a communication error is a problem, and almost no digital oscillator is used.
For example, fig. 2 is a graph showing the frequency drift of the ATCXO. In the ATCXO, as shown in fig. 2, when the temperature changes with the passage of time, the frequency drift thereof also shrinks within a range (± FD) of allowable frequency drift (allowable frequency error). In fig. 2, the frequency drift (frequency error) is expressed by a ratio (frequency probability, ppb) to a nominal oscillation frequency (for example, around 16 MHz). In order to prevent communication errors, for example, it is necessary to narrow the frequency drift within a range (FD) that allows the frequency drift within a predetermined period TP (20msec, for example). The FD is, for example, about several ppb.
On the other hand, fig. 3 is a graph showing frequency drift when using a conventional DTCXO. As shown in fig. 3, in the conventional DTCXO, the frequency drift is not narrowed within a range that allows the frequency drift, and frequency hopping beyond the range is generated. Therefore, a communication error (lock-out of GPS or the like) due to the frequency hopping occurs, and this becomes an obstacle to the use of DTCXO as a reference signal source for an actual product.
Further, the oscillator is known to generate phase noise corresponding to the characteristics of the oscillator. D1 in fig. 16, which will be described later, is an example of a general C/N characteristic of a quartz resonator, and the intensity of phase noise (unit dBc/Hz on the vertical axis) is inversely proportional to the third power of the detuning frequency f at a position where the detuning frequency (unit Hz on the horizontal axis) with respect to the oscillation frequency is low, and inversely proportional to the second power of f in a range of about 1k to 10 kHz. In the frequency range of 10kHz or less, the influence of so-called 1/f noise is large. On the other hand, at frequencies higher than 10kHz, the influence of thermal noise is large, and the characteristic is flat regardless of f. That is, it is inevitable that a signal having a frequency other than the desired oscillation frequency is generated in the characteristics of the oscillator, and in an oscillator (and a circuit device including the oscillator) such as DTCXO, a design is performed in which there is no problem even if phase noise having a C/N characteristic such as D1 is generated.
However, in the DTCXO, an output frequency fs of data (frequency control data DDS) for controlling the oscillation frequency and a spurious component of the intensity corresponding to the change Δ f of the oscillation frequency are generated. Detailed description of the inventionThe parasitic component generated is fs with respect to the offset frequency of the fundamental wave (oscillation frequency) and is equal to (Δ f/fs) in intensity, as described later using the following equation (10) or the like2The corresponding value. Further, depending on the values of fs and Δ f, there is a possibility that spurious signals having a strength larger than the original phase noise of the oscillator shown in D1 may occur. D2 in fig. 16 is an example of parasitics when Δ f is 0.1Hz and fs is 100kHz, and D3 is an example of parasitics when Δ f is 0.1Hz and fs is 600 kHz. Any spurious D2, D3 is stronger than the original phase noise (D1) of the oscillator.
Since the parasitics shown by D2, D3 are generated, the signal strength at a frequency other than the desired oscillation frequency relatively increases, and the C/N characteristic of the oscillator 400 deteriorates. The deterioration of the C/N characteristic is related to the decrease in data accuracy obtained using the oscillation signal. For example, in the case of the above-described GPS, the accuracy of the GPS reception signal, specifically, the accuracy of the position information obtained from the GPS reception signal, is lowered. Thus, the generation of spurious signals corresponding to frequency fluctuations is also an obstacle to the use of DTCXOs as a reference signal source for an actual product. Further, the parasitics shown in D2 and D3 in fig. 16 deteriorate the C/N characteristics without decreasing the intensity thereof. Thus, if noise reduction processing for reducing the parasitic intensity by smoothing or the like of the filter circuit is performed, the method of the present embodiment does not hinder the use of the values of Δ f and fs corresponding to D2 and D3. The details will be described later.
2. Structure of the product
Fig. 4 shows a basic configuration example of the circuit device of the present embodiment. The circuit device is a circuit device (semiconductor chip) that realizes a digital oscillator such as DTCXO and OCXO. For example, by housing the circuit device and the oscillator XTAL in a package, a digital oscillator can be realized.
The circuit device of fig. 4 includes an a/D conversion unit 20, a processing unit 50, and an oscillation signal generation circuit 140. The circuit device may further include a temperature sensor unit 10 and a buffer circuit 160. The configuration of the circuit device is not limited to the configuration shown in fig. 4, and various modifications may be made to omit some of the components (for example, a temperature sensor unit, a buffer circuit, an a/D converter unit, and the like), add other components, and the like.
The vibrator XTAL is a piezoelectric vibrator such as a quartz vibrator. The oscillator XTAL may be an oven (oven) type oscillator (OCXO) provided in an oven chamber. The vibrator XTAL may be a resonator (an electromechanical resonator or an electrical resonant circuit). As the vibrator XTAL, a piezoelectric vibrator, a saw (surface Acoustic wave) resonator, an mems (micro Electro Mechanical systems) vibrator, or the like can be used. As a substrate material of the resonator XTAL, a piezoelectric single crystal such as quartz, lithium tantalate, or lithium niobate, a piezoelectric material such as piezoelectric ceramics such as lead zirconate titanate, or a silicon semiconductor material can be used. As the oscillation means of the vibrator XTAL, a means based on a piezoelectric effect may be used, and electrostatic driving based on coulomb force may be used.
The temperature sensor section 10 outputs a temperature detection voltage VTD. Specifically, a temperature-dependent voltage that varies depending on the temperature of the environment (circuit device) is output as the temperature detection voltage VTD. A specific configuration example of the temperature sensor section 10 will be described later.
The a/D conversion unit 20 performs a/D conversion of the temperature detection voltage VTD from the temperature sensor unit 10 and outputs temperature detection data DTD. For example, digital temperature detection data DTD (a/D result data) corresponding to the a/D conversion result of the temperature detection voltage VTD is output. As the a/D conversion method of the a/D conversion unit 20, for example, a successive approximation method, a method similar to the successive approximation method, or the like can be used. The a/D conversion method is not limited to this method, and various methods (counter type, parallel comparison type, series-parallel type, or the like) can be used.
The processing unit 50(DSP unit: digital signal processing unit) performs various kinds of signal processing. For example, the processing unit 50 (temperature compensation unit) performs temperature compensation processing of the oscillation frequency (frequency of the oscillation signal) based on the temperature detection data DTD. Then, the frequency control data DDS of the oscillation frequency is output. Specifically, the processing unit 50 performs temperature compensation processing for making the oscillation frequency constant even when the temperature changes, based on temperature detection data DTD (temperature-dependent data) that changes according to the temperature, coefficient data for temperature compensation processing (data of a coefficient of an approximation function), and the like. The processing unit 50 may be implemented by an ASIC circuit such as a gate array, or may be implemented by a processor and a program operating on the processor.
The oscillation signal generation circuit 140 generates an oscillation signal SSC. For example, the oscillation signal generation circuit 140 generates an oscillation signal SSC of an oscillation frequency set by the frequency control data DDS using the frequency control data DDS and the oscillator XTAL from the processing unit 50. For example, the oscillation signal generation circuit 140 generates the oscillation signal SSC by oscillating the oscillator XTAL at an oscillation frequency set according to the frequency control data DDS.
The oscillation signal generation circuit 140 may be a circuit that generates the oscillation signal SSC by a direct digital synthesizer method. For example, an oscillation signal of the oscillator XTAL (oscillation source of a fixed oscillation frequency) may be used as a reference signal, and the oscillation signal SSC of the oscillation frequency set by the frequency control data DDS may be digitally generated.
The oscillation signal generation circuit 140 may include a D/a conversion section 80 and an oscillation circuit 150. However, the oscillation signal generation circuit 140 is not limited to such a configuration, and various modifications may be made such as omitting a part of the components or adding another component.
The D/a conversion unit 80 performs D/a conversion of the frequency control data DDS (output data of the processing unit) from the processing unit 50. The frequency control data DDS input to the D/a conversion unit 80 is frequency control data (frequency control code) after the temperature compensation process of the processing unit 50. For example, a resistor string type (resistor division type) can be adopted as the D/a conversion method of the D/a conversion section 80. However, the D/a conversion method is not limited to this, and various methods such as a resistance ladder type (R-2R ladder type, etc.), a capacitance array type, or a pulse width modulation type may be employed. The D/a converter 80 may include a control circuit, a modulation circuit, a filter circuit, and the like, in addition to the D/a converter.
As described above, the oscillation circuit 150 can be realized by a direct digital synthesizer system, and in this case, the oscillation frequency of the oscillator XTAL becomes a reference frequency and a frequency different from the oscillation frequency of the oscillation signal SSC.
The buffer circuit 160 buffers the oscillation signal SSC generated by the oscillation signal generation circuit 140 (oscillation circuit 150), and outputs a buffered signal SQ. That is, buffering is performed for enabling sufficient driving of the external load. Signal SQ is, for example, a clipped sine wave signal. However, the signal SQ may be a square wave signal. Alternatively, the buffer circuit 160 may be a circuit capable of outputting both the clipped sine wave signal and the rectangular wave signal as the signal SQ.
Fig. 5 shows a detailed configuration example of the circuit device of the present embodiment. In fig. 5, the D/a converter 80 includes a modulation circuit 90, a D/a converter 100, and a filter circuit 120.
The modulation circuit 90 of the D/a conversion unit 80 receives frequency control data DDS (i, n, m are integers equal to or greater than 1) of i ═ n + m bits from the processing unit 50. For example, i is 20, n is 16, and m is 4. The modulation circuit 90 modulates n-bit (for example, 16-bit) data of the frequency control data DDS based on m-bit (for example, 4-bit) data of the frequency control data DDS. Specifically, the modulation circuit 90 performs PWM modulation of the frequency control data DDS. The modulation method of the modulation circuit 90 is not limited to PWM modulation (pulse width modulation), and may be pulse modulation such as PDM modulation (pulse density modulation), or may be a modulation method other than pulse modulation. For example, bit spreading (bit spreading from n bits to i bits) may be realized by performing dither processing (dither processing) on n bits of frequency control data DDS.
The D/a converter 100 performs D/a conversion of the n-bit data modulated by the modulation circuit 90. For example, D/a conversion of data having 16 bits n is performed. As a D/a conversion method of the D/a converter 100, for example, a resistor string type, a resistor ladder type, or the like can be used.
The filter circuit 120 smoothes the output voltage VDA of the D/a converter 100. For example, low-pass filtering is performed to smooth the output voltage VDA. By providing such a filter circuit 120, for example, PWM demodulation of a PWM-modulated signal can be performed. The cutoff frequency of the filter circuit 120 may be set according to the frequency of the PWM modulation of the modulation circuit 90. That is, since the signal of the output voltage VDA from the D/a converter 100 includes the fundamental frequency of the PWM modulation and the ripple (ripple) of the harmonic component, the ripple is attenuated by the filter circuit 120. The filter circuit 120 may be a passive filter using a passive element such as a resistor or a capacitor. However, an active filter such as an SCF may be used as the filter circuit 120.
As will be described later, in order to suppress the occurrence of a communication error due to the frequency hopping described in fig. 3 and improve the frequency accuracy, it is necessary to increase the resolution of the D/a conversion section 80 as high as possible.
However, it is difficult to realize high-resolution D/a conversion, for example, i ═ 20 bits, only by using the D/a converter 100 of, for example, a resistor string type. Further, when the output noise of the D/a conversion section 80 is large, it is difficult to achieve an improvement in frequency accuracy due to the noise.
Therefore, in fig. 5, a modulation circuit 90 is provided in the D/a conversion section 80. The processing unit 50 outputs frequency control data DDS having i ═ m + n bits, which has more bits than n bits (for example, 16 bits) that are the resolution of the D/a converter 100. The processing unit 50 performs floating point arithmetic and the like in order to realize digital signal processing such as temperature compensation processing, and therefore, it is easy to output such frequency control data DDS having i + n bits that have more bits than n bits (for example, n is 16 bits).
The modulation circuit 90 modulates (e.g., PWM modulation) n-bit data i-m + n based on m-bit data i-m + n, and outputs the modulated n-bit data DM to the D/a converter 100. The D/a converter 100 performs D/a conversion of the data DM and the filter circuit 120 performs smoothing processing of the obtained output voltage VDA, thereby realizing high-resolution D/a conversion of i + n bits (for example, 20 bits).
According to this configuration, for example, a resistor string type or the like with less output noise can be used as the D/a converter 100, and therefore, the output noise of the D/a converter 80 can be reduced, and deterioration in frequency accuracy can be easily suppressed. For example, although noise is generated by modulation by the modulation circuit 90, the noise can be sufficiently attenuated by setting the cutoff frequency of the filter circuit 120, and deterioration in frequency accuracy due to the noise can be suppressed.
The resolution of the D/a converter 80 is not limited to i of 20 bits, and may be higher than 20 bits or lower than 20 bits. The number of modulation bits of the modulation circuit 90 is not limited to m ═ 4 bits, and may be larger than 4 bits (for example, m ═ 8 bits) or smaller than 4 bits.
In fig. 5, a case where the processing unit 50 for performing digital signal processing such as temperature compensation processing is provided in a stage prior to the D/a conversion unit 80 is effectively utilized. In other words, the processing unit 50 executes digital signal processing such as temperature compensation processing with high accuracy by, for example, floating point arithmetic operation. Therefore, for example, the low order bits of the mantissa of the floating point operation result are also handled as valid data, and if the data is converted into binary data, it is also possible to easily output frequency control data DDS having a high bit number, for example, i ═ m + n ═ 20 bits. In fig. 5, with this in mind, the frequency control data DDS having the high bit number i of m + n bits is supplied to the D/a converter 80, and the high-resolution D/a conversion having the i of m + n bits is successfully achieved using the m-bit modulation circuit 90 and the n-bit D/a converter 100.
By setting the resolution of the D/a converter 80 to a high resolution in this way, the occurrence of the frequency hopping can be suppressed. This can suppress the occurrence of communication errors and the like due to frequency hopping.
In addition to the problem of such frequency hopping, a very high frequency accuracy of an oscillation frequency is required in a digital oscillator such as a DTCXO or an OCXO. For example, in the TDD scheme, uplink and downlink transmit and receive data in a time division manner using the same frequency, and an isolation time is set between time slots allocated to the respective devices. Therefore, in order to realize appropriate communication, time synchronization is required in each device, and a clock with accurate absolute time is required. For example, when a hold phenomenon (hold) occurs in which a reference signal (GPS signal or signal via the internet) disappears or is abnormal, it is necessary to accurately count the absolute time by the oscillator side in a state where there is no reference signal. Therefore, an oscillator used for such a device (GPS-related device, base station, etc.) requires very high oscillation frequency accuracy.
In order to meet such a demand, for example, when a method of setting an atomic clock or the like for each device is adopted, the cost and the scale of the device are increased. Further, it is not desirable that the oscillator with high frequency accuracy be realized, but it results in a large-scale circuit device for the oscillator or a very large power consumption.
In this regard, according to the configuration of the circuit device of fig. 5, the D/a converter 80 having a very high resolution, i.e., i ≧ 20 bits, can be realized by merely providing the modulation circuit 90 and the filter circuit 120 to the D/a converter 80, and by increasing the resolution in this way, the oscillation frequency can be highly accurate. In addition, the increase in the chip size or the increase in the power consumption of the circuit device due to the provision of the modulation circuit 90 and the filter circuit 120 in this manner is not so large. In addition, the processing unit 50 can easily output the frequency control data DDS, i ≧ 20 bits, for example, to the D/a conversion unit 80 while realizing the temperature compensation processing by floating point arithmetic or the like. The structure of the circuit arrangement of fig. 5 therefore has the following advantages: the high accuracy of the oscillation frequency and the increase in the scale and power consumption of the circuit device can be suppressed at the same time.
The circuit devices of fig. 4 and 5 can also be used as an oscillation IC in a PLL circuit having a phase comparison circuit that compares a reference signal (GPS signal or signal via the internet) with an input signal based on an oscillation signal. In this case, the processing unit 50 may perform temperature compensation processing, aging correction processing, or the like on the frequency control data from the phase comparison circuit, and generate the oscillation signal by the oscillation signal generation circuit 140.
When the temperature changes from the 1 st temperature to the 2 nd temperature, the processing unit 50 outputs the frequency control data DDS that changes (changes k × LSB each time) in units of k × LSB from the 1 st data corresponding to the 1 st temperature (1 st temperature detection data) to the 2 nd data corresponding to the 2 nd temperature (2 nd temperature detection data). Here, k is not less than 1, and k is an integer of 1 or more. For example, when the number of bits of the frequency control data DDS (resolution of the D/A converter) is i, k is<2iK is AND 2iCompared to a sufficiently small integer (e.g., k 1-8). More specifically, k<2m. For example, when k is 1, the processing unit 50 outputs frequency control data DDS in which 1LSB is the unit (1 bit unit) and the 1 st data is changed to the 2 nd data. That is, the frequency control data DDS is output which changes from 1 st data to 2 nd data by 1LSB (1 bit) shift. The change step of the frequency control data DDS is not limited to 1LSB, and may be, for example, 2 × LSB or more, such as 2 × LSB, 3 × LSB, and 4 × LSB · · s.
For example, the processing unit 50 includes an arithmetic unit 60 and an output unit 70. The calculation unit 60 calculates temperature compensation processing of the oscillation frequency based on the temperature detection data DTD. The temperature compensation process is realized by digital signal processing based on, for example, floating point operation or the like. The output unit 70 receives the calculation result data CQ from the calculation unit 60 and outputs frequency control data DDS. When the calculation result data CQ is changed from the 1 st data corresponding to the 1 st temperature to the 2 nd data corresponding to the 2 nd temperature, the output unit 70 performs an output process of the frequency control data DDS for changing the 1 st data to the 2 nd data in units of k × LSB.
Accordingly, if the frequency control data DDS output from the processing unit 50 changes by k × LSB every time, for example, when the temperature changes from the 1 st temperature to the 2 nd temperature, the output voltage VQ of the D/a conversion unit 80 changes greatly in voltage, and the occurrence of the frequency hopping in fig. 3 due to the voltage change can be suppressed. This can prevent occurrence of a communication error or the like due to the frequency hopping.
More specifically, the processing unit 50 compares the 1 st data, which is the calculation result data (CQ) of the temperature compensation process of the previous time (previous timing), with the 2 nd data, which is the calculation result data of the temperature compensation process of the current time (current timing).
When the 2 nd data is larger than the 1 st data, the processing unit 50 (output unit 70) performs a process of adding a predetermined value to the 1 st data, for example, a process of adding k × LSB as the predetermined value. For example, when k is 1, a process of adding 1LSB as a predetermined value is performed. The predetermined value to be added is not limited to 1LSB, and may be 2 × LSB or more. The processing unit 50 performs this addition processing until the addition result data reaches the 2 nd data, for example, and outputs the addition result data as frequency control data DDS.
On the other hand, when the 2 nd data corresponding to the 2 nd temperature is smaller than the 1 st data corresponding to the 1 st temperature, the processing unit 50 (output unit 70) performs a process of subtracting a predetermined value from the 1 st data. For example, a process of subtracting k × LSB as a predetermined value is performed. For example, when k is 1, the process of subtracting 1LSB from the predetermined value is performed. The predetermined value to be subtracted is not limited to 1LSB, and may be 2 × LSB or more. The processing unit 50 performs the subtraction processing until the subtraction result data reaches the 2 nd data, for example, and outputs the subtraction result data as frequency control data DDS.
Thus, if the frequency control data DDS is output by adding a predetermined value to the 1 st data or subtracting a predetermined value from the 1 st data, the frequency control data DDS can be output in units of k × LSB corresponding to the predetermined value, for example, when the arithmetic result data of the temperature compensation process is changed from the 1 st data corresponding to the 1 st temperature to the 2 nd data corresponding to the 2 nd temperature.
In the 1 st mode (normal mode), the processing unit 50 (output unit 70) performs output processing of the frequency control data DDS that changes in units of k × LSB. This can suppress the occurrence of communication errors and the like due to frequency hopping.
On the other hand, in the 2 nd mode (high speed mode), the processing unit 50 does not perform the output processing of the frequency control data DDS that changes in units of k × LSB, but outputs the calculation result data of the temperature compensation processing as the frequency control data DDS. Specifically, the calculation result data CQ from the calculation unit 60 is output as the frequency control data DDS. Thereby, the frequency control data DDS that changes at a higher speed than in the 1 st mode can be supplied to the D/a conversion section 80, and a high-speed mode can be realized.
The 1 st mode is set when the circuit device is normally operated (during normal operation). On the other hand, the 2 nd mode is set, for example, at the time of starting up (during start-up) or at the time of inspection (during test). That is, the circuit device is set to the 2 nd mode in the operation other than the normal operation.
For example, by setting the 1 st mode at the time of normal operation of the circuit device, the processing unit 50 outputs the frequency control data DDS that changes in units of k × LSB. This prevents problems such as frequency hopping and achieves high accuracy of the oscillation frequency.
On the other hand, by setting the mode 2 at the time of starting or checking the circuit device, the processing of changing the frequency control data DDS in units of k × LSB is not performed, and the calculation result data CQ from the calculation unit 60 is directly output as the frequency control data DDS. This can shorten the startup time of the circuit device, and can start the circuit device at high speed. In addition, the inspection period (test period) in manufacturing the circuit device, the oscillator, or the like can be shortened, and the manufacturing period can be shortened.
In the present embodiment, the processing unit 50 outputs the frequency control data DDS at an output rate faster than the output rate of the temperature detection data DTD from the a/D conversion unit 20. Thereby, the frequency control data DDS can be output with the change from the 1 st data to the 2 nd data in k × LSB units. For example, the frequency control data DDS can be changed in a stepwise manner every k × LSB during a period corresponding to the a/D conversion period.
Fig. 6 is a diagram showing an example of frequency deviation of the oscillation frequency due to the temperature of the oscillator XTAL (AT oscillator or the like). The processing unit 50 performs temperature compensation processing for keeping the oscillation frequency of the oscillator XTAL having the temperature characteristic shown in fig. 6 constant regardless of the temperature.
Specifically, the processing unit 50 executes temperature compensation processing for making the output data (temperature detection data) of the a/D conversion unit 20 and the input data (frequency control data) of the D/a conversion unit 80 correspond to each other as shown in fig. 7. The correspondence relationship (frequency correction table) in fig. 7 can be obtained by, for example, placing an oscillator equipped with a circuit device in a thermostatic bath, and monitoring input data (DDS) of the D/a conversion unit 80 and output data (DTD) of the D/D conversion unit 20 at each temperature.
Then, coefficient data of an approximation function for temperature compensation for realizing the correspondence relationship of fig. 7 is stored in a memory unit (nonvolatile memory) of the circuit device. The processing unit 50 performs an arithmetic process based on the coefficient data read from the memory unit and the temperature detection data DTD from the a/D conversion unit 20, thereby realizing a temperature compensation process for keeping the oscillation frequency of the oscillator XTAL constant without depending on the temperature.
The temperature detection voltage VTD of the temperature sensor portion 10 has, for example, negative temperature characteristics as described later. Therefore, the temperature dependence of the oscillation frequency of the oscillator XTAL of fig. 6 can be compensated by cancellation using the temperature compensation characteristic shown in fig. 7.
3. Method of the present embodiment
Next, the method of the present embodiment will be described in detail. First, a communication error of gps (global Positioning system) due to frequency hopping will be described with reference to fig. 8. The C/N characteristics and parasitics of the oscillator 400 will be described with reference to fig. 16 to 19.
3.1 frequency hopping
The GPS satellite includes information on satellite orbit, time of day, and the like in the navigation message of fig. 8, and transmits the information as a GPS satellite signal at a data rate of 50 BPs. Thus, the length of 1 bit is 20msec (20 periods of the PN code). The 1 navigation message is composed of 1 main frame, and the 1 main frame is composed of 25 frames composed of 1500 bits.
The GPS satellite signal is modulated in a BPSK modulation manner according to the bit value of the navigation message as shown in fig. 8. Specifically, BPSK modulation is performed by multiplying the navigation message by a PN code (pseudo random code) to perform spectrum spreading, and multiplying the spectrum-spread signal by a carrier (1575.42 MHz). In fig. 8, the PN code of part B1 of the navigation message is shown, and the carrier of part B2 of the PN code is shown. The timing of the change in the logic level of the PN code is phase reversal of the carrier as shown by B3. The carrier 1-wavelength period is about 0.635 ns. The GPS receiver receives a carrier of the navigation message modulated in the BPSK modulation scheme, and demodulates a received signal of the carrier to obtain the navigation message.
In such demodulation processing of the received signal, if the residual frequency with respect to the frequency of the carrier (1575.42MHz) is not narrowed to within 4Hz/20msec, an erroneous determination occurs in the demodulation processing. That is, if the residual frequency with respect to the frequency of the carrier is not narrowed to within 4Hz within a period TP of 1 bit length of the GPS navigation message (the period of the GPS navigation message) of 20msec, a communication error due to frequency hopping occurs.
Since the ratio of the 4Hz to the frequency 1575.42MHz of the carrier wave is about several ppb, the allowable frequency drift FD shown in fig. 2 and 3 is also about several ppb.
In a receiver of GPS, for example, the frequency of a carrier wave in demodulation processing is set based on an oscillation signal generated by a circuit device (oscillator) according to the present embodiment. Therefore, the frequency drift of the oscillation frequency of the oscillation signal needs to be narrowed to ± FD within TP 20 msec. This prevents erroneous determination from occurring in the demodulation processing of the received signal of the GPS satellite signal, and thus avoids occurrence of a communication error (reception error).
However, in a conventional digital oscillator such as DTCXO, the frequency drift is not suppressed within ± FD (about several ppb) in the period TP (20 msec). Therefore, there is a problem that a communication error occurs due to an erroneous determination in the demodulation process due to the frequency hopping shown in fig. 3.
Therefore, in the present embodiment, the problem of the frequency hopping is solved by using the method described in fig. 9 to fig. 13 and the like.
In fig. 9, the frequency control voltage corresponding to the 1 st temperature T1 is set as the 1 st control voltage VC 1. In addition, the frequency control voltage corresponding to the 2 nd temperature T2 is set as the 2 nd control voltage VC 2. The frequency control voltage (oscillation control voltage) is a frequency control voltage of the oscillation circuit 150 in fig. 4 and 5, and corresponds to, for example, the output voltage VQ of the D/a converter 80. The 1 st temperature T1 and the 2 nd temperature T2 are temperatures detected by the temperature sensor unit 10, and correspond to the temperature detection data DTD from the a/D conversion unit 20.
For example, the temperature detection data DTD of the a/D conversion section 20 at the 1 st temperature T1 is assumed to be the 1 st temperature detection data DTD 1. The temperature detection data DTD of the a/D conversion section 20 at the 2 nd temperature T2 is assumed to be the 2 nd temperature detection data DTD 2.
In this case, the 1 st control voltage VC1 in fig. 9 becomes a frequency control voltage corresponding to the 1 st temperature detection data DTD1 in the temperature compensation characteristic described in fig. 7. In addition, the 2 nd control voltage VC2 becomes a frequency control voltage corresponding to the 2 nd temperature detection data DTD2 under the above temperature compensation characteristic.
In fig. 9, for convenience, a case where the frequency control voltage is increased when the temperature is increased is assumed. That is, as is apparent from fig. 6 and 7, when the temperature increases, there is a temperature range in which the frequency control voltage increases, and there is also a temperature range in which the frequency control voltage decreases, and the description will be given assuming the former case.
As shown in fig. 10, in the case of a change from the 1 st temperature T1 to the 2 nd temperature T2, the differential voltage of the 1 st control voltage VC1 and the 2 nd control voltage VC2 is VDF. Therefore, if no study is made, in the case of changing from the 1 st temperature T1 to the 2 nd temperature T2, the output voltage VQ of the D/a conversion section 80 changes from VC1 to VC 2. That is, the output voltage VQ of the D/a conversion section 80 changes in steps of the differential voltage VDF.
That is, as described above, the 1 st control voltage VC1 becomes a frequency control voltage corresponding to the 1 st temperature detection data DTD1 and the 2 nd control voltage VC2 becomes a frequency control voltage corresponding to the 2 nd temperature detection data DTD2 under the temperature compensation characteristic of fig. 7. Therefore, normally, the D/a converter 80 outputs the 1 st control voltage VC1, which is a frequency control voltage corresponding to the 1 st temperature detection data DTD1, at the 1 st temperature T1, and outputs the 2 nd control voltage VC2, which is a frequency control voltage corresponding to the 2 nd temperature detection data DTD2, at the 2 nd temperature T2. Therefore, the output voltage VQ of the D/a conversion section 80 changes from the 1 st control voltage VC1 to the 2 nd control voltage VC2, changing greatly in steps of the differential voltage VDF.
When the output voltage VQ of the D/a converter 80 is greatly changed by the step of the differential voltage VDF in this way, the frequency hopping shown in fig. 3 occurs. That is, the oscillation circuit 150 in fig. 4 and 5 oscillates the oscillator XTAL using the output voltage VQ of the D/a converter 80 as the frequency control voltage. Therefore, when the output voltage VQ of the D/a converter 80 changes in steps of the differential voltage VDF, the oscillation frequency of the oscillator XTAL also changes in steps corresponding to the differential voltage VDF. As a result, the frequency hopping shown in fig. 3 occurs, and the communication error described in fig. 8 occurs.
Therefore, in the present embodiment, as shown in fig. 11, when the temperature changes from the 1 st temperature T1 to the 2 nd temperature T2, the output voltage VQ that changes with a voltage width smaller than the absolute value of the differential voltage VDF of the 1 st control voltage VC1 and the 2 nd control voltage VC2 is output from the D/a conversion section 80 to the oscillation circuit 150.
The absolute value of the differential voltage VDF is, for example, | VC 1-VC 2 |. In this case, VC1 > VC2 may be used, or VC1< VC2 may be used. Since there is no temperature change or the like, when VC1 is VC2(DTD1 is DTD2), the voltage width of change of the output voltage VQ is also 0V, and the absolute value of the differential voltage VDF matches the voltage width of change of the output voltage VQ. That is, this case is an exceptional case of the method of the present embodiment.
For example, in the case where the method of the present embodiment is not employed, and the temperature is changed from T1 to T2, the output voltage VQ of the D/a conversion section 80 is changed in steps of the differential voltage VDF as shown in C1 of fig. 11.
In contrast, in the method of the present embodiment, as shown in C2 of fig. 11, the output voltage VQ of the D/a converter 80 is changed at a voltage width VA smaller than the absolute value of the differential voltage VDF. The voltage width VA is, for example, a voltage change of the output voltage VQ in the period TDAC.
As shown in C2 of fig. 11, if the output voltage VQ of the D/a converter 80 is changed so that VA < VDF, the change in the oscillation frequency of the oscillation circuit 150 is also very small compared to the case of C1. Therefore, the occurrence of the frequency hopping shown in fig. 3 can be suppressed, and the occurrence of the communication error described in fig. 8 can be prevented.
More specifically, in the present embodiment, the D/a converter 80 outputs the output voltage VQ which varies in steps of voltage corresponding to k × LSB (k ≧ 1) assuming that the minimum resolution of data in D/a conversion is LSB. For example, as shown in C2 of fig. 11, the output voltage VQ of the D/a converter 80 changes stepwise (stepwise) in steps of voltage corresponding to k × LSB. That is, the voltage width VA is, for example, a step of the voltage corresponding to k × LSB of the D/a converter 80. Note that the voltage width VA may be set to be smaller than the step of the voltage corresponding to k × LSB, for example, by a method of a modification described later.
Here, LSB is the minimum resolution of data input to the D/a conversion section 80 (frequency control data DDS output by the processing section 50). The voltage corresponding to the LSB is a minimum resolution voltage that is a voltage of minimum resolution of the D/a conversion. Therefore, the voltage corresponding to k × LSB corresponds to a voltage k times the minimum resolution voltage.
In addition, for example, when the resolution of the D/a conversion section 80 is set to i bits, k is<2iK is a ratio of 2iSufficiently small integers (e.g., k 1-8). More specifically, by providing the modulation circuit 90 or the like, when the resolution of the D/a conversion unit 80 is expanded from n bits to i n + m bits, k can be set to<2m。
For example, when k is 1, the output voltage VQ of the D/a conversion unit 80 changes in steps of a voltage corresponding to 1LSB (1 bit). For example, the output voltage VQ of the D/a converter 80 changes (increases or decreases) stepwise (stepwise) in steps of a voltage corresponding to 1 LSB.
That is, the output voltage VQ of the D/a conversion section 80 varies in steps of voltage corresponding to 1LSB (k × LSB in a broad sense) without depending on the input data DDS input to the D/a conversion section 80. This can be achieved by: for example, when the temperature changes from the 1 st temperature to the 2 nd temperature, the processing unit 50 (output unit 70) in fig. 5 outputs the frequency control data DDS changing from the 1 st data corresponding to the 1 st temperature to the 2 nd data corresponding to the 2 nd temperature in units of 1LSB (k × LSB units).
Further, the stepwise change in the step of the voltage corresponding to k × LSB shown in C2 of fig. 11 can be realized by: the processing unit 50 outputs the frequency control data DDS at an output rate faster than the output rate of the temperature detection data DTD (DTD1, DTD2) from the a/D conversion unit 20 (D/a conversion by the D/a conversion unit 80).
For example, the a/D conversion section 20 outputs temperature detection data DTD every period TAD as shown in fig. 11. For example, the a/D conversion section 20 outputs the 1 st temperature detection data DTD1 corresponding to the 1 st temperature T1, and then, after the lapse of the period TAD, outputs the 2 nd temperature detection data DTD2 corresponding to the 2 nd temperature T2. The period TAD corresponds to an a/D conversion interval (sampling interval of the temperature detection voltage) of the a/ D conversion section 20, and 1/TAD corresponds to the output rate of the a/D conversion section 20.
When the 2 nd temperature detection data DTD2 is output, the a/D conversion unit 20 performs digital signal processing such as temperature compensation processing on the processing unit 50 that receives the 2 nd temperature detection data DTD2, and outputs the frequency control data DDS corresponding to the 2 nd temperature detection data DTD 2. At this time, as shown in fig. 21 and 22 to be described later, the processing unit 50 changes the frequency control data DDS stepwise in units of k × LSB. Therefore, the output voltage VQ of the D/a converter 80 that receives the frequency control data DDS that changes in units of k × LSB and performs D/a conversion also changes in steps of voltage corresponding to k × LSB every period TDAC, as shown by C2 in fig. 11.
Here, the period TDAC corresponds to the D/a conversion interval of the D/a conversion unit 80 (the output interval of the frequency control data DDS of the processing unit 50), and the 1/TDAC corresponds to the output rate of the processing unit 50 and the D/a conversion unit 80.
Further, as shown in fig. 11, TAD > TDAC, the output rate 1/TDAC of the processing section 50 and the D/a conversion section 80 is faster than the output rate 1/TAD of the a/D conversion section 20. Therefore, even if the variation width of the output voltage VQ per period TDAC (per output rate 1/TDAC) is such a small voltage width that VA is k × LSB, the output voltage VQ can be varied from the control voltage VC1 to the control voltage VC2 within the period TAD. That is, when the temperature changes from T1 to T2 and the temperature detection data changes from DTD1 to DTD2, the output voltage VQ can be changed from the control voltage VC1 corresponding to the temperature detection data DTD1 to the control voltage VC2 corresponding to the temperature detection data DTD2 during the period TAD that is the a/D conversion interval. Further, since the voltage width VA of the voltage change at this time is small, occurrence of frequency hopping can be suppressed.
Fig. 12 is a diagram illustrating the method of the present embodiment in the frequency domain. For example, the frequency variable range of the oscillation frequency of the oscillation signal generation circuit 140 (the D/a conversion unit 80 and the oscillation circuit 150) is FR. For example, the oscillation signal generation circuit 140 may perform the scheduling in fig. 13 for the temperature variation, which is in the frequency variable range FR. That is, if the corresponding frequency adjustment range is narrowed down to a temperature change within the frequency variable range FR, the frequency can be adjusted by the oscillation signal generation circuit 140.
The allowable frequency drift of the oscillation frequency in the predetermined period TP is FD. In order to prevent the occurrence of a communication error as described in fig. 8, for example, it is necessary to reduce the frequency drift of the oscillation frequency within the predetermined period TP to within the allowable frequency drift FD. If the frequency drift of the oscillation frequency is not contained within the allowable frequency drift FD due to the frequency hopping shown in fig. 3, an erroneous determination occurs in the demodulation process of the received signal such as the GPS satellite signal, for example, and a communication error occurs.
The full-scale voltage of the D/a converter 80 is VFS. The D/a converter 80 can change the output voltage VQ within the range of the full-scale voltage VFS. The full-scale voltage VFS corresponds to the frequency control data DDS such as 0-2 inputted to the D/A converter 80iThat is, the voltage range when varied over the entire range.
The voltage width of the voltage variation of the output voltage VQ at the D/a conversion interval (TDAC) of the D/a conversion unit 80 described in fig. 11 is VA. In this case, in the method of the present embodiment, as shown in fig. 12, the following expression (1) holds.
VA<(FD/FR)×VFS (1)
Specifically, when the resolution of the D/a converter 80 is i bits, the following expression (2) holds.
1/2i<(FD/FR) (2)
By adopting the methods of the present embodiment shown in the above equations (1) and (2), as shown in fig. 12, the frequency drift of the oscillation frequency with respect to the nominal oscillation frequency fos (for example, about 16 MHz) in the predetermined period TP (for example, 20msec) can be narrowed to within the allowable frequency drift FD (for example, about several ppb). This can suppress the occurrence of a communication error or the like due to the frequency hopping described with reference to fig. 3 or the like.
For example, the right side (FD/FR) × VFS of the above expression (1) is obtained by multiplying the full-scale voltage VFS of the D/a converter 80 by the ratio (FD/FR) of the allowable frequency drift FD to the frequency variable range FR.
Further, if the voltage width VA of the change in the output voltage VQ at the D/a conversion interval (TDAC) of the D/a converter 80 is made smaller than the (FD/FR) × VFS, the frequency drift with respect to the nominal oscillation frequency fos can be narrowed within the allowable frequency drift FD in the frequency domain as shown in fig. 12. That is, the voltage width VA of the change in the output voltage VQ of the D/a converter 80 can be reduced as shown by C2 in fig. 11, and occurrence of frequency hopping can be suppressed.
For example, if the above equation (1) is not satisfied, as shown in fig. 14, frequency hopping occurs in which the frequency drift with respect to the nominal oscillation frequency fos is not shrunk within the allowable frequency drift FD, and a communication error or the like described in fig. 8 occurs. In the present embodiment, by changing the output voltage VQ of the D/a converter 80 so that the above expression (1) is satisfied, it is possible to suppress occurrence of such frequency hopping and prevent a communication error and the like.
That is, the D/a converter 80 changes the output voltage VQ within the range of the full-scale voltage VFS, and adjusts the oscillation frequency of the oscillation circuit 150 within the frequency variable range FR shown in fig. 13, thereby realizing the temperature compensation processing of the oscillation frequency described in fig. 6 and 7.
However, when the voltage amplitude VA of the change of the output voltage VQ of the D/a converter 80 becomes large, for example, VA ≧ (FD/FR) × VFS, the frequency drift of the oscillation frequency exceeds the allowable frequency drift FD, resulting in the frequency hopping shown in fig. 14.
In contrast, in the present embodiment, the output voltage VQ of the D/a converter 80 is changed within a small voltage width VA in which the relationship VA < (FD/FR) × VFS is satisfied, and occurrence of the frequency hopping shown in fig. 14 can be suppressed.
When the resolution of the D/a converter 80 is set to i bits, 1/2 is expressed by the above expression (2) in the present embodimenti<(FD/FR) holds.
For example, when both sides of the above expression (2) are multiplied by the full-scale voltage VFS of the D/a conversion unit 80, the following expression (3) is obtained.
VFS×1/2i<(FD/FR)×VFS (3)
Left side VFS × 1/2 of the above formula (3)iA voltage (minimum resolution voltage) corresponding to 1LSB of the D/a converter 80. The above expressions (2) and (3) mean that VFS × 1/2 corresponding to the voltage of 1LSB is set to be equal toiLess than (FD/FR). times.VFS. If set to VFS × 1/2 in this wayi<(FD/FR) × VFS, when the output voltage VQ of the D/a converter 80 is changed in steps of 1LSB voltage as shown in C2 of fig. 11, the frequency drift of the oscillation frequency does not exceed the allowable frequency drift FD, and the occurrence of frequency hopping can be suppressed.
In other words, i bits, which are the resolution of the D/a converter 80, are set so that the above equations (2) and (3) are satisfied.
In this case, in order to secure a sufficient range in consideration of various variations such as manufacturing variations, it is desirable to set the resolution of the D/a conversion unit 80 so as to be 1/2 compared with (FD/FR)iIs small enough. Specifically, the resolution of the D/a conversion unit 80 is set to, for example, i equal to or greater than 20 bits.
Thus, for example, when the allowable frequency drift within the predetermined period TP is about several ppb as described in fig. 8, the above expressions (2) and (3) are sufficient. Therefore, it is possible to effectively suppress the occurrence of a communication error or the like due to frequency hopping.
For example, fig. 15 is a diagram illustrating improvement in frequency drift when the method of the present embodiment described in fig. 11 to 13 is employed. As is clear from comparison of fig. 2, 3, and 15, according to the method of the present embodiment, even when a circuit configuration such as DTCXO is employed, the frequency drift can be narrowed to the same extent as the ATCXO of fig. 2.
That is, in a conventional circuit device such as DTCXO, frequency drift shown in fig. 3 occurs, which causes a communication error or the like.
On the other hand, if the method of the present embodiment is adopted, as shown in fig. 15, the frequency drift can be narrowed to the same extent as the ATCXO of fig. 2. Therefore, by adopting a circuit configuration such as DTCXO, for example, the following unique effects are obtained: the chip size of the circuit device can be reduced, the frequency accuracy can be improved, and the occurrence of communication errors and the like can be prevented by suppressing frequency hopping.
3.2 parasitic and C/N characteristics of the oscillator
Spurious occurs due to variation in the frequency control data DDS (bit variation in the D/a conversion section 80 in a narrow sense). The parasitic characteristics will be described first. Let Vo be the amplitude voltage of the main signal of the oscillator 400, and f0 be the frequency (oscillation frequency) of the main signal of the oscillator 400. The phase noise (spurious) when the minimum bit fluctuates by a small amount in the D/a converter 80 and becomes a phase fluctuation satisfies the following expressions (4) to (10) with respect to Vo and f 0.
Each of these embodiments will be described in detail. When the frequency of the phase fluctuation is fs, fs corresponds to the output frequency of the frequency control data DDS. Here, as shown in fig. 4, when the oscillation signal generation circuit 140 includes the D/a conversion unit 80 and the oscillation circuit 150, the output frequency fs of the frequency control data DDS is the sampling frequency (1/TDAC) of the D/a conversion unit 80, and the variation Δ f of the oscillation frequency is the variation amount of the oscillation frequency due to 1D/a conversion.
Since the minimum frequency resolution is Δ f, the amplitude of the phase swing in the phase variation is set to
In the case of (a) in (b),
every sampling frequency fs swings in frequency changes 0 or + Δ f or- Δ f. This is considered to be within the amplitude Δ fA frequency change is performed, and therefore,
represented by the following formula (4).
Using these variables, a signal obtained by applying a phase variation to the main signal can be expressed by the following expression (5).
The above equation (5) may be modified to the following equation (6) according to the sum-product equation of trigonometric functions.
In addition, in the above formula (6), the
The above formula (6) may be modified to the following formula (7) by simplifying the process on the premise that it is sufficiently smaller than 1.
The above equation (7) can be modified to the following equation (8) according to the sum-product equation of trigonometric functions.
As can be seen from the above equation (8), the signal component can be observed as the sum of the first term of the main signal, the second term and the third term at positions where the side band of the phase fluctuation component is located in upper and lower symmetry with respect to the main signal frequency. The power ratio P _ ratio (fs) of the main signal and the side band can be obtained from the following equation (9) using the amplitude levels of each other. When the intensity l (fs) of the spurious main signal is expressed in dBc/Hz, the following expression (10) is obtained.
D1 in fig. 16 is a graph showing the general C/N characteristics (phase noise characteristics) of the oscillator 400. In fig. 16, the horizontal axis represents the detuning frequency with respect to the fundamental wave (oscillation frequency) in a logarithmic manner, and the vertical axis represents the signal intensity. As is clear from D1, it is inevitable that phase noise is generated in the oscillator 400, and the design is performed on the premise that the phase noise is generated. That is, even if the spurious of the intensity shown in the above expression (10) occurs, if the intensity is smaller than the phase noise inherent to the oscillator, the influence of the spurious in the circuit device 500 is sufficiently small, and the accuracy of the data to be acquired can be suppressed from being lowered. On the contrary, as shown in D2 and D3 of fig. 16, when the intensity of the spurious signal is too large compared to the original phase noise of the oscillator, the C/N characteristic of the oscillator 400 is deteriorated by the spurious signal, and the accuracy of the data to be acquired is lowered. For example, accuracy of the position information obtained from the GPS reception signal is degraded.
In the circuit device 500 of the present embodiment, as described above, the variation of the frequency control data DDS is made to be k × LSB or less in order to suppress the defect due to the frequency drift. Therefore, the value of Δ f is expected to be small to some extent, but under this condition, there is no guarantee that the deterioration of the C/N characteristics due to parasitics can be suppressed. That is, it is necessary to define the relationship between Δ f and fs so that the variation of the frequency control data DDS is k × LSB or less and the spurious becomes strong enough to be masked by the original phase noise of the oscillator.
A specific relation example will be described with reference to fig. 17. E1 in fig. 17 shows a general C/N characteristic of the quartz resonator, similarly to D1 in fig. 16. E1 is the C/N characteristic of an AT-cut quartz resonator, for example, and corresponds to the case where the characteristic of the Q value is the worst (C/N characteristic difference) within the required range. That is, in the actual circuit device 500, there is no problem even if phase noise having an intensity shown in E1 occurs, and if the spurious intensity can be made to be an intensity that is masked by E1, a decrease in data accuracy can be suppressed.
E2 in FIG. 17 indicates that Δ f/fs is 1/106The intensity of parasitic light is E3, Δ f/fs is 1/107The intensity of parasitic light is E4, Δ f/fs is 1/108The intensity of the parasitics. Since the parasitic intensity is determined by Δ f/fs as shown in the above equation (10), when Δ f/fs is a predetermined value, the parasitic intensity is a fixed value regardless of the offset frequency, and becomes a straight line parallel to the horizontal axis as shown in E2 to E4. Since the spurious offset frequency is fs, the output frequency fs of the frequency control data DDS may be considered on the horizontal axis from E2 to E4. This is also the same for E5 and E6 described later.
Here, if Δ f/fs can be set<1/108Since the intensity of the spurious signal is lower than that of the straight line shown in E4, the spurious signal can be smaller than the original phase noise of the oscillator shown in E1. That is, in the circuit device 500 of the present embodiment, Δ f/fs is satisfied<1/108And (4) finishing. However, in order to decrease Δ f/fs, fs must be increased or Δ f must be decreased. If fs is increased, power consumption in the D/a conversion section 80 increases, and if Δ f is decreased, resolution in the D/a conversion section 8 needs to be increased (the width of change in frequency corresponding to the change of 1LSB is decreased). That is, under the condition that Δ f/fs is set to be smaller than a predetermined value, there is a trade-off relationship as follows: if Δ f is increased to suppress the requirement for resolution, fs must be increased to increase the conversion speed in the D/a conversion section 80, and if fs is decreased to suppress the requirement for the D/a conversion section 80, Δ f must be decreased to secure higher resolution. Therefore, although Δ f/fs is satisfied<1/108Such conditions are ideal, but take into account the difficulty of implementation.
Thus, in the present embodiment, the ratio Δ f/fs may be used<1/108Mild conditions. For example, the D/a converter 80 of the present embodiment includes a filter circuit 120 (or a filter described later) at a stage subsequent to the D/a converter 100Circuit 130). The output voltage of the D/a converter 100 can be smoothed by the filter circuit 120, thereby reducing the fluctuation of the oscillation frequency. That is, Δ f can be substantially reduced by the filter circuit 120.
For example, if the sampling frequency fs of the D/a converter 100 is set high and the cutoff ratio is set to about 1/100 by the filter circuit 120, the parasitic intensity can be improved by about 1/100 (-40 dB or less). In this case, even if Δ f/fs is 1/106(E2) Since the improved spurious level by the filter circuit 120 is also equal to or lower than E1, the spurious level can be masked by the phase noise inherent in the oscillator. I.e. even if Δ f/fs is used<1/106Under such conditions, the accuracy degradation due to the oncomelanization of the C/N characteristic can be suppressed.
As described above, the circuit device 500 of the present embodiment includes: an a/D conversion unit 20 that performs a/D conversion of the temperature detection voltage from the temperature sensor unit 10 and outputs temperature detection data DTD; a processing unit 50 that performs temperature compensation processing of the oscillation frequency based on the temperature detection data DTD and outputs frequency control data DDS of the oscillation frequency; and an oscillation signal generation circuit 140 that generates an oscillation signal of an oscillation frequency set by the frequency control data DDS, using the frequency control data DDS and the oscillator XTAL from the processing unit 50. In order to suppress defects due to frequency hopping, the processing unit 50 outputs frequency control data DDS that changes from 1 st data corresponding to the 1 st temperature to 2 nd data corresponding to the 2 nd temperature in units of k × LSB (k ≧ 1) when the temperature changes from the 1 st temperature to the 2 nd temperature.
In the present embodiment, in order to improve the accuracy of data obtained using an oscillation signal, when the output frequency of the frequency control data DDS that changes in units of k × LSB of the processing unit 50 is fs and the change in the oscillation frequency of the frequency control data DDS that changes in units of k × LSB is Δ f, Δ f/fs is satisfied<1/106。
If the variation of the frequency control data DDS is in units of k × LSB, the magnitude of Δ f is thus also limited. For example, when the circuit device 500 includes the D/a converter 100, the change width Δ VDAC of the output voltage of the D/a converter 100 is a value corresponding to the change width of the frequency control data DDS. The capacitance value of a variable capacitor included in the oscillation circuit varies depending on the voltage, and the coefficient of variation (C/V) thereof is determined. Further, the oscillation frequency of the oscillation circuit 150 varies depending on the capacitance value of the variable capacitance, and the variation coefficient (f/C) thereof is also determined. That is, in this example, since Δ f is in a relationship of Δ VDAC × (C/V) × (f/C), the change Δ f in the oscillation frequency has a value corresponding to the change width k × LSB of the frequency control data DDS.
That is, although Δ f is limited to a predetermined value or less by satisfying the 1 st condition that the frequency control data DDS is changed in units of k × LSB, in the present embodiment, Δ f/fs is also satisfied<1/106Such a2 nd condition is established. This can suppress a defect or the like due to frequency hopping, and can suppress a decrease in accuracy due to spurious emission.
Specifically, what value of Δ f corresponds to k × LSB of the frequency control data DDS is determined by the value of k, the full scale of the D/a converter 100, the characteristics of the variable capacitor, the characteristics of the oscillator circuit 150, and the like. Further, for satisfying Δ f/fs<1/106The specific value of Δ f is determined according to the output frequency fs of the frequency control data DDS. Therefore, which of the 1 st condition and the 2 nd condition is the strict condition differs depending on the situation, but in any case, in the present embodiment, it is sufficient to set a condition satisfying a more strict condition.
As described above, in order to suppress a defect or the like caused by frequency hopping, the circuit device 500 of the present embodiment sets DV < (FD/FR) × DFS when the frequency variable range of the oscillation frequency by the oscillation signal generation circuit 140 is FR, the allowable frequency drift of the oscillation frequency within a predetermined period is FD, the full-scale value of the frequency control data DDS is DFS, and the variation value of the frequency control data DDS at the output interval of the frequency control data DDS by the processing unit 50 is DV.
By making the variation value DV of the frequency control data DDS DV < (FD/FR) × DFS, the magnitude of Δ f is limited. For example, when the circuit device 500 includes the D/a converter 100, the change width Δ VDAC of the output voltage of the D/a converter 100 is a value corresponding to the change value DV of the frequency control data DDS. The capacitance value of a variable capacitor included in the oscillation circuit varies depending on the voltage, and the coefficient of variation (C/V) thereof is determined. Further, the oscillation frequency of the oscillation circuit 150 varies depending on the capacitance value of the variable capacitance, and the variation coefficient (f/C) thereof is also determined. That is, in this example, since Δ f is in a relationship of Δ VDAC × (C/V) × (f/C), the change Δ f in the oscillation frequency is a value corresponding to the change value DV of the frequency control data DDS.
That is, by making the variation value DV of the frequency control data DDS satisfy DV<The 1 st condition of (FD/FR) × DFS is that Δ f is limited to a predetermined value or less, but in the present embodiment, Δ f/fs is also satisfied<1/106Such a condition 2 is established. This can suppress a defect or the like due to frequency hopping, and can suppress a decrease in accuracy due to spurious emission.
The change value DV of the frequency control data DDS is specifically determined depending on what value of Δ f is, for example, the full-scale of the D/a converter 100, the characteristic of the variable capacitor, and the characteristic of the oscillator circuit 150. Further, for satisfying Δ f/fs<1/106The specific value of Δ f is determined according to the output frequency fs of the frequency control data DDS. Therefore, which of the 1 st condition and the 2 nd condition is the strict condition differs depending on the situation, but in any case, in the present embodiment, it is sufficient to set a condition satisfying a more strict condition.
Further,. DELTA.f/fs<1/106Such conditions are obtained from the following viewpoints: regardless of the value of the offset frequency (the output frequency fs of the frequency control data DDS), the spurious is masked by the intrinsic phase noise of the oscillator. However, as is clear from E1 in fig. 17, in a frequency band in which the influence of 1/f noise is large, the smaller the frequency, the larger the phase noise inherent in the oscillator. That is, even if a spurious with a higher intensity is generated in a frequency band with a relatively low offset frequency, the spurious is masked by the phase noise of the oscillator 400, and the influence on the accuracy is small.
That is, Δ f/fs is satisfied regardless of the spurious offset frequency (fs)<1/106Such a condition, from suppression based on oscillation signalsThe data accuracy of the number is a sufficient condition from the viewpoint of being lowered, but may be an excessively strict condition.
Thus, in the present embodiment, Δ f/fs and Δ f/fs can be used as well<1/106Different conditions. Fig. 17E 5 and E6 show parasitic characteristics when Δ f is set to a predetermined fixed value. As shown in fig. 17, when the unit of the vertical axis is dBc/Hz and the horizontal axis is the logarithm of the offset frequency, the parasitic intensity when Δ f is a fixed value is represented by a monotonously decreasing straight line. Further, the linear slice varies by varying Δ f, and the larger Δ f, the higher the parasitic intensity at the same offset frequency. Fig. 17, E5 shows the characteristic of the spurious response when Δ f is 0.1mHz, and E6 shows the characteristic of the spurious response when Δ f is 1 mHz.
As can be seen from fig. 17, E5 having Δ f of 0.1mHz is located below E1 representing the C/N characteristic of oscillator 400, regardless of the position on the abscissa. That is, by satisfying Δ f<0.1mHz, the parasitic intensity can be made smaller than the phase noise inherent to the oscillator. However,. DELTA.f<0.1mHz is also equal to Δ f/fs 1/108The same ideal conditions, even more moderate conditions in practice, have less influence on the accuracy. Specifically, in the present embodiment, Δ f is defined as the upper limit of the straight line indicated by E6<1 mHz.
However, the condition of Δ f <1mHz is also too strict in a situation where the offset frequency (fs) is large. From the above equation (10), it is understood that the higher fs, the lower the intensity of spurious radiation. That is, when fs is large, even if Δ f is large, the parasitic intensity can be suppressed from increasing, and the influence on the accuracy is small. Under the condition that Δ f is less than 1mHz, there is a possibility that the strict condition that Δ f is too small even when fs is large is set.
Thus, in the present embodiment, Δ f/fs can be switched according to the situation<1/106And Δ f<1 mHz. Specifically, the conditions may be switched so as to be bounded by fs being 1kHz, which is the intersection of E2 and E6 in fig. 17. When fs ≧ 1kHz, which is the right side of the intersection point, E2 is located above E6, so the condition of E2 is more moderate. On the other hand, on the left side of the intersection point, fs<At 1kHz, E6 is located above E2Accordingly, the condition of E6 is more moderate. That is, in the present embodiment, Δ f/fs is set to be larger than or equal to 1kHz<1/106At fs, in<In the case of 1kHz,. DELTA.f<1 mHz. This can alleviate the conditions to be satisfied, and thus, for example, the requirement for resolution of the D/a converter 100 can be reduced, and the circuit device 500 can be easily realized.
Further, the method of the present embodiment is not limited to the combined use of Δ f/fs<1/106And Δ f<1 mHz. For example, the processing unit 50 may output the frequency control data DDS changing from 1 st data corresponding to the 1 st temperature to 2 nd data corresponding to the 2 nd temperature in units of k × LSB (k ≧ 1) when the temperature changes from the 1 st temperature to the 2 nd temperature, and may output the frequency control data DDS changing in units of k × LSB and Δ f when the output frequency of the frequency control data DDS changing in units of k × LSB of the processing unit 50 is fs and the change in the oscillation frequency of the frequency control data DDS caused by the change in units of k × LSB is Δ f<In the case of 1kHz,. DELTA.f<1 mHz. In addition, when the output frequency of the frequency control data DDS is fs and the change in the oscillation frequency due to the change in the change value DV of the frequency control data DDS is Δ f, fs may be set to<In the case of 1kHz,. DELTA.f<1 mHz. In this case, when fs is 1kHz or more, Δ f/fs can be used<1/106Under different conditions, fs ≧ 1kHz may not be used as an application target of the method of the present embodiment.
In addition, various design methods of a circuit device in which Δ f and fs satisfy the above conditions may also be considered. For example, the conversion speed (sampling frequency) of the D/a converter 80 is required to be different depending on the circuit device. In a given circuit arrangement, a higher sampling frequency of fs 100kHz can be set; in a different circuit device, from the viewpoint of power consumption, it is conceivable to allow only a low sampling frequency of fs 100 Hz. In a circuit arrangement allowing fs to be 100kHz, provided that Δ f/fs is set as described above<1/106As a condition, Δ f<100 mHz. In this case, and Δ f<The Δ f can be increased compared to 1mHz, and there is no problem even if the resolution is low. On the other hand, in a circuit device in which fs is 100Hz, Δ f is used as described above<1 mHz. In this case, it is preferable that,while the resolution is required to be high, a circuit device and the like with low power consumption can be realized.
Here, the resonator XTAL of the present embodiment is, for example, a quartz resonator. Further, it is known that characteristics such as the oscillation frequency of the quartz resonator vary depending on the cutting orientation with respect to the crystal axis. The quartz resonator according to the present embodiment may be an AT-cut resonator, an SC-cut (Stress Compensation-cut) resonator, or a SAW resonator, which are widely used.
The AT-cut oscillator is an oscillator which has an angle of 35.15 DEG with respect to the crystal axis and is used as an oscillation source of 10MHz to 500MHz for SPXO, TCXO and VCXO. The SC-cut resonator is a resonator used in an OCXO as an oscillation source of 10MHz to 100MHz due to its feature of extremely small temperature characteristics at high temperatures. The oscillation frequencies of the AT-cut oscillator and the SC-cut oscillator are determined by thickness shear oscillation. The SAW resonator is a resonator to which a Surface Acoustic Wave (Surface Acoustic Wave) is applied, and vibrates depending on an electrode pattern on a quartz Surface. The SAW resonator is a vibrator with oscillation frequency as high as 100 MHz-3.5 GHz and good C/N characteristic (high Q value).
Further,. DELTA.f/fs<1/106Is a condition relating to the ratio of Δ f to fs. Therefore, it is considered that Δ f/fs is satisfied in a large amount<1/106Combinations of Δ f and fs of (1). Fig. 18 shows an example of combinations of values of Δ f and fs when data with high accuracy can be obtained without deteriorating the C/N characteristics. In fig. 18, F1 indicates (Δ F, fs) ═ 0.1Hz, 4MHz, F2 indicates (Δ F, fs) ═ 4MHz, 100kHz, and F3 indicates (Δ F, fs) ═ 1MHz, 10 kHz.
In the present embodiment, the combination of the values of Δ f and fs is limited to one value and is not an obstacle. For example, only one of F1 to F3 is set to the combination of Δ F and fs, and the circuit device 500 operates so as to satisfy the required set value. However, the method of the present embodiment is not limited to this, and the combination of the values of Δ f and fs may be variable. For example, 3 kinds of candidates of values of Δ F and fs, such as F1 to F3, may be retained, and any of the 3 kinds may be adopted depending on the situation.
For example, the combination of values of Δ f and fs to be used is determined according to whether or not the circuit device 500 is within a predetermined period from the start of operation. At the time of starting operation, since temperature compensation processing for the temperature detection data DTD has not been performed before, a difference (hereinafter, referred to as a frequency error) between the oscillation frequency of the oscillation signal SSC to be output and a desired oscillation frequency may be large. Although the frequency control data DDS for reducing the frequency error (0 in a narrow sense) can be obtained by the temperature compensation process of the processing unit 50, the present embodiment has a limitation of suppressing the fluctuation of the oscillation frequency per time to Δ f. That is, the frequency error is reduced by Δ f only during 1 output of the frequency control data DDS, and a long time may be required to set the frequency error to 0.
Therefore, in the present embodiment, Δ f may be set to a large value at the start of operation so as to satisfy Δ f/fs<1/106But fs is also made to be a large value. In the above examples of F1 to F3, (Δ F, fs) indicated by F1 is (0.1Hz, 4 MHz). As a result, Δ f is large, and therefore, the oscillation frequency of the oscillation signal can be made close to the desired frequency (the frequency error can be made close to 0) in a short time.
However, to increase Δ f, fs must also be increased, which leads to an increase in power consumption, and the like. Thus, when a certain amount of time has elapsed (or when the frequency error is small to a certain degree), it is desirable to reduce Δ f and fs. In the example of fig. 18, the combination of values of Δ F and fs to be used is changed from F1 to (Δ F, fs) ═ 4mHz, 100kHz, as shown in F2. When the time has further elapsed (when the frequency error becomes small), the combination of the values of Δ F and fs to be used may be changed from F2 to (Δ F, fs) ═ 1mHz, 10kHz shown in F3.
Fig. 19 is a diagram for explaining the above control. In fig. 19, the vertical axis represents the frequency error (Hz), and the horizontal axis represents the elapsed time from the start of operation (start-up) in logarithmic form. As shown at t1 to t2 in fig. 19, the operation is performed within a predetermined period from the start-up by using the parameters shown in F1. Since the sampling frequency fs is high and the frequency change amount Δ f per unit time is also large, the frequency error of 0.2Hz or more at the time of start-up can be made close to 0 in a short time. The parameter operation shown by F2 is performed for a period from t2 to t3, and the parameter operation shown by F3 is performed for a period after t 3.
Thus, Δ f/fs can be realized using a parameter corresponding to the situation<1/106The conditions shown. Specifically, in a situation where the frequency error is likely to be large, when the target value is tracked at high speed and tracking is completed to some extent, fs is reduced to suppress an increase in power consumption.
Although 3 combinations of Δ f and fs are described here, it is needless to say that 2 combinations or 4 or more combinations may be used. In addition, as long as Δ f, fs satisfy Δ f/fs<1/106The specific numerical values are not limited to F1 to F3 in fig. 18. Further, it is shown that<1/106Although Δ f and fs are made variable under such conditions, k may be made variable under such conditions that the frequency control data DDS is made variable in units of k × LSB (k ≧ 1).
Although the configuration in which the oscillation signal generation circuit 140 includes the D/a conversion unit 80 has been described above, the method of the present embodiment is not limited to this. For example, when the oscillation signal generation circuit 140 having a configuration not including the D/a converter 80 as described later using fig. 39 is used, Δ f/fs can be satisfied<1/106、Δf<The condition of 1mHz suppresses the deterioration of C/N characteristics caused by parasitics, and realizes data acquisition with high accuracy. In addition, when the oscillation signal generation circuit 140 does not include the D/a converter 80, the filter circuit 120 (filter circuit 130) is not included, and there is a possibility that the spurious caused by the filter circuit 120 is not reduced. In this case, the conditional ratio Δ f/fs to be satisfied for Δ f and fs may be set to<1/106、Δf<The conditions of 1mHz were strict.
4. Detailed description of the exemplary embodiments
4.1 treatment section
Next, a detailed configuration example of each part of the circuit device of the present embodiment is shown. Fig. 20 is a diagram showing a detailed configuration example of the processing unit 50.
As shown in fig. 20, the processing unit 50(DSP unit) includes a control unit 52, an arithmetic unit 60, and an output unit 70. The control unit 52 performs control of the arithmetic unit 60 and the output unit 70 and various determination processes. The arithmetic unit 60 performs an arithmetic operation of temperature compensation processing of the oscillation frequency based on the temperature detection data DTD from the a/D conversion unit 20. The output unit 70 receives the calculation result data from the calculation unit 60 and outputs frequency control data DDS.
The control unit 52 includes a determination unit 53. The determination unit 53 has comparison units 54 and 55, and performs various determination processes based on the comparison results of the comparison units 54 and 55.
The arithmetic section 60 includes type conversion sections 61, 62, 68, multiplexers 63, 65, an arithmetic unit 64, and work registers 66, 67, 69. The operator 64 includes a multiplier 58 and an adder 59.
The type conversion unit 61 receives coefficient data from the memory unit 180, performs type conversion from a binary type (integer) to a floating-point type (single precision), and outputs the coefficient data after the type conversion to the multiplexer 63. The type conversion unit 62 receives the temperature detection data DTD from the a/D conversion unit 20, performs type conversion from the binary type to the floating point type, and outputs the temperature detection data DTD after the type conversion to the multiplexer 63. For example, binary temperature detection data DTD of 15 bits is type-converted into floating point data of 32 bits (exponent part: 8 bits, mantissa: 23 bits, and sign: 1 bit). The multiplexer 63 receives the constant number data from the ROM190 storing the constant number data of a fixed value for temperature compensation processing.
The multiplexer 63 selects any one of the output data of the arithmetic unit 64, the output data of the operation registers 66 and 67, the output data of the type conversion sections 61 and 62, and the output data of the ROM190 and outputs the selected data to the arithmetic unit 64. The arithmetic unit 64 performs arithmetic processing such as 32-bit floating-point product-sum operation by using the multiplier 58 and the adder 59, thereby executing temperature compensation processing. The multiplexer 65 selects any one of the output data of the multiplier 58 and the adder 59 of the arithmetic unit 64 and outputs the selected one to any one of the operation registers 66 and 67 and the type conversion unit 68. The type conversion unit 68 converts the operation result data of the operation unit 60 (the operator 64) from the floating-point type to the binary type. For example, 32-bit floating-point operation result data is type-converted into 20-bit binary operation result data. The operation result data after the type conversion is held in the work register 69.
The arithmetic unit 60 (arithmetic unit 64) performs temperature compensation processing for approximating the curve of the temperature characteristic of fig. 6 by an approximation function (polynomial equation) of, for example, 5 th order, as shown in the following equation (11).
VCP＝b·(T－T0)5+c·(T－T0)4+d·(T－T0)3+e·(T－T0) (11)
In the above equation (11), T corresponds to the temperature indicated by the temperature detection data DTD, and T0 corresponds to the reference temperature (e.g., 25 ℃). b. c, d, e are coefficients of the approximation function, and data of the coefficients are stored in the memory section 180. The arithmetic unit 64 executes arithmetic processing such as product-sum operation of the above expression (11).
The output unit 70 includes a multiplexer 71, an output register 72, an LSB adder 73, and an LSB reducer 74. The multiplexer 71 selects any one of the operation result data as the output data of the operation unit 60, the output data of the LSB adder 73, and the output data of the LSB reducer 74 and outputs the selected data to the output register 72. The determination unit 53 of the control unit 52 monitors the output data of the operation register 69 and the output data of the output register 72. Various comparison determinations are performed by using the comparison units 54 and 55, and the multiplexer 71 is controlled based on the determination result.
In the present embodiment, as shown in fig. 21 and 22, when the temperature changes from the 1 st temperature to the 2 nd temperature, the output unit 70 outputs the frequency control data DDS that changes in units of k × LSB from the 1 st data DAT1 corresponding to the 1 st temperature to the 2 nd data DAT2 corresponding to the 2 nd temperature. The frequency control data DDS, which changes in units of 1LSB with k being 1, for example, is output.
For example, the output register 72 stores the 1 st data DAT1 as the operation result data of the operation unit 60 at the previous time (timing of the n-1 st). The work register 69 stores the 2 nd data DAT2 as the operation result data of the operation unit 60 of this time (the nth timing).
As shown in fig. 21, when the 2 nd data DAT2, which is the current operation result data, is larger than the 1 st data DAT1, which is the previous operation result, the output unit 70 performs a process of adding 1LSB (broadly, k × LSB) that is a predetermined value to the 1 st data DAT1 until the addition result data reaches the 2 nd data DAT2, and outputs the addition result data as the frequency control data DDS.
On the other hand, as shown in fig. 22, when the 2 nd data DAT2, which is the current operation result data, is smaller than the 1 st data DAT1, which is the previous operation result, the output unit 70 performs a process of subtracting 1LSB (k × LSB), which is a predetermined value, from the 1 st data DAT1 until the subtraction result data reaches the 2 nd data DAT2, and outputs the subtraction result data as the frequency control data DDS.
Specifically, the determination part 53 of the control part 52 compares the 1 st data DAT1 stored in the output register 72 with the 2 nd data DAT2 stored in the operation register 69. The comparison is determined by the comparison unit 54.
As shown in fig. 21, when DAT2 is larger than DAT1, the LSB adder 73 adds 1LSB to DAT1 of the output register 72, and the multiplexer 71 selects the output data of the LSB adder 73. Thus, as shown in fig. 21, the output register 72 holds addition result data obtained by sequentially adding 1LSB to DAT 1. Then, the addition result data updated by sequentially adding 1LSB is output as the frequency control data DDS. This addition process is repeated until the addition result data reaches DAT 2. The comparison unit 55 performs comparison processing for determining whether the addition result data matches the DAT 2.
On the other hand, as shown in fig. 22, when DAT2 is smaller than DAT1, the LSB adder 74 subtracts 1LSB from DAT1 of the output register 72, and the multiplexer 71 selects the output data of the LSB adder 73. Thus, as shown in fig. 22, the output register 72 holds subtraction result data obtained by sequentially subtracting 1LSB from DAT 1. Then, the subtraction result data updated by sequentially subtracting 1LSB is output as the frequency control data DDS. This subtraction process is repeated until the subtraction result data reaches DAT 2.
The maximum number of addition processes and subtraction processes by the LSB adder 73 and the LSB reducer 74 is set to a predetermined number (for example, 8). Further, a maximum temperature change of the ambient temperature, for example, may be specified (e.g., 2.8 ℃/10 seconds). Therefore, the temperature change corresponding to, for example, 1LSB × a predetermined number of times (temperature change corresponding to, for example, 1LSB × 8 times of voltage) is set to sufficiently exceed the above-described maximum temperature change.
As described in fig. 11, the output rate (1/TDAC) of the frequency control data DDS of the processing section 50 is faster than the output rate (1/TAD) of the temperature detection data DTD of the a/D conversion section 20. Therefore, for example, after the temperature detection data DTD2 is input from the a/D conversion section 20 to the processing section 50 in fig. 11, the processing of adding or subtracting 1LSB by a given number of times shown in fig. 21 and 22 can be performed in the period TAD until the temperature detection data DTD3 is input next. For example, the addition process or the subtraction process may be performed a predetermined number of times (for example, 8 times) as the maximum number of times.
As described above, according to the processing unit 50 having the configuration of fig. 20, as shown in fig. 21 and 22, for example, it is possible to output the frequency control data DDS varying in units of k × LSB from the 1 st data DAT1 corresponding to the 1 st temperature (1 st temperature detection data DTD1) to the 2 nd data DAT2 corresponding to the 2 nd temperature (2 nd temperature detection data DTD 2). Thus, the method of the present embodiment described with reference to fig. 11 to 13 can be realized by the output control of the frequency control data DDS by the processing unit 50.
In the present embodiment, for example, the processing of the arithmetic unit 60 can be realized by high-precision arithmetic processing of, for example, 32 bits. Therefore, for example, when the type conversion unit 68 performs type conversion on 32-bit floating-point operation result data, it is possible to acquire, for example, 20-bit binary frequency control data DDS (operation result data) from 23-bit mantissas with guaranteed precision. As described with reference to fig. 5, the frequency control data DDS having i equal to 20 bits, for example, can be input from the processing unit 50 to the D/a conversion unit 80. The modulation circuit 90 modulates the data of the frequency control data DDS having n-16 bits from the data of m-4 bits of the i-20 bits, and the D/a converter 100 performs D/a conversion on the modulated data having n-16 bits, thereby realizing D/a conversion with a resolution of i-20 bits.
4.2D/A converter
Fig. 23 and 24 are diagrams showing detailed configuration examples of the D/a converter 80. The D/a converter 80 includes a modulation circuit 90, a D/a converter 100, and a filter circuit 120.
As shown in fig. 23, the D/a converter 100 includes a high-side D/a converter DACA, a low-side D/a converter DACB, and operational amplifiers (operational amplifiers) OPA, OPB, and OPC connected in voltage-following manner.
The high-order DACA receives high-order q-bit data of n-bit (n ═ q + p) data DM from the modulation circuit 90, and the low-order DACB receives low-order p-bit (for example, p ═ q ═ 8) data. These high-side DACA and low-side DACB are resistor string type D/a converters that select a voltage corresponding to input data from a plurality of divided voltages obtained by voltage-dividing a plurality of resistors connected in series, for example.
As shown in fig. 24, the high-side DACA includes a plurality of resistors RA1 to RAN connected in series between the node of the high-side power supply voltage VDDA and the node of the low-side power supply voltage VSS. The high-side DACA includes a plurality of switching elements SA1 to SAN +1 having one ends connected to voltage division nodes based on the resistors RA1 to RAN, and a decoder 104 (switching control circuit) that generates switching control signals for turning on or off the switching elements SA1 to SAN +1 based on the high-order q-bit data of the data DM.
The high-order DACA outputs one of the divided voltages at both ends of the resistor, which is determined by the high-order q-bit data of the resistors RA1 to RAN, to the non-inverting input terminal of the operational amplifier OPA, and outputs the other divided voltage to the non-inverting input terminal of the operational amplifier OPB. Thus, the one voltage is impedance-converted by the operational amplifier OPA connected to the voltage follower, and is supplied to the low-order DACB as the voltage VX. Further, the other voltage is impedance-converted by the operational amplifier OPB of the voltage follower connection, and supplied as a voltage VY to the lower DACB.
When the resistor RA1 is determined by, for example, q-bit data of high order, the divided voltage on the high side among the divided voltages across the resistor RA1 is supplied as the voltage VX via the switching element SA1 and the operational amplifier OPA that are turned on. The low-potential-side divided voltage is supplied as a voltage VY via the switching element SA2 and the operational amplifier OPB that are turned on. When the resistor RA2 is determined by the q-bit data, the divided voltage on the low potential side among the divided voltages across the resistor RA2 is supplied as the voltage VX via the switching element SA3 and the operational amplifier OPA that are turned on. The high-side divided voltage is supplied as a voltage VY via the turned-on switching element SA2 and the operational amplifier OPB.
The low-side DACB includes a plurality of resistors RB1 to RBM connected in series between a node of the voltage VX and a node of the voltage VY. The low-side DACB includes a plurality of switching elements SB1 to SBM +1 having one ends connected to voltage division nodes based on the resistors RB1 to RBM, and a decoder 106 (switching control circuit) that generates switching control signals for turning on or off the switching elements SB1 to SBM +1 in accordance with the low-p-bit data of the data DM.
The low-side DACB outputs 1 divided voltage selected by the low-order p-bit data among the plurality of divided voltages based on the resistances RB1 to RBM to the non-inverting input terminal of the operational amplifier OPC connected to the voltage follower via the on-state switching element as a selection voltage. This selection voltage is thus output as the output voltage VDA of the D/a converter 100.
Fig. 25, 26, and 27 are explanatory diagrams of the modulation circuit 90. As shown in fig. 25, the modulation circuit 90 receives the frequency control data DDS having i ═ n + m bits from the processing unit 50. Then, PWM modulation of data of the upper n bits (bits b5 to b20) of the frequency control data DDS is performed based on the data of the lower m bits (bits b1 to b4) of the frequency control data DDS. As described with reference to fig. 23 and 24, q-bit data (bits b13 to b20) of the n-bit data are input to the DACA on the higher side, and p-bit data (bits b5 to b12) are input to the DACB on the lower side.
Fig. 26 is an explanatory diagram of the 1 st embodiment of PWM modulation. DY and DZ are higher n-bit data of the data DM, and DY is satisfied in the n-bit expression as DZ + 1.
In the case where the duty ratio indicated by the data of 4 bits in the lower m for PWM modulation is, for example, 8 to 8, 8 pieces of 16-bit data DY and 8 pieces of 16-bit data DZ are output from the modulation circuit 90 to the D/a converter 100 in a time-division manner as shown in fig. 26.
Further, in the case where the duty ratio indicated by the data of which lower m is 4 bits is 10 to 6, 10 data DY and 6 data DZ are output from the modulation circuit 90 to the D/a converter 100 in a time division manner. Likewise, in the case where the duty ratio represented by the data of which lower m is 4 bits is 14 to 2, 14 data DY and 2 data DZ are output in a time division manner.
Fig. 27 is an explanatory diagram of the 2 nd embodiment of PWM modulation. When each of the bits b4, b3, b2, and b1 of m-4 bits used for PWM modulation is at a logic level "1", an output pattern corresponding to each bit in fig. 27 (an output pattern shown on the right side of each bit) is selected.
For example, when the bit b4 is 1 and the bit b3 is b2 is b1 is 0, only the output pattern corresponding to the bit b4 is output in the periods P1 to P16. That is, the data of n-16 bits is output from the modulation circuit 90 to the D/a converter 100 in time division in the order DZ, DY, DZ, DY ·. This makes it possible to output data DY, DZ 8 times in total, and to realize PWM modulation similar to the case where the duty ratio is 8 to 8 in fig. 26.
When the bit b4 is b2 is 1 and the bit b3 is b1 is 0, the output pattern corresponding to the bits b4 and b2 is output in the periods P1 to P16. Thus, data DY and DZ are output 10 times and 6 times, respectively, and PWM modulation can be realized similarly to the case where the duty ratio is 10 to 6. Similarly, when the bit b4 is b3 is b2 is 1 and the bit b1 is 0, the output frequency of the data DY and the DZ is 14 and 2 times, respectively, and the same PWM modulation as that in the case of the duty ratio of 14 to 2 can be realized.
As described above, according to the modulation circuit 90 of fig. 5 and 23, PWM modulation can be realized by controlling only the number of times of outputting the data DY, DZ, and the like, and although the D/a converter 100 using a resolution of 16 bits, for example, can realize a resolution of D/a conversion of 20 bits or more, for example.
In D/a conversion of, for example, a resistor string type or a resistor ladder type with less noise, a resolution of, for example, around 16 bits is a substantial limit. In this regard, according to the configurations of fig. 5 and 23, the resolution of D/a conversion can be improved to 20 bits or more, for example, by providing only the modulation circuit 90 and the filter circuit 120 having a small circuit scale. Therefore, the resolution of the D/a conversion section 80 can be improved while suppressing an increase in circuit scale to a minimum. Further, by increasing the resolution of the D/a converter 80, it is possible to achieve high accuracy of oscillation frequency accuracy, suppress frequency hopping, and provide an oscillator suitable for time synchronization.
4.3 temperature sensor unit and oscillation circuit
Fig. 28 shows a configuration example 1 of the temperature sensor section 10. The temperature sensor portion 10 of fig. 28 has a current source IST and a bipolar transistor TRT to which a current from the current source IST is supplied to a collector. The bipolar transistor TRT is diode-connected such that its collector and base are connected, and outputs a temperature detection voltage VTD having temperature characteristics to a node of the collector of the bipolar transistor TRT. The temperature characteristic of the temperature detection voltage VTD is generated due to the temperature dependency of the base-emitter voltage of the bipolar transistor TRT. As shown in fig. 30, the temperature detection voltage VTD has a negative temperature characteristic (1 st order temperature characteristic with a negative gradient).
Fig. 29 shows a configuration example 2 of the temperature sensor section 10. In fig. 29, the current source IST of fig. 28 is implemented by a resistor RT. One end of the resistor RT is connected to a node of the power supply voltage, and the other end is connected to a collector of the bipolar transistor TRT 1. Further, the emitter of the bipolar transistor TRT1 is connected to the collector of the bipolar transistor TRT 2. Further, the bipolar transistors TRT1 and TRT2 are both diode-connected, and the voltage VTSQ output to the node of the collector of the bipolar transistor TRT1 has a negative temperature characteristic (1-step temperature characteristic having a negative gradient) as shown in fig. 30.
In addition, the temperature sensor section 10 of fig. 29 is further provided with an operational amplifier OPD and resistors RD1 and RD 2. The voltage VTSQ is input to the non-inverting input terminal of the operational amplifier OPD, and the inverting input terminal is connected to one end of the resistor RD1 and one end of the resistor RD 2. The other end of the resistor RD1 is supplied with the reference temperature voltage VTA0, and the other end of the resistor RD2 is connected to the output terminal of the operational amplifier OPD.
The operational amplifier OPD and the resistors RD1 and RD2 constitute an amplifier that positively amplifies the voltage VTSQ with reference to the reference temperature voltage VAT 0. Thus, the temperature sensor unit 10 outputs a temperature detection voltage VTD of VAT0+ (1+ RD2/RD1) × (VTSQ-VAT 0). The reference temperature T0 can be adjusted by adjusting the reference temperature voltage VAT 0.
Fig. 31 shows a configuration example of the oscillation circuit 150. The oscillation circuit 150 includes a current source IBX, a bipolar transistor TRX, a resistor RX, a variable capacitance capacitor CX1, and capacitors CX2 and CX 3.
The current source IBX provides a bias current to the collector of the bipolar transistor TRX. The resistor RX is provided between the collector and the base of the bipolar transistor TRX.
One end of the variable capacitance capacitor CX1 whose capacitance is variable is connected to one end of the oscillator XTAL. Specifically, one end of the variable capacitance capacitor CX1 is connected to one end of the oscillator XTAL via the 1 st oscillator terminal (oscillator pad) of the circuit device. One end of the capacitor CX2 is connected to the other end of the oscillator XTAL. Specifically, one end of the capacitor CX2 is connected to the other end of the oscillator XTAL via the 2 nd oscillator terminal (oscillator pad) of the circuit device. One end of the capacitor CX3 is connected to one end of the oscillator XTAL, and the other end is connected to the collector of the bipolar transistor TRX.
A base-emitter current generated by oscillation of the oscillator XTAL flows through the bipolar transistor TRX. When the base-emitter current increases, the collector-emitter current of the bipolar transistor TRX increases, and the bias current branched from the current source IBX to the resistor RX decreases, so that the collector voltage VCX decreases. On the other hand, when the base-emitter current of the bipolar transistor TRX decreases, the collector-emitter current decreases, and the bias current branched from the current source IBX to the resistor RX increases, so the collector voltage VCX increases. This collector voltage VCX is fed back to the oscillator XTAL via a capacitor CX 3.
The oscillation frequency of the oscillator XTAL has a temperature characteristic (for example, the temperature characteristic of fig. 6) which is compensated by the output voltage VQ (frequency control voltage) of the D/a conversion portion 80. That is, the output voltage VQ is input to the variable capacitance capacitor CX1, and the capacitance value of the variable capacitance capacitor CX1 is controlled by the output voltage VQ. When the capacitance value of the variable capacitance capacitor CX1 changes, the resonance frequency of the oscillation circuit changes, and therefore, the fluctuation of the oscillation frequency due to the temperature characteristic of the oscillator XTAL is compensated. The variable capacitance capacitor CX1 may be implemented by, for example, a variable capacitance diode (varactor) or the like.
The oscillation circuit 150 of the present embodiment is not limited to the configuration shown in fig. 31, and various modifications can be made. For example, although CX1 is illustrated as a variable capacitance capacitor in fig. 31, CX2 or CX3 may be a variable capacitance capacitor controlled by the output voltage VQ. In addition, a plurality of CX1 to CX3 may be variable capacitance capacitors controlled by VQ.
5. Modification example
Next, various modifications of the present embodiment will be described. For example, as shown in fig. 21 and 22, the case where the processing unit 50 outputs the frequency control data DDS that changes in units of k × LSB to realize the method of the present embodiment of fig. 11 to 13 has been described, but the present embodiment is not limited to this.
In the modification of fig. 32, a filter circuit 130 composed of an SCF (switched capacitor filter) is provided at a stage subsequent to the D/a converters DACC, DACD. The D/a converter DACC of, for example, 8 bits outputs a voltage DA1 according to the data D (n) at the timing n. Further, the 8-bit D/a converter DACD outputs the voltage DA2 according to the data D (n +1) at the next timing n + 1.
When the clock frequency of the SCF of the filter circuit 130 is fCk, a circuit including the capacitor CS1, the switching elements SS1, and SS2 can realize a resistance RG of 1/(CS1 × fck). A circuit including the capacitor CS2 and the switching elements SS3 and SS4 can realize a resistance RF of 1/(CS2 × fck).
In addition, the time constant τ of the filter circuit 130 can be expressed by the following equation (12).
τ＝RF×CS3＝(CS3/CS2)×(1/fck) (12)
For example, CS3 ═ 5pF, CS2 ═ 0.1pF, and fck ═ 5KHz are used, whereby τ ═ 10msec can be realized. By making the time constant τ sufficiently long in this way, as shown in fig. 34, it is possible to realize an output voltage VQ that gradually changes from the voltage DA1 to the voltage DA2 with the time constant τ.
For example, as shown in fig. 33, when the period TP (for example, 20msec) described in fig. 8 is taken as the horizontal axis and the allowable frequency drift FD (for example, about several ppb) is taken as the vertical axis, the slope is SL1 ═ FD/TP. In this case, the method of the present embodiment of fig. 11 to 13 can be realized by reducing the slope SL2 realized with the time constant τ of fig. 34 as compared with the slope SL 1. That is, the filter circuit 130 having the slope SL1 defined by the period TP and the allowable frequency drift FD and not capable of generating such a strong low-pass filter characteristic is provided at the subsequent stage of the D/a converters DACC and DACD. Thus, as shown in C2 of fig. 11, the output voltage VQ of the D/a converter 80 can have the same voltage waveform as the voltage waveform that changes in steps of the voltage of 1LSB, and the problem of frequency hopping can be solved.
However, when the time constant τ of the filter circuit 130 is longer than the period TP, the output voltage VQ of the filter circuit 130 cannot be corrected for the variation in the temperature characteristic of the oscillator XTAL, and a frequency shift occurs.
For example, fig. 35 is a graph showing a frequency shift with respect to a temperature change in the case where the time constant τ is 20 mesc. By setting τ to TP as shown in fig. 35, the problem of frequency hopping can be solved. On the other hand, fig. 36 and 37 are graphs of frequency shifts with respect to temperature changes when τ is 22msec or 40msec, respectively. As described above, in the modification example of fig. 32, there is a problem that the time constant τ becomes long and the characteristics of the frequency drift deteriorate, and there is a disadvantage that it is difficult to obtain the optimal solution.
Fig. 38 shows an example of the structure of the a/D converter 20. As shown in fig. 38, the a/D conversion unit 20 includes a processing unit 23, a register unit 24, D/a converters DACE, DACF, and a comparison unit 27. Further, an amplifier 28 for a temperature sensor unit may be included. The processing unit 23 and the register unit 24 are provided as a logic unit 22, and the D/a converters DACE and DACF, the comparison unit 27, and the temperature sensor unit amplifier 28 are provided as an analog unit 26.
The register unit 24 stores result data such as intermediate results and final results of a/D conversion. The register unit 24 corresponds to a successive comparison result register in the successive comparison system, for example. The D/a converters DACE, DACF perform D/a conversion on the result data of the register section 24. These DACE and DACF may be D/a converters having the same structures as those of fig. 23 and 24. The comparison unit 27 compares the output voltages of the D/a converters DACE and DACF with a temperature detection voltage VTD (a voltage amplified by the temperature sensor unit amplifier 28). The comparison section 27 may be realized by, for example, a chopper type comparator or the like. The processing unit 23 performs a determination process based on the comparison result of the comparison unit 27, and performs an update process of the result data of the register unit 24. The final temperature detection data DTD obtained by the update process is output from the a/D conversion unit 20 as the a/D conversion result of the temperature detection voltage VTD. With such a configuration, for example, a/D conversion by the successive approximation method, a/D conversion by a method similar to the successive approximation method, and the like can be realized. The method of the present embodiment described with reference to fig. 11 to 13 can be realized by examining the output mode of the temperature detection data DTD of the a/D conversion unit 20 in fig. 38.
Fig. 39 shows a configuration example of a circuit device according to a modification of the present embodiment.
The circuit arrangement of fig. 39 comprises: an a/D conversion unit 20 that performs a/D conversion of the temperature detection voltage VTD from the temperature sensor unit 10 and outputs temperature detection data DTD; a processing unit 50 that performs temperature compensation processing of the oscillation frequency based on the temperature detection data DTD and outputs frequency control data DDS of the oscillation frequency; and an oscillation signal generation circuit 140.
When the temperature changes from the 1 st temperature to the 2 nd temperature, the processing unit 50 outputs the frequency control data DDS changing from the 1 st data corresponding to the 1 st temperature to the 2 nd data corresponding to the 2 nd temperature in units of k × LSB. The oscillation signal generation circuit 140 generates an oscillation signal SSC having an oscillation frequency set by the frequency control data DDS, using the frequency control data DDS and the oscillator XTAL from the processing unit 50.
That is, in fig. 39, unlike fig. 4 and 5, the oscillation signal generating circuit 140 is not provided with the D/a converter 80. The oscillation frequency of the oscillation signal SSC generated by the oscillation signal generation circuit 140 is directly controlled based on the frequency control data DDS from the processing unit 50. That is, the oscillation frequency of the oscillation signal SSC is controlled without passing through the D/a converter.
For example, in fig. 39, the oscillation signal generation circuit 140 has a variable capacitance circuit 142 and an oscillation circuit 150. The oscillation signal generating circuit 140 is not provided with the D/a converter 80 shown in fig. 4 and 5. The variable capacitance circuit 142 is provided instead of the variable capacitance capacitor CX1 in fig. 31, and one end of the variable capacitance circuit 142 is connected to one end of the oscillator XTAL.
The variable capacitance circuit 142 controls the capacitance value thereof based on the frequency control data DDS from the processing unit 50. For example, the variable capacitance circuit 142 includes a plurality of capacitors (capacitor array) and a plurality of switching elements (switch array) that control on and off of the respective switching elements in accordance with frequency control data DDS. Each of the plurality of switching elements is electrically connected to each of the plurality of capacitors. By turning on or off these plurality of switching elements, the number of capacitors, one end of which is connected to one end of the oscillator XTAL, among the plurality of capacitors, changes. Thus, the capacitance value of the controllable variable capacitance circuit 142 is controlled, and the capacitance value of one end of the oscillator XTAL changes. Therefore, the frequency control data DDS can be used to directly control the capacitance of the variable capacitance circuit 142 and control the oscillation frequency of the oscillation signal SSC.
Thus, the method of the present embodiment in which the frequency control data DDS is changed in units of k × LSB as shown in fig. 21 and 22 can be realized in a configuration in which the oscillation signal generation circuit 140 is not provided with the D/a conversion unit 80 as shown in fig. 39. Further, by changing the frequency control data DDS in units of k × LSB, the same effect as the method of the present embodiment described in fig. 11 to 13 can be achieved, and occurrence of frequency hopping in fig. 3 can be suppressed, and communication errors and the like due to frequency hopping can be prevented. In the configuration of fig. 39, the oscillation signal SSC may be generated by a direct digital synthesizer method.
In the configuration of the circuit device in fig. 39, for example, the following expression (13) can be used as the expression corresponding to the expression (1) described in fig. 12 and 13 in the method of the present embodiment.
DV<(FD/FR)×DFS (13)
That is, as described above, the frequency variable range of the oscillation frequency of the oscillation signal generation circuit 140 is FR, and the allowable frequency drift of the oscillation frequency in the predetermined period (TP) is FD. In addition, the full scale value of the frequency control data DDS is set to DFS. For example, when the number of bits of the frequency control data DDS is set to i, the full-scale value DFS can be expressed as 2i(0～2i). However, the full-scale value DFS is not limited thereto. Further, a variation value of the frequency control data DDS at an output interval of the frequency control data DDS by the processing unit 50 is set to DV. This output interval corresponds to TDAC of fig. 11. For example, in fig. 21 and 22, the frequency control data DDS changes in units of k × LSB every output interval. In this case, in the present embodiment, DV is expressed by the above formula (13)<(FD/FR). times.DFS holds.
For example, the processing unit 50 can realize the temperature compensation processing of the oscillation frequency described in fig. 6 and 7 by changing the frequency control data DDS within the range of the full scale value DFS and adjusting the oscillation frequency of the oscillation signal generation circuit 140 within the frequency variable range FR shown in fig. 13.
However, when the variation DV of the output interval (TDAC) of the frequency control data DDS becomes large, for example, DV ≧ (FD/FR) × DFS, the frequency drift of the oscillation frequency exceeds the allowable frequency drift FD, resulting in the frequency hopping shown in fig. 14.
On the other hand, in the present embodiment, since the frequency control data DDS is changed by the small change value DV at which the relationship DV < (FD/FR) × DFS is satisfied, occurrence of the frequency hopping shown in fig. 14 can be suppressed. For example, as shown in fig. 21 and 22, the frequency control data DDS is changed in units of k × LSB, thereby suppressing occurrence of frequency hopping.
In addition, in the above formula (13), it is also desirable to establish the following formula (14) as in the above formula (2).
1/2i<(FD/FR) (14)
In this case, i in the above equation (14) is the number of bits of the frequency control data DDS. The processing unit 50 outputs 1/2i<Frequency control data DDS having a high number of bits i that holds (FD/FR), thereby suppressing occurrence of frequency hopping.
For example, when the full-scale value DFS of the frequency control data DDS is multiplied to both sides of the above expression (14), the following expression (15) is obtained.
DFS×1/2i<(FD/FR)×DFS (15)
Left DFS × 1/2 of above formula (15)iCorresponding to 1LSB of the frequency control data DDS. The above expressions (14) and (15) mean that DFS × 1/2 corresponding to the 1LSB is set to be equivalentiLess than (FD/FR). times.DFS. If so, DFS × 1/2i<
(FD/FR) × DFS, when the frequency control data DDS is changed in units of 1LSB as shown in fig. 21 and 22, the frequency drift of the oscillation frequency does not exceed the allowable frequency drift FD, and occurrence of frequency hopping can be suppressed.
6. Oscillator, electronic apparatus, and moving object
Fig. 40 shows a configuration example of an oscillator 400 including the circuit device 500 of the present embodiment. As shown in fig. 40, oscillator 400 includes oscillator 420 and circuit device 500. The vibrator 420 and the circuit device 500 are mounted in the package 410 of the oscillator 400. Terminals of the vibrator 420 and terminals (pads) of the circuit device 500(IC) are electrically connected by internal wirings of the package 410.
Fig. 41 shows a configuration example of an electronic device including the circuit device 500 of the present embodiment. The electronic device includes the circuit device 500 of the present embodiment, a resonator 420 such as a quartz resonator, an antenna ATN, a communication unit 510, and a processing unit 520. The display device may further include an operation unit 530, a display unit 540, and a storage unit 550. Oscillator 400 is configured by oscillator 420 and circuit device 500. The electronic device is not limited to the configuration shown in fig. 41, and various modifications such as omitting a part of the components and adding another component may be made.
As the electronic device in fig. 41, for example, a wearable device such as a GPS built-in clock, a living body information measurement device (a pulse meter, a pedometer, or the like), or a head-mounted display device, a portable information terminal (a portable terminal) such as a smartphone, a mobile phone, a portable game device, a notebook PC, or a tablet PC, a content providing terminal for delivering content, a video device such as a digital camera or a video camera, or a network work related device such as a base station or a router, and the like can be assumed.
The communication unit 510 (wireless circuit) performs processing for receiving data from the outside or transmitting data to the outside via the antenna ATN. The processing unit 520 performs control processing of the electronic device, various kinds of digital processing of data transmitted and received via the communication unit 510, and the like. The function of the processing unit 520 can be realized by a processor such as a microcomputer.
The operation unit 530 is used for a user to perform an input operation, and may be implemented by operation buttons, a touch panel display, and the like. The display unit 540 is used to display various information, and may be implemented by a display such as a liquid crystal display or an organic EL display. When a touch panel display is used as the operation unit 530, the touch panel display also functions as the operation unit 530 and the display unit 540. The storage unit 550 stores data, and its function can be realized by a semiconductor memory such as a RAM or a ROM, a HDD (hard disk), or the like.
Fig. 42 shows an example of a mobile body including the circuit device of the present embodiment. The circuit device (oscillator) according to the present embodiment can be mounted on various moving bodies such as a vehicle, an airplane, a motorcycle, a bicycle, or a ship, for example. The mobile body is an apparatus or device that has a driving mechanism such as an engine or a motor, a steering mechanism such as a steering wheel or a rudder, and various electronic devices (vehicle-mounted devices), and moves on land, in the air, and on the sea. Fig. 42 schematically shows an automobile 206 as a specific example of the mobile body. The automobile 206 incorporates the circuit device of the present embodiment and an oscillator (not shown) having a vibrator. The control device 208 operates according to the clock signal generated by the oscillator. The control device 208 controls the hardness of the suspension or the brakes of the wheels 209 in accordance with, for example, the posture of the vehicle body 207. For example, the control device 208 can be used to automatically operate the vehicle 206. The device incorporating the circuit device and the oscillator according to the present embodiment is not limited to the control device 208, and may be incorporated into various devices (in-vehicle devices) provided in a mobile body such as the automobile 206.
While the present embodiment has been described in detail, those skilled in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages of this invention. Therefore, all such modifications are included in the scope of the present invention. For example, in the specification or the drawings, a term described at least once together with a broader or synonymous non-general term may be replaced with a different term in any part of the specification or the drawings. All combinations of the embodiment and the modifications are also included in the scope of the present invention. The circuit device, the oscillator, the electronic apparatus, the structure or operation of the mobile object, the D/a conversion method, the frequency control data processing method, the frequency control data output method of the processing unit, the voltage output method of the D/a conversion unit, the frequency control method of the oscillator, and the like are not limited to those described in the present embodiment, and various modifications can be made.
Description of the reference symbols
XTAL … oscillator, DACA-DACF … D/A converter,
OPA-OPD, OPS … operational amplifier, CX 1-CX 3 … capacitor,
VTD … temperature detection voltage, DTD … temperature detection data, DDS … frequency control data, VQ … output voltage (frequency control voltage), SSC … oscillation signal,
t1 … temperature 1, T2 … temperature 2, DTD1 … temperature 1 detection data, DTD2 … temperature 2 detection data, VC1 … temperature 1 control voltage, VC2 … temperature 2 control voltage, VDF … differential voltage, VA … voltage amplitude,
FD … allows frequency drift during TAD, TDAC …, TP … specification,
FR … frequency variable range, VFS … full scale voltage,
DAT1 … data 1, DAT2 … data 2,
a 10 … temperature sensor section, a 20 … A/D conversion section, a 22 … logic section, a 23 … processing section, a 24 … register section, a 26 … analog section, a 27 … comparison section,
28 … temperature sensor part amplifier, 50 … processing part, 52 … control part, 53 … judging part, 54, 55 … comparing part, 58 … multiplier, 59 … adder, 60 … arithmetic part,
61. a 62 … type conversion section, a 63 … multiplexer, a 64 … operator,
a 65 … multiplexer, 66, 67 … working registers, a 68 … type conversion section,
69 … working registers, 70 … output, 71 … multiplexer,
a 72 … output register, a 73 … LSB adder, a 74 … LSB reducer,
80 … D/A converter, 90 … modulation circuit, 100 … D/A converter,
104. 106 … decoder, 120 … filter circuit, 130 … filter circuit, 140 … oscillation signal generating circuit, 142 … variable capacitance circuit, 150 … oscillation circuit,
160 … cache circuits, 180 … memory sections, 190 … ROM,
206 … car, 207 … car body, 208 … control device, 209 wheel 209 …,
a 400 … oscillator, a 410 package, a 420 … vibrator, a 500 … circuit arrangement,
510 … communication part, 520 … processing part, 530 … operation part, 540 … display part and 550 … storage part
Claims (20)
1. A circuit arrangement, characterized in that the circuit arrangement has:
an A/D converter for A/D converting the temperature detection voltage from the temperature sensor unit and outputting temperature detection data;
a processing unit that performs temperature compensation processing of an oscillation frequency based on the temperature detection data and outputs frequency control data of the oscillation frequency; and
an oscillation signal generation circuit for generating an oscillation signal of the oscillation frequency set based on the frequency control data by using the frequency control data from the processing unit and a vibrator,
the processing unit outputs the frequency control data changing from 1 st data corresponding to the 1 st temperature to 2 nd data corresponding to the 2 nd temperature in units of k × LSB when the temperature changes from 1 st temperature to 2 nd temperature, where k ≧ 1,
when the output frequency of the frequency control data that changes in k × LSB of the processing unit is fs, and the change in the oscillation frequency due to the change in k × LSB of the frequency control data is Δ f,
let us satisfy Δ f/fs<1/106(Δ f, fs) is (Δ f1, fs1) and the other is (Δ f2, fs2), Δ f1 > Δ f2, fs1 > fs2,
(1) during the period 1 of the first time period,
the output frequency of the frequency control data is fs1,
the processing unit outputs the frequency control data that changes in k × LSB units using k, which is a value corresponding to Δ f1,
(2) during a2 nd period different from the 1 st period,
the output frequency of the frequency control data is fs2,
the processing unit outputs the frequency control data that changes in k × LSB units using k of a value corresponding to Δ f 2.
2. The circuit arrangement according to claim 1,
Δ f/fs at fs ≧ 1kHz<1/106，
In the case of fs <1kHz, Δ f <1 mHz.
3. The circuit arrangement according to claim 1,
the 1 st period is an operation start period of the circuit device,
the 2 nd period is a period after the operation start period of the circuit device.
4. The circuit arrangement according to claim 1,
the vibrator is a quartz vibrator.
5. The circuit arrangement according to claim 4,
the quartz oscillator is an AT-cut oscillator, an SC-cut oscillator or an acoustic surface wave resonator.
6. The circuit arrangement according to claim 1,
the oscillation signal generation circuit includes:
a D/a conversion unit that performs D/a conversion on the frequency control data from the processing unit; and
an oscillation circuit for generating the oscillation signal using the output voltage of the D/A converter and the oscillator,
the output frequency fs of the frequency control data is a sampling frequency of the D/a conversion section,
the change Δ f in the oscillation frequency is the amount of change in the oscillation frequency caused by 1 time of the D/a conversion.
7. The circuit arrangement according to claim 6,
the D/A conversion section includes:
a D/A converter that performs D/A conversion of the frequency control data; and
a filter circuit that smoothes an output voltage of the D/A converter.
8. The circuit arrangement according to claim 6,
when the frequency control voltage, which is the output voltage of the D/A converter corresponding to the 1 st temperature, is set to the 1 st control voltage and the frequency control voltage corresponding to the 2 nd temperature is set to the 2 nd control voltage,
when the temperature changes from the 1 st temperature to the 2 nd temperature, the output voltage that changes with a voltage width smaller than the absolute value of the difference voltage between the 1 st control voltage and the 2 nd control voltage is output from the D/a conversion unit to the oscillation circuit.
9. The circuit arrangement according to claim 8,
when the minimum resolution of data in the D/A conversion is LSB, the D/A conversion unit outputs the output voltage varied in steps of voltage corresponding to k × LSB, where k is equal to or greater than 1.
10. The circuit arrangement according to claim 9,
k＝1。
11. the circuit arrangement according to claim 8,
when the temperature detection data of the A/D conversion part is 1 st temperature detection data when the temperature is 1 st temperature, and the temperature detection data of the A/D conversion part is 2 nd temperature detection data when the temperature is 2 nd temperature,
the 1 st control voltage is the frequency control voltage corresponding to the 1 st temperature detection data in the temperature compensation characteristic of the temperature compensation process,
the 2 nd control voltage is the frequency control voltage corresponding to the 2 nd temperature detection data in the temperature compensation characteristic of the temperature compensation process.
12. The circuit arrangement according to claim 1,
the processing unit compares the 1 st data which is the operation result data of the previous temperature compensation process with the 2 nd data which is the operation result data of the current temperature compensation process,
performing, in a case where the 2 nd data is larger than the 1 st data, a process of adding a prescribed value to the 1 st data until addition result data reaches the 2 nd data, and outputting the addition result data as the frequency control data,
in a case where the 2 nd data is smaller than the 1 st data, a process of subtracting a prescribed value from the 1 st data is performed until subtraction result data reaches the 2 nd data, and the subtraction result data is output as the frequency control data.
13. The circuit arrangement of claim 12,
the processing unit includes:
a calculation unit that performs calculation of the temperature compensation processing of the oscillation frequency based on the temperature detection data and outputs the calculation result data of the temperature compensation processing; and
an output unit that receives the calculation result data from the calculation unit and outputs the frequency control data,
when the operation result data changes from the 1 st data corresponding to the 1 st temperature to the 2 nd data corresponding to the 2 nd temperature, the output unit outputs the frequency control data that changes from the 1 st data to the 2 nd data in units of k × LSB.
14. A circuit arrangement, characterized in that the circuit arrangement has:
an A/D converter for A/D converting the temperature detection voltage from the temperature sensor unit and outputting temperature detection data;
a processing unit that performs temperature compensation processing of an oscillation frequency based on the temperature detection data and outputs frequency control data of the oscillation frequency; and
an oscillation signal generation circuit for generating an oscillation signal of the oscillation frequency set based on the frequency control data by using the frequency control data from the processing unit and a vibrator,
when the frequency variable range of the oscillation frequency realized by the oscillation signal generation circuit is FR, the allowable frequency drift of the oscillation frequency within a predetermined period is FD, the full-scale value of the frequency control data is DFS, and the variation value of the frequency control data at the output interval of the frequency control data of the processing unit is DV,
DV<(FD/FR)×DFS。
15. the circuit arrangement of claim 14,
when the output frequency of the frequency control data of the processing unit is fs and the change of the oscillation frequency caused by the change of the change value DV of the frequency control data is Δ f, Δ f/fs<1/106。
16. The circuit arrangement of claim 15,
Δ f/fs at fs ≧ 1kHz<1/106，
In the case of fs <1kHz, Δ f <1 mHz.
17. The circuit arrangement of claim 14,
in the case where fs is an output frequency of the frequency control data of the processing section and Δ f is a change in the oscillation frequency due to a change in the variation value DV of the frequency control data,
in the case of fs <1kHz, Δ f <1 mHz.
18. An oscillator comprising the circuit device according to claim 1 and the oscillator.
19. An electronic device, characterized in that the electronic device is provided with a circuit arrangement as claimed in claim 1.
20. A movable body characterized by having the circuit device according to claim 1.
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| JP2016099723A JP2017085536A (en) | 2015-10-27 | 2016-05-18 | Circuit device, oscillator, electronic equipment and mobile body |
| JP2016-099722 | 2016-05-18 | ||
| JP2016-099723 | 2016-05-18 | ||
| JP2016099722A JP6720687B2 (en) | 2015-10-27 | 2016-05-18 | Circuit devices, oscillators, electronic devices and mobile units |
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| CN113349463A (en) * | 2021-06-29 | 2021-09-07 | 荣成歌尔微电子有限公司 | Airflow sensor and electronic cigarette |
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