JP6771823B2 - Mobile terminal - Google Patents

Description

The present invention relates to an intermittent reception technology for a mobile terminal, and particularly when a mobile terminal is configured by using a standard processor for embedded devices, the existing hardware is added by adding less hardware resources under the constraint of the number of interface signal lines. It relates to a mobile terminal that can incorporate a time scheduler function in intermittent reception control into hardware.

In order to make the best use of portability, mobile terminals for mobile communication are required to have a technology for lengthening the continuous standby time so that the mobile terminals can be continuously used without being charged. In order to improve this continuous standby time, it is important to have a technology to reduce the power consumption during incoming call standby. After receiving a signal for a certain reception time and confirming the presence or absence of an incoming call, it is in a sleep state for a predetermined period. Therefore, a so-called intermittent reception technique of repeating the operation of receiving a signal again for a certain reception period is widely used (see, for example, Patent Document 1 and Patent Document 2).

On the other hand, in mobile communication, with the rapid increase in users and the evolution of usage patterns, higher performance continues to be required for mobile terminals, with the aim of shortening the development period and reducing equipment costs. As a product development method for mobile terminals, a method is adopted in which a semiconductor vendor consistently performs from specification to design of a processor for embedded devices and develops a product using ASPP (Application Specific Standard Product) provided as a standard product. (See, for example, Non-Patent Document 1).

JP-A-2002-368676 Japanese Unexamined Patent Publication No. 2008-160407

Kiyotaka Takahashi, Etsuya Shibayama, "Software Development Support for Multi-Core Processors for Embedded Systems", IPSJ Journal: Programming, Vol.48, No.SIG 4 (PRO 32), pp.27-47 (2007) ..

Non-Patent Document 1 shows an example of developing a mobile phone using an OMAP processor manufactured by TI (equipped with a CPU core manufactured by ARM and a DSP core manufactured by TI) as a processor for embedded devices. Since processors for embedded devices have been developed as standard products, many of them do not have a circuit-mounted time scheduler for performing the above-mentioned intermittent reception. In such a case, the time is mainly applied to the second processing unit (embodied by a relatively low-performance microcomputer or the like) prepared for display control of the standby screen during sleep of the mobile terminal and reception of key interrupts. The function of the scheduler is incorporated.

In this case, since both the processor for embedded devices and the second processing unit are off-the-shelf products, the number of signal lines of the interface signal connecting the two is restricted, and under the constraint on the number of interface signal lines, intermittent reception control is performed. Hardware design that satisfies the timing conditions is required. Further, since the second processing unit has relatively low performance, the data bit length to be handled is also relatively short, and the time of the wireless frame length cannot be expressed by the data bit length, so that the time scheduler function can be realized. There is also a situation that the timer part needs to be devised. That is, under the constraint of the number of interface signal lines, a technique of incorporating the function of the time scheduler into the second processing unit by adding less hardware resources is desired.

Therefore, the present invention presents a time scheduler function in intermittent reception control to existing hardware by adding less hardware resources under the constraint of the number of interface signal lines when configuring a mobile terminal using a standard processor for embedded devices. The purpose is to provide a mobile terminal capable of incorporating the above.

In order to solve the above problems, the invention of claim 1 includes a radio unit that processes a radio frequency signal, a processing unit that includes at least a CPU core and a DSP core and processes a baseband signal, and the radio. A mobile terminal comprising a timer unit including a counter that counts the clock with a sample timing from the unit as a clock input , a CPU, and a second processing unit that performs intermittent control of the processing unit. At the time of transition to the sleep state, the unit notifies the second processing unit of the start timing from the CPU core, and supplies a positive logic or negative logic DSP intermittent sleep start signal from the DSP core to the second processing unit. , The second processing unit masks the interrupts other than the external interrupt by the DSP intermittent sleep start signal at the rising or falling edge of the DSP intermittent sleep start signal, and the DSP intermittent sleep start signal. when an external interrupt by falling or rising edge of the timer unit said counter counts to start of the count value of the counter can be activated to release the sleep state of the processor upon reaching the start timing It is characterized by.

In the invention of claim 1, when the DSP intermittent sleep start signal is positive logic, the second processing unit masks the interrupts other than the external interrupt by the DSP intermittent sleep start signal at the rising edge of the DSP intermittent sleep start signal. At the time of an external interrupt due to the falling edge of the DSP intermittent sleep start signal, the counter of the timer unit is started to count, and when the count value of the counter reaches the start timing, the sleep state of the processing unit is released and started. Further, when the DSP intermittent sleep start signal has negative logic, the second processing unit masks interrupts other than external interrupts due to the DSP intermittent sleep start signal at the falling edge of the DSP intermittent sleep start signal, and DSP intermittent sleep. At the time of an external interrupt due to the rising edge of the start signal, the counting of the counter of the timer unit is started, and when the counting value of the counter reaches the start timing, the sleep state of the processing unit is released and started. Here, during the period from the first edge for masking interrupts to the second edge for starting counter counting, interrupts other than external interrupts due to the DSP intermittent sleep start signal, for example, key interrupts by the user are not accepted. It is desirable to limit the period from the first edge to the second edge to less than the time (generally 100 [msec]) that can be tolerated even if there is no reaction from the device side to the user operation.

The invention of claim 2 is characterized in that, in the mobile terminal according to claim 1, the rising edge or falling edge of the DSP intermittent sleep start signal is located in the first half of one cycle of the clock.

The invention of claim 3 is the mobile terminal according to any one of claim 1 or 2, wherein the processing unit is in a normal state, a sleep state, and a deep sleep state of the CPU core and the DSP core. The processing unit includes a power management unit that manages the transition, and the processing unit notifies the second processing unit from the CPU core of the startup timing and the reception timing at the time of transition to the deep sleep state, and the DSP core performs the DSP intermittent sleep. After supplying the start signal to the second processing unit, the process shifts to the sleep state and then to the deep sleep state, and the second processing unit shifts to the power when the count value of the counter reaches the start timing. Notifying the management unit to that effect, the deep sleep state of the CPU core and the DSP core is released, the DSP core is activated to shift to the state of waiting for a reception interrupt, and the count value of the counter is set to the reception timing. When it reaches the DSP core, the DSP core is notified to that effect and the reception process is started.

In the invention of claim 3, the power management unit manages the transition between the normal state, the sleep state and the deep sleep state. For example, when the supply voltage is lowered to reduce power consumption, the sleep state is a state in which the CPU core and the DSP core are lowered to the minimum voltage required to execute the program, and the deep sleep state is the CPU core and the DSP core. Is in a state of being lowered to the minimum voltage required for operation.

According to the invention of claim 4, in the mobile terminal according to claim 3, the timer unit has a first comparison set value register in which a comparison set value of the start timing is set at a predetermined timing, and the reception timing at a predetermined timing. The second comparison setting value register in which the comparison setting value is set is compared with the output of the counter, the value of the first comparison setting value register, and the value of the second comparison setting value register for each cycle of the clock. Then, when any of the values is matched, the counter has a comparison unit that notifies the CPU of the second processing unit of a timer interrupt, and the counter is an N-bit (N is a positive integer) counter and is wireless. When the numerical value obtained by dividing the time of the frame length by the cycle of the clock exceeds the maximum value that can be expressed by N bits, the second processing unit performs the start timing at each predetermined cycle defined by the count value of the counter. Alternatively, it is determined whether or not the difference value obtained by subtracting the elapsed time from the start of counting of the counter from the reception timing can be expressed by N bits, and if it can be expressed by N bits, the remaining count is performed at the timing of the predetermined cycle. The number is set in the corresponding first comparison set value register or the second comparison set value register.

In the invention of claim 4, it is determined at each predetermined cycle whether or not the difference value obtained by subtracting the elapsed time from the start of counting of the counter from the start timing can be expressed by N bits, and if it can be expressed by N bits. The remaining count number is set in the first comparison set value register at the timing of the predetermined cycle. Further, for each predetermined cycle, it is determined whether or not the difference value obtained by subtracting the elapsed time from the start of counting of the counter from the reception timing can be expressed by N bits, and if it can be expressed by N bits, the timing of the predetermined cycle. Set the remaining count number in the second comparison set value register. Here, if the predetermined cycle defined by the count value of the counter is set to 1/2 ^M (M is a positive integer of 0 or more) of the maximum period that can be counted by the counter, it becomes easy to set the predetermined cycle.

According to the invention of claim 1, at the first edge of the DSP intermittent sleep start signal, the second processing unit is made to mask the interrupt other than the external interrupt due to the DSP intermittent sleep start signal, and the second DSP intermittent sleep start signal is generated. Since counting of the counter of the timer section is started at the time of an external interrupt due to the edge of, the time required for receiving and executing the interrupt (clearing the contents of the counter and enabling the counting operation) can be shortened. It is possible to keep the start timing of the external interrupt by the DSP intermittent sleep start signal and the counting start timing of the timer unit counter within the same clock cycle, and the counting operation of the timer unit counter is performed by the processing unit (DSP core). Can be synchronized with. Further, since two different types of instructions are given to the second processing unit using one interface signal, hardware that satisfies the timing condition in intermittent reception control even when the number of interface signal lines is restricted. The design can be realized. In addition, a processing unit equipped with a CPU core and a DSP core is embodied in a standard processor for embedded devices, and a microcomputer prepared for display control of the standby screen during sleep of a mobile terminal and for receiving key interrupts, etc. If the second processing unit is used, it is possible to realize a mobile terminal capable of incorporating a time scheduler function in interrupt reception control into existing hardware even under the constraint of the number of interface signal lines.

According to the invention of claim 2, since the rising or falling edge of the DSP intermittent sleep start signal is located in the first half of one cycle of the clock, the time required for receiving and executing the interrupt is set to one cycle of the clock. In the latter half of the above, it is possible to reliably fit the start timing of the external interrupt by the DSP intermittent sleep start signal and the counting start timing of the timer section counter within the same clock cycle, and the timer section counter counting. The operation can be reliably synchronized with the processing unit (DSP core).

According to the invention of claim 3, the present invention can be applied to a processor (standard product) for embedded devices having a sleep mode and a deep sleep mode.

According to the invention of claim 4, the first comparison setting value register and the second comparison setting value register are provided for setting the comparison value of the start timing and the reception timing, and at the timing of the predetermined cycle defined by the count value of the counter. In addition, when the difference value obtained by subtracting the elapsed time from the start of counting of the counter can be expressed by N bits, the remaining count number is set as the comparison value, so that the data bit length handled by the second processing unit is short. The present invention can be applied even when the time of the radio frame length cannot be expressed by the data bit length. As a result, it is possible to realize a mobile terminal capable of incorporating a time scheduler function in intermittent reception control into existing hardware by adding less hardware resources.

It is a block diagram of the mobile terminal which concerns on embodiment of this invention. It is explanatory drawing (the 1) explaining the flow of the intermittent control in the mobile terminal 1 of embodiment. It is explanatory drawing (the 2) explaining the flow of intermittent control in the mobile terminal 1 of embodiment. It is explanatory drawing (the 1) which explains the flow of the intermittent control in the mobile terminal 1 of embodiment by exemplifying the count value of a counter and each comparison set value. It is explanatory drawing (the 2) explaining the flow of the intermittent control in the mobile terminal 1 of embodiment by exemplifying the count value of a counter and each comparison set value. It is explanatory drawing explaining the setting timing and the settable range of the comparison setting value in the setting timing.

Hereinafter, the present invention will be described based on the illustrated embodiment. There are various aspects of mobile communication terminals such as mobile phones and PDAs (Personal Digital Assistants), and the present invention can be applied to any type of mobile terminal. .. In the following description, an example in which an OMAP processor manufactured by TI (equipped with a CPU core manufactured by ARM and a DSP core manufactured by TI) is used as a processor for embedded devices in a mobile phone will be shown.

FIG. 1 is a configuration diagram of a mobile terminal 1 according to an embodiment of the present invention. In the figure, the mobile terminal 1 incorporates a radio unit 3 that processes a radio frequency signal, a processing unit 4 that processes a baseband signal, and a time scheduler function as functional blocks, and is in sleep mode. It includes a second processing unit 5 prepared for display control of the standby screen and reception of key interrupts.

Here, a sample timing signal (which is an external load pulse signal and has a clock frequency of 128 [kHz]) is constantly supplied from the radio unit 3 to the processing unit 4 and the second processing unit 5 as a clock CL. The functional blocks are synchronized. Synchronous control with the base station (not shown) and management of frames, slots, and symbol timings are performed by a program executed on the DSP core of the processing unit 4.

The processing unit 4 is a processor for embedded devices (OMAP processor manufactured by TI), and includes a CPU core 6 manufactured by ARM, a DSP core 7 manufactured by TI, and a power management unit 8.

Here, the CPU core 6 mainly executes system control including OS (Operating System) processing and various application programs, and as an interface with the second processing unit 5, the I2C (Inter-Integrated Circuit) interface unit 61 and It has a GPIO (General Purpose Input-Output) interface unit 62. When the processing unit 4 shifts to the deep sleep state, the CPU core 6 notifies the second processing unit 5 of the DSP activation timing and the reception timing by the DSP activation / reception timing notification signal 101 via the I2C interface unit 61. To do. Here, the DSP activation timing is the timing for activating the CPU core 6 and the DSP core 7 after the deep sleep, and the reception timing is the timing for starting the reception process by the DSP core 7 after the deep sleep. Further, after the external interrupt to the second processing unit 5 is activated by the DSP intermittent sleep start signal 104 described later, the CPU core 6 enters the sleep state and enables the deep sleep request signal 103 via the GPIO interface unit 62. , Requests the second processing unit 5 to shift to the deep sleep state. Further, as will be described later, when the count value of the counter 11 of the second processing unit 5 (timer unit 10) reaches the DSP start timing previously notified, the second processing unit 5 notifies the DSP start instruction signal 102. The processing unit 4 is released from the sleep state, and the CPU core 6 receives the DSP start instruction signal 102 via the I2C interface unit 61.

Further, the DSP core 7 mainly executes media processing such as audio and video, and has a GPIO (General Purpose Input-Output) interface unit 71 as an interface with the second processing unit 5. When the processing unit 4 shifts to the deep sleep state, the DSP core 7 outputs the DSP intermittent sleep start signal 104 (positive logic signal) to the second processing unit 5 via the GPIO interface unit 71. At the rising edge of the DSP intermittent sleep start signal 104, the CPU 9 of the second processing unit 5 is instructed to mask interrupts other than external interrupts due to the DSP intermittent sleep start signal 104, and the DSP intermittent sleep start signal after a predetermined time. The counting of the counter 11 of the timer unit 10 is started by the external interrupt by the falling edge of 104. Further, as will be described later, when the count value of the counter 11 of the second processing unit 5 (timer unit 10) reaches the reception timing previously notified, the second processing unit 5 enables the DSP reception timing signal 105. The DSP core 7 receives the DSP reception timing signal 105 via the GPIO interface unit 71.

Further, the power management unit 8 manages the transition of the CPU core 6 and the DSP core 7 to the normal state, the sleep state, and the deep sleep state. For example, when reducing the supply voltage to the CPU core 6 and the DSP core 7 to reduce the power consumption, the sleep state is a state in which the CPU core 6 and the DSP core 7 are lowered to the minimum voltage required to execute the program. Yes, the deep sleep state is a state in which the voltage is lowered to the minimum required for the CPU core 6 and the DSP core 7 to operate. Specifically, when the CPU 9 of the second processing unit 5 sets the negative logic deep sleep signal 106 to enable (Low level), the CPU core 6 and the DSP core 7 shift to the deep sleep state, and the second processing unit 5 When the CPU 9 of the 5 sets the deep sleep signal 106 to disable (High level), the CPU core 6 and the DSP core 7 are released from the deep sleep state.

Next, the second processing unit 5 is prepared for display control of the standby screen during sleep of the mobile terminal 1 and reception of key interrupts, and is embodied by a 16-bit microcomputer in this embodiment. .. The second processing unit 5 includes a timer unit 10, a CPU 9, an I2C interface unit 51, and a GPIO interface unit 52.

The CPU 9 includes a first buffer 16 and a second buffer 17 that hold the DSP start timing and the reception timing notified from the CPU core 6 of the processing unit 4 via the DSP start / reception timing notification signal 101, respectively. ..

As described above, when the processing unit 4 shifts to the deep sleep state, first, the DSP core 7 prepares to start counting by the counter 11 of the timer unit 10 via the DSP intermittent sleep start signal 104. Will be notified. On the second processing unit 5 side, the GPIO interface unit 52 detects the rising edge of the DSP intermittent sleep start signal 104 to determine that the notification has been made. As a preparatory process, the CPU 9 masks interrupts other than the external interrupt by the DSP intermittent sleep start signal 104, and enters a state of waiting for an external interrupt by the DSP intermittent sleep start signal 104. At this time, the CPU 9 disables the DSP reception timing signal 105. When the count value of the counter 11 of the timer unit 10 reaches the reception timing (contents held in the second buffer 17), the DSP reception timing signal 105 is enabled and notifies the processing unit 4 to that effect. Therefore, this disable setting is required as a preliminary step.

Further, the notification of the external interrupt by the DSP intermittent sleep start signal 104 from the DSP core 7 is determined by detecting the falling edge of the DSP intermittent sleep start signal 104 in the GPIO interface unit 52. Based on this notification, the CPU 9 causes the counter 11 of the timer unit 10 to start counting the clock CL. Specifically, the start operation of the counter 11 is an operation of setting the enable terminal of the counter 11 to "valid" and clearing the contents of the counter 11. At this time, as described above, the interrupts other than the external interrupt by the DSP intermittent sleep start signal 104 are masked, and there is no interrupt handler overhead. Therefore, the reception and execution time of this external interrupt is the DSP intermittent sleep start signal 104. The time required for the falling edge detection and the start operation of the counter 11 can be shortened to about half the cycle of the clock CL. Further, this makes it possible to keep the start timing of the external interrupt by the DSP intermittent sleep start signal 104 and the count start timing of the counter 11 of the timer unit 10 within the same cycle of the clock CL, and the counter 11 of the timer unit 10 The counting operation of can be synchronized with the processing unit 4 (DSP core 7). If the timing of the falling edge of the DSP intermittent sleep start signal 104 is set to be located in the first half of one cycle of the clock CL, the time required for receiving and executing the external interrupt is set to the latter half of the cycle of the clock CL. The start timing of the external interrupt by the DSP intermittent sleep start signal 104 and the counting start timing of the counter 11 of the timer unit 10 can be surely stored in the same cycle of the clock CL.

When the count value of the counter 11 of the timer unit 10 reaches the DSP start timing (contents held in the first buffer 16) after the processing unit 4 shifts to the deep sleep state, the timer unit 10 sends the CPU 9 to the CPU 9. The timer interrupt is notified, and the CPU 9 disables the deep sleep signal 106 in the GPIO interface unit 52. In response to this, on the processing unit 4, the CPU core 6 and the DSP core 7 shift from the deep sleep state to the sleep state under the control of the power management unit 8, and the GPIO interface unit 62 of the CPU core 6 receives the deep sleep request signal 103. Is set to disabled. Then, the CPU 9 confirms that the deep sleep request from the processing unit 4 side has been canceled, and notifies the DSP start instruction signal 102 in the I2C interface unit 51. In response to this, the processing unit 4 side releases the sleep state.

Further, when the count value of the counter 11 of the timer unit 10 reaches the reception timing (contents held in the second buffer 17), the timer unit 10 notifies the CPU 9 of the timer interrupt, and the CPU 9 is the GPIO interface unit. At 52, the DSP reception timing signal 105 is enabled. In response to this, the processing unit 4 side starts the reception processing by the DSP core 7.

Next, a specific configuration of the timer unit 10 will be described. The timer unit 10 compares the reception timing with the counter 11 that counts the clock CL with the sample timing from the radio unit 3 as the clock input, the first comparison setting value register 12 in which the comparison setting value of the DSP start timing is set, and the reception timing. A second comparison set value register 13 in which a set value is set, a third comparison set value register 14 in which a comparison set value for defining a predetermined cycle (setting timing) is set based on the count value of the counter 11, and a clock. A comparison unit 15 that compares the output of the counter 11 with the value of the first comparison setting value register 12, the value of the second comparison setting value register 13, and the value of the third comparison setting value register 14 for each CL cycle. To be equipped. When any of the register values is matched in the comparison unit 15, a timer interrupt is notified to the CPU 9.

If the data bit length handled by the second processing unit 5 (timer unit 10) can express the time of the wireless frame length, the DSP activation timing and reception timing notified via the DSP activation / reception timing notification signal 101. May be set in the first comparison setting value register 12 and the second comparison setting value register 13, respectively. In other words, the first buffer 16 and the second buffer 17 in the CPU 9, and the third comparison set value register 14 are required because the radio frame length time exceeds the numerical value expressed in 16 bits. Is.

In the comparison unit 15, the timer interrupt when the value of the third comparison setting value register 14 is matched defines the predetermined period, and the timer interrupt sets the first comparison setting value register 12 and the second comparison setting value register 13. It will be the timing. For each set timing, it is determined whether or not the difference value obtained by subtracting the elapsed time from the start of counting of the counter 11 from the value of the DSP start timing in the first buffer 16 can be expressed in 16 bits, and can be expressed in 16 bits. In this case, the remaining count number is set in the first comparison set value register 12 at the set timing. Further, for each set timing, it is determined whether or not the difference value obtained by subtracting the elapsed time from the start of counting of the counter 11 from the value of the reception timing in the second buffer 17 can be expressed in 16 bits, and can be expressed in 16 bits. In this case, the remaining count number is set in the second comparison set value register 13 at the set timing. Here, the elapsed time from the start of counting of the counter 11 is "the current counting value of the counter 11 + the counting cycle of the counter 11 x the number of overflows of the counter 11" or "predetermined cycle x the number of timer interrupts that specify the setting timing". It is calculated by.

Next, the flow of intermittent control in the mobile terminal 1 of this embodiment will be described with reference to FIGS. 2 and 3. In FIGS. 2 and 3, (a) shows the relationship between the super frame and the data reception processing section, and (b), (c), (d), and (e) show the DSP core 7 and the CPU core 6, respectively. The processing flow in the interface unit, the second processing unit 5, and the timer unit 10 of the CPU core 6 is shown, and the DSP intermittent sleep start signal 104 and the deep sleep are shown in (f), (g), (h), and (i), respectively. The time chart of the request signal 103, the deep sleep signal 106, and the DSP reception timing signal 105 is shown. In the following description, the flow of the processing steps shown in (b), (c), (d), and (e) will be described.

At the time of standby, if reception processing is performed by the DSP core 7 and there is no incoming call, the processing unit 4 shifts to the deep sleep state. In that case, first, the DSP core 7 shifts to the deep sleep state. The DSP start timing and the reception timing at which the DSP core 7 starts the reception process after the start is set (step S11 in FIG. 2). These set DSP start timings and reception timings are notified to the CPU core 6, set as intermittent information in the CPU core 6 (step S21), and in the I2C interface unit 61, the DSP start / reception timing notification signal 101 is used to set the DSP start timing and reception timing. 2 Serial transmission to the processing unit 5 (step S31). Then, the second processing unit 5 receives this via the I2C interface unit 51, and stores the DSP activation timing data and the reception timing data in the first buffer 16 and the second buffer 17, respectively (step S41).

Next, the DSP core 7 notifies the second processing unit 5 that the timer unit 10 is ready to start counting by the counter 11 (step S12). Specifically, as shown in FIG. 2 (f), the rising edge of the DSP intermittent sleep start signal 104 output via the GPIO interface unit 71 notifies the second processing unit 5 to that effect, and the second processing Part 5 (CPU 9) masks interrupts other than external interrupts due to the DSP intermittent sleep start signal 104. At this time, as shown in FIG. 2 (i), the DSP reception timing signal 105 is set to disabled (Low level) in the GPIO interface unit 52 of the second processing unit 5.

Then, after the predetermined time D has elapsed, the DSP core 7 has a timer in the second processing unit 5 (CPU 9) by an external interrupt (step S13) to the second processing unit 5 by the falling edge of the DSP intermittent sleep start signal 104. The counting of the counter 11 of the unit 10 is started (step S42). The rising edge timing t1 and the falling edge timing t2 of the DSP intermittent sleep start signal 104 are determined at the time of setting the timing in step S11. Further, the period D from the rising edge (timing t1) to the falling edge (timing t2) is the time required for the second processing unit 5 to mask interrupts other than the external interrupt by the DSP intermittent sleep start signal 104 (for example). The condition is that it is 1 [msec]) or more. Further, in the period D, interrupts other than the external interrupt by the DSP intermittent sleep start signal 104, for example, the key interrupt by the user cannot be accepted, so that the user allows the period D even if there is no reaction from the device side to the user operation. It is desirable to limit it to less than possible time (generally 100 [msec]).

Further, the fact that the external interrupt has been notified to the second processing unit 5 is notified to the CPU core 6, which causes the CPU core 6 to enter the sleep state (step S22). At this time, in the GPIO interface unit 62 of the CPU core 6, as shown in FIG. 2 (g), the deep sleep request signal 103 is set to enable (High level) (step S32), and the second processing unit 5 is contacted. Is required to move to the deep sleep state. Then, in response to this request, in the second processing unit 5, as shown in FIG. 2H, the deep sleep signal 106 is set to enable (Low level) by the CPU 9 (step S43), and the CPU core 6 and the DSP are set. The core 7 enters the deep sleep state under the control of the power management unit 8 of the processing unit 4 (step S14).

Next, after the CPU core 6 and the DSP core 7 enter the deep sleep state (step S14), when the count value of the counter 11 reaches the DSP start timing in the timer unit 10 of the second processing unit 5, the timer unit The timer interrupt is notified from 10 to the CPU 9 (step S54). By this timer interrupt, the CPU 9 sets the deep sleep signal 106 to disable (High level) as shown in FIG. 3 (h) (step S44). Then, the power management unit 8 of the processing unit 4 shifts the CPU core 6 and the DSP core 7 from the deep sleep state to the sleep state in response to this setting, and the CPU core 6 in the sleep state is shown in FIG. 3 (g). As shown, the GPIO interface unit 62 sets the deep sleep request signal 103 to disable (Low level) and notifies the CPU 9 that the deep sleep request has been canceled (step S33). Further, the CPU 9 receives the notification of the cancellation of the deep sleep request and notifies the DSP activation instruction signal 102 (step S45).

The CPU core 6 in the sleep state continues to monitor signals in the I2C interface unit 61 and the GPIO interface unit 62 (step S34), and when the CPU 9 notifies the DSP start instruction signal 102, the CPU core 6 and the DSP core 7 To the normal state from the sleep state (step S24). At this time, the DSP core 7 is in a state of waiting for a reception interrupt (step S15).

Then, in the timer unit 10 of the second processing unit 5, when the count value of the counter 11 reaches the reception timing, the timer unit 10 notifies the CPU 9 of the timer interrupt (step S56). By this timer interrupt, the CPU 9 sets the DSP reception timing signal 105 to enable (High level) as shown in FIG. 3 (i) (step S46). In the DSP core 7 of the processing unit 4, the reception process is started in response to this.

Next, specific processing in the timer unit 10 of the second processing unit 5 will be described with reference to FIGS. 4 to 6. 4 and 5 are time charts of various signals in the intermittent control of the mobile terminal 1 and the holding contents of various registers and buffers. FIG. 4A is a DSP intermittent sleep start signal 104, and FIG. 5B is a deep sleep request signal 103. (C) is the deep sleep signal 106, (d) is the DSP reception timing signal 105, (e) is the count value of the counter 11, (f) is the clock CL, and (g) is the setting in the third comparison set value register 14. The comparison setting value for defining the timing, (h) is the DSP start timing comparison setting value in the first comparison setting value register 12, and (i) is the reception timing comparison setting value in the second comparison setting value register 13, ( j) indicates the holding content (DSP start timing) of the first buffer 16, and (k) indicates the holding content (reception timing) of the second buffer 17. Further, FIG. 6 is an explanatory diagram for explaining the setting timing and the settable range of the comparison set value at the setting timing, (a) is the count value of the counter 11, (b) is the elapsed time, and (c) is the DSP activation. The range of values that can be set as the timing comparison set value and the reception timing comparison set value is shown.

As shown in FIGS. 4 and 5 (e) and 5 (f), the 16-bit counter 11 of the timer unit 10 counts the clock CL having a frequency of 128 [kHz] after the start operation by the CPU 9. In FIG. 4, the timing t1 of the rising edge of the DSP intermittent sleep start signal 104 is located in the counter cycle TSM, and the timing t2 of the falling edge of the DSP intermittent sleep start signal 104 is located in the counter cycle TS0. During the period D from (timing t1) to the falling edge (timing t2), interrupts other than external interrupts due to the DSP intermittent sleep start signal 104 are masked in the second processing unit 5. Further, the counting operation of the counter 11 is enabled by the external interrupt (falling edge of the timing t2) by the DSP intermittent sleep start signal 104, and the contents of the counter 11 are cleared.

Further, when the processing unit 4 shifts to the deep sleep state, the DSP activation / reception timing notification signal 101 notifies the second processing unit 5 of the DSP activation timing and the reception timing, but this is due to serial transmission. Therefore, as shown in FIGS. 4 (j) and 4 (k), the first buffer 16 of the CPU 9 has a counter cycle slower than the counter cycle TS0 of the start operation of the counter 11 (when the value of the counter 11 is 2), respectively. And it is stored in the second buffer 17. Here, assuming that the DSP start timing is set to about 586 [msec] and the reception timing is set to about 977 [msec], the first buffer 16 is set to 75,000 (= 585.9375 [msec]]. / 7.8125 [μsec]) and 125000 (= 976.5625 [msec] /7.8125 [μsec]) are stored in the second buffer 17.

As described above, since the values of the DSP start timing and the reception timing exceed the numerical values expressed by 16 bits, in the second processing unit 5, the timer unit 10 has the first comparison setting value register 12 and the second comparison setting. A configuration in which a value register 13 and a third comparison set value register 14 are provided, and a DSP start timing and a reception timing are reset in the first comparison set value register 12 and the second comparison set value register 13 in a predetermined cycle (setting timing), respectively. It has become.

In the third comparison setting value register 14, comparison setting values for defining the setting timings of the first comparison setting value register 12 and the second comparison setting value register 13 (a predetermined cycle based on the count value of the counter 11) are set. The register. Here, in order to facilitate the setting of the predetermined cycle (setting timing), the predetermined cycle defined by the count value of the counter 11 is 1/2 ^M of the maximum period that can be counted by the counter 11 (M is 0). The above positive integer) may be used, but here, M = 1 and half of the counter 11 counting cycle. That is, as shown in FIG. 6A, the setting timings (counter cycle TS1, ..., Counter cycle TS5) are generated every half cycle of the counting operation by the counter 11.

Further, the setting timing is generated by the timer interrupt when the value of the third comparison setting value register 14 is matched, and the comparison for generating the next setting timing in the counter cycle of the setting timing by the processing of this timer interrupt. It has been updated to the set value.

Further, in the timer interrupt when the value of the third comparison set value register 14 is matched, the following processing is also performed. That is, it is determined whether or not the difference value obtained by subtracting the elapsed time from the start of counting of the counter 11 from the value of the DSP start timing in the first buffer 16 can be expressed in 16 bits, and if it can be expressed in 16 bits. At the set timing, the remaining count number is set in the first comparison set value register 12, and the difference value obtained by subtracting the elapsed time from the start of counting of the counter 11 from the value of the reception timing in the second buffer 17 is 16 bits. It is a process of determining whether or not it can be expressed, and if it can be expressed by 16 bits, the remaining count number is set in the second comparison set value register 13 at the setting timing.

For example, at the setting timing of the counter cycle TS1, the count value of the counter 11 is "32768", and the difference value "42232" obtained by subtracting the counter count value "32768" from the DSP start timing value "75000" can be expressed in 16 bits. Therefore, “75,000-65536 = 9464” is set in the first comparison set value register 12 as the remaining count number at the setting timing (see FIG. 4 (h)). Here, since the setting timing of the counter cycle TS1 is the intermediate timing of the counter 11 counting cycle and the difference value "42232" exceeds the counting value "32768" for half the cycle of the counter 11 counting cycle, the DSP is started. The timing timer interrupt occurs not within the predetermined cycle starting at the current set timing (TS1), but within the predetermined cycle starting at the next set timing (TS2) (after the counter 11 overflows and is reset). Since it is assumed that there is, the difference value "42232" is not used as the remaining count to be set, but the difference value obtained by subtracting the count value "65536" for the counter 11 counting cycle from the DSP start timing value "75000". It was decided to use "9464".

More specifically, it is determined in advance whether or not to set the remaining count number in the first comparison setting value register 12 or the second comparison setting value register 13 at the setting timing of an arbitrary counter cycle according to a predetermined cycle. It is performed depending on whether or not the remaining count number falls within the timing setting range (see FIG. 6C). Here, the timing setting range is a total that the counter 11 can take in a predetermined cycle starting at the next setting timing of the setting timing (that is, 256 [m seconds] to 512 [m seconds] ahead of the setting timing. It is a range of numerical values. That is, the remaining count in the first comparison setting value register 12 or the second comparison setting value register 13 in (setting timing) one predetermined cycle before the predetermined cycle starting at an arbitrary setting timing. The number setting is determined. Regarding the timing setting range at the initial setting timing (counter cycle TS1), the counter 11 sets the counter 11 in the period from 10 [msec] to 512 [msec] as the initial setting. It was decided to use the range of possible count values, that is, "34048 to 65535 and 0 to 32768".
Therefore, at the setting timing of the counter cycle TS1, the difference value "9464" falls within the timing setting range "34048 to 65535 and 0 to 32768", so that "9464" is set in the first comparison set value register 12 as the remaining count number. Will be.

Further, at the setting timing of the counter cycle TS1, the difference value "92232" obtained by subtracting the counter count value "32768" from the reception timing value "125000" cannot be expressed in 16 bits, so that the second comparison setting value register 13 is entered. No settings are made. Specifically, since the difference value "92232" does not fall within the timing setting range "34048 to 65535 and 0 to 32768" in the counter cycle TS1, the remaining count number is not set in the second comparison set value register 13.

Further, at the setting timing of the counter cycle TS2, the count value of the counter 11 is "65536", and the difference value "59464" obtained by subtracting the counter count value "65536" from the reception timing value "125000" can be expressed by 16 bits. Therefore, the difference value "59464" is set in the second comparison set value register 13 as the remaining count number at the setting timing (see FIG. 4 (i)). Specifically, since the difference value "59464" falls within the timing setting range "32769 to 65535" in the counter cycle TS2, the remaining count number "59464" is set in the second comparison set value register 13.

In the timer unit 10 of the second processing unit 5, when the count value of the counter 11 reaches the comparison set value (DSP start timing) set in the first comparison set value register 12 (counter cycle TS11), the timer unit The timer interrupt is notified from 10 to the CPU 9, and the deep sleep signal 106 is set to disabled (High level) by the CPU 9 as shown in FIG. 5 (c). Then, the CPU core 6 and the DSP core 7 of the processing unit 4 are activated through the series of processes described above.

Further, in the timer unit 10 of the second processing unit 5, when the count value of the counter 11 reaches the comparison set value (reception timing) set in the second comparison set value register 13, the timer unit 10 to the CPU 9. The timer interrupt is notified, and as shown in FIG. 5D, the DSP reception timing signal 105 is set to enable (High level) by the CPU 9, and the reception process by the DSP core 7 is started.

As described above, in the mobile terminal 1 of this embodiment, at the rising edge of the DSP intermittent sleep start signal 104, the second processing unit is made to mask the interrupts other than the external interrupt by the DSP intermittent sleep start signal 104, and the DSP Since counting of the counter 11 of the timer unit 10 is started at the time of an external interrupt due to the falling edge of the intermittent sleep start signal 104, it is possible to accept and execute the interrupt (clear the contents of the counter 11 and enable the counting operation). The required time can be shortened, and the start timing of the external interrupt by the DSP intermittent sleep start signal 104 and the count start timing of the counter 11 of the timer unit 10 can be contained in the same clock cycle, and the timer can be set. The counting operation of the counter 11 of the unit 10 can be synchronized with the processing unit 4 (DSP core 7). Further, since two different types of instructions are given to the second processing unit 5 using one interface signal, hardware that satisfies the timing condition in intermittent control even when the number of interface signal lines is restricted. The design can be realized.

Further, the first comparison setting value register 12 and the second comparison setting value register 13 are provided for setting the comparison value of the start timing and the reception timing, and the counter 11 has a predetermined cycle defined by the count value of the counter 11. When the difference value obtained by subtracting the elapsed time from the start of counting is set to 16 bits, the remaining count number is set as a comparison value, so that the data bit length handled by the second processing unit 5 is short, and the data bit The present invention can be applied even when the length cannot express the time of the radio frame length. As a result, it is possible to realize a mobile terminal capable of incorporating a time scheduler function in intermittent reception control into existing hardware by adding less hardware resources.

Although the embodiment of the present invention has been described above, the specific configuration is not limited to the above-described embodiment, and even if there is a design change or the like within a range that does not deviate from the gist of the present invention. Included in the invention.

1 Mobile terminal 3 Wireless unit 4 Processing unit 5 2nd processing unit 6 CPU core 7 DSP core 8 Power management unit 9 CPU
10 Timer section 11 Counter 12 1st comparison set value register 13 2nd comparison set value register 14 3rd comparison set value register 15 Comparison section 16 1st buffer 17 2nd buffer 51, 61 I2C interface section 52, 62, 71 GPIO interface Part 101 DSP start / reception timing notification signal 102 DSP start instruction signal 103 Deep sleep request signal 104 DSP intermittent sleep start signal 105 DSP reception timing signal 106 Deep sleep signal CL clock

Claims (4)

A radio unit that processes radio frequency signals and
A processing unit that has at least a CPU core and a DSP core and processes baseband signals,
A mobile terminal having a timer unit including a counter that counts the clock with a sample timing from the wireless unit as a clock input , a CPU, and a second processing unit that performs intermittent control of the processing unit.
At the time of transition to the sleep state, the processing unit notifies the second processing unit of the start timing from the CPU core, and supplies a positive logic or negative logic DSP intermittent sleep start signal to the second processing unit from the DSP core. After that, it goes to sleep and
The second processing unit
At the rising or falling edge of the DSP intermittent sleep start signal, interrupts other than external interrupts due to the DSP intermittent sleep start signal are masked.
Wherein when an external interrupt by falling or rising edge of the DSP intermittent sleep start signal to start the counting of said counter of said timer section,
A mobile terminal characterized in that when the count value of the counter reaches the activation timing, the processing unit is released from the sleep state and activated. The mobile terminal according to claim 1, wherein the rising or falling edge of the DSP intermittent sleep start signal is located in the first half of one cycle of the clock. The processing unit includes a power management unit that manages the transition of the CPU core and the DSP core to the normal state, sleep state, and deep sleep state.
At the time of transition to the deep sleep state, the processing unit notifies the second processing unit of the start timing and the reception timing from the CPU core, and supplies the DSP intermittent sleep start signal from the DSP core to the second processing unit. Later, it goes to sleep, then goes to deep sleep,
When the count value of the counter reaches the start timing, the second processing unit notifies the power management unit to that effect, releases the deep sleep state of the CPU core and the DSP core, and causes the DSP core. Is started to shift to the state of waiting for a receive interrupt,
The movement according to any one of claims 1 or 2, wherein when the count value of the counter reaches the reception timing, the DSP core is notified to that effect and the reception process is started. Terminal. The timer unit
The first comparison setting value register in which the comparison setting value of the start timing is set at a predetermined timing, and
A second comparison setting value register in which the comparison setting value of the reception timing is set at a predetermined timing, and
Compared said output and said first comparator setting value register of the counter every period of the clock value and the value of the second comparator setting value register, respectively, wherein the timer interrupt when that match any of the values It has a comparison unit that notifies the CPU of the second processing unit , and
When the counter is an N-bit (N is a positive integer) counter and the value obtained by dividing the time of the radio frame length by the period of the clock exceeds the maximum value that can be expressed by N bits.
The second processing unit can express, in N bits, a difference value obtained by subtracting the elapsed time from the start of counting of the counter from the starting timing or the receiving timing at each predetermined cycle defined by the counting value of the counter. It is characterized in that it is determined whether or not, and if it can be expressed by N bits, the remaining count number is set in the corresponding first comparison set value register or the second comparison set value register at the timing of the predetermined cycle. The mobile terminal according to claim 3.

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