JP6771410B2 - Manufacturing method of support and semiconductor device - Google Patents

Description

Embodiments of the present invention relate to a method of manufacturing a support and a semiconductor device.

In the process of manufacturing a semiconductor device, the substrate may be processed so as to be thin.
For example, system LSI (Large Scale Integrated circuit), DRAM (Dynamic Random Access Memory), NAND / NOR type flash memory, MRAM (Magneto ferroelectric Random Access Memory), and FeRAM (Ferroelectric). In Random Access Memory (ferroelectric RAM), the back surface side of the substrate (the surface side opposite to the surface on which the semiconductor element is provided) may be processed for the purpose of forming a multi-layer chip or thin packaging. ..

Further, in a discrete semiconductor device, the back surface side of the substrate may be processed for the purpose of reducing conduction loss. For example, power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) reduce on-resistance (RonA), and IGBTs (Insulated Gate Bipolar Transistors) use on-voltage (VCE (VCE). The back surface side of the substrate is processed for the purpose of reducing sat)).
When processing the back surface of a substrate, the substrate is placed on the stage so that the front surface of the substrate (the surface provided with the semiconductor element) and the stage of the processing apparatus (for example, a grinding apparatus) face each other. ..

Here, a convex portion may be provided on the surface of the substrate. For example, in order to insulate the wiring provided on the surface of the substrate, a linear insulating film may be provided on the surface of the substrate. When the substrate provided with the convex portion is placed on the stage, the substrate is supported by the convex portion. Therefore, due to the load during processing, stress concentration may occur in the region where the convex portion of the substrate is provided, and cracks may occur in the substrate.

In this case, the stress concentration can be relaxed by providing a dummy convex portion on the surface of the substrate. However, for example, electrodes and heat dissipation regions are provided on the surface of the substrate. Therefore, if a dummy convex portion is added to the surface of the substrate, wiring and soldering may become difficult, and heat dissipation may decrease.
Therefore, it has been desired to develop a technique capable of alleviating the stress concentration generated when processing the back surface of the substrate without adding an element to the front surface of the substrate.

International Publication No. 2009/081880

An object to be solved by the present invention is to provide a support capable of alleviating stress concentration generated when processing the back surface of a substrate, and a method for manufacturing a semiconductor device.

Support according to the embodiment includes a semiconductor element, a first convex portion, a plurality have a first region provided is a substrate having the protective tape is attached to cover the plurality of first regions It is a supporting support.
The support is provided in each of the base having a plurality of second regions facing the plurality of first regions and the plurality of second regions, and the first region and the second region are provided . A second convex portion that comes into contact with the portion of the first region where the first convex portion is not provided is provided via the protective tape when the regions are confronted with each other.

It is a schematic perspective view for exemplifying the support 1 which concerns on this embodiment. (A) is a schematic plan view of the region 10. (B) is a schematic cross-sectional view of the region 10. (A) to (d) are schematic views for exemplifying the protrusions and holes of the support 1 according to another embodiment. It is a schematic cross-sectional view for exemplifying the back surface processing of the substrate 100 which concerns on a comparative example. It is a schematic plan view for exemplifying the convex portion 103a. It is a schematic cross-sectional view for exemplifying the back surface processing of the substrate 100 which concerns on this embodiment.

Hereinafter, embodiments will be illustrated with reference to the drawings. In each drawing, similar components are designated by the same reference numerals and detailed description thereof will be omitted as appropriate.

(Support 1)
FIG. 1 is a schematic perspective view for exemplifying the support 1 according to the present embodiment.
FIG. 2A is a schematic plan view of region 10 (corresponding to an example of the second region).
FIG. 2B is a schematic cross-sectional view of the region 10.
As shown in FIGS. 1, 2 (a) and 2 (b), the support 1 is provided with a base 11 and a convex portion 12 (corresponding to an example of the second convex portion).

The base 11 may be plate-shaped. One main surface 11a of the base 11 is partitioned into a plurality of regions 10. The plurality of regions 10 are arranged in a matrix. The arrangement of the plurality of regions 10 corresponds to the arrangement of the plurality of regions 102 (corresponding to an example of the first region) in which the semiconductor elements of the substrate 100 (for example, the semiconductor wafer) to be mounted are provided. Therefore, when the substrate 100 is placed on the support 1, one region 10 of the support 1 faces one region 102 of the substrate 100.
That is, the support 1 supports the substrate 100 having a plurality of regions 102 in which the semiconductor element and the convex portion 103 (corresponding to an example of the first convex portion) are provided. The support 1 includes a base portion 11 having a plurality of regions 10 each facing the plurality of regions 102, and a convex portion 12 provided in each of the plurality of regions 10.
The number and arrangement of the plurality of regions 10 are not limited to those illustrated, and may be appropriately changed according to the number and arrangement of the plurality of regions 102 provided on the substrate 100 to be mounted. Can be done.

The planar shape and planar dimensions of the base portion 11 are not particularly limited, but considering that the support 1 (base portion 11) is held by the stage 105 of the processing apparatus, the planar shape and planar dimensions of the base portion 11 are those of the substrate 100. It is preferable that the shape is the same as the plane shape and the plane dimensions.
The material and thickness of the base 11 are not particularly limited, but the base 11 is preferably lightweight and has a certain degree of rigidity.

The material of the base 11 can be, for example, a metal such as aluminum, silicon, resin, glass or the like.
The thickness of the base portion 11 can be, for example, 0.5 mm or more and 1 mm or less.

A plurality of convex portions 12 are provided on one main surface 11a of the base portion 11. At least one convex portion 12 is provided in one region 10. In the case of the support 1 illustrated in FIGS. 1, 2 (a) and 2 (b), four convex portions 12 are provided in one region 10.

As will be described later, when the substrate 100 is placed on the side of the support 1 on which the plurality of convex portions 12 are provided, the substrate 100 is provided on the plurality of convex portions 12 and the surface side of the substrate 100. It is supported by the plurality of convex portions 103. In this case, if the difference between the height of the convex portion 12 and the height of the convex portion 103 becomes too large, the effect of relaxing the stress concentration is reduced. According to the knowledge obtained by the present inventor, it is preferable that the difference between the height of the convex portion 12 and the height of the convex portion 103 is ± 1 μm or less. In this case, the height of the convex portion 12 can be, for example, 1 μm or more and 20 μm or less.

The top surface 12a of the convex portion 12 is preferably a flat surface. If the top surface 12a of the convex portion 12 is a flat surface, the contact area with the substrate 100 can be increased, so that it is possible to suppress the generation of a large local stress on the substrate 100.

Further, if the total area of the top surface 12a of the convex portion 12 in one region 10 is increased, it becomes easy to suppress the generation of a large local stress on the substrate 100.
Therefore, the total area of the top surface 12a of the convex portion 12 in one region 10 is preferably 0.12 mm ² or more. For example, when four convex portions 12 are provided in one region 10, the area of the top surface 12a of one convex portion 12 is preferably 0.03 mm ² or more. In this case, when the convex portion 12 is a cylinder, the diameter dimension of one convex portion 12 may be 0.2 mm or more. As shown in FIG. 3D, which will be described later, when one convex portion 12 is provided in one region 10, the area of the top surface 12a of the convex portion 12 is 0.12 mm ² or more. do it.

The material of the plurality of convex portions 12 is not particularly limited, and can be appropriately selected in consideration of workability. The material of the plurality of convex portions 12 can be, for example, a metal such as aluminum or a resin such as polyimide.
The plurality of convex portions 12 can be formed integrally with the base portion 11, or the plurality of convex portions 12 can be provided on the main surface 11a of the base portion 11. For example, the plurality of convex portions 12 and the base portion 11 can be integrally formed by cutting. Further, the main surface 11a of the base portion 11 using silicon, aluminum, resin, glass or the like can be coated with resin and patterned to form a plurality of convex portions 12.

Further, a plurality of holes 13 can be provided in the base portion 11. The plurality of holes 13 penetrate the base 11 in the thickness direction. As shown in FIG. 6, which will be described later, the support 1 is placed on the stage 105 of the processing apparatus. The substrate 100 is placed on the support 1. The stage 105 is provided with a suction portion 105a such as a groove or a hole, and the suction portion 105a is connected to the suction device. The support 1 is sucked by the suction device connected to the suction unit 105a, and the support 1 is held by the stage 105. At this time, the substrate 100 is sucked through the plurality of holes 13 provided in the base 11, and the substrate 100 is held by the stage 105 via the support 1. That is, the plurality of holes 13 are provided for sucking the substrate 100.

As illustrated in FIG. 1, holes 13 can be provided in all regions 10, but it is not always necessary to provide holes 13 in all regions 10 as long as the substrate 100 can be held. Further, a plurality of holes 13 may be provided in one region 10. That is, the support 1 is provided in at least a part of the plurality of regions 10 and has holes 13 penetrating in the thickness direction.

The plurality of holes 13 are provided at positions that do not overlap with the plurality of convex portions 12. In this case, the plurality of holes 13 may be evenly arranged so as to be evenly spaced, or may be unevenly distributed in the peripheral region and the central region of the base 11. The opening shape of the plurality of holes 13 is not particularly limited, and can be appropriately changed according to the arrangement of the plurality of convex portions 12. As shown in FIG. 2A, if the opening shape of the plurality of holes 13 is circular, the processing of the plurality of holes 13 becomes easy.

The number of the plurality of holes 13 and the opening size can be appropriately changed according to the required suction force. For example, when the substrate 100 is an 8-inch wafer, a plurality of holes 13 having a diameter of about 1 mm can be provided in a matrix at a pitch of 9.8 mm.

3 (a) to 3 (d) are schematic views for exemplifying the protrusions and holes of the support 1 according to other embodiments.
As shown in FIG. 3A, the planar shape of the plurality of convex portions 12b can be polygonal. In FIG. 3A, the planar shape of the plurality of convex portions 12b is a quadrangle. The plurality of convex portions 12b can be arranged in a matrix at equal pitches. One of the plurality of convex portions 12b may be provided at the center of the region 10 or may be provided at a position deviated from the center of the region 10. In FIG. 3A, one of the plurality of convex portions 12b is provided at the center of the region 10. The opening shape of the hole 13a can be polygonal. In FIG. 3A, the opening shape of the hole 13a is a quadrangle.

As shown in FIG. 3B, the planar shape of the convex portion 12 can be a figure composed of a curved line such as a circle or an ellipse. In FIG. 3B, the planar shape of the plurality of convex portions 12 is circular. The plurality of convex portions 12 can be arranged in a matrix at equal pitches. One of the plurality of convex portions 12 may be provided at the center of the region 10, or may be provided at a position deviated from the center of the region 10. In FIG. 3B, one of the plurality of convex portions 12 is provided at the center of the region 10. A plurality of holes 13 can be provided. The opening shape of the plurality of holes 13 can be a figure composed of a curved line such as a circle or an ellipse. In FIG. 3B, the opening shapes of the plurality of holes 13 are circular.

Further, in FIGS. 3A and 3B, a plurality of convex portions 12 and 12a arranged in a matrix are illustrated, but the plurality of convex portions 12 and 12a can be provided on the circumference or concentric circles. .. Further, the plurality of convex portions 12 and 12a can be arranged regularly as described above, or can be provided at random positions.

As shown in FIG. 3C, the planar shape of the convex portion 12c can be a shape in which a plurality of straight portions intersect. In FIG. 3C, the planar shape of the convex portion 12c is a square shape. In this case, the square-shaped straight portions may be arranged at equal pitches or may be provided at random positions. Further, the plurality of straight lines may or may not be parallel to each other.

As shown in FIG. 3D, the number of convex portions 12d can be one. When the number of convex portions 12d is one, the area of the top surface of the convex portions 12d may be increased. For example, as described above, the area of the top surface 12 of the convex portion 12d may be 0.12 mm ² or more. When the plane dimension of the convex portion 12d becomes large, C chamfering or R chamfering can be performed on the corner portion of the convex portion 12d in the plan view. In FIG. 3D, R chamfering is performed on the corner portion of the convex portion 12d in a plan view.

Further, as shown in FIGS. 3A to 3D, when the substrate 100 is placed on the support 1, one region 10 of the support 1 confronts one region 102 of the substrate 100. .. Further, a convex portion 103 is provided on the peripheral edge of the region 102. Then, as shown in FIG. 6, which will be described later, a protective tape 104 is provided between the support 1 and the substrate 100. Therefore, in a plan view, if the shortest distance L1 between the outer edge of the convex portions 12, 12b to 12d and the inner edge of the convex portion 103 becomes too short, the protective tape 104 becomes difficult to bend, and the convex portions 12, 12b to 12d There is a possibility that a gap may be generated between the substrate 100 and the convex portion 103 and the base portion 11.
According to the knowledge obtained by the present inventor, when the thickness of the protective tape 104 is T (mm), if “L1 ≧ 2T” is set, the convex portions 12, 12b to 12d and the substrate 100 It is possible to suppress the formation of a gap between the protrusions and the formation of a gap between the convex portion 103 and the base portion 11.

Next, the action of the support 1 will be illustrated.
FIG. 4 is a schematic cross-sectional view for exemplifying the back surface processing of the substrate 100 according to the comparative example.
Semiconductor elements and wiring (not shown) are provided on the surface 100a of the substrate 100.
As shown in FIG. 4, the surface 100a of the substrate 100 is divided into a plurality of regions 102, and semiconductor elements and wiring are provided in each of the plurality of regions 102. As will be described later, the substrate 100 is cut along the peripheral edge of the region 102, and a plurality of semiconductor devices 101 are manufactured.

Here, in order to facilitate the connection between the semiconductor device 101 and the external circuit, wiring is provided near the peripheral edge of the semiconductor device 101. Then, a convex portion 103 may be further provided to insulate the wiring provided near the peripheral edge of the semiconductor device 101. The convex portion 103 is a linear insulating film using a resin such as polyimide. The height of the convex portion 103 is, for example, about 15 μm.

When processing the back surface 100b of the substrate 100, the substrate 100 is placed on the stage 105 so that the side to which the protective tape 104 of the substrate 100 is attached and the stage 105 of the processing apparatus (for example, a grinding apparatus) face each other. Placed on top. Further, the substrate 100 is sucked through the protective tape 104 by the suction device connected to the suction unit 105a, and the substrate 100 is held on the stage 105.
At this time, the substrate 100 is supported by the convex portion 103.

When the back surface 100b of the substrate 100 is processed in such a state, stress concentration may occur in the region where the convex portion 103 of the substrate 100 is provided due to the load P during processing, and crack 106 may occur in the substrate 100. .. The crack 106 is more likely to occur as the height of the convex portion 103 increases.

In this case, if a dummy convex portion 103a is provided on the surface 100a of the substrate 100, the stress concentration can be relaxed.
FIG. 5 is a schematic plan view for exemplifying the convex portion 103a.
As shown in FIG. 5, in a plan view, if a dummy convex portion 103a is provided inside the convex portion 103 provided so as to surround the peripheral edge of the region 102, the stress concentration can be relaxed.
However, the region 102 is provided with semiconductor elements and wiring, as well as electrodes and a heat radiating region. Therefore, if a dummy convex portion 103a is added to the surface 100a of the substrate 100, wiring and soldering may become difficult, and heat dissipation may decrease. In this case, if the convex portion 103a is provided on the stage 105, it is not possible to quickly respond when the shape or size of the region 102 changes, for example, when the type of the semiconductor device 101 changes.
Therefore, in the back surface processing of the substrate 100 according to the present embodiment, the support 1 is provided between the substrate 100 and the stage 105.

FIG. 6 is a schematic cross-sectional view for exemplifying the back surface processing of the substrate 100 according to the present embodiment.
As shown in FIG. 6, the surface 100a and the convex portion 103 of the substrate 100 are covered with the protective tape 104. That is, the protective tape 104 covers the plurality of areas 102. The protective tape 104 can be a so-called dicing tape. The substrate 100 side of the protective tape 104 has adhesiveness, and the side of the protective tape 104 opposite to the substrate 100 side has no adhesiveness. The thickness of the protective tape 104 can be, for example, about 0.08 mm.

The support 1 is placed on the stage 105. The surface of the base 11 opposite to the side on which the plurality of convex portions 12 are provided (the side on which the plurality of regions 10 are provided) faces the stage 105. Further, the substrate 100 is placed on the support 1 so that the side on which the protective tape 104 of the substrate 100 is attached and the side of the base 11 on which the plurality of convex portions 12 are provided face each other. There is. That is, the plurality of regions 102 of the substrate 100 are confronted with the plurality of regions 10 of the support 1. As described above, the support 1 is sucked by the suction device connected to the suction unit 105a, and the support 1 is held by the stage 105. At this time, the substrate 100 to which the protective tape 104 is attached is held on the stage 105 through the plurality of holes 13 provided in the base portion 11.

Since the base portion 11 is provided with the convex portion 12, the substrate 100 is supported by the convex portion 12 and the convex portion 103 as shown in FIG. Further, as described above, the difference between the height of the convex portion 12 and the height of the convex portion 103 is reduced.

When the back surface 100b of the substrate 100 is processed in such a state, stress concentration occurs in the region where the convex portion 103 of the substrate 100 is provided and the region where the convex portion 12 of the substrate 100 contacts due to the load P during processing. .. However, since the difference between the height of the convex portion 12 and the height of the convex portion 103 is small, the stress concentration generated can be relaxed. Therefore, it is possible to suppress the occurrence of cracks 106 on the substrate 100.
In this case, if the difference between the height of the convex portion 12 and the height of the convex portion 103 is set to ± 1 μm or less, or the total area of the top surface 12a of the convex portion 12 in one region 10 is set to 0.12 mm ² or more. It becomes easy to relax the stress concentration.

Further, when the thickness of the protective tape 104 is T (mm), if “L1 ≧ 2T” is set, a gap is generated between the convex portion 12 and the substrate 100, or the convex portion 103 and the base portion 11 are formed. It is possible to suppress the formation of a gap between the two.

Further, if a plurality of types of supports 1 are provided corresponding to a plurality of types of the semiconductor device 101, it is possible to quickly respond when the type of the semiconductor device 101 changes. In this case, the configuration of the support 1 is simple, and the number of supports 1 can be reduced, so that the manufacturing cost does not increase significantly.

(Manufacturing method of semiconductor device)
First, the surface 100a of the substrate 100 is divided into a plurality of regions 102, and elements such as semiconductor elements, wirings, electrodes, and heat dissipation regions are sequentially formed in each of the plurality of regions 102. Further, a convex portion 103 is formed in each of the plurality of regions 102.
Subsequently, the protective tape 104 is attached so as to cover the plurality of areas 102.
Since known semiconductor manufacturing processes can be applied to these formations, detailed description thereof will be omitted.

Next, the back surface 100b of the substrate 100 (the surface opposite to the side on which the region 102 is provided) is processed.
First, the support 1 is placed on the stage 105 of the processing apparatus. The surface of the base portion 11 opposite to the side on which the convex portion 12 is provided faces the stage 105.
Subsequently, the substrate 100 is placed on the support 1 so that the side on which the protective tape 104 of the substrate 100 is attached and the side of the base 11 on which the convex portion 12 is provided face each other.
Subsequently, the support 1 is sucked by the suction device connected to the suction unit 105a, and the support 1 is held by the stage 105. At this time, the substrate 100 to which the protective tape 104 is attached is held on the stage 105 through the plurality of holes 13 provided in the base portion 11.
Subsequently, the back surface 100b of the substrate 100 is processed using a tool such as a grinding wheel provided in the processing apparatus. Since known techniques can be applied to machining procedures and machining conditions, detailed description thereof will be omitted.
When the processing is completed, the suction by the suction device is stopped, and the substrate 100 is removed from the processing device.

Next, the substrate 100 is cut along the peripheral edge of the region 102 to separate the plurality of semiconductor devices 101 into pieces. Since the substrate 100 can be cut by using a known dicing device or the like, detailed description thereof will be omitted.
The semiconductor device 101 can be manufactured as described above.

As described above, the method for manufacturing a semiconductor device according to the present embodiment can include the following steps.
A step of placing the support 1 on the stage 105 of the processing apparatus.
A step of mounting a substrate 100 having a plurality of regions 102 provided with a semiconductor element and a convex portion 103 on the support 1.
A step of processing the surface of the substrate 100 on the side opposite to the side on which the region 102 is provided.
Then, in the step of mounting the support 1 on the stage 105 of the processing apparatus, the surface of the support 1 opposite to the side on which the plurality of regions 10 are provided is made to face the stage 105, and the substrate 100 is mounted. In the process, the plurality of regions 102 of the substrate 100 are made to face the region 10 of the support 1.
In this case, the substrate 100 may further have a protective tape 104 that covers the plurality of regions 102.

Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, changes, etc. can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof. In addition, the above-described embodiments can be implemented in combination with each other.

1 Support, 10 regions, 11 bases, 11a main surface, 12 convex parts, 12a top surface, 12b to 12d convex parts, 13 holes, 100 substrates, 100a front surface, 100b back surface, 101 semiconductor devices, 102 regions, 103 convex parts , 103a Convex, 104 Protective Tape, 105 Stage, 106 Crack

Claims (6)

A semiconductor element, a first convex portion, a first region provided with a plurality of perforated, a support for supporting a substrate protective tape is attached to cover the plurality of first regions,
A base, each having a plurality of second regions facing the plurality of first regions,
A portion provided in each of the plurality of second regions, in which the first convex portion of the first region is not provided when the first region and the second region are confronted with each other. With the second convex portion that comes into contact with the protective tape ,
Support that features. The support according to claim 1, wherein the support is provided in at least a part of the plurality of second regions and further includes a hole penetrating in the thickness direction. The base comprises at least one of silicon, metal, resin, and glass.
The support according to claim 1 or 2, wherein the second convex portion contains a resin. The support according to claim 1 or 2, wherein the base portion and the second convex portion contain a metal and are integrally provided. The step of placing the support according to any one of claims 1 to 4 on the stage of the processing apparatus, and
On the support, placing the semiconductor element, a first convex portion, a plurality have a first region provided is a substrate having the protective tape is attached to cover the plurality of first regions The process of placing and
A step of processing a surface of the substrate opposite to the side on which the first region is provided, and
With
In the step of placing the support on the stage of the processing apparatus, the surface of the support opposite to the side on which the plurality of second regions are provided is made to face the stage.
In the step of placing the substrate, Rutotomoni not a plurality of first regions of the substrate is opposed to the plurality of second regions of the support, the second convex portion provided in the second region wherein said first portion projecting portions are not provided in the first region, the semiconductor device manufacturing method Ru contacting via the protective tape. The method for manufacturing a semiconductor device according to claim 5, wherein the substrate further has a protective tape covering the plurality of first regions.

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