JP6771065B2 - Light emitting element and light emitting element package - Google Patents

Description

The present invention relates to light emitting devices and light emitting device packages.

As the light emitting element, those described in FIGS. 3 and 4 of Patent Document 1 are known. The light emitting device described in Patent Document 1 includes a sapphire substrate, a GaN buffer layer laminated on the surface of the sapphire substrate in order, a non-doped GaNn layer, a Si-doped GaN layer (n-type contact layer), and a Si-doped GaN layer (n-type clad layer). ), InGaN layer (active layer), Mg-doped AlGaN layer (p-type clad layer), and Mg-doped GaN layer (p-type contact layer). The p-type contact layer, p-type clad layer, active layer, n-type clad layer and n-type contact layer are partially removed, and an n-side electrode is formed on the exposed surface of the n-type contact layer. Further, a p-side electrode is formed on the p-type contact layer.

The p-side electrode is composed of a p-side current diffusing portion (p-side transparent electrode layer) having translucency and a p-side pad portion having no translucency formed in a predetermined part of the p-side current diffusing portion. It is configured. A plurality of openings (through holes) are formed in the p-side current diffusion portion. These openings are formed to enable light to be taken out while reducing the electrical resistance of the p-side current diffusing portion even when the p-side current diffusing portion is formed into a thick film that does not have translucency. ing.

Japanese Unexamined Patent Publication No. 2004-221259

An object of the present invention is to provide a light emitting element and a light emitting element package capable of improving the light extraction efficiency.

One embodiment of the present invention has a substrate having a front surface and a back surface, and an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer that are sequentially laminated on the surface of the substrate, and the p-type semiconductor layer is the light emitting layer. The semiconductor laminated structure portion having the surface opposite to the above, and the semiconductor laminated structure portion formed so as to enter the semiconductor laminated structure portion into a predetermined current injection region of the surface on the p-type semiconductor layer side of the semiconductor laminated structure portion. A plurality of recesses extending from the p-type semiconductor layer into the semiconductor laminated structure portion, a first insulating film formed in a part of the current injection region on the surface on the p-type semiconductor layer side, and the p-type semiconductor layer. It is formed on the surface of the p-semiconductor layer and covers the entire area of the predetermined current injection region on the surface on the p-type semiconductor layer side or almost the entire area of the predetermined current injection region on the surface on the p-type semiconductor layer side. The p-side transparent electrode layer covering the first insulating film and the p-side electrode formed at a position facing the surface of the first insulating layer on the surface of the p-side transparent electrode layer opposite to the p-type semiconductor layer. To provide a light emitting element including.

In one embodiment of the present invention, the first insulating film is made of SiO ₂ .
In one embodiment of the present invention, the first insulating film has a circular shape in a plan view, and the p-side electrode has a circular shape having a diameter smaller than that of the first insulating film in a plan view.
In one embodiment of the present invention, the first insulating film has a truncated cone shape in which the cross-sectional area decreases from the surface on the p-type semiconductor layer side toward the p-side transparent electrode layer.

In one embodiment of the present invention, the plurality of recesses are dug down from the surface of the p-side transparent electrode layer opposite to the conductor laminated structure portion and extend into the semiconductor laminated structure portion.
In one embodiment of the present invention, the plurality of recesses are dug down from the surface of the p-side transparent electrode layer opposite to the conductor laminated structure portion, and the transparent electrode layer, the p-type semiconductor layer and the light emitting light are formed. It penetrates the layer and enters the middle of the n-type semiconductor layer in the thickness direction.

In one embodiment of the present invention, a second insulating film is formed on the inner surface of the recess, and a region of the surface of the p-side transparent electrode layer on which the p-side electrode is not formed and the recess. The area where is not formed is exposed.
In one embodiment of the present invention, the inner surface of the recess is formed as an inclined surface in which the cross-sectional area of the recess gradually decreases toward the bottom surface of the recess.
In one embodiment of the present invention, the inner surface of the recess is formed on an inclined surface in which the cross-sectional area of the recess gradually increases toward the bottom surface of the recess.

In one embodiment of the present invention, a lead-out portion electrically connected to the n-type semiconductor layer and drawn out from the semiconductor laminated structure portion in a direction parallel to the substrate, and an n-side electrode formed on the lead-out portion. And further include.
In one embodiment of the present invention, the n-side electrode comprises an n-side transparent electrode layer formed on the surface of the n-type semiconductor and an n-side pad formed on the n-side transparent electrode layer.

In one embodiment of the present invention, the n-side transparent electrode layer is made of ITO or ZnO, and the n-side pad is made of Cr or Au.
In one embodiment of the present invention, a plurality of convex portions covered with the n-type semiconductor layer are formed on the surface of the substrate.
In one embodiment of the present invention, the convex portion is made of SiN.

One embodiment of the present invention has the light emitting element, a front surface and a back surface, and is fixed to the support substrate and the support substrate that support the light emitting element so that the light emitting element is arranged on the front surface. The light emitting element includes a resin package arranged so as to surround the light emitting element, so that the surface of the substrate opposite to the n-type semiconductor layer faces the surface of the support substrate. The present invention provides a light emitting element package supported by the support substrate.

One embodiment of the present invention has the light emitting element, a front surface and a back surface, and is fixed to the support substrate and the support substrate that support the light emitting element so that the light emitting element is arranged on the front surface. The light emitting element includes a resin package arranged so as to surround the light emitting element, and the surface of the p side transparent electrode layer opposite to the p-type semiconductor layer is the surface of the support substrate. Provided is a light emitting element package supported by the support substrate in a facing posture.

In one embodiment of the present invention, the resin package includes an annular wall that surrounds the light emitting element, and the inner surface of the annular wall is a space surrounded by the annular wall as the distance from the surface of the support substrate increases. The inclined surface is formed on an inclined surface having a large cross-sectional area, and the inclined surface constitutes a reflecting portion for reflecting the light emitted from the light emitting element and taking it out to the outside.

FIG. 1 is a schematic plan view of a light emitting device according to an embodiment of the first invention. FIG. 2 is a schematic cross-sectional view of the light emitting element of FIG. FIG. 3A is a schematic plan view showing an example of the arrangement pattern of the convex portions. FIG. 3B is a schematic plan view showing another example of the arrangement pattern of the convex portion. FIG. 4A is a schematic plan view showing an example of the arrangement pattern of the concave portions when the convex portions are arranged in the arrangement pattern of FIG. 3A. FIG. 4B is a schematic plan view showing an example of the arrangement pattern of the concave portions when the convex portions are arranged in the arrangement pattern of FIG. 3B. FIG. 5A is a schematic cross-sectional view showing an example of the shape of the recess. FIG. 5B is a schematic cross-sectional view showing another example of the shape of the recess. FIG. 6A is a schematic cross-sectional view showing a method of manufacturing the light emitting element shown in FIGS. 1 and 2. FIG. 6B is a schematic cross-sectional view showing the next step of FIG. 6A. FIG. 6C is a schematic cross-sectional view showing the next step of FIG. 6B. FIG. 6D is a schematic cross-sectional view showing the next step of FIG. 6C. FIG. 6E is a schematic cross-sectional view showing the next step of FIG. 6D. FIG. 6F is a schematic cross-sectional view showing the next step of FIG. 6E. FIG. 6G is a schematic cross-sectional view showing the next step of FIG. 6E. FIG. 7 is a schematic cross-sectional view of the light emitting element package. FIG. 8 is a schematic plan view for explaining the x-direction shift amount Δx and the y-direction shift amount Δy. FIG. 9 is a graph showing the simulation results. FIG. 10 is a schematic cross-sectional view showing another example of the light emitting device package. FIG. 11 is a schematic plan view of the light emitting device according to the embodiment of the second invention. FIG. 12 is a schematic cross-sectional view of the light emitting element of FIG. FIG. 13A is a schematic plan view showing an example of the arrangement pattern of the convex portions. FIG. 13B is a schematic plan view showing another example of the arrangement pattern of the convex portion. FIG. 14A is a schematic plan view showing an example of the arrangement pattern of the second insulating film when the convex portion is arranged in the arrangement pattern of FIG. 13A. FIG. 14B is a schematic plan view showing an example of the arrangement pattern of the second insulating film when the convex portion is arranged in the arrangement pattern of FIG. 13B. FIG. 15A is a schematic cross-sectional view showing a method of manufacturing the light emitting element shown in FIGS. 11 and 12. FIG. 15B is a schematic cross-sectional view showing the next step of FIG. 15A. FIG. 15C is a schematic cross-sectional view showing the next step of FIG. 15B. FIG. 15D is a schematic cross-sectional view showing the next step of FIG. 15C. FIG. 15E is a schematic cross-sectional view showing the next step of FIG. 15D. FIG. 15F is a schematic cross-sectional view showing the next step of FIG. 15E. FIG. 16 is a schematic cross-sectional view of the light emitting element package. FIG. 17 is a schematic cross-sectional view showing another example of the light emitting device package.

Hereinafter, embodiments of the first invention and the second invention will be described in detail with reference to the accompanying drawings.
[1] First Invention An embodiment of the first invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a light emitting device according to an embodiment of the first invention. FIG. 2 is a schematic cross-sectional view of the light emitting element of FIG.

The light emitting element 1 has a chip shape having a rectangular shape in a plan view. The light emitting element 1 includes a substrate 2 having a front surface 2A and a back surface 2B, and an n-type conductive semiconductor layer 3, a light emitting layer 4, and a p-type conductive semiconductor layer 5 which are sequentially laminated on the front surface 2A of the substrate 2. Hereinafter, the n-type conductive semiconductor layer 3 is referred to as an “n-type semiconductor layer 3”, and the p-type conductive semiconductor layer 5 is referred to as a “p-type semiconductor layer 5”. The substrate 2 has a rectangular shape in a plan view. The semiconductor laminated structure portion 6 is composed of a portion of the n-type semiconductor layer 3 excluding the vicinity of the peripheral edge portion, a light emitting layer 4, and a p-type semiconductor layer 5. The semiconductor laminated structure portion 6 has a quadrangular shape substantially similar to that of the substrate 2 in a plan view, and has a cut portion 6A at one corner portion. The side surface of the excised portion 6A is formed on a curved surface protruding inward in a plan view.

The substrate 2 is made of a material (eg, sapphire, GaN or SiC) that is transparent to the emission wavelength λ (eg 450 nm) of the light emitting layer 4. Specifically, "transparent with respect to the emission wavelength" means, for example, a case where the transmittance of the emission wavelength is 60% or more. In this embodiment, the substrate 2 is a sapphire substrate. The thickness of the substrate 2 is, for example, 200 μm to 300 μm.

On the surface 2A of the substrate 2, a plurality of truncated cone-shaped convex portions 7 projecting to the n-type semiconductor layer 3 are formed. As shown in FIG. 3A, these convex portions 7 are arranged discretely. In FIG. 3A, in a plan view, the direction along one of the two adjacent sides of the surface 2A of the substrate 2 is shown as the x direction, and the direction along the other side is shown as the y direction. In this embodiment, in a plan view, a plurality of convex portions 7 are arranged on the surface 2A of the substrate 2 in a pattern in which convex portions 7 are arranged at each apex and center (centroid) of each regular hexagon in an aggregate of regular hexagons. Is formed in. In other words, a plurality of convex portions 7 are formed on the surface 2A of the substrate 2 in a pattern in which convex portions 7 are arranged at the vertices of the six equilateral triangles constituting each regular hexagon in the aggregate of regular hexagons. There is. In this embodiment, each convex portion 7 is formed of SiN. Each convex portion 7 may be formed by etching the surface 2A of the substrate 2.

As shown in FIG. 3B, the plurality of convex portions 7 may be arranged in a matrix at intervals from each other.
Since the convex portion 7 is formed on the surface 2A of the substrate 2, it is possible to suppress total reflection of light at the interface between the surface 2A of the substrate 2 and the n-type semiconductor layer 3. Thereby, the light extraction efficiency can be improved. For example, light reflected by the back surface 2B of the substrate 2 and incident on the interface between the substrate 2 and the n-type semiconductor layer 3 at various angles is totally reflected to the back surface 2B side of the substrate 2 at the interface. Can be suppressed. Thereby, the light extraction efficiency can be improved.

The n-type semiconductor layer 3 is laminated on the surface 2A of the substrate 2. The n-type semiconductor layer 3 covers the entire surface 2A of the substrate 2. All the convex portions 7 are covered by the n-type semiconductor layer 3. The n-type semiconductor layer 3 is made of n-type GaN and is transparent to the emission wavelength λ of the light emitting layer 4.
Regarding the n-type semiconductor layer 3, in FIG. 2, the lower surface covering the front surface 2A of the substrate 2 is referred to as the back surface 3B, and the upper surface opposite to the back surface 3B is referred to as the front surface 3A. The surface 3A of the n-type semiconductor layer 3 has a high-level region in the central portion and a low-level region lower than the high-level region around the high-level region in a broad sense. As a result, a step is formed on the surface 3A of the n-type semiconductor layer 3 at the boundary between the high-level region and the low-level region.

The n-type semiconductor layer 3 in the high-order region constitutes the n-type semiconductor layer in the semiconductor laminated structure portion 6. The n-type semiconductor layer 3 in the lower region is referred to as a lead-out portion 8 drawn out from the semiconductor laminated structure portion 6. The pull-out portion 8 is pulled out to a position where its side surface is flush with the side surface of the substrate 2. The lead-out portion 8 is formed so as to surround the periphery of the semiconductor laminated structure portion 6.

On the surface of the lead-out portion 8, the n-side electrode 9 is formed in contact with the region corresponding to the cut-out portion 6A of the semiconductor laminated structure portion 6. The n-side electrode 9 includes an n-side transparent electrode layer 10 formed on the surface of the drawer portion 8 and an n-side pad 11 formed on the n-side transparent electrode layer 10. The n-side transparent electrode layer 10 has a quadrangular shape having four sides parallel to the four sides of the substrate 2 in a plan view, and a corner portion facing the side surface of the cut portion 6A of the semiconductor laminated structure portion 6 projects outward. It is formed on a curved surface. The n-side transparent electrode layer 10 is made of, for example, a material (for example, ITO, ZnO) that is transparent to the emission wavelength λ of the light emitting layer 4. The n-side pad 11 has a circular shape in a plan view. The n-side pad 11 is made of, for example, Cr or Au.

The light emitting layer 4 is laminated on the n-type semiconductor layer 3. The light emitting layer 4 covers almost the entire high-order region on the surface 3A of the n-type semiconductor layer 3. In this embodiment, the light emitting layer 4 is made of a nitride semiconductor containing In (for example, InGaN).
The p-type semiconductor layer 5 is laminated on the light emitting layer 4. The p-type semiconductor layer 5 covers almost the entire surface of the light emitting layer 4. The p-type semiconductor layer 5 is made of p-type GaN and is transparent to the emission wavelength λ of the light emitting layer 4. As described above, the light emitting diode structure (semiconductor laminated structure portion 6) in which the light emitting layer 4 is sandwiched between the n-type semiconductor layer 3 and the p-type semiconductor layer 5 is formed.

On the surface of the p-type semiconductor layer 5 opposite to the light emitting layer 4, a circular insulating film 12 is formed in a plan view at a position near the corner facing the cut portion 6A of the semiconductor laminated structure portion 6. .. The insulating film 12 is made of, for example, SiO ₂ .
A p-side transparent electrode layer 14 is formed on the surface of the p-type semiconductor layer 5. The p-side transparent electrode layer 14 covers almost the entire region of a predetermined current injection region 13 on the surface of the p-type semiconductor layer 5 (region other than the second portion 16B of the recess 16 described later in the current injection region 13). In this embodiment, the current injection region 13 is set to a region excluding the peripheral edge of the surface of the p-type semiconductor layer 5. The region on the surface of the p-type semiconductor layer 5 on which the insulating film 12 is formed is included in the current injection region 13, and the insulating film 12 is covered with the p-side transparent electrode layer 14. The p-side transparent electrode layer 14 is made of, for example, a material (for example, ITO, ZnO) that is transparent to the emission wavelength λ of the light emitting layer 4. The thickness of the p-side transparent electrode layer 14 is, for example, about 100 nm to 300 nm.

On the surface of the p-side transparent electrode layer 14 opposite to the p-type semiconductor layer 5, the p-side electrode (p-side) is located at a position facing the surface of the insulating film 12 (position directly above the insulating film 12 in FIG. 2). Pad) 15 is formed. The p-side electrode 15 has a circular shape having a diameter smaller than that of the insulating film 12 in a plan view. The p-side electrode 15 is made of, for example, Cr and Au. As is well known, the above-mentioned insulating film 12 is provided in order to reduce the light blocked by the p-side electrode 15 by passing a current other than directly under the p-side electrode 15 in the semiconductor laminated structure portion 6. ..

On the surface of the p-side transparent electrode layer 14 opposite to the p-type semiconductor layer 5, a plurality of recesses 16 that penetrate the p-side transparent electrode layer 14 and enter the inside of the semiconductor laminated structure 6 are formed. .. An insulating film 17 made of SiO ₂ is formed on the inner wall surface (bottom surface and inner peripheral surface) of each recess 16. In this embodiment, each recess 16 reaches the inside of the n-type semiconductor layer 3 from the surface of the p-side transparent electrode layer 14. Each recess 16 has a first portion (through hole) 16A penetrating the p-side transparent electrode layer 14 and a second portion (recess) communicating with the first portion 16A and entering the inside of the semiconductor laminated structure portion 6. It consists of 16B.

These recesses 16 are discretely arranged as shown in FIG. 4A. In this embodiment, a position directly above the center of each convex portion 7 formed on the substrate 2 (a position facing each convex portion 7) and three two-dimensionally adjacent convex portions in the plurality of convex portions 7. The recess 16 is formed at a position directly above the center position between the portions 7 (a position facing the center position between the three two-dimensionally adjacent convex portions 7). As shown in FIG. 4A, when the convex portions 7 are arranged at the vertices of the six equilateral triangles constituting each equilateral triangle in the aggregate of the equilateral hexagons, the center of gravity of each equilateral triangle is two-dimensional. It is the central position between the three convex portions 7 that are adjacent to each other. Therefore, in this case, the recess 16 is arranged at each vertex and each center of gravity of the six equilateral triangles constituting each regular hexagon.

The recess 16 may be arranged only at a position directly above the center of the convex portion 7 formed on the substrate 2. That is, the recess 16 may be arranged only at each vertex of the six equilateral triangles constituting each regular hexagon shown in FIG. 4A.
The recess 16 may be formed only at a position directly above the center position between the three two-dimensionally adjacent convex portions 7 in the plurality of convex portions 7 formed on the substrate 2. That is, the recess 16 may be arranged only at each center of gravity of the six equilateral triangles constituting each regular hexagon shown in FIG. 4A.

When the convex portions 7 are arranged in a matrix as shown in FIG. 3B, for example, as shown in FIG. 4B, the plurality of concave portions 16 are located directly above the center of each convex portion 7 in a plan view. It may be arranged at (a position facing each convex portion 7) and a central position between four two-dimensionally adjacent convex portions 7.
When the convex portions 7 are arranged in a matrix as shown in FIG. 3B, the plurality of concave portions 16 may be arranged only at a position directly above the center of each convex portion 7 in a plan view. It may be arranged only at a position directly above the center position between the four dimensionally adjacent convex portions 7.

In this embodiment, the recess 16 has a circular shape in a plan view. Further, in this embodiment, as shown in FIG. 5A, the recess 16 has a narrowed hem shape so that the area of the cross section becomes smaller toward the lower side. Therefore, the side surface (inner peripheral surface) of the inner wall surface of the recess 16 is an inclined surface inclined with respect to the surface 2A of the substrate 2.
As shown in FIG. 5B, the recess 16 may have a hem-spreading shape such that the area of the cross section increases toward the bottom. Also in this case, the side surface (inner peripheral surface) of the inner wall surface of the recess 16 is an inclined surface with respect to the surface 2A of the substrate 2.

6A to 6G are simulated cross-sectional views showing a method of manufacturing the light emitting element shown in FIGS. 1 and 2.
First, as shown in FIG. 6A, a layer (SiN) made of SiN is formed on the surface 2A of the substrate 2, and the SiN layer is formed into a plurality of convex portions 7 by etching using a resist pattern (not shown) as a mask. Separate into. Next, as shown in FIG. 6B, a layer made of n-type GaN (n-GaN layer) is formed on the surface 2A of the substrate 2 so as to cover all the convex portions 7. As a result, the n-type semiconductor layer 3 is formed on the surface 2A of the substrate 2.

Next, as shown in FIG. 6C, a nitride semiconductor containing In (for example, an InGaN layer) is formed on the surface of the n-type semiconductor layer 3. As a result, the light emitting layer 4 is formed on the surface of the n-type semiconductor layer 3. The emission wavelength λ of the light emitting layer 4 is controlled to 440 nm to 460 nm by adjusting the composition of In or Ga. Next, a layer made of n-type GaN (n-GaN layer) is formed on the surface of the light emitting layer 4. As a result, the p-type semiconductor layer 5 is formed on the surface of the light emitting layer 4.

Next, a resist pattern (not shown) having an opening in a region where the insulating film 12 should be formed is formed on the p-type semiconductor layer 5. Then, as shown in FIG. 6D, the insulating film 12 made of SiO ₂ is formed through the resist pattern, for example, by a sputtering method or a plasma CVD method.
Next, a resist pattern (not shown) having an opening in the region (current injection region 13) where the p-side transparent electrode layer 14 should be formed is formed on the p-type semiconductor layer 5. Then, a layer made of ITO (ITO layer) is deposited on the p-type semiconductor layer 5 through the resist pattern, for example, by a sputtering method. Then, the unnecessary portion of the ITO material is lifted off together with the resist pattern. As a result, as shown in FIG. 6E, the p-side transparent electrode layer 14 that covers the insulating film 12 is formed on the surface of the p-type semiconductor layer 5.

Next, as shown in FIG. 6F, each of the p-type semiconductor layer 5, the light emitting layer 4, and the n-type semiconductor layer 3 is selectively removed by etching using a resist pattern (not shown) as a mask. As a result, the semiconductor laminated structure portion 6 and the drawing portion 8 drawn out from the semiconductor laminated structure portion 6 are formed.
Next, a resist pattern (not shown) having an opening in the region where the recess 16 should be formed is formed on the p-side transparent electrode layer 14. Then, as shown in FIG. 6G, the recess 16 is formed by etching the p-side transparent electrode layer 14, the p-type semiconductor layer 5, the light emitting layer 4, and the n-type semiconductor layer 3 through the resist pattern. Next, the SiO ₂ layer is formed on the resist pattern and on the inner wall surface of the recess 16 with the resist pattern left. Then, the unnecessary portion of the SiO ₂ layer is lifted off together with the resist pattern. As a result, the insulating film 17 made of SiO ₂ is formed on the inner wall surface (bottom surface and side surface) of the recess 16.

After that, the n-side electrode 9 is formed on the surface of the lead-out portion 8 (n-type semiconductor layer 3), and the p-side electrode 15 is formed in the region directly above the insulating film 12 on the surface of the p-side transparent electrode layer 14. .. As a result, the light emitting elements shown in FIGS. 1 and 2 are obtained.
In this light emitting element 1, when a forward voltage is applied between the n-side electrode 9 (n-side pad 11) and the p-side electrode (p-side pad) 15, a current is applied from the p-side electrode 15 to the n-side electrode 9. Flows. The current flows from the p-side electrode 15 toward the n-side electrode 9 through the p-side transparent electrode layer 14, the p-type semiconductor layer 5, the light emitting layer 4, and the n-type semiconductor layer 3 in this order. When the current flows in this way, electrons are injected from the n-type semiconductor layer 3 into the light emitting layer 4, and holes are injected from the p-type semiconductor layer 5 into the light emitting layer 4. Then, these holes and electrons are recombined in the light emitting layer 4, so that light having a wavelength of 440 nm to 460 nm is generated from the light emitting layer 4. This light passes through the p-type semiconductor layer 5 and the p-side transparent electrode layer 14 and is taken out from the surface of the p-side transparent electrode layer 14.

The light directed from the light emitting layer 4 toward the n-type semiconductor layer 3 passes through the n-type semiconductor layer 3. Then, a part of this light is reflected at the interface between the n-type semiconductor layer 3 and the substrate 2, the back surface of the substrate 2, and the like. The reflected light passes through the n-type semiconductor layer 3, the light emitting layer 4, the p-type semiconductor layer 5, and the p-side transparent electrode layer 14 in this order, and is taken out from the surface of the p-side transparent electrode layer 14.
In this embodiment, a plurality of recesses 16 are formed which penetrate the p-side transparent electrode layer 14 from the surface of the p-side transparent electrode layer 14 and enter the inside of the semiconductor laminated structure portion 6. As a result, the light propagating in the semiconductor laminated structure portion 6 is reflected by the side surface of the inner wall surface of the recess 16 and the light is extracted to the p-side transparent electrode layer 14 side, so that the light extraction efficiency can be improved. In particular, in this embodiment, since the recess 16 has the second portion 16B that has entered the inside of the p-side transparent electrode layer 14, compared to the case where the recess is formed only in the p-side transparent electrode layer 14. The light extraction efficiency can be improved.

Further, in this embodiment, the recess 16 reaches the n-type semiconductor layer 3. As the depth of the recess 16 becomes deeper, the area of the side surface of the inner wall surface of the recess 16 becomes larger, so that the light extraction efficiency can be improved as compared with the case where the recess 16 does not reach the n-type semiconductor layer 3. When the recess 16 is formed until it reaches the n-type semiconductor layer 3, the recess 16 penetrates the light emitting layer 4, so that the area of the light emitting layer 4 is reduced. However, before the light generated in the light emitting layer 4 is absorbed in the light emitting layer 4, the light can be taken out of the light emitting layer 4 by the recess 16, so that the light extraction efficiency can be improved.

Further, in this embodiment, since a plurality of convex portions 7 are formed on the surface 2A of the substrate 2, the light extraction efficiency can be improved.
When a plurality of convex portions 7 are formed on the surface 2A of the substrate 2, the n-type semiconductor layer 3 is crystal-grown on the substrate 2 in the region directly above the center of the convex portions 7 in the n-type semiconductor layer 3. When it is made to grow, the growth in the lateral direction is combined, so that a defective portion is likely to occur. Further, in the region directly above the center position between the plurality of two-dimensionally adjacent convex portions 7 in the plurality of convex portions 7 in the n-type semiconductor layer 3, the defect portion of the substrate 2 can be easily inherited. Is likely to occur. When the defective portion is present in the n-type semiconductor layer 3, the resistance value of the defective portion is low, so that the current is concentrated and flows in the defective portion, and the light emitting element 1 may be destroyed.

In this embodiment, the recess 16 is arranged directly above the center position of each convex portion 7, and the true position of the center position between the plurality of two-dimensionally adjacent convex portions 7 in the plurality of convex portions 7 is true. The recess 16 is arranged at the upper position. That is, the recess 16 is arranged directly above the portion so that a defective portion in the n-type semiconductor layer 3 is likely to occur. As a result, it becomes difficult for the current from the p-side transparent electrode layer 14 to flow to a place where a defect portion in the n-type semiconductor layer 3 is likely to occur. As a result, it is possible to suppress the concentrated flow of current in the defective portion, so that the reliability of the light emitting element 1 can be improved. Further, in this embodiment, since the insulating film 17 is formed on the inner wall surface of the recess 16, the current can be made less likely to flow in the place where the defect is likely to occur, so that the reliability of the light emitting element 1 can be further improved. ..

The effect of suppressing the concentrated flow of current in the defective portion can be achieved even when the recess 16 is composed of only the second portion 16B. That is, if the concave portion is formed on the surface of the semiconductor laminated structure portion 6, even if the concave portion is not formed on the p-side transparent electrode layer 14, the effect of suppressing the current concentrated flow in the defective portion can be obtained. Be done.
FIG. 7 is a schematic cross-sectional view of the light emitting element package.

The light emitting element package 51 includes a light emitting element 1, a support substrate 52, and a resin package 53. The support substrate 52 includes an insulating substrate 54 that supports the light emitting element 1 and a pair of electrodes 55 and 56 that are provided so as to be exposed from both ends of the insulating substrate 54.
The light emitting element 1 is supported by the support substrate 52 in such a posture that the surface 2A of the substrate 2 faces upward. Specifically, the back surface 2B of the substrate 2 of the light emitting element 1 is bonded to the insulating substrate 54 via the adhesive layer 57. That is, the light emitting element 1 is face-up mounted. The n-side electrode 9 (n-side pad 11) of the light emitting element 1 and one electrode 55 are connected by a wire 58. The p-side electrode 15 of the light emitting element 1 and the other electrode 56 are connected by a wire 59.

The resin package 53 is a case filled with resin, and is fixed to the support substrate 52 in a state in which the light emitting element 1 is housed (covered) and protected. The resin package 53 has a reflecting portion 60 on the side surface (a portion facing the light emitting element 1) for reflecting the light emitted from the light emitting element 1 and taking it out to the outside. The reflective portion 60 is made of, for example, a resin.

Some of the resins constituting the resin package 53 contain a phosphor or a reflective agent. For example, when the light emitting element 1 emits blue light, the light emitting element package 51 can emit white light by containing a yellow phosphor in the resin. The light emitting element package 51 can be used for lighting equipment such as a light bulb by gathering a large number of them, and can also be used for a backlight of a liquid crystal television or a headlamp of an automobile or the like.

In such a light emitting element package 51, the light emitted by the light emitting layer 4 of the light emitting element 1 immediately passes through the p-type semiconductor layer 5 and is emitted from the surface of the p-side transparent electrode layer 14, or the n-type semiconductor layer 3 Is transmitted and once reflected by the back surface 2B of the substrate 2, and then emitted from the surface of the p-side transparent electrode layer 14.
In consideration of the light emitting element package as shown in FIG. 7, a plurality of virtual samples shown in Table 1 (hereinafter, simply referred to as "samples") are subjected to a simulation using a ray tracing method (ray tracing). The amount of light emitted from S1 to S24 was calculated.

表１において、「下地凸部」とは、基板２の表面２Ａに形成される凸部７を示している。「上部凹部」とは、ｐ型透明電極層１５の表面から半導体積層構造部６内部に達する凹部１６を示している。「上部凹部形状」とは、凹部１６の形状を示しており、図５Ａに示すような裾狭まりの形状を「形状Ａ」で示し、図５Ｂに示すような裾広がりの形状を「形状Ｂ」で示している。「上部凹部シフト量」の定義については、後述する。

In Table 1, the “base convex portion” indicates a convex portion 7 formed on the surface 2A of the substrate 2. The “upper recess” refers to a recess 16 that reaches the inside of the semiconductor laminated structure 6 from the surface of the p-type transparent electrode layer 15. The "upper concave shape" indicates the shape of the concave portion 16, the shape of the hem narrowing as shown in FIG. 5A is indicated by "shape A", and the shape of the hem widening as shown in FIG. 5B is "shape B". It is shown by. The definition of "upper concave shift amount" will be described later.

Each of the samples S1 to S24 has the above-mentioned light emitting element 1 as a basic structure, but has a structure different from that of the light emitting element 1. Samples S1 and S2 are comparative examples, and samples S3 to S24 are examples.
First, among the samples S3 to S24 of the examples, the samples S5 to S24 will be described. These samples S5 to S24 have a convex portion 7 and a concave portion 16. However, the pattern of the entire concave portion 16 and the position of the concave portion 16 with respect to the convex portion 7 are different from those of the light emitting element 1 described above. Further, the shape of the concave portion of the samples S5 to S14 is "shape A", and the shape of the concave portion of the samples S15 to S24 is "shape B".

The pattern of the entire recess 16 of the samples S5 to S24 will be described. The convex portions 7 on the surface of the substrate 2 are arranged in the pattern shown in FIG. 3A. The pattern of the entire concave portion 16 was the same as the pattern of the entire convex portion 7. The positions of the concave portions 16 with respect to the convex portions 7 are different between the samples S5 to S14 and between the samples S15 to S24.
From the state where each concave portion 16 is arranged directly above the center position of each convex portion 7, the central position between the three convex portions 7 where each concave portion 16 is two-dimensionally adjacent (the center of gravity of each equilateral triangle in FIG. 3A). The position of the concave portion 16 with respect to the convex portion 7 was changed by slightly shifting the position of each concave portion 16 with respect to the corresponding convex portion 7 until the concave portion 16 was arranged directly above the position). The amount of deviation of the position of the concave portion 16 with respect to the convex portion 7 is different between the samples S5 to S14 and between the samples S15 to S24.

The amount of deviation of the position of the concave portion 18 with respect to the convex portion 7 is the “upper concave portion shift amount” shown in Table 1. The "upper concave shift amount" includes an x-direction shift amount and a y-direction shift amount. As shown in FIG. 8, the deviation amount (distance between center points) Δx of the concave portion 18 with respect to the convex portion 7 in the x direction (same as the x direction in FIG. 3A) is defined as the x direction shift amount, and the y direction (in FIG. 3A). The deviation amount (distance between center points) Δy (same as in the y direction) is defined as the shift amount in the y direction.

“L” and “H” used in the “upper concave shift amount” in Table 1 are defined as follows. In FIG. 3A, the length of one side of the six equilateral triangles constituting the hexagon was defined as L [μm], and the height of those equilateral triangles was defined as H [μm].
For example, in the sample S5 and the sample S15, the concave portion 18 is arranged only at a position directly above the center of each convex portion 7 (Δx = Δy = 0). Further, for example, in the sample S14 and the sample S24, the recess 18 is arranged only at a position directly above the center position between the three two-dimensionally adjacent convex portions 7 (Δx = L, Δy = H /). 3).

Sample S1 of the comparative example is a light emitting element in which the convex portion 7 and the concave portion 16 do not exist with respect to the light emitting element 1. Sample S2 of the comparative example is a light emitting element in which the convex portion 7 is present but the concave portion 16 is not present with respect to the light emitting element 1.
The sample S3 of the example is a light emitting element in which the convex portion 7 does not exist but the concave portion 16 exists. However, the pattern, shape, and size of the recess 16 of the sample S3 are the same as those of the sample S5 described above. The sample S4 of the example is a light emitting element in which the convex portion 7 does not exist but the concave portion 16 exists. However, the pattern, shape, and size of the recess 16 of the sample S4 are the same as those of the sample S15 described above.

FIG. 9 is a graph showing the simulation results. In FIG. 9, the standardized light emission amount [%] after standardizing the light emission amount of each sample S1 to S24 with the light emission amount of the sample S2 as 100% is shown in a bar graph.
From FIG. 9, it can be seen that the light emission amount of the samples S3 and S4 is larger than the light emission amount of the samples S1 and S2. That is, in a light emitting element in which the concave portion 16 exists even if the convex portion 7 does not exist, compared with a light emitting element in which both the convex portion 7 and the concave portion 16 do not exist or a light emitting element in which the convex portion 7 exists but the concave portion 16 does not exist. Therefore, the amount of light emitted from the light emitting element (light emission brightness) can be increased.

Further, it can be seen from FIG. 9 that the amount of light emitted from samples S5 to S14 is larger than the amount of light received by sample S3. Similarly, it can be seen that the amount of light emitted from samples S15 to S24 is larger than the amount of light received by sample S4. That is, when the shapes of the concave portions 16 are the same, light emission in which both the concave portions 16 and the convex portions 7 are present as compared with the light emitting element in which only the concave portions 16 are present among the concave portions 16 and the convex portions 7. It can be seen that the element can increase the amount of light emitted (emission brightness) of the light emitting element.

Since the defect portion in the n-type semiconductor layer 3 is not considered in this simulation, the influence of the effect of suppressing the current from flowing through the defect portion due to the arrangement position of the recess 16 is reflected in the simulation result. Absent.
FIG. 10 is a schematic cross-sectional view showing another example of the light emitting device package.
The light emitting element package 71 includes a light emitting element 1, a support substrate 72, and a resin package 73. The support substrate 72 is formed on the surface of the insulating substrate 74 in the resin package 73, the insulating substrate 74 that supports the light emitting element 1, the pair of electrodes 75 and 76 provided so as to be exposed from both ends of the insulating substrate 74. The n-side electrode layer 77 and the p-side electrode layer 78 are provided, and the n-side bonding layer 79 and the p-side bonding layer 80 formed on the surfaces of the n-side electrode layer 77 and the p-side electrode layer 78 are provided. The n-side electrode layer 77 is connected to one of the electrodes 75. The p-side electrode layer 78 is connected to the other electrode 76.

The light emitting element 1 is supported by the support substrate 72 in such a posture that the surface 2A of the substrate 2 faces downward. Specifically, the surface of the n-side electrode 9 (n-side pad 11) of the light emitting element 1 is bonded to the n-side bonding layer 79, and the surface of the p-side electrode 15 of the light emitting element 1 is bonded to the p-side bonding layer 80. ing. That is, the light emitting element 1 is face-down mounted. A reflecting portion 81 for reflecting the light transmitted through the p-side transparent electrode layer 14 of the light emitting element 1 is formed at a required portion on the surface of the insulating substrate 74. The reflective portion 81 is made of, for example, a resin.

The resin package 73 is a case filled with resin, and is fixed to the support substrate 72 in a state in which the light emitting element 1 is housed (covered) and protected. The resin package 73 has a reflecting portion 82 on the side surface (a portion facing the light emitting element 1) for reflecting the light emitted from the light emitting element 1 and taking it out to the outside. The reflective portion 82 is made of, for example, a resin.

In such a light emitting element package 71, the light emitted by the light emitting layer 4 of the light emitting element 1 immediately passes through the n-type semiconductor layer 3 and is emitted from the back surface 2B of the substrate 2, or the p-type semiconductor layer 5 and the p side. After passing through the transparent electrode layer 14 and being reflected by the reflecting portion 81, it is emitted from the back surface 2B of the substrate 2.
Although the embodiment of the first invention has been described above, the first invention can be implemented in still other embodiments. In the above embodiment, the recess 16 reaches the inside of the n-type semiconductor layer 3 from the surface of the p-side transparent electrode layer 14, but reaches the inside of the p-type semiconductor layer 5 from the surface of the p-side transparent electrode layer 14 (light emission). It may not reach layer 4). Further, the recess 16 may be composed of only the second portion 16B formed on the surface of the semiconductor laminated structure portion 6 (the surface of the p-type semiconductor layer 5). That is, the recess 16 (first portion 16A) may not be formed in the p-side transparent electrode layer 14. In this case, the entire area of the current injection region 13 on the surface of the p-type semiconductor layer 5 is covered with the p-side transparent electrode layer 14.

Further, in the above-described embodiment, the recess 16 is formed in a circular shape in a plan view, but may be formed in a polygonal shape (quadrangle, hexagon, etc.) in a plan view.
Further, in the above-described embodiment, GaN is exemplified as the nitride semiconductor constituting the n-type semiconductor layer 3 and the p-type semiconductor layer 5, but other nitride semiconductors such as aluminum nitride (AlN) and indium nitride (InN) are exemplified. May be used. Nitride semiconductors can generally be expressed as Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1). Further, the present invention may be applied not only to nitride semiconductors but also to other compound semiconductors such as GaAs and light emitting devices using semiconductor materials (for example, diamond) other than compound semiconductors.

In addition, various design changes can be made within the scope of the matters described in the claims.
[2] Second Invention The second invention has the following features.
A1. A substrate having a front surface and a back surface, a semiconductor laminated structure portion having an n-type semiconductor layer, a light emitting layer and a p-type semiconductor layer laminated in this order on the surface of the substrate, and a side opposite to the light emitting layer in the p-type semiconductor layer. Within a predetermined current injection region on the surface of the above, a plurality of transparent insulating films formed discretely and the current injection region on the surface of the p-type semiconductor layer opposite to the light emitting layer are formed and the transparent. A light emitting element including a transparent electrode layer covering an insulating film and a p-side electrode formed on a surface of the transparent electrode layer opposite to the p-type semiconductor layer.

In this configuration, the light incident on the transparent electrode layer from the semiconductor laminated structure portion is reflected by the side surface of the transparent insulating film and is taken out from the surface of the transparent electrode layer opposite to the p-type semiconductor layer. Efficiency can be increased.
A2. “A1.” Further including a lead-out portion electrically connected to the n-type semiconductor layer and drawn out from the semiconductor laminated structure portion in a direction parallel to the substrate, and an n-side electrode formed on the lead-out portion. The light emitting element according to the above.

A3. A plurality of convex portions covered with the n-type semiconductor layer are formed on the surface of the substrate, and the plurality of transparent insulating films are arranged to face each other in the n-type semiconductor layer where defects are likely to occur. The light emitting element according to "A1." Or "A2.", Which comprises a transparent insulating film.
In this configuration, since a plurality of convex portions are formed on the surface of the substrate, it is possible to suppress total reflection of light at the interface between the substrate and the n-type semiconductor layer. As a result, the light extraction efficiency can be improved.

Further, in this configuration, the plurality of transparent insulating films include the transparent insulating films arranged so as to face each other in the n-type semiconductor layer where defects are likely to occur. As a result, it becomes difficult for the current from the transparent electrode side to flow to the place where a defect portion in the n-type semiconductor layer is likely to occur. As a result, it is possible to suppress the concentrated flow of current to the defective portion in the n-type semiconductor layer, so that the reliability of the light emitting element can be improved.

A4. The light emitting element according to claim 3, wherein the plurality of transparent insulating films include transparent insulating films arranged so as to face each of the convex portions.
When a plurality of convex portions are formed on the surface of the substrate, lateral growth occurs when the n-type semiconductor layer is crystal-grown on the substrate in the region directly above the center of the convex portions in the n-type semiconductor layer. Since they are combined, defective parts are likely to occur. In this configuration, the plurality of transparent insulating films include transparent insulating films arranged so as to face each convex portion. As a result, it becomes difficult for the current from the transparent electrode side to flow to the place where a defect portion in the n-type semiconductor layer is likely to occur. As a result, it is possible to suppress the concentrated flow of current to the defective portion in the n-type semiconductor layer, so that the reliability of the light emitting element can be improved.

A5. The light emission according to claim 3, wherein the plurality of transparent insulating films include a transparent insulating film arranged so as to face a central position between a plurality of two-dimensionally adjacent convex portions in the plurality of convex portions. element.
When a plurality of convex portions are formed on the surface of the substrate, the substrate is formed in the region directly above the center position between the plurality of two-dimensionally adjacent convex portions in the n-type semiconductor layer. Since it is easy to take over the defects of, defects are likely to occur. In this configuration, the plurality of transparent insulating films include a transparent insulating film arranged so as to face the central position between the plurality of two-dimensionally adjacent convex portions in the plurality of convex portions. As a result, it becomes difficult for the current from the transparent electrode side to flow to the place where a defect portion in the n-type semiconductor layer is likely to occur. As a result, it is possible to suppress the concentrated flow of current to the defective portion in the n-type semiconductor layer, so that the reliability of the light emitting element can be improved.

A6. The light emitting element according to any one of claims 3 to 5, wherein the convex portion is formed by an insulating film formed on the surface of the substrate.
A7. The light emitting element according to any one of claims 3 to 5, wherein the convex portion is formed by etching the surface of the substrate.
A8. The light emitting device according to any one of claims 1 to 7, wherein the thickness of the transparent insulating film is 10 nm or more and 5 μm or less.

A9. A current blocking insulating film is formed on the surface of the p-type semiconductor layer opposite to the light emitting layer at a position facing the p-side electrode, and the transparent insulating film is the same as the current blocking insulating film. The light emitting element according to any one of claims 1 to 8, which is formed in the process.
Embodiments of the second invention will be described in detail with reference to the accompanying drawings.
FIG. 11 is a schematic plan view of the light emitting device according to the embodiment of the second invention. FIG. 12 is a schematic cross-sectional view of the light emitting element of FIG.

The light emitting element 101 has a chip shape having a rectangular shape in a plan view. The light emitting element 101 includes a substrate 102 having a front surface 102A and a back surface 102B, an n-type conductive semiconductor layer 103, a light emitting layer 104, and a p-type conductive semiconductor layer 105 that are sequentially laminated on the front surface 102A of the substrate 102. Hereinafter, the n-type conductive semiconductor layer 103 is referred to as an “n-type semiconductor layer 103”, and the p-type conductive semiconductor layer 105 is referred to as a “p-type semiconductor layer 105”. The substrate 102 has a rectangular shape in a plan view. The semiconductor laminated structure portion 106 is composed of a portion of the n-type semiconductor layer 103 excluding the vicinity of the peripheral edge portion, a light emitting layer 104, and a p-type semiconductor layer 105. The semiconductor laminated structure portion 106 has a quadrangular shape substantially similar to that of the substrate 102 in a plan view, and has a cut portion 106A at one corner portion. The side surface of the excised portion 106A is formed on a curved surface protruding inward in a plan view.

The substrate 102 is made of a material (eg, sapphire, GaN or SiC) that is transparent to the emission wavelength λ (eg 450 nm) of the light emitting layer 104. Specifically, "transparent with respect to the emission wavelength" means, for example, a case where the transmittance of the emission wavelength is 60% or more. In this embodiment, the substrate 102 is a sapphire substrate. The thickness of the substrate 102 is, for example, 200 μm to 300 μm.

On the surface 102A of the substrate 102, a plurality of truncated cone-shaped convex portions 107 projecting to the n-type semiconductor layer 103 are formed. These convex portions 107 are discretely arranged as shown in FIG. 13A. In FIG. 13A, in a plan view, the direction along one side of the two adjacent sides of the surface 102A of the substrate 102 is shown as the x direction, and the direction along the other side is shown as the y direction. In this embodiment, in a plan view, the plurality of convex portions 107 are arranged on the surface 102A of the substrate 102 in such a pattern that the convex portions 107 are arranged at the vertices and the centers (centroids) of each regular hexagon in the aggregate of the regular hexagons. Is formed in. In other words, a plurality of convex portions 107 are formed on the surface 102A of the substrate 102 in a pattern in which convex portions 107 are arranged at the vertices of the six equilateral triangles constituting each regular hexagon in the aggregate of regular hexagons. There is. In this embodiment, each convex portion 107 is formed of SiN. Each convex portion 107 may be formed by etching the surface 102A of the substrate 102.

As shown in FIG. 13B, the plurality of convex portions 107 may be arranged in a matrix at intervals from each other.
Since the convex portion 107 is formed on the surface 102A of the substrate 102, it is possible to suppress total reflection of light at the interface between the surface 102A of the substrate 102 and the n-type semiconductor layer 103. Thereby, the light extraction efficiency can be improved. For example, light reflected by the back surface 102B of the substrate 102 and incident on the interface between the substrate 102 and the n-type semiconductor layer 103 at various angles is totally reflected on the back surface 102B side of the substrate 102 at the interface. Can be suppressed. Thereby, the light extraction efficiency can be improved.

The n-type semiconductor layer 103 is laminated on the surface 102A of the substrate 102. The n-type semiconductor layer 103 covers the entire surface 102A of the substrate 102. All the protrusions 107 are covered by the n-type semiconductor layer 103. The n-type semiconductor layer 103 is made of n-type GaN and is transparent to the emission wavelength λ of the light emitting layer 104.
Regarding the n-type semiconductor layer 103, in FIG. 12, the lower surface covering the front surface 102A of the substrate 102 is referred to as the back surface 103B, and the upper surface opposite to the back surface 103B is referred to as the front surface 103A. The surface 103A of the n-type semiconductor layer 103 has a high-level region in the central portion and a low-level region lower than the high-level region around the high-level region. As a result, a step is formed on the surface 103A of the n-type semiconductor layer 103 at the boundary between the high-level region and the low-level region.

The n-type semiconductor layer 103 in the high-order region constitutes the n-type semiconductor layer in the semiconductor laminated structure portion 106. The n-type semiconductor layer 103 in the lower region is referred to as a drawing portion 108 drawn from the semiconductor laminated structure portion 106. The pull-out portion 108 is pulled out to a position where its side surface is flush with the side surface of the substrate 102. The lead-out portion 108 is formed so as to surround the semiconductor laminated structure portion 106.

On the surface of the drawer portion 108, the n-side electrode 109 is formed in contact with the region corresponding to the cut portion 106A of the semiconductor laminated structure portion 106. The n-side electrode 109 includes an n-side transparent electrode layer 110 formed on the surface of the drawer portion 108 and an n-side pad 111 formed on the n-side transparent electrode layer 110. The n-side transparent electrode layer 110 has a quadrangular shape having four sides parallel to the four sides of the substrate 102 in a plan view, and a corner portion facing the side surface of the cut portion 106A of the semiconductor laminated structure portion 106 projects outward. It is formed on a curved surface. The n-side transparent electrode layer 110 is made of, for example, a material (for example, ITO, ZnO) that is transparent to the emission wavelength λ of the light emitting layer 104. The n-side pad 111 has a circular shape in a plan view. The n-side pad 111 is made of, for example, Cr or Au.

The light emitting layer 104 is laminated on the n-type semiconductor layer 103. The light emitting layer 104 covers the entire high-order region on the surface 103A of the n-type semiconductor layer 103. In this embodiment, the light emitting layer 104 is made of a nitride semiconductor containing In (for example, InGaN).
The p-type semiconductor layer 105 is laminated on the light emitting layer 104. The p-type semiconductor layer 105 covers the entire surface of the light emitting layer 104. The p-type semiconductor layer 105 is made of p-type GaN and is transparent to the emission wavelength λ of the light emitting layer 104. As described above, the light emitting diode structure (semiconductor laminated structure portion 106) in which the light emitting layer 104 is sandwiched between the n-type semiconductor layer 103 and the p-type semiconductor layer 105 is formed.

On the surface of the p-type semiconductor layer 105 opposite to the light emitting layer 104, a first insulating film (for current interruption) having a circular shape in a plan view is located at a position near the corner facing the cut portion 106A of the semiconductor laminated structure portion 106. Insulating film) 112 is formed. Further, a plurality of circular second insulating films (transparent insulating films) 113 in a plan view are formed in a predetermined current injection region 114 on the surface of the p-type semiconductor layer 105. The first insulating film 112 and the second insulating film 113 are made of, for example, SiO ₂ which is transparent to the emission wavelength λ of the light emitting layer 104. In this embodiment, the current injection region 114 is set to a region excluding the peripheral edge of the surface of the p-type semiconductor layer 105. The region where the first insulating film 112 is formed on the surface of the p-type semiconductor layer 105 is included in the current injection region 114.

A p-side transparent electrode layer 115 is formed in the current injection region 114 on the surface of the p-type semiconductor layer 105. The first insulating film 112 and the second insulating film 113 are covered with the p-side transparent electrode layer 115. The p-side transparent electrode layer 115 is made of, for example, a material (for example, ITO, ZnO) that is transparent to the emission wavelength λ of the light emitting layer 104. The thickness of the p-side transparent electrode layer 115 is, for example, about 100 nm to 300 nm. The thickness of the second insulating film 113 is, for example, 10 nm or more and 5000 nm or less. In order to enhance the light extraction effect, the thickness of the second insulating film 113 is preferably 1500 nm or more.

On the surface of the p-side transparent electrode layer 115 opposite to the p-type semiconductor layer 105, the p-side is located at a position facing the surface of the first insulating film 112 (position directly above the first insulating film 112 in FIG. 12). An electrode (p-side pad) 116 is formed. The p-side electrode 116 has a circular shape having a diameter smaller than that of the first insulating film 112 in a plan view. The p-side electrode 116 is made of, for example, Cr and Au. As is well known, the above-mentioned first insulating film 112 is provided in order to reduce the light blocked by the p-side electrode 116 by passing a current other than directly under the p-side electrode 116 in the semiconductor laminated structure portion 106. ing.

The second insulating film (transparent insulating film) 113 is discretely arranged as shown in FIG. 14A. In this embodiment, a position directly above the center of each convex portion 107 formed on the substrate 102 (a position facing each convex portion 107) and a plurality of two-dimensionally adjacent convex portions in the plurality of convex portions 107. The second insulating film 113 is formed at a position directly above the center position between the portions 107 (a position facing the center position between the three two-dimensionally adjacent convex portions 107). As shown in FIG. 14A, when the convex portions 107 are arranged at the vertices of the six equilateral triangles constituting each equilateral hexagon in the assembly of the equilateral hexagons, the center of gravity of each equilateral triangle is two-dimensional. It is the center position between the three convex portions 107 that are adjacent to each other. Therefore, in this case, the second insulating film 113 is arranged at each vertex and each center of gravity of the six equilateral triangles constituting each regular hexagon.

The second insulating film 113 may be arranged only at a position directly above the center of the convex portion 107 formed on the substrate 102. That is, the second insulating film 113 may be arranged only at each vertex of the six equilateral triangles constituting each regular hexagon shown in FIG. 14A.
The second insulating film 113 may be formed only at a position directly above the center position between the three two-dimensionally adjacent convex portions 107 in the plurality of convex portions 107 formed on the substrate 102. That is, the second insulating film 113 may be arranged only at the center of gravity of each of the six equilateral triangles constituting each regular hexagon shown in FIG. 14A.

When the convex portions 107 are arranged in a matrix as shown in FIG. 13B, for example, as shown in FIG. 14B, the plurality of second insulating films 113 are at the center of each convex portion 107 in a plan view. It may be arranged at a position directly above (a position facing each convex portion 107) and a central position between four two-dimensionally adjacent convex portions 107.
When the convex portions 107 are arranged in a matrix as shown in FIG. 13B, the plurality of second insulating films 113 may be arranged only at a position directly above the center of each convex portion 107 in a plan view. Often, it may be arranged only at a position directly above the center position between the four two-dimensionally adjacent convex portions 107.

15A to 15F are simulated cross-sectional views showing a method of manufacturing the light emitting element shown in FIGS. 11 and 12.
First, as shown in FIG. 15A, a layer (SiN) made of SiN is formed on the surface 102A of the substrate 102, and the SiN layer is formed into a plurality of convex portions 107 by etching using a resist pattern (not shown) as a mask. Separate into. Next, as shown in FIG. 15B, a layer made of n-type GaN (n-GaN layer) is formed on the surface 102A of the substrate 102 so as to cover all the convex portions 107. As a result, the n-type semiconductor layer 103 is formed on the surface 102A of the substrate 102.

Next, as shown in FIG. 15C, a nitride semiconductor containing In (for example, an InGaN layer) is formed on the surface of the n-type semiconductor layer 103. As a result, the light emitting layer 104 is formed on the surface of the n-type semiconductor layer 103. The emission wavelength λ of the light emitting layer 104 is controlled to 440 nm to 460 nm by adjusting the composition of In or Ga. Next, a layer made of n-type GaN (n-GaN layer) is formed on the surface of the light emitting layer 104. As a result, the p-type semiconductor layer 105 is formed on the surface of the light emitting layer 104.

Next, a resist pattern (not shown) having an opening in a region where the first insulating film 112 and the second insulating film 113 should be formed is formed on the p-type semiconductor layer 105. Then, as shown in FIG. 15D, the first insulating film 112 and the second insulating film 113 made of SiO ₂ are formed through the resist pattern, for example, by a sputtering method or a plasma CVD method.
Next, a resist pattern (not shown) having an opening in the region (current injection region 114) where the p-side transparent electrode layer 115 should be formed is formed on the p-type semiconductor layer 105. Then, a layer made of ITO (ITO layer) is deposited on the p-type semiconductor layer 105 through the resist pattern, for example, by a sputtering method. Then, the unnecessary portion of the ITO material is lifted off together with the resist pattern. As a result, as shown in FIG. 15E, the p-side transparent electrode layer 115 that covers the first insulating film 112 and the second insulating film 113 is formed on the surface of the p-type semiconductor layer 105.

Next, as shown in FIG. 15F, each of the p-type semiconductor layer 105, the light emitting layer 104, and the n-type semiconductor layer 103 is selectively removed by etching using a resist pattern (not shown) as a mask. As a result, the semiconductor laminated structure portion 106 and the drawing portion 108 drawn out from the semiconductor laminated structure portion 106 are formed.
After that, the n-side electrode 109 is formed on the surface of the lead-out portion 108 (n-type semiconductor layer 103), and the p-side electrode 116 is placed in the region directly above the first insulating film 112 on the surface of the p-side transparent electrode layer 115. Form. As a result, the light emitting elements shown in FIGS. 11 and 12 are obtained.

In this light emitting element 101, when a forward voltage is applied between the n-side electrode 109 (n-side pad 111) and the p-side electrode (p-side pad) 116, a current is applied from the p-side electrode 116 toward the n-side electrode 109. Flows. The current flows from the p-side electrode 116 toward the n-side electrode 109 through the p-side transparent electrode layer 115, the p-type semiconductor layer 105, the light emitting layer 104, and the n-type semiconductor layer 103 in this order. By the current flowing in this way, electrons are injected from the n-type semiconductor layer 103 into the light emitting layer 104, and holes are injected from the p-type semiconductor layer 105 into the light emitting layer 104. Then, these holes and electrons are recombined in the light emitting layer 104 to generate light having a wavelength of 440 nm to 460 nm from the light emitting layer 104. This light passes through the p-type semiconductor layer 105 and the p-side transparent electrode layer 115, and is taken out from the surface of the p-side transparent electrode layer 115.

The light directed from the light emitting layer 104 toward the n-type semiconductor layer 103 passes through the n-type semiconductor layer 103. Then, a part of this light is reflected at the interface between the n-type semiconductor layer 103 and the substrate 102, the back surface of the substrate 102, and the like. The reflected light passes through the n-type semiconductor layer 103, the light emitting layer 104, the p-type semiconductor layer 105, and the p-side transparent electrode layer 115 in this order, and is taken out from the surface of the p-side transparent electrode layer 115.

In this embodiment, a plurality of second insulating films 113 are formed on the surface of the p-type semiconductor layer 105. As a result, the light incident on the p-side transparent electrode layer 115 from the semiconductor laminated structure portion 106 is reflected by the side surface of the second insulating film 113, and the side of the p-side transparent electrode layer 115 opposite to the p-type semiconductor layer 105. Since it is taken out from the surface of the light, the light extraction efficiency can be improved.

Further, in this embodiment, since a plurality of convex portions 107 are formed on the surface 102A of the substrate 102, the light extraction efficiency can be improved.
When a plurality of convex portions 107 are formed on the surface 102A of the substrate 102, the n-type semiconductor layer 103 is crystal-grown on the substrate 102 in the region directly above the center of the convex portions 107 in the n-type semiconductor layer 103. When it is made to grow, the growth in the lateral direction is combined, so that a defective portion is likely to occur. Further, in the region directly above the center position between the plurality of two-dimensionally adjacent convex portions 107 in the plurality of convex portions 107 in the n-type semiconductor layer 103, the defects of the substrate 102 are easily inherited, so that the defective portions Is likely to occur. When the defective portion exists in the n-type semiconductor layer 103, the resistance value of the defective portion is low, so that the current is concentrated and flows in the defective portion, and the light emitting element 101 may be destroyed.

In this embodiment, the second insulating film 113 is arranged directly above the center position of each convex portion 107, and the center between the plurality of two-dimensionally adjacent convex portions 107 in the plurality of convex portions 107. The second insulating film 113 is arranged at a position directly above the position. That is, the second insulating film 113 is arranged directly above the portion so that a defective portion in the n-type semiconductor layer 103 is likely to occur. As a result, it becomes difficult for the current from the p-side transparent electrode layer 115 to flow to a place where a defect portion in the n-type semiconductor layer 103 is likely to occur. As a result, it is possible to suppress the concentrated flow of current in the defective portion, so that the reliability of the light emitting element 101 can be improved.

Further, in the vicinity of the interface between the surface layer portion of the p-type semiconductor layer 105 and the second insulating film 113, n-type carriers increase and the p-type carriers are canceled due to damage during film formation of the second insulating film 113. The electrical resistance is increasing. As a result, it is possible to make it more difficult for the current to flow to the location where a defect is likely to occur, so that the reliability of the light emitting element 101 can be further improved.
FIG. 16 is a schematic cross-sectional view of the light emitting element package.

The light emitting element package 151 includes a light emitting element 101, a support substrate 152, and a resin package 153. The support substrate 152 includes an insulating substrate 154 that supports the light emitting element 101, and a pair of electrodes 155 and 156 that are provided so as to be exposed from both ends of the insulating substrate 154.
The light emitting element 101 is supported by the support substrate 152 in such a posture that the surface 102A of the substrate 102 faces upward. Specifically, the back surface 102B of the substrate 102 of the light emitting element 101 is bonded to the insulating substrate 154 via the adhesive layer 157. That is, the light emitting element 101 is face-up mounted. The n-side electrode 109 (n-side pad 111) of the light emitting element 101 and one electrode 155 are connected by a wire 158. The p-side electrode 116 of the light emitting element 101 and the other electrode 156 are connected by a wire 159.

The resin package 153 is a case filled with resin, and is fixed to the support substrate 152 in a state in which the light emitting element 101 is housed (covered) and protected. The resin package 153 has a reflecting portion 160 on the side surface (a portion facing the light emitting element 101) for reflecting the light emitted from the light emitting element 101 and taking it out to the outside. The reflective portion 160 is made of, for example, a resin.

Some of the resins constituting the resin package 153 contain a phosphor and a reflective agent. For example, when the light emitting element 101 emits blue light, the light emitting element package 151 can emit white light by containing a yellow phosphor in the resin. The light emitting element package 151 can be used for lighting equipment such as a light bulb by gathering a large number of them, and can also be used for a backlight of a liquid crystal television or a headlamp of an automobile or the like.

In such a light emitting element package 151, the light emitted by the light emitting layer 104 of the light emitting element 101 immediately passes through the p-type semiconductor layer 105 and is emitted from the surface of the p-side transparent electrode layer 115, or the n-type semiconductor layer 103. Is once reflected by the back surface 102B or the like of the substrate 102, and then emitted from the surface of the p-side transparent electrode layer 115.
FIG. 17 is a schematic cross-sectional view showing another example of the light emitting device package.

The light emitting element package 171 includes a light emitting element 101, a support substrate 172, and a resin package 173. The support substrate 172 is formed on the surface of the insulating substrate 174 in the resin package 173 and the insulating substrate 174 that supports the light emitting element 101, a pair of electrodes 175 and 176 provided so as to be exposed from both ends of the insulating substrate 174. The n-side electrode layer 177 and the p-side electrode layer 178 are provided, and the n-side bonding layer 179 and the p-side bonding layer 180 formed on the surfaces of the n-side electrode layer 177 and the p-side electrode layer 178, respectively. The n-side electrode layer 177 is connected to one of the electrodes 175. The p-side electrode layer 178 is connected to the other electrode 176.

The light emitting element 101 is supported by the support substrate 172 in such a posture that the surface 102A of the substrate 102 faces downward. Specifically, the surface of the n-side electrode 109 (n-side pad 111) of the light emitting element 101 is bonded to the n-side bonding layer 179, and the surface of the p-side electrode 116 of the light emitting element 101 is bonded to the p-side bonding layer 180. ing. That is, the light emitting element 101 is face-down mounted. A reflecting portion 181 for reflecting the light transmitted through the p-side transparent electrode layer 115 of the light emitting element 101 is formed at a required portion on the surface of the insulating substrate 174. The reflective portion 181 is made of, for example, a resin.

The resin package 173 is a case filled with resin, and is fixed to the support substrate 172 in a state in which the light emitting element 101 is housed (covered) and protected. The resin package 173 has a reflecting portion 182 on the side surface (a portion facing the light emitting element 101) for reflecting the light emitted from the light emitting element 101 and taking it out to the outside. The reflective portion 182 is made of, for example, a resin.

In such a light emitting element package 171, the light emitted by the light emitting layer 104 of the light emitting element 101 immediately passes through the n-type semiconductor layer 103 and is emitted from the back surface 102B of the substrate 102, or the p-type semiconductor layer 105 and the p-side. After passing through the transparent electrode layer 115 and being reflected by the reflecting portion 181, it is emitted from the back surface 102B of the substrate 102.
Although the embodiment of the second invention has been described above, the second invention can be implemented in still other embodiments. In the above embodiment, the second insulating film 113 is formed in a circular shape in a plan view, but may be formed in a polygonal shape (quadrangle, hexagon, etc.) in a plan view.

Further, in the above-described embodiment, GaN is exemplified as the nitride semiconductor constituting the n-type semiconductor layer 103 and the p-type semiconductor layer 105, but other nitride semiconductors such as aluminum nitride (AlN) and indium nitride (InN) are exemplified. May be used. Nitride semiconductors can generally be expressed as Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1). Further, the present invention may be applied not only to nitride semiconductors but also to other compound semiconductors such as GaAs and light emitting devices using semiconductor materials (for example, diamond) other than compound semiconductors.

1 Light emitting element 2 Substrate 3 n-type semiconductor layer 4 Light emitting layer 5 p-type semiconductor layer 6 Semiconductor laminated structure part 7 Convex part 8 Drawer part 9 n-side electrode 13 Current injection area 14 p-side transparent electrode 15 p-side electrode 16 Concave 16A No. 1 part 16B 2nd part 17 Insulation film 101 Light emitting element 102 Substrate 103 n-type semiconductor layer 104 Light emitting layer 105 p-type semiconductor layer 106 Semiconductor laminated structure part 107 Convex part 108 Draw-out part 109 n-side electrode 112 1st insulation film (current cutoff) Insulation film)
113 Second insulating film (transparent insulating film)
114 Current injection area 115 p-side transparent electrode 116 p-side electrode

Claims (17)

A substrate with front and back surfaces and
A semiconductor laminated structure portion having an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer laminated on the surface of the substrate in this order, and the p-type semiconductor layer having a surface opposite to the light emitting layer,
A plurality of convex portions formed on the surface of the substrate and covered with the n-type semiconductor layer, and the plurality of convex portions in a plan view include a plurality of convex portions arranged in a staggered pattern.
A plurality of semiconductor laminated structure portions formed so as to enter the semiconductor laminated structure portion in a predetermined current injection region on the surface of the p-type semiconductor layer side, and extend from the p-type semiconductor layer into the semiconductor laminated structure portion. With a recess in
A first insulating film formed on a part of the current injection region on the surface on the p-type semiconductor layer side, and
Formed on the surface of the p-type semiconductor layer, the entire area of the predetermined current injection region on the surface on the p-type semiconductor layer side or almost the entire area of the predetermined current injection region on the surface on the p-type semiconductor layer side. And the p-side transparent electrode layer that covers the first insulating film at the same time,
The saw including a first insulating layer on the surface facing the p-side electrode formed at a position on the surface opposite to the p-type semiconductor layer in the p-side transparent electrode layer,
The plurality of recesses include recesses arranged so as to face the position of the center of gravity of a triangle whose apex is the center of each of the three two-dimensionally adjacent convex portions in the plurality of convex portions in a plan view. Light emitting element. A substrate with front and back surfaces and
A semiconductor laminated structure portion having an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer laminated on the surface of the substrate in this order, and the p-type semiconductor layer having a surface opposite to the light emitting layer,
A plurality of convex portions formed on the surface of the substrate and covered with the n-type semiconductor layer, and the plurality of convex portions in a plan view include a plurality of convex portions arranged in a matrix.
A plurality of semiconductor laminated structure portions formed so as to enter the semiconductor laminated structure portion in a predetermined current injection region on the surface of the p-type semiconductor layer side, and extend from the p-type semiconductor layer into the semiconductor laminated structure portion. With a recess in
A first insulating film formed on a part of the current injection region on the surface on the p-type semiconductor layer side, and
Formed on the surface of the p-type semiconductor layer, the entire area of the predetermined current injection region on the surface on the p-type semiconductor layer side or almost the entire area of the predetermined current injection region on the surface on the p-type semiconductor layer side. And the p-side transparent electrode layer that covers the first insulating film at the same time,
The p-side electrode formed at a position facing the surface of the first insulating layer on the surface of the p-side transparent electrode layer opposite to the p-type semiconductor layer is included.
The plurality of recesses include recesses arranged so as to face the position of the center of gravity of a quadrangle whose apex is the center of each of the four two-dimensionally adjacent convex portions in the plurality of convex portions in a plan view. Light emitting element. The light emitting device according to claim 1 or 2, wherein the first insulating film is made of SiO ₂ . The first insulating film has a circular shape in a plan view.
The light emitting element according to any one of claims 1 to 3, wherein the p-side electrode has a circular shape having a diameter smaller than that of the first insulating film in a plan view. The light emitting element according to claim 4, wherein the first insulating film has a truncated cone shape in which the cross-sectional area decreases from the surface on the p-type semiconductor layer side toward the p-side transparent electrode layer. The plurality of recesses are dug down from the surface of the p-side transparent electrode layer opposite to the conductor laminated structure portion and extend into the semiconductor laminated structure portion, according to any one of claims 1 to 5. The light emitting element described. The plurality of recesses are dug down from the surface of the p-side transparent electrode layer opposite to the conductor laminated structure portion, and penetrate the transparent electrode layer, the p-type semiconductor layer, and the light emitting layer to form the n-type. The light emitting element according to claim 6, which is inserted in the middle of the semiconductor layer in the thickness direction. A second insulating film is formed on the inner surface of the recess.
The light emitting device according to claim 6 or 7, wherein in the surface of the p-side transparent electrode layer, a region where the p-side electrode is not formed and a region where the recess is not formed are exposed. The light emitting element according to any one of claims 1 to 8, wherein the inner surface of the recess is formed on an inclined surface in which the cross-sectional area of the recess gradually decreases toward the bottom surface of the recess. The light emitting element according to any one of claims 1 to 8, wherein the inner surface of the recess is formed on an inclined surface in which the cross-sectional area of the recess gradually increases toward the bottom surface of the recess. A drawing portion that is electrically connected to the n-type semiconductor layer and is drawn out from the semiconductor laminated structure portion in a direction parallel to the substrate.
The light emitting element according to any one of claims 1 to 10, further comprising an n-side electrode formed on the lead-out portion. The light emitting element according to claim 11, wherein the n-side electrode comprises an n-side transparent electrode layer formed on the surface of the n-type semiconductor and an n-side pad formed on the n-side transparent electrode layer. The light emitting device according to claim 12, wherein the n-side transparent electrode layer is made of ITO or ZnO, and the n-side pad is made of Cr or Au. The light emitting device according to any one of claims 1 to 13, wherein the convex portion is made of SiN. The light emitting device according to any one of claims 1 to 14,
A support substrate having a front surface and a back surface and supporting the light emitting element so that the light emitting element is arranged on the front surface.
Including a resin package fixed to the support substrate and arranged so as to surround the light emitting element.
The light emitting element is a light emitting element package in which the surface of the substrate opposite to the n-type semiconductor layer is supported by the support substrate in a posture of facing the surface of the support substrate. The light emitting device according to any one of claims 1 to 14,
A support substrate having a front surface and a back surface and supporting the light emitting element so that the light emitting element is arranged on the front surface.
Including a resin package fixed to the support substrate and arranged so as to surround the light emitting element.
The light emitting element is supported by the support substrate in a posture in which the surface of the p-side transparent electrode layer opposite to the p-type semiconductor layer faces the surface of the support substrate. .. The resin package includes an annular wall that surrounds the light emitting element.
The inner surface of the annular wall is formed on an inclined surface in which the cross-sectional area of the space surrounded by the annular wall increases as the distance from the surface of the support substrate increases.
The light emitting element package according to claim 15 or 16, wherein the inclined surface constitutes a reflecting portion for reflecting the light emitted from the light emitting element and taking it out to the outside.

Images