JP6747871B2 - Imaging device - Google Patents

Description

The present invention relates to an image pickup device, and more particularly to an image pickup device having a solid-state image pickup element driven by a predetermined clock signal.

An endoscope system including an endoscope that captures a subject inside a subject and an image processing device that generates an observation image of the subject captured by the endoscope is widely used in medical fields, industrial fields, and the like. It is used.

As an endoscope in such an endoscope system, conventionally, a solid-state image sensor (for example, a CMOS image sensor) driven by a predetermined clock signal is adopted, and an image signal output from this solid-state image sensor is used. There is known an endoscope in which a cable for transmission is arranged.

On the other hand, in recent years, there has been a strong demand for higher pixel counts in image pickup devices mounted on endoscopes, and along with this, there has been a demand for higher clock speeds. Here, in a cable or the like that transmits the clock, there is a possibility that the radiation characteristic deteriorates as the clock speed increases.

As a measure against the deterioration of the radiation characteristic, that is, as a so-called EMI (Electro Magnetic Interference) suppressing measure, in recent years, an example in which high frequency filtering or spread spectrum clock (SSC) is applied is known.

For example, Japanese Patent Laying-Open No. 2006-095330 (Patent Document 1) discloses a configuration example in which a spread spectrum clock (SSC) for the purpose of suppressing EMI is applied to an endoscope system.

Spread spectrum modulation using the spread spectrum clock (SSC) spreads the power spectrum by dynamically changing the frequency of the clock, thereby suppressing the peak of the radiation intensity, that is, suppressing EMI.

JP 2006-095330 A

Regarding the configuration to which the spread spectrum clock (SSC) described above is applied, there are the following problems. The problem will be described below with reference to the conventional endoscope 102 shown in FIG.

(1) A spread spectrum clock (SSC) module or the like will be added to the endoscope device or the like (for example, the SSC 165 arranged in the connector 122 in FIG. 9), and in this respect, an increase in component cost and board size Will be forced to increase in size.

(2) As described above, the spread spectrum modulation often changes the frequency at several tens of kHz, which increases the input jitter to the image sensor to be supplied (for example, the image sensor 121 shown in FIG. 9). Or, there is a possibility that unnecessary phase noise will increase. Therefore, it is necessary to further take measures against phase noise or jitter.

For example, the following measures will be required.
In the conventional spread spectrum modulation, the clock frequency for transmitting the cable (cable 123 shown in FIG. 9) is dynamically changed. Therefore, both the rising edge (Positive edge) and the falling edge (Negative edge) of the clock are displaced (see the clock signal line 71 shown in FIG. 9).

Then, in the solid-state image pickup device (image pickup device 121 shown in FIG. 9) such as a CMOS image sensor, since the AD conversion unit (ADC 153 shown in FIG. 9) installed therein operates at the rising edge (Positive edge) of the clock, the accuracy due to the jitter is increased. There is a risk of deterioration, and it is necessary to take measures against this.

(3) Since the high frequency component is removed by spread spectrum modulation, the slew rate may decrease.

(4) Since there are some predetermined endoscope systems that cannot use the spread spectrum clock SSC due to the video standard, it is necessary to prepare two systems, a clock to which spread spectrum is applied and a clock to which spread spectrum is not applied. There is.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image pickup apparatus capable of suppressing EMI caused by a transmitted clock without affecting the timing design of the image pickup element. ..

An image pickup apparatus according to an aspect of the present invention is an image pickup apparatus including an image pickup element driven in synchronization with one edge of a clock input from the outside, and a first clock generation unit that generates a predetermined first clock. And, without using a delay circuit, by changing the periodic timing of the other edge while fixing the periodic timing of the one edge in the first clock, a modulated clock having a pulse width modulated is generated. A modulation clock generation unit, a modulation clock output unit that outputs the modulation clock generated by the modulation clock generation unit as a second clock, and a cable that has one end connected to the output unit and that transmits the second clock. An imaging device that is connected to the other end of the cable and has a modulation clock input unit that inputs the transmitted second clock, and that is driven based on the second clock input to the modulation clock input unit comprising a device, wherein the image sensor is a one edge of the second clock, only one edge of the periodic timing is fixed is driven synchronously, the modulated clock generating unit, a predetermined A pseudo random number generator for generating a random number is provided, and the duty ratio of the pulse width of the modulated clock is controlled based on the random number generated by the pseudo random number generator.

According to the present invention, it is possible to provide an imaging device capable of suppressing EMI caused by a transmitted clock without affecting the timing design of the imaging element.

FIG. 1 is a diagram showing a configuration of an endoscope system including an endoscope according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the electrical configuration of the endoscope of the first embodiment. FIG. 3 is a block diagram showing a specific configuration of the FPGA in the connector circuit of the endoscope of the first embodiment. FIG. 4 is a timing chart showing an operation at a predetermined point in the FPGA in the connector circuit of the endoscope according to the first embodiment. FIG. 5: is a block diagram which shows the electric constitution of the endoscope of the 2nd Embodiment of this invention. FIG. 6 is a diagram showing an example of a radiation level from a cable in a state in which spread spectrum modulation is turned off in the endoscope of the second embodiment. FIG. 7 is a diagram showing an example of the radiation level from the cable in the state where the spread spectrum modulation is turned on in the endoscope of the second embodiment. FIG. 8: is a block diagram which shows the electric constitution of the endoscope of the 3rd Embodiment of this invention. FIG. 9 is a block diagram showing an example of the electrical configuration of a conventional endoscope.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram showing a configuration of an endoscope system including an image pickup apparatus (endoscope) according to the first embodiment of the present invention, and FIG. 2 is an electrical diagram of the endoscope according to the first embodiment. FIG. 3 is a block diagram showing another configuration.

Note that, in the present embodiment, an endoscope that has a solid-state image pickup element and picks up an image of a subject inside a subject will be described as an example of the image pickup apparatus.

As shown in FIGS. 1 and 2, an endoscope system 1 having an image pickup apparatus (endoscope) according to the first embodiment includes an endoscope 2 for observing and imaging a subject, and the endoscope. 2, a video processor 3 which receives the image pickup signal and performs a predetermined image processing, a light source device 4 which supplies illumination light for illuminating a subject, and a monitor device which displays an observation image according to the image pickup signal. 5 and.

The endoscope 2 includes an elongated insertion portion 6 that is inserted into a body cavity of a subject and the like, and an endoscope operation portion 10 that is disposed on the proximal end side of the insertion portion 6 and that is grasped and operated by an operator. , A universal cord 41 having one end provided so as to extend from the side of the endoscope operation unit 10.

The insertion portion 6 includes a hard distal end portion 7 provided on the distal end side, a bendable bending portion 8 provided at the rear end of the distal end portion 7, and a long and flexible bendable portion 8 provided at the rear end of the bending portion 8. And a flexible tube portion 9 having flexibility.

A connector 42 is provided on the proximal end side of the universal cord 41, and the connector 42 is connected to the light source device 4. That is, the base (not shown) that is the connection end of the fluid conduit protruding from the tip of the connector 42 and the light guide base (not shown) that is the supply end of the illumination light are detachable from the light source device 4. It is designed to be connected with.

Further, one end of a connection cable 43 is connected to an electric contact portion provided on the side surface of the connector 42. A signal line for transmitting an image pickup signal from the image pickup device 21 (see FIG. 2) of the endoscope 2 is internally provided in the connection cable 43, and a connector portion at the other end is connected to the video processor 3. It is like this.

The connector 42 includes an FPGA 61, a crystal oscillator (VCXO) 63, a modulated clock signal output unit 64, and a storage unit (not shown) that stores specific ID information unique to the endoscope 2. The connector circuit 22 (see FIG. 2) having the above is provided (the FPGA 61, the crystal oscillator (VCXO) 63, and the modulated clock signal output unit 64 will be described in detail later).

Further, an objective optical system (not shown) including a lens for entering a subject image, and an image pickup device 21 arranged on an image forming surface of the objective optical system are arranged at the tip portion 7 of the insertion portion 6. It is set up.

Further, the endoscope 2 extends from the image pickup device 21, and extends from the image pickup device 21 to the connector 42 (and the internal connector circuit 22) via the insertion portion 6, the operation portion 10 and the universal cord 41. An extended cable 23 is provided.

The electrical configuration of the endoscope 2 of the first embodiment will be described below with reference to FIG.
As described above, the image pickup device 21 is provided at the tip portion 7, but the image pickup device 21 is a solid-state image pickup device configured by the CMOS image sensor in the present embodiment.

As shown in FIG. 2, the image pickup device 21 includes an image pickup unit 51 (in FIG. 2) having photodiodes (PDs) that are a plurality of photoelectric conversion units that photoelectrically convert light according to incident light to generate signal charges. , Imaging Pixel Array).

Further, the image pickup device 21 includes a modulation clock input section 56 connected to the clock signal line 71 in the cable 23, a PLL (phase locked loop) 57 connected to the output end of the modulation clock input section 56, and a cable in the cable 23. A timing generator 58 connected to the control signal line 72.

The modulated clock input unit 56 is an input unit for inputting the modulated clock (second clock described later in detail) generated in the connector circuit 22 and transmitted through the clock signal line 71 in the cable 23.

Further, the PLL 57 is a so-called phase synchronization circuit, which multiplies the modulation clock input from the modulation clock input unit 56 by a predetermined number and supplies it to each unit in the image pickup device 21 other than the image pickup unit 51 described above. ing.

The timing generator 58 receives a control signal (a drive signal such as a vertical synchronizing signal or a horizontal synchronizing signal) transmitted via the control signal line 72 in the cable 23, generates a predetermined timing pulse signal, and outputs the predetermined timing pulse signal. Besides, it is adapted to be supplied to each part in the image pickup device 21. The control signal is transmitted by a so-called I2C (Inter-Integrated Circuit) in this embodiment.

On the other hand, the image pickup device 21 has an AFE (analog front end) connected to the output of the image pickup unit 51. The AFE includes a CDS (Correlation Double Sampling) not shown, an analog amplifier (Analog AMP) 52, an AD converter (ADC) 53, etc., and controls the timing pulse signal from the timing generator 58. Then, the analog image pickup signal from the image pickup unit 51 is converted into a digital signal.

Further, the image pickup device 21 performs a predetermined process on a digital processing unit (Digital Processing) 54 that performs a predetermined process on the digital image pickup signal AD-converted by the AFE, and a parallel image pickup signal output from the digital processing unit 54 in a predetermined serial manner. And a P/S conversion unit 55 for converting into a signal.

A signal obtained by performing parallel/serial conversion in the P/S conversion unit 55 is transmitted as a serial image pickup signal to the FPGA 61 in the image pickup device 22 via the image pickup signal line 73 in the cable 23.

The cable 23 connects the image pickup device 21 and the connector circuit 22 as described above, that is, extends from the image pickup device 21, passes from the image pickup device 21 through the insertion portion 6, the operation portion 10, the universal cord 41, and It extends to the connector circuit 22 provided in the connector 42.

Further, in the cable 23, a clock signal line 71 that connects the modulation clock output unit 64 (described in detail later) in the connector circuit 22 and the modulation clock input unit 56 in the image pickup device 21, the FPGA 61 in the connector circuit 22, and the image pickup. A control signal line 72 connecting the timing generator 58 in the element 21 and an image pickup signal line 73 connecting the S/P converter 62 in the connector circuit 22 and the P/S converter 55 in the image pickup device 21. Install internally.

The clock signal line 71 in the cable 23 transmits the clock signal (modulation clock; second clock in this embodiment) generated in the connector circuit 22, but conventionally, it is caused by the clock signal transmitted in the cable 23. EMI (Electro Magnetic Interference) has been a problem.

The present invention provides an imaging device capable of suppressing EMI due to the clock transmitted through the cable 23 by a unique method.

On the other hand, in the endoscope 2, as described above, the connector circuit 22 is arranged in the connector 42 arranged on the proximal end side of the universal cord 41.

The connector circuit 22 has a function of generating control signals such as a clock signal and a synchronization signal for driving the image pickup device 21 arranged at the distal end portion 7 of the insertion portion, and has an FPGA 61 and a crystal oscillator (VCXO) 63. , A modulated clock signal output unit 64, and a storage unit (not shown) that stores specific ID information unique to the endoscope 2.

The FPGA 61 is configured by a so-called FPGA (Field Programmable Gate Array), receives the operation control from the video processor 3, drives the image pickup device 21, and processes an image pickup signal from the image pickup device 21. It has a function of controlling various circuits in the endoscope 2.

That is, in the present embodiment, as a part of the FPGA 61, a function of generating a modulated clock signal (second clock; CLK3) for driving the image pickup device 21, and a control signal such as various synchronization signals as a master of I2C transmission. A generation function, a video processing function related to a digital image pickup signal input from the image pickup device 21, and the like are formed.

The above-described function of generating the modulated clock signal (second clock; CLK3) in the FPGA 61 will be described later in detail with reference to FIG.

A crystal oscillator VCXO (Voltage-Controlled Crystal Oscillator) 63 (hereinafter, VCXO 63) is a voltage-controlled crystal oscillator and is adapted to generate and output a predetermined first clock CLK1. In this way, the VCXO 63 serves as a first clock generation unit that generates a predetermined first clock.

The modulation clock output unit 64 functions as a modulation clock output unit that receives the modulation clock (second clock CLK3) generated in the FPGA 61 and outputs it to the subsequent stage (imaging device 21) via the clock signal line 71. Fulfill

The S/P conversion unit 62 has a serial/parallel conversion function of converting a serial digital image pickup signal input via the image pickup signal line 73 into a predetermined parallel signal.

<Generation function of modulated clock signal (second clock; CLK3)>
FIG. 3 is a block diagram showing a specific configuration of the FPGA in the connector circuit of the endoscope of the first embodiment, and FIG. 4 is a timing chart showing an operation at a predetermined point in the FPGA.

As shown in FIG. 3, the FPGA 61 has a function of generating a modulated clock signal (second clock; CLK3) as a part of its function, and specifically, a counter unit 81, a pseudo random number generation unit 82, and a modulation unit. A clock generator 83 is formed.

Although only the counter unit 81, the pseudo random number generation unit 82, and the modulation clock generation unit 83 are shown as the functions of the FPGA 61 in FIG. 3, the FPGA 61 has various other functions, for example, various types as described above. A function of generating a control signal such as a synchronization signal, a video processing function of an input digital image pickup signal, and the like are formed.

As shown in FIG. 3, the counter unit 81 is configured to include a PLL (phase locked loop) 91, a multiplexer 92, and a counter 93.

The PLL 91 receives the first clock CLK1 generated in the VCXO 63 and outputs CLK2 obtained by multiplying the first clock by a predetermined number. As shown in FIG. 4, the counter 93 and the multiplexer 92 periodically count a predetermined number of CLK2 (0 to 9) and output the periodic count value as a count signal (CNT).

The pseudo random number generator 82 includes a pseudo random number generator 94 and two multiplexers 95 and 96.

The pseudo random number generator 94 is a pseudo random number generator that generates a predetermined random number, and the random number information generated by the pseudo random number generator 94 is passed through the two-stage multiplexers 95 and 96 to be "0" to "8". A random number signal (SETD) that randomly takes the value of "" is output (see FIG. 4).

The modulated clock generation unit 83 is configured by a multiplexer 97, and the multiplexer 97 compares the value of the count signal (CNT) from the counter unit 81 with the value of the random number signal (SETD) from the pseudo random number generation unit 82. Is input as a selection control signal of the multiplexer.

Specifically, in this embodiment, the count signal (CNT) periodically takes a value of "0" to "9", while the random number signal (SETD) takes a value of "0" to "8". Is taken randomly. Then, the multiplexer 97 is
Count signal (CNT) <= Random number signal (SETD)
When the condition is satisfied, "1" is input to the selection control input terminal, and at this time, the "H" signal is output to the output of the multiplexer 97b.

In the present embodiment, the output signal of the multiplexer 97 is output as the modulation clock (second clock; CLK3) generated in the modulation clock generation unit 83.

Here, in the clock CLK3 generated in the modulated clock generation unit 83, the rising edge (Positive edge) of the clock is fixed periodically every cycle, while the falling edge (Negative edge) is the pseudo random number generation unit. Depending on the random number generated at 82, its periodic timing will change.

That is, in the present embodiment, the duty ratio of the pulse width in CLK3 is controlled based on the random number generated by the pseudo random number generator 82.

This is because the counter 81, the pseudo random number generator 82, and the modulation clock generator 83 in the FPGA 61 generate a modulated clock (second clock; CLK3) whose pulse width is modulated in every cycle from CLK1 which is the first clock. It means that it was created.

In other words, in the present embodiment, in the FPGA 61, the frequency of the clock generated by the VCXO 63, which is the original vibration, is dynamically changed and output, and the dynamically changed clock is output to the cable 23 in the endoscope 2. The power spectrum is diffused by transmitting in the above, and thereby the peak of the radiation intensity is suppressed, that is, EMI is suppressed.

As described above, the FPGA 61 fixes the periodic timing of one edge (the rising edge (Positive edge)) in the first clock while fixing the periodic timing of the other edge (the falling edge (Negative edge)). By acting as a modulation clock generation unit that generates a modulation clock whose pulse width is modulated.

The present embodiment is also characterized in that the above-described pulse width modulation is realized without using a so-called "delay circuit".

Further, in the solid-state image pickup device such as the CMOS image sensor adopted in the present embodiment, for example, the circuit such as the AD conversion unit 53 described above operates at the rising edge (Positive edge) of the clock, and thus the rising edge changes. Then, there is a possibility that accuracy may deteriorate due to jitter.

However, as described above, in the present embodiment, the modulation clock CLK3 generated in the modulation clock generating unit 83 in the FPGA 61 depends on the random number generated in the pseudo random number generating unit 82 for its falling edge (Negative edge). Then, the cyclic timing is changed, but since the rising edge (Positive edge) of the clock is cyclically fixed every cycle, there is no influence on the timing control in the image sensor 21.

As described above, according to the endoscope of the first embodiment, it is possible to provide an image pickup apparatus capable of suppressing the EMI caused by the transmitted clock without affecting the timing design of the image pickup element. You can

<Second Embodiment>
Next, a second embodiment of the present invention will be described.

FIG. 5: is a block diagram which shows the electric constitution of the endoscope of the 2nd Embodiment of this invention. Further, FIG. 6 is a diagram showing an example of the radiation level from the cable in the state where the spread spectrum modulation is turned off in the endoscope of the second embodiment, and FIG. FIG. 4 is a diagram showing an example of the radiation level from the cable in the state where spread spectrum modulation is turned on in the endoscope.

The endoscope of the second embodiment has the same basic configuration as that of the first embodiment, and when transmitting the modulation clock generated in the FPGA 61, the modulation clock inverted together with the modulation clock is transmitted. Is differentially transmitted.

Therefore, only the differences from the first embodiment will be described here, and the description of the common parts will be omitted.

As shown in FIG. 5, also in the endoscope 202 of the second embodiment, an objective optical system (not shown) including a lens that allows a subject image to enter, and an objective optical system at the distal end of the insertion portion. And an image pickup device 221 disposed on the image forming surface of the connector, and a connector circuit 222 is disposed in the connector 42 disposed on the proximal end side of the universal cord.

Further, the endoscope 202 extends from the image pickup device 221, and extends from the image pickup device 221 to the connector 42 (and the internal connector circuit 222) via the insertion portion 6, the operation portion 10 and the universal cord 41. An extended cable 223 is arranged.

The image pickup device 221 is a solid-state image pickup device configured by a CMOS image sensor in the present embodiment as in the first embodiment.

As shown in FIG. 5, the image pickup device 221 has the same image pickup unit 251, analog amplifier unit 252, AD conversion unit 253, digital processing unit 254, P/S conversion unit 255, and modulation clock input as in the first embodiment. It has a unit 256, a PLL 257 and a timing generator 258.

Here, in the second embodiment, the modulation clock input unit 256 is adapted to be connected to the clock signal line 271a that transmits the second clock CLK3 that is the same modulation clock as in the first embodiment. There is.

Further, in the second embodiment, the image pickup device 221 has the terminating resistor 259 connected to the clock signal line 271b that transmits the third clock that is the inverted clock of the second clock CLK3 that is the modulation clock described above. Equipped with.

In the second embodiment, the cable 223 connects the image pickup device 221 and the connector circuit 222 as described above, that is, extends from the image pickup device 221 and extends from the image pickup device 221 to the insertion portion 6, the operation portion 10, It extends through the universal cord 41 to the connector circuit 222 provided in the connector 42.

Further, in the cable 223, in addition to the clock signal line 271a connecting the modulation clock output unit 264 in the connector circuit 222 and the modulation clock input unit 256 in the image pickup device 221, the second clock CLK3 which is the modulation clock is inverted. A clock signal line 271b for transmitting a third clock, which is a clock, is internally provided.

Further, the cable 223 has a control signal line 272 connecting the FPGA 261 of the connector circuit 222 and the timing generator 258 of the image pickup device 221, an S/P converter 262 of the connector circuit 222, and the P/S of the image pickup device 221. An image pickup signal line 273 that connects to the conversion unit 255 is internally provided.

On the other hand, in the endoscope 202 of the present embodiment, as described above, the connector circuit 222 is arranged in the connector 42 arranged on the proximal end side of the universal cord 41.

The connector circuit 222 includes a FPGA 261, a VCXO 263, and an S/P conversion unit 262 having the same configuration as that of the first embodiment, and a modulation clock output unit 264a having the same configuration as that of the first embodiment. Have.
The second embodiment further includes a modulation clock output unit 264b configured by an inverter for generating a third clock which is a clock obtained by inverting the second clock CLK3.

That is, in the second embodiment, the CLK3 (second clock) that is the modulation clock generated in the FPGA 261 and the third clock that is the modulation clock that is the inverted CLK3 are arranged in the same cable 23. A feature is that differential transmission is performed by the provided clock signal line 271a and clock signal line 271b.

Next, the function and effect of the second embodiment will be described.
FIG. 6 is a diagram showing an example of a radiation level from a cable in a state where spread spectrum modulation is turned off in the endoscope of the second embodiment, and FIG. 7 is an endoscope of the second embodiment. FIG. 3 is a diagram showing an example of an emission level from a cable in a state where spread spectrum modulation is turned on in FIG.

As shown in FIG. 6, it is assumed that the spread spectrum modulation is turned off. In this case, since the duty ratio is 50%, the even-numbered harmonics are small, but the odd-numbered components are differentially canceled, but the original power is strong, so it is conceivable that even a small leakage will be a large value.

On the other hand, as shown in FIG. 7, when the spread spectrum modulation is turned on in the second embodiment, the duty ratio is made non-50% as described above, so that the even harmonics are However, since the odd-numbered component can be made smaller than the original power by spread spectrum modulation, the radiation level can be suppressed.

As described above, in the second embodiment, by adjusting the generation levels of the odd-numbered component and the even-numbered component, it is possible to suppress the peak level of the radiation characteristic to be small as a whole.

As described above, the endoscope according to the second embodiment can realize the suppression of the EMI caused by the transmitted clock without affecting the timing design of the image sensor, and further, the radiation can be achieved. The level can be suppressed.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.
FIG. 8: is a block diagram which shows the electric constitution of the endoscope of the 3rd Embodiment of this invention.

The endoscope of the third embodiment has the same basic configuration as that of the second embodiment, but is an endoscope having a plurality of image pickup elements, and the driving of each endoscope is performed. The feature is that EMI in clock transmission is suppressed.

For this purpose, in the third embodiment, the same modulation clock as in the first and second embodiments is supplied to one of the image pickup devices and the inverted clock is supplied to the other image pickup device. The modulated clocks thus generated are supplied, and the modulated clocks and a clock obtained by inverting the modulated clocks are differentially transmitted through the same cable.

Therefore, only the differences from the first and second embodiments will be described here, and the description of common parts will be omitted.

As shown in FIG. 8, also in the endoscope 302 of the third embodiment, an objective optical system (not shown) including a lens that allows a subject image to enter, and an objective optical system at the tip of the insertion portion. The first image pickup device 321 and the second image pickup device 421 arranged on the image forming plane are arranged.

Further, a connector circuit 322 is arranged in the connector 42 arranged on the base end side of the universal cord.

Further, the endoscope 302 extends from the first image pickup device 321 and the second image pickup device 421, and from the first image pickup device 321 and the second image pickup device 421 through the insertion portion 6, the operation portion 10, and the universal cord 41. A cable 323 is provided extending to the connector 42 (and the connector circuit 322 provided therein).

The first image pickup device 321 and the second image pickup device 421 are solid-state image pickup devices configured by a CMOS image sensor in the present embodiment as in the first embodiment.

As shown in FIG. 8, the first image pickup device 321 includes an image pickup unit 351, an analog amplifier unit 352, an AD conversion unit 353, a digital processing unit 354, a P/S conversion unit 355, and a modulation unit similar to those of the first embodiment. It has a clock input unit 356, a PLL 357, and a timing generator 358.

Here, in the third embodiment, the modulation clock input section 356 is connected to the clock signal line 371 that transmits the second clock CLK3 that is the same modulation clock as in the first embodiment. There is.

Further, in the third embodiment, the second image pickup device 421 has the same image pickup unit 451, analog amplifier unit 452, AD conversion unit 453, digital processing unit 454, and P/S conversion unit 455 as in the first embodiment. , A modulation clock input unit 456, a PLL 457, and a timing generator 458.

Here, the second image sensor 421 includes an inverter 459 connected to a clock signal line 471 that transmits a third clock that is a clock obtained by inverting the second clock CLK3 that is the above-described modulation clock.

In the third embodiment, the cable 323 connects the first image pickup device 321 and the second image pickup device 421 to the connector circuit 322 as described above, that is, extends from the first image pickup device 321 and the second image pickup device 421. The first image pickup device 321 and the second image pickup device 421 extend from the first image pickup device 321 and the second image pickup device 421 to the connector circuit 322 inside the connector 42 through the insertion portion 6, the operation portion 10 and the universal cord 41.

Further, in the cable 323, in addition to the clock signal line 371 connecting the modulation clock output section 364 in the connector circuit 322 and the modulation clock input section 356 in the image pickup device 321, the second clock CLK3 which is the modulation clock is inverted. A clock signal line 471 for transmitting the third clock, which is a clock, is provided internally.

Further, the cable 323 has a control signal line 372 connecting the FPGA 361 in the connector circuit 322 and the timing generator 358 in the image pickup device 321, an S/P converter 362 in the connector circuit 322, and the P/S in the image pickup device 321. An image pickup signal line 373 connecting to the conversion unit 355 is internally provided.

In addition, the cable 323 has a control signal line 472 connecting the FPGA 361 in the connector circuit 322 and the timing generator 458 in the image sensor 421, the S/P converter 462 in the connector circuit 322, and the P/S in the image sensor 421. An image pickup signal line 473 connecting to the conversion unit 455 is internally provided.

On the other hand, in the endoscope 302 of the third embodiment, as described above, the connector circuit 322 is arranged in the connector 42 arranged on the proximal end side of the universal cord 41.

The connector circuit 322 includes a FPGA 361, a VCXO 363, and an S/P converter 362, which have the same configuration as the first embodiment, and a modulation clock output unit 364, which has the same configuration as the first embodiment. Have.

Further, in the third embodiment, in addition to the S/P conversion unit 462, a modulation clock output unit 464 composed of an inverter for generating a third clock which is a clock obtained by inverting the second clock CLK3 is provided. ..

That is, in the third embodiment, the CLK3 (second clock) which is the modulation clock generated in the FPGA 361 and the third clock which is the modulation clock obtained by inverting the CLK3 are arranged in the same cable 323. It is characterized in that differential transmission is performed by the provided clock signal line 371 and clock signal line 471.

Next, the function and effect of the third embodiment will be described.
As described above, the endoscope 302 of the third embodiment includes the plurality of (two in the present embodiment) image pickup devices 321, 421, and for each of the image pickup devices 321, 421, Modulated clocks that are inverted from each other are supplied via differential transmission.

Further, as described above, the second image sensor 421 is provided with the inverter 459 so that the modulation clock that has been inverted once is inverted again and output as the fourth clock.

As a result, in the third embodiment, even when the endoscope 302 has a plurality of image pickup devices, the mutually inverted modulated clocks are differentially transmitted to the respective image pickup devices 321 and 421. Similarly to the second embodiment, the peak level of the radiation characteristic can be suppressed to a low level comprehensively, and the respective image pickup devices can be controlled in synchronization with each other.

As described above, according to the endoscope of the third embodiment as well, it is possible to realize the suppression of the EMI caused by the transmitted clock without affecting the timing design of each of the plurality of mounted image pickup devices. The radiation level can be suppressed, and the respective image pickup devices can be controlled in synchronization with each other.

Although the FPGA 61 (261, 361) is provided in the connector circuit 22 in the above-described embodiment, the present invention is not limited to this and may be provided in the video processor 3 connected to the endoscope. ..

Further, in the above-described embodiment, the PLL 91 (see FIG. 3) formed in the FPGA 61 (261, 361) is not limited to this, and the video is connected to a portion other than the FPGA 61 in the connector circuit 22 or to the endoscope. It may be provided in the processor 3.

Further, in the third embodiment described above, the inverter 459 is provided inside the second image sensor 421, but the present invention is not limited to this, and may be provided at the cable 323.

The present invention is not limited to the embodiments described above, and various changes and modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1... Endoscope system 2... Endoscope 3... Video processor 4... Light source 5... Monitor device 21... Imaging device 22... Connector circuit 23... Cable 51... Imaging unit 52... Analog amplifier 53... AD converter 54... Digital Processing unit 56... Modulated clock input unit 57... PLL
58... Timing generator 61... FPGA
63... Crystal oscillator VCXO
64... Modulated clock output unit 71... Clock signal line 72... Control signal line 73... Imaging signal line 81... Counter unit 82... Pseudo-random number generator 83... Modulated clock generator 91... PLL
93... Counter 94... Pseudo random number generator

Claims (5)

An imaging device comprising an imaging device driven in synchronization with one edge of a clock input from the outside,
A first clock generator that generates a predetermined first clock;
A modulation clock that generates a modulation clock having a pulse width modulated by changing the periodic timing of one edge while fixing the periodic timing of one edge in the first clock without using a delay circuit. A generator,
A modulation clock output unit that outputs the modulation clock generated by the modulation clock generation unit as a second clock;
A cable having one end connected to the output unit and transmitting the second clock;
Which is connected to the other end of the cable, transmitted the conjunction with a modulated clock input unit for inputting a second clock, the image pickup device is driven based on the second clock input to the modulator clock input When,
Equipped with
The image pickup device is driven in synchronization with only one edge of the second clock, the one edge having a fixed periodic timing,
The modulation clock generation unit has a pseudo random number generator that generates a predetermined random number, and controls the duty ratio of the pulse width of the modulation clock based on the random number generated by the pseudo random number generator. A characteristic imaging device. The image pickup apparatus according to claim 1 , wherein both the first clock and the second clock have the one edge as a rising edge and the other edge as a falling edge. A second output unit that inverts the modulated clock generated by the modulated clock generation unit and outputs the inverted clock as a third clock;
One end of the cable is connected to the second output section together with the output section, and the second clock output from the output section and the third clock output from the second output section The image pickup apparatus according to claim 1, wherein the image pickup apparatus performs differential transmission. The image pickup device according to claim 3 , wherein the image pickup device includes a terminating resistor that is connected to the other end of the cable and that inputs the third clock. A second image sensor different from the image sensor, which is driven in synchronization with one edge of a clock input from the outside,
The second imaging device has an inverting unit connected to the other end of the cable, which inputs the third clock, inverts the third clock, and outputs the inverted fourth clock, and further, the fourth clock. The image pickup device according to claim 3 , wherein the image pickup device is driven in synchronization with only one of the two edges in which the periodic timing is fixed.

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