JP6744781B2 - Switching regulator and integrated circuit package - Google Patents

Description

The present invention relates to a buck-boost switching regulator and an integrated circuit package that can be used as one component of a buck-boost switching regulator.

In an idling-stop vehicle that restarts the engine many times, battery power continues to be consumed by in-vehicle devices such as AV devices and air conditioners while the engine is temporarily stopped. The battery voltage drop will be more severe than before. By using the step-up/down type switching regulator that holds the output voltage when the input voltage (battery voltage) decreases, the in-vehicle device can be operated normally even when the battery voltage greatly decreases during cranking.

Therefore, the demand for buck-boost switching regulators is increasing in the in-vehicle device market.

Here, the configuration and operation of a general step-up/down type switching regulator will be described. FIG. 23 is a diagram showing the configuration of a general step-up/down type switching regulator.

The step-up/down switching regulator shown in FIG. 23 includes MOS transistors Q11 and Q12 that are step-down switches, an inductor L11, MOS transistors Q13 and Q14 that are step-up switches, an output capacitor C11, resistors R11 to R14, and a control circuit. Section CNT11.

The control unit CNT11 monitors the output voltage V _OUT with the output of the voltage dividing circuit including the resistors R11 and R12, and monitors the battery voltage V _BAT that is the input voltage with the output of the voltage dividing circuit including the resistors R13 and R14. ing.

When the battery voltage V _BAT is higher than the first predetermined value A1, the control unit CNT11 selects the step-down mode (see FIG. 24). In the step-down mode, the control unit CNT11 controls the MOS transistors Q11 and Q12 to be turned on/off according to the output voltage V _OUT , keeps the MOS transistor Q13 always off, and keeps the MOS transistor Q14 always on. As a result, the first switch voltage V _SW1 that is the connection node voltage of the MOS transistors Q11 and Q12 and the second switch voltage V _SW2 that is the connection node voltage of the MOS transistors Q13 and Q14 become as shown in FIG. 25A. ..

When the battery voltage V _BAT is less than or equal to the first predetermined value A1 and greater than the second predetermined value A2, the control unit CNT11 selects the buck-boost mode (see FIG. 24). The buck-boost mode, the control unit CNT11 is a MOS transistor Q11 and Q12 turn on / off controlled according to the output voltage _{V OUT,} on / off control of the MOS transistors Q11 and Q12 in accordance with the output voltage _{V OUT.} As a result, the first switch voltage V _SW1 that is the connection node voltage of the MOS transistors Q11 and Q12 and the second switch voltage V _SW2 that is the connection node voltage of the MOS transistors Q13 and Q14 become as shown in FIG. 25B. ..

When the battery voltage V _BAT is equal to or lower than the second predetermined value A2, the control unit CNT11 selects the boost mode (see FIG. 24). In the boost mode, the control unit CNT11 always turns on the MOS transistor Q11, always turns off the MOS transistor Q12, and turns on/off the MOS transistors Q13 and Q14 according to the output voltage V _OUT . As a result, the first switch voltage V _SW1 which is the connection node voltage of the MOS transistors Q11 and Q12 and the second switch voltage V _SW2 which is the connection node voltage of the MOS transistors Q13 and Q14 are as shown in FIG. 25C. ..

Japanese Patent No. 3556652 (Claim 7, Fig. 11)

In the step-up/step-down mode and step-up mode in which the step-up operation is performed by switching the MOS transistors Q13 and Q14, the transfer function H( A term of T(s) represented by the following equation (1) appears in (s).

T(s) represented by the equation (1) represents a right-half-plane-zero characteristic (a characteristic in which a zero point exists on the right half plane), and the buck-boost switching regulator shown in FIG. The response can be expected only in the lower frequency range than the frequency f expressed by the equation. The following equation (2) is obtained by replacing s=jω=j·2πf in the above equation (1).

As a measure for improving the responsiveness, a measure for increasing the capacity of the output capacitor C11 in the step-up/down type switching regulator shown in FIG. 23 can be considered. In addition, it is possible to consider a measure to change to a configuration in which a step-down switching regulator section is provided after the step-up switching regulator section.

However, the former measure causes a problem that the cost of the output capacitor C11 increases, and the latter measure increases the cost of the reactor because the step-up switching regulator section and the step-down switching regulator section require separate reactors. The problem arises.

Although the DC-DC converter disclosed in Patent Document 1 can solve the above problem, the duty of the first control signal generated by the feedforward control circuit depends on the input voltage. However, there is a problem that correction is difficult if the transfer function of the DC-DC converter changes linearly due to the duty.

Further, when the step-up/down type switching regulator is realized by one integrated circuit package, one step-down switch is provided in the integrated circuit package, and a reactor and a pair of step-up switches are externally attached at the subsequent stage of the integrated circuit package. Become. That is, the number of external parts is increased as compared with the case where the step-down switching regulator is realized by one integrated circuit package.

In order to reduce the number of external parts, a step-down switching regulator is provided without providing a step-up switch, and in order to prevent the input voltage input to the integrated circuit package from decreasing when the battery voltage V _BAT decreases. Measures to increase the capacity of the input capacitor can be considered.

In view of the above situation, the present invention can prevent the appearance of right-half-plane-zero characteristics while suppressing an increase in cost, exhibits a response characteristic similar to a step-down characteristic, and changes output voltage due to input voltage fluctuation. A first object of the present invention is to provide a step-up/down type switching regulator capable of suppressing the above.

In view of the above situation, the present invention can prevent the appearance of right-half-plane-zero characteristics while suppressing an increase in cost, exhibits a response characteristic similar to the step-down characteristic, and reduces the frequency of the step-down control signal. A second object is to provide a step-up/down type switching regulator in which the frequencies of boosting control signals are equal.

In view of the above situation, the present invention can prevent the appearance of right-half-plane-zero characteristics while suppressing an increase in cost, and is a component of a step-up/down type switching regulator that exhibits a response characteristic similar to a step-down characteristic. A third object is to provide an integrated circuit package that can be used and can determine whether or not it is used as one component of a step-up/down type switching regulator.

In view of the above situation, the present invention can prevent the appearance of right-half-plane-zero characteristics while suppressing an increase in cost, and is a component of a step-up/down type switching regulator that exhibits a response characteristic similar to a step-down characteristic. A fourth object is to provide an integrated circuit package that can be used and can support the additional function of the buck-boost switching regulator.

The first to fourth objects are to prevent the appearance of right-half-plane-zero characteristics, and to show a step-up/down type switching regulator or a part of the step-up/down type switching regulator that exhibits response characteristics similar to the step-down characteristics. It is common to provide an integrated circuit package that can be used as. The present invention only needs to be able to solve at least one of the first to fourth objects.

<First technical feature>
Among the switching regulators disclosed in this specification, a switching regulator having the first technical feature is a switching regulator that generates an output voltage from an input voltage, and a first end applies the input voltage. A first switch connected to the end; a second switch having a first end connected to the second end of the first switch and a second end connected to an application end of a predetermined voltage lower than the input voltage; An inductor having a first end connected to a connection node of the first switch and the second switch, a first end connected to a second end of the inductor, and a second end connected to the application end of the predetermined voltage. A third switch, a fourth switch having a first end connected to a connection node of the inductor and the third switch, and a second end connected to a terminal to which the output voltage is applied, and the third switch according to the output voltage. A first control circuit for generating a step-down control signal for complementarily turning on/off the first switch and the second switch; and an on-duty D (0≦D≦1) of the third switch in the buck-boost mode. To a fixed value D′ (0<D′<1) to generate a boosting control signal for complementarily turning on/off the third switch and the fourth switch. The first control circuit includes a ramp voltage generation unit that generates a ramp voltage having a slope according to the input voltage, and generates the step-down control signal according to the ramp voltage (first-first). 1)).

In the switching regulator having the 1-1st configuration described above, the ramp voltage generation unit is configured to generate the ramp voltage having a slope according to the fixed value D′ in the buck-boost mode (configuration 1-2). May be.

In the switching regulator having the 1-1 or 1-2 configuration, the first control circuit may include an error amplifier that generates an error signal according to a difference between a voltage according to the output voltage and a reference voltage; A comparator that compares a ramp voltage with the error signal to generate a reset signal that is a comparison signal, an oscillator that generates a set signal that is a clock signal of a predetermined frequency, and the voltage step-down device according to the set signal and the reset signal. And a timing control circuit that generates a control signal (first to third configurations).

In the switching regulator having the first to third configurations, the comparator is a configuration (first to fourth configuration) that applies an offset according to a current flowing through the inductor to one of the lamp voltage and the error signal. May be.

In the switching regulator having the first to third or fourth configurations, the predetermined frequency does not depend on the input voltage, and the frequency of the lamp voltage is the same as the predetermined frequency (first to fifth). Configuration).

In the switching regulator having the first to fifth configurations, the first control circuit includes a detection unit that detects whether or not an external clock signal is supplied to an external clock signal input terminal, and the detection unit outputs the external signal. When it is detected that a clock signal is supplied to the external clock signal input terminal, the oscillator has a configuration (first to sixth configuration) that varies the predetermined frequency according to the frequency of the external clock signal. May be.

In the switching regulator having any one of the 1-1 to 1-6 configurations, the lamp voltage generation unit charges a current generation unit that generates a current according to the input voltage and an output current of the current generation unit. And a capacitor (1-7th configuration).

In the switching regulator having the 1st-7th configuration, the ramp voltage generating section further includes a charging switch for connecting/disconnecting a current path from the output end of the current generating section to the capacitor (1-8th). Configuration).

In the switching regulator having the 1st-7th or 1-8th configuration, the ramp voltage generation unit includes a reset unit configured to discharge the capacitor and reset a charging voltage of the capacitor (a 1st-9th configuration). ).

Among the switching regulators disclosed in this specification, a switching regulator having the first technical feature is a switching regulator that generates an output voltage from an input voltage, and a first end applies the input voltage. A first switch connected to the end; a second switch having a first end connected to the second end of the first switch and a second end connected to an application end of a predetermined voltage lower than the input voltage; An inductor having a first end connected to a connection node of the first switch and the second switch, a first end connected to a second end of the inductor, and a second end connected to the application end of the predetermined voltage. A third switch, a fourth switch having a first end connected to a connection node of the inductor and the third switch, and a second end connected to a terminal to which the output voltage is applied, and the third switch according to the output voltage. A first control circuit for generating a step-down control signal for complementarily turning on/off the first switch and the second switch; and an on-duty of the third switch in the step-up/down mode, the output voltage and the input voltage. A second control circuit that is set independently of each other to generate a boosting control signal for complementary turning on/off of the third switch and the fourth switch, and the first control circuit A ramp voltage generating section that generates a ramp voltage having a slope according to the input voltage is provided, and the step-down control signal is generated according to the ramp voltage (configuration 1-10).

Among the integrated circuit packages disclosed in the present specification, the integrated circuit package having the first technical feature is provided with a first external pin to which an input voltage is applied and a predetermined voltage lower than the input voltage. A second external pin, a third external pin to which a feedback voltage is applied, a first switch having a first end connected to the first external pin, and a first end connected to a second end of the first switch. A second switch having a second end connected to the second external pin, a fourth external pin connected to a connection node of the first switch and the second switch, and the first switch depending on the feedback voltage. A first control circuit that generates a step-down control signal for complementary turning on/off of the switch and the second switch, and an on-duty D (0≦D≦1) in the buck-boost mode has a fixed value D′(0 <D′<1), a second control circuit that generates a pulse signal, and a fifth external pin that outputs the pulse signal to the outside in the step-up/down mode, and the first control circuit includes A ramp voltage generation unit that generates a ramp voltage having a slope according to the input voltage is provided, and the step-down control signal is generated according to the ramp voltage (first to eleventh configurations).

Among the vehicles disclosed in this specification, a vehicle equipped with the first technical feature supplies power to the switching regulator having any one of the above 1-1 to 1-10 configurations and the switching regulator. And a battery to be supplied (first to twelfth configuration).

<Second technical feature>
Among the switching regulators disclosed in this specification, a switching regulator having the second technical feature is a switching regulator that generates an output voltage from an input voltage, and a first end applies the input voltage. A first switch connected to the end; a second switch having a first end connected to the second end of the first switch and a second end connected to an application end of a predetermined voltage lower than the input voltage; An inductor having a first end connected to a connection node of the first switch and the second switch, a first end connected to a second end of the inductor, and a second end connected to the application end of the predetermined voltage. A third switch, a fourth switch having a first end connected to a connection node of the inductor and the third switch, and a second end connected to a terminal to which the output voltage is applied, and the third switch according to the output voltage. A first control circuit for generating a step-down control signal for complementarily turning on/off the first switch and the second switch; and an on-duty D (0≦D≦1) of the third switch in the buck-boost mode. To a fixed value D′ (0<D′<1) to generate a boosting control signal for complementarily turning on/off the third switch and the fourth switch. The first control circuit and the second control circuit each include a ramp voltage generation unit that generates a ramp voltage having a slope according to an internal power supply voltage, and the first control circuit has a first voltage of the internal power supply voltage. The second control circuit has a second comparator for comparing the second divided voltage of the internal power supply voltage with the lamp voltage; and The first control circuit generates the step-down control signal having the same frequency as the output signal of the first comparator, and the second control circuit sets the output signal of the second comparator as the step-up control signal ( 2-1).

In the switching regulator having the 2-1st configuration, a plurality of the second comparators are provided, and a second divided voltage value of the internal power supply voltage supplied to each of the plurality of second comparators is different (second configuration). -2)).

In the switching regulator having the 2-1st or 2-2nd configuration, the lamp voltage generation unit charges a current generation unit that generates a current according to the internal power supply voltage, and an output current of the current generation unit. A configuration having a capacitor (second configuration) may be used.

In the switching regulator having the 2-3rd configuration, the lamp voltage generating section further includes a charging switch for connecting/disconnecting a current path from the output terminal of the current generating section to the capacitor (2-4). Configuration).

In the switching regulator having the 2-3rd or 2-4th configuration, the ramp voltage generation unit includes a reset unit configured to discharge the capacitor and reset a charging voltage of the capacitor (configuration 2-5). ).

Among the switching regulators disclosed in this specification, a switching regulator having the second technical feature is a switching regulator that generates an output voltage from an input voltage, and a first end applies the input voltage. A first switch connected to the end; a second switch having a first end connected to the second end of the first switch and a second end connected to an application end of a predetermined voltage lower than the input voltage; An inductor having a first end connected to a connection node of the first switch and the second switch, a first end connected to a second end of the inductor, and a second end connected to the application end of the predetermined voltage. A third switch, a fourth switch having a first end connected to a connection node of the inductor and the third switch, and a second end connected to a terminal to which the output voltage is applied, and the third switch according to the output voltage. A first control circuit for generating a step-down control signal for complementarily turning on/off the first switch and the second switch; and an on-duty of the third switch in the step-up/down mode, the output voltage and the input voltage. A second control circuit that is set independently of each other to generate a boosting control signal for complementary turning on/off of the third switch and the fourth switch, and the first control circuit and The second control circuit includes a ramp voltage generation unit that generates a ramp voltage according to an internal power supply voltage, and the first control circuit and the second control circuit generate a ramp voltage having a slope according to the internal power supply voltage. A ramp voltage generating section for generating the ramp voltage, the first control circuit has a first comparator for comparing the first divided voltage of the internal power supply voltage with the ramp voltage, and the second control circuit has the internal voltage. A second comparator that compares a second voltage division of the power supply voltage with the ramp voltage, and the first control circuit generates the step-down control signal having the same frequency as the output signal of the first comparator; The second control circuit is configured to use the output signal of the second comparator as the boosting control signal (second configuration).

Among the integrated circuit packages disclosed in the present specification, the integrated circuit package having the second technical feature includes a first external pin to which an input voltage is applied and a predetermined voltage lower than the input voltage. A second external pin, a third external pin to which a feedback voltage is applied, a first switch having a first end connected to the first external pin, and a first end connected to a second end of the first switch. A second switch having a second end connected to the second external pin, a fourth external pin connected to a connection node of the first switch and the second switch, and the first switch depending on the feedback voltage. A first control circuit that generates a step-down control signal for complementary turning on/off of the switch and the second switch, and an on-duty D (0≦D≦1) in the buck-boost mode has a fixed value D′(0 <D′<1), a second control circuit that generates a pulse signal, and a fifth external pin that outputs the pulse signal to the outside in the step-up/step-down mode. The second control circuit includes a ramp voltage generation unit that generates a ramp voltage having a slope according to an internal power supply voltage, and the first control circuit divides the first divided voltage of the internal power supply voltage and the ramp voltage. The second control circuit has a first comparator for comparing, the second control circuit has a second comparator for comparing the second divided voltage of the internal power supply voltage with the ramp voltage, and the first control circuit has the first comparator. The second control circuit is configured to generate the step-down control signal having the same frequency as the output signal of the comparator, and the second control circuit uses the output signal of the second comparator as the pulse signal (second to seventh configurations).

Among the vehicles disclosed in this specification, a vehicle having the second technical feature supplies power to the switching regulator having any one of the above 2-1 to 2-7 configurations and the switching regulator. And a battery to be supplied (configuration 2-8).

<Third technical feature>
Among the integrated circuit packages disclosed in the present specification, the integrated circuit package having the third technical feature is provided with a first external pin to which an input voltage is applied and a predetermined voltage lower than the input voltage. A second external pin, a third external pin to which a feedback voltage is applied, a first switch having a first end connected to the first external pin, and a first end connected to a second end of the first switch. A second switch having a second end connected to the second external pin, a fourth external pin connected to a connection node of the first switch and the second switch, and the first switch depending on the feedback voltage. A first control circuit that generates a step-down control signal for complementary turning on/off of the switch and the second switch, and an on-duty D (0≦D≦1) in the buck-boost mode has a fixed value D′(0 A second control circuit for generating a pulse signal fixed to <D'<1), a fifth external pin for outputting the pulse signal to the outside in the step-up/down mode, and an external connected to the fifth external pin. And a determination unit that determines whether or not the external component is the third switch based on the impedance determination result.

In the integrated circuit package having the above 3-1th configuration, when the integrated circuit package is activated, the determination unit determines whether the external component is the third switch, and the determination unit finishes the determination. After that, the first control circuit may start generating the step-down control signal (third-second configuration).

In the integrated circuit package having the 3-1st or 3-2nd configuration, the second control circuit operates when the determination unit determines that the external component is the third switch, and the external component is The configuration may not operate when the determination unit determines that is not the third switch (third configuration).

In the integrated circuit package having the third to third configurations, the determination unit determines whether the fifth external pin is pulled up, and the second control circuit pulls up the fifth external pin. If the determination unit determines that the external component is not the third switch, the configuration operates exceptionally even though the determination unit determines that the external switch is not the third switch (configuration 3-4). It may be.

In the integrated circuit package having any one of the third to third aspects, when the determination unit determines that the external component is the third switch when the integrated circuit package is started, When the input voltage is less than the first threshold, the operation of the first control circuit is prohibited, and when the input voltage is less than the second threshold that is greater than the first threshold, the operation of the second control circuit is prohibited. The configuration (3-5th configuration) may be adopted.

In the integrated circuit package having any one of the above 3-1 to 3-5 configurations, the determination unit is configured to determine whether the external component is the third switch, and the second control circuit. The output level is indefinite, a constant current is supplied to the connection point between the second control circuit and the fifth external pin, and the external component is based on the potential at the connection point between the second control circuit and the fifth external pin. The configuration (third-sixth configuration) for determining the impedance may be used.

Among the switching regulators disclosed in this specification, a switching regulator provided with a third technical feature is an integrated circuit package having any one of the above 3-1 to 3-6 configurations, and the fourth And a inductor connected to an external pin (third to seventh configuration).

Among the vehicles disclosed in the present specification, a vehicle having the third technical feature has a switching regulator having the above third to seventh configuration, and a battery that supplies power to the switching regulator. It is a configuration (third-third configuration).

Among the integrated circuit packages disclosed in the present specification, the integrated circuit package having the third technical feature is provided with a first external pin to which an input voltage is applied and a predetermined voltage lower than the input voltage. A second external pin, a third external pin to which a feedback voltage is applied, a first switch having a first end connected to the first external pin, and a first end connected to a second end of the first switch. A second switch having a second end connected to the second external pin, a fourth external pin connected to a connection node of the first switch and the second switch, and the first switch depending on the feedback voltage. A first control circuit that generates a step-down control signal for complementary turning on/off of the switch and the second switch, and an on-duty D (0≦D≦1) in the buck-boost mode has a fixed value D′(0 A second control circuit that generates a pulse signal fixed to <D'<1), a fifth external pin that outputs the pulse signal to the outside in the step-up/down mode, a sixth external pin, and control by the pulse signal Additional function unit for realizing at least one additional function of the third switch and the fourth switch by using a signal output from the sixth external pin to the outside or a signal supplied from the outside to the sixth external pin. And (4th configuration).

In the integrated circuit package having the 4-1th configuration, the second external pin may be disposed between the fifth external pin and the sixth external pin (the 4-2nd configuration).

In the integrated circuit package having the 4-1th or 4-2nd configuration, the additional function unit includes a determination unit that determines whether the load of the switching regulator including the integrated circuit package is a light load, A configuration (fourth-third configuration) in which a signal indicating the determination result of the determination unit is output from the sixth external pin to the outside may be used.

Among the switching regulators disclosed in this specification, a switching regulator having a fourth technical feature is an integrated circuit package according to the above 4-3, and a first end of the switching regulator is the fourth external pin. A connected inductor, a third switch having a first end connected to the second end of the inductor and a second end connected to the application end of the predetermined voltage, a first end connected to the inductor and the third switch. A switching switch having a fourth switch connected to a connection node of the switch, wherein when the load of the switching regulator is a light load in the buck-boost mode, a signal indicating a determination result of the determination unit is output. Based on this, the fourth switch may be fixed in the off state (fourth-fourth configuration).

In the integrated circuit package having the 4-1th or 4-2nd configuration, the additional function unit includes the first control circuit and the second control circuit based on a signal supplied from the outside to the sixth external pin. The configuration (4-5th configuration) in which the operation of (4) is stopped may be used.

Among the switching regulators disclosed in this specification, a switching regulator having a fourth technical feature is the integrated circuit package according to the above 4-5, the third switch and the fourth switch. A sub-integrated circuit package for storing the switching regulator, wherein the signal supplied from the outside to the sixth external pin is a temperature information signal of the sub-integrated circuit package (fourth to sixth configuration). May be

In the switching regulator having the fourth to sixth configurations, the sub integrated circuit package has a temperature detection unit, and a drive current of the temperature detection unit is supplied to the sub integrated circuit package from the sixth external pin ( 4th-7th configuration) may be used.

In the switching regulator having the 4th to 7th configuration, the temperature detection unit may be arranged near the fourth switch (4th to 8th configuration).

Among the switching regulators disclosed in this specification, a switching regulator having the fourth technical feature is an integrated circuit package having any one of the above 4-1 to 4-3 and 4-5 configurations. And an inductor connected to the fourth external pin (fourth to ninth configuration).

Among the vehicles disclosed in this specification, a vehicle having the fourth technical feature is a switching regulator according to any one of claims 4 and 6 to 9, and power is supplied to the switching regulator. And a battery to be supplied (configuration 4-10).

Among the switching regulators disclosed in this specification, according to the switching regulator having the first technical feature, it is possible to prevent the appearance of the right-half-plane-zero characteristic while suppressing an increase in cost. Therefore, it is possible to realize a step-up/down type switching regulator that exhibits a response characteristic similar to the step-down characteristic and that can suppress the output voltage fluctuation due to the input voltage fluctuation.

Among the switching regulators disclosed in this specification, according to the switching regulator having the second technical feature, it is possible to prevent the right-half-plane-zero characteristic from appearing while suppressing an increase in cost. Therefore, it is possible to realize a step-up/down type switching regulator that exhibits a response characteristic similar to the step-down characteristic and that the frequency of the step-down control signal is equal to the frequency of the step-up control signal.

Among the integrated circuit packages disclosed in this specification, according to the integrated circuit package having the third technical feature, it is possible to prevent the right-half-plane-zero characteristic from appearing while suppressing an increase in cost. An integrated circuit that can be used as a part of a step-up/down type switching regulator exhibiting a response characteristic similar to that of a step-down characteristic and can be used as a part of a step-up/down type switching regulator. A circuit package can be realized.

Among the integrated circuit packages disclosed in this specification, according to the integrated circuit package having the fourth technical feature, it is possible to prevent the right-half-plane-zero characteristic from appearing while suppressing an increase in cost. In addition, it is possible to realize an integrated circuit package that can be used as a part of a buck-boost switching regulator that exhibits a response characteristic similar to that of a step-down characteristic and that can support the additional functions of the buck-boost switching regulator. it can.

The figure which shows the example of whole structure of 1st Embodiment of a switching regulator. FIG. 3 is a diagram showing a configuration example of a step-down control circuit according to the first embodiment. The figure which shows the rough waveform of the ratio of the input voltage to the output voltage. The figure which shows one structural example of the lamp circuit in 1st Embodiment. Time chart showing an operation example of the lamp circuit in the step-down mode Time chart showing one operation example of the lamp circuit in the step-down mode and the step-up/step-down mode The figure which shows the other structural example of the lamp circuit in 1st Embodiment. The figure which shows the modification of the comparator in 1st Embodiment. The figure which shows the whole structural example of 2nd Embodiment of a switching regulator. The figure which shows the example of 1 structure of the step-down control circuit in 2nd Embodiment. The figure which shows the example of 1 structure of the lamp circuit and oscillator in 2nd Embodiment. The figure which shows the other structural example of the lamp circuit and oscillator in 2nd Embodiment. The figure which shows the structure of the fixed duty circuit and oscillator in 3rd Embodiment. Time chart showing operation of fixed duty circuit and oscillator shown in FIG. The figure which shows the example of whole structure of 4th Embodiment of a switching regulator. Diagram showing the overall configuration of a step-down switching regulator The figure which shows one structural example of the decision circuit The figure which shows the whole structural example of 5th Embodiment of a switching regulator. The figure which shows the example of 1 structure of an additional function part and a signal processing part. The figure which shows the other structural example of an additional function part and a signal processing part. The figure which shows the example of arrangement|positioning of the external pin in 5th Embodiment. Exterior view showing an example of the configuration of a vehicle equipped with in-vehicle equipment Diagram showing the configuration of a general buck-boost switching regulator Diagram showing the schematic waveform of the battery voltage Diagram showing the schematic waveform of each switch voltage in step-down mode The figure which shows the outline waveform of each switch voltage in the buck-boost mode. The figure which shows the outline waveform of each switch voltage in the boost mode.

<Overall configuration (first embodiment)>
FIG. 1 is a diagram showing an example of the overall configuration of a first embodiment of a switching regulator. A switching regulator 101 shown in FIG. 1 is a step-up/down type switching regulator, and includes a step-down control circuit 1, MOS transistors Q1 to Q4, an inductor L1, an output capacitor C1, an output resistor R0, a voltage dividing resistor R1 and The R2, the AND gate 2, the fixed duty circuit 3, and the NOT gate 4 are provided. The main integrated circuit package MP1 has external pins P1 to P5, and stores the MOS transistors Q1 to Q2, the step-down control circuit 1, the AND gate 2, and the fixed duty circuit 3. The sub integrated circuit package SP1 has external pins P11 to P14 and stores the MOS transistors Q3 to Q4 and the NOT gate 4.

The MOS transistor Q1 is an N-channel MOS transistor, and is an example of a switch for connecting/disconnecting a current path from the external pin P1 to which the input voltage V _IN is applied to the external pin P4 to which one end of the inductor L1 is connected. Is. The drain of the MOS transistor Q1 is connected to the external pin P1. The source of the MOS transistor Q1 is connected to the external pin P4 and the drain of the MOS transistor Q2.

The MOS transistor Q2 is an N-channel type MOS transistor and is an example of a switch for connecting/disconnecting a current path from the grounded external pin P2 to the external pin P4. The drain of the MOS transistor Q2 is connected to the external pin P4 and the source of the MOS transistor Q1 as described above. The source of the MOS transistor Q2 is connected to the external pin P2. A diode may be used instead of the MOS transistor Q2.

The MOS transistor Q3 is an N-channel MOS transistor, and is an example of a switch for connecting/disconnecting the current path from the external pin P11 to the external pin P14. The drain of the MOS transistor Q3 is connected to the external pin P4 via the external pin 11 and the inductor L1. The source of the MOS transistor Q3 is connected to the external pin P14. The external pin P14 is grounded.

The MOS transistor Q4 is an N-channel MOS transistor, and is an example of a switch for connecting/disconnecting the current path from the external pin 11a to the external pin P12. The drain of the MOS transistor Q4 is connected to the external pin P11 and the drain of the MOS transistor Q3. The source of the MOS transistor Q4 is connected to the external pin P12. The external pin P12 is connected to one end of the output capacitor C1 and the external pin P3. The other end of the output capacitor C1 is grounded. A diode may be used instead of the MOS transistor Q4.

The output capacitor C1 is a smoothing capacitor for reducing the ripple of the output voltage V _OUT . Further, the output voltage V _OUT is phase-compensated by the phase compensation circuit configured by the output capacitor C1 and the output resistor R0.

The output voltage V _OUT is supplied to the external pin P3 as a feedback voltage. Dividing resistors R1 and R2 divide the output voltage _{V OUT} min generates a divided feedback voltage _{V FB,} and supplies the divided feedback voltage _{V FB} to the step-down control circuit 1.

The step-down control circuit 1 generates a gate signal G1 of the MOS transistor Q1 and a gate signal G2 of the MOS transistor Q2 for turning on/off the MOS transistors Q1 and Q2 complementarily in accordance with the _divided feedback voltage V _FB , The gate signals G1 and G2 are supplied to the gates of the MOS transistors Q1 and Q2. It is preferable to provide a dead time during which both the MOS transistor Q1 and the MOS transistor Q2 are turned off when the MOS transistor Q1 and the MOS transistor Q2 are switched on/off.

The AND gate 2 outputs a signal S3 which is a logical product of the mode designation signal S1 and the pulse signal S2 whose fixed on-duty is output from the fixed duty circuit 3. The mode designating signal S1 becomes a signal designating a step-down mode when it is at a low level and a signal designating a step-up/down mode when it is at a high level. The switching regulator 101 may have a configuration in which a circuit (not shown) that generates the mode designation signal S1 is incorporated, or the switching regulator 101 may receive the mode designation signal S1 from the outside.

The output signal S3 of the AND gate 2 is supplied to the gate of the MOS transistor Q3 via the external pins P5 and P13, and is logically inverted by the NOT gate 4 and then supplied to the gate of the MOS transistor Q4. It is preferable to use a dead time generation circuit instead of the NOT gate 4 and provide a dead time when both the MOS transistor Q3 and the MOS transistor Q4 are switched on/off.

<Configuration example of step-down control circuit>
FIG. 2 is a diagram showing a configuration example of the step-down control circuit 1. In the example shown in FIG. 2, the step-down control circuit 1 includes an error amplifier 11, a reference voltage source 12, a resistor R3, a capacitor C2, a ramp circuit 13, a comparator 14, an oscillator 15, and a timing control circuit 16. Composed by.

The error amplifier 11 generates an error signal V _C according to the difference between the _divided feedback voltage V _FB and the reference voltage V _REF output from the reference voltage source 3. The error signal V _C is phase-compensated by the phase compensation circuit composed of the resistor R3 and the capacitor C2.

Lamp circuit 13 generates and outputs a ramp voltage V _R of the gradient corresponding to the input voltage V _IN. Further, the ramp circuit 13 has a ramp voltage V _{R having} a slope corresponding to the value of the on-duty output from the fixed duty circuit 3 and the input voltage V _IN when the mode designating signal S1 is at a high level, that is, in the buck-boost mode. Is generated and output.

The comparator 14 compares the phase-compensated error signal V _C and the ramp voltage V _R to generate a reset signal which is a comparison signal.

The oscillator 15 outputs a clock signal of a predetermined frequency to the timing control circuit 16.

The timing control circuit 16 switches the gate signal G1 from low level to high level when the set signal (clock signal output from the oscillator 15) switches from high level to low level, and resets the reset signal from low level to high level. At the time of switching, the gate signal G1 is switched from high level to low level.

<Operation mode>
As an example of switching the operation mode, here, when the ratio of the input voltage V _IN to the output voltage V _OUT is equal to or higher than the threshold value TH, the mode designation signal S1 is set to the low level, and the ratio of the input voltage V _IN to the output voltage V _OUT is the threshold value. A case where the mode designation signal S1 is set to the high level when it is less than TH will be described.

When the ratio of the input voltage V _IN to the output voltage V _OUT is greater than or equal to the threshold value TH, the switching regulator 101 operates in the step-down mode (see FIG. 3). In the step-down mode, the step-down control circuit 1 controls ON/OFF of the MOS transistors Q1 and Q2 according to the _divided feedback voltage V _FB , and the mode specifying signal S1 is at the low level, so that the MOS transistor Q3 is held off. MOS transistor Q4 is held in the ON state.

The transfer characteristic of the entire switching regulator 101 in the step-down mode is expressed by the following equation (3).

On the other hand, when the ratio of the input voltage V _IN to the output voltage V _OUT is less than the threshold value TH, the switching regulator 101 operates in the buck-boost mode (see FIG. 3). In the step-up/down mode, the step-down control circuit 1 controls ON/OFF of the MOS transistors Q1 and Q2 according to the _divided feedback voltage V _FB , and the mode designating signal S1 is at the high level. In the state where 0≦D≦1) is fixed to a fixed value D′ (0<D′<1), the MOS transistors Q3 and Q4 are complementarily turned on/off. In the buck-boost mode, the on-duty of the MOS transistor Q3 is set independently of the output voltage V _OUT and the input voltage V _IN .

The transfer characteristic of the entire switching regulator 101 in the buck-boost mode is represented by the following equation (4).

From the expressions (3) and (4), the transfer characteristic of the entire switching regulator 101 in the buck-boost mode is equal to the product of (1-D′) and the transfer characteristic of the entire switching regulator 101 in the step-down mode. As a result, the response characteristic of the switching regulator 101 in the step-up/down mode becomes similar to the response characteristic of the switching regulator 101 in the step-down mode. Therefore, the transfer function of the switching regulator 101 in the buck-boost mode does not have the right-half-plane-zero characteristic. Therefore, the output capacitor C1 does not need to have a large capacity, and the cost of the output capacitor can be suppressed.

Further, since the switching regulator 101 does not require separate reactors for the step-up switching regulator section and the step-down switching regulator section, the cost of the reactor can be suppressed. Further, in the above-described operation mode switching example, the buck-boost mode and the step-down mode are switched depending on whether the ratio of the input voltage V _IN to the output voltage V _OUT is equal to or greater than the threshold value TH. On the other hand, the general step-up/down type switching regulator shown in FIG. 23 switches between the step-up/down mode or the step-up mode and the step-down mode depending on whether the battery voltage V _BAT is the first predetermined value A1 or less. In the general step-up/down type switching regulator shown in FIG. 23, the problem that the optimum value of the first predetermined value A1 changes depending on the setting of the output voltage V _OUT occurs, whereas in the switching regulator 101, the output voltage Even if the setting of V _OUT changes, the optimum value of the threshold TH does not change, so it is not necessary to change the setting of the threshold TH.

<Example of generating lamp voltage>
FIG. 4 is a diagram showing a configuration example of the lamp circuit 13. In the example shown in FIG. 4, the lamp circuit 13 includes a resistor R4, MOS transistors Q5 to Q9, capacitors C3 and C4, and a charge/discharge control unit (not shown). A resistor R4, a MOS transistor Q5 which is a NDMOS (N-channel Double-diffused MOS) transistor for withstand voltage, a MOS transistor Q6 which is a charging switch, and a capacitor C3 are arranged in order from the application terminal of the input voltage V _IN to the ground terminal. Connected in series. A MOS transistor Q7, which is a discharge switch, is connected in parallel with the capacitor C3. Further, the MOS transistor Q8 as a charging switch and the capacitor C4 are sequentially connected in series from the connection node of the MOS transistor Q6 and the capacitor C3 toward the ground terminal. A MOS transistor Q9, which is a discharge switch, is connected in parallel with the capacitor C4.

FIG. 5 is a time chart showing an operation example of the ramp circuit 13 shown in FIG. 4 when the switching regulator 101 is in the step-down mode.

A charge/discharge control unit (not shown) controls the MOS transistors Q6 to Q9 to be turned on/off at a predetermined cycle T which is the same as the cycle of the clock signal output from the oscillator 15 in synchronization with the clock signal output from the oscillator 15. To do. Thus, the period of the lamp voltage V _R becomes a predetermined period T. Lamp voltage V _R is in buck mode is the charging voltage of the capacitor C3 and C4. The charging current of the capacitors C3 and C4 is proportional to the input voltage V _IN .

Therefore, in the ramp circuit 13 shown in FIG. 4, for example, when the input voltage V _IN is doubled (α→2α) in the step-down mode as shown in FIG. 5, the charging currents of the capacitors C3 and C4 are doubled. becomes the inclination of the voltage _{V R} is doubled, resulting on-duty of the MOS transistor Q1 is halved (t / T → 0.5t / T ). The step-up/step-down mode is different from the step-down mode only in that the capacitor to be charged is only the capacitor C3 as described later.

That is, the ramp circuit 13 shown in FIG. 4 feed-forward-controls the slope of the ramp voltage V _R when the input voltage V _IN fluctuates to suppress the fluctuation of the error signal V _C. Accordingly, the switching regulator 101 can suppress the fluctuation of the output voltage V _OUT due to the fluctuation of the input voltage V _IN .

FIG. 6 is a time chart showing an operation example of the ramp circuit 13 shown in FIG. 4 when the switching regulator 101 shifts from the step-down mode to the step-up/step-down mode. Here, a case where the fixed value D′ is 0.5 will be described as an example.

The ramp circuit 13 shown in FIG. 4 holds the MOS transistor Q8 in the off state and the MOS transistor Q9 in the on state in the step-up/down mode, so that only the capacitor C3 is charged. Further, the capacitor C3 is half the combined capacitance of the capacitors C3 and C4. Thus the lamp circuit 13 shown in FIG. 4, for example when moving the buck-boost mode from the buck mode as shown in FIG. 6, twice the slope of the ramp voltage V _R the capacitance of the capacitor to be charged is halved As a result, the on-duty of the MOS transistor Q1 is halved (t/T→0.5t/T). As a result, the product of the reciprocal of the value obtained by subtracting the fixed value D′ from 1 and the on-duty of the MOS transistor Q1 immediately after shifting from the step-down mode to the step-up/step-down mode immediately before the step-up/step-down mode is changed. It becomes equal to the on-duty of the MOS transistor Q1.

That is, the ramp circuit 13 shown in FIG. 4 feed-forward-controls the slope of the ramp voltage V _R when shifting from the step-down mode to the step-up/step-down mode to suppress the fluctuation of the error signal V _C. Further, the lamp circuit shown in FIG. 4 13, an error signal even when the feedforward control the slope of the same ramp voltage V _R in the case of transition from buck mode to buck-boost mode when the transition from buck-boost mode to buck mode V The fluctuation of _C is suppressed. As a result, the switching regulator 101 can suppress fluctuations in the output voltage V _OUT due to switching between the step-down mode and the step-up/step-down mode.

In the above description, the fixed value of the on-duty set by the fixed duty circuit 3 is single, but the fixed value of the on-duty set by the fixed duty circuit 3 may be plural. For example, when 0.5 and 0.3 are set as the fixed value D′ and either 0.5 or 0.3 can be selected as the fixed value D′, the ramp circuit 13 is shown in FIG. 7, for example. It may be configured.

In the ramp circuit 13 shown in FIG. 7, the capacitors to be charged in the step-down mode are capacitors C3 to C5, and the capacitors to be charged in the buck-boost mode when the fixed value D′ is 0.5 are capacitors C3 and C4. , The capacitor to be charged in the buck-boost mode when the fixed value D′ is 0.3 is the capacitor C3. The ratio of the combined capacitance of the capacitors C3 to C5, the combined capacitance of the capacitors C3 and C4, and the capacitance of the capacitor C3 is calculated as follows: combined capacitance of the capacitors C3 to C5: combined capacitance of the capacitors C3 and C4: capacitance of the capacitor C3=1. It may be set to 0:0.5:0.3.

Further, in the above description, the switching regulator 101 is a voltage mode control type switching regulator, but a current detection unit that acquires information on the current flowing through the inductor L1 is provided, and information on the current flowing through the inductor L1 is displayed as shown in FIG. provided input terminals to the comparator 14, the comparator 14 is applied an offset corresponding to the current flowing through the inductor L1 to one of the lamp voltage V _R and a phase compensated error signal V _C configuration, that is, the current-mode control switching regulator You can

Even when the offset is present, the relationship between the on-duty of the slope and MOS transistor Q1 of the ramp voltage V _R is the same as that in the case where the offset is not present. That is, also in the current mode control type switching regulator, the same effect as the voltage mode control type switching regulator can be obtained.

<Overall configuration (second embodiment)>
FIG. 9 is a diagram showing an example of the overall configuration of the second embodiment of the switching regulator. Hereinafter, the switching regulator 102 shown in FIG. 9 will be described, but the description of the same parts as those of the switching regulator 101 described above will be appropriately omitted.

In the switching regulator 102, the main integrated circuit package MP1 has an external pin P6. An external resistor R _C for setting the clock frequency is connected to the external pin P6. In the switching regulator 102, the clock frequency changes according to the resistance value of the external resistor R _C.

<Configuration example of step-down control circuit>
FIG. 10 is a diagram showing a configuration example of the step-down control circuit 1 in the second embodiment. The oscillator 15 generates a clock signal CLK1 having a frequency according to the resistance value of the external resistor R _C. Lamp circuit 13 generates a ramp voltage _{V R} of the same frequency as the frequency of the clock signal CLK1 (clock frequency).

FIG. 11 is a diagram showing a configuration example of the ramp circuit 13 and the oscillator 15 in the second embodiment. In FIG. 11, the same parts as those in FIG. 4 are designated by the same reference numerals.

The voltage dividing circuit 21 generates a divided voltage V _B of the input voltage V _IN . The voltage-current conversion circuit 22 converts the divided voltage V _B of the input voltage V _IN into a current I1 at a conversion rate according to the resistance value of the external resistor R _C.

The current mirror circuit 23 uses the internal power supply voltage V _DD to generate the currents I2 and I3 based on the current I1. For example, a constant voltage generated by using the input voltage V _IN in the main integrated circuit package MP1, the input voltage V _IN itself, a divided voltage of the input voltage V _IN , or the like can be used as the internal power supply voltage V _DD . The current I2 is a current obtained by multiplying the current I1 by a first predetermined value, and the current I3 is a current obtained by multiplying the current I1 by a second predetermined value. The first predetermined multiple and the second predetermined multiple may have the same value or different values.

Only the capacitor C3 to the capacitor C3 and C4 buck-boost mode is charged in the buck mode when the current I2 is charged ramp voltage V _R is generated.

On the other hand, the capacitor 26 is charged by the current I2 when the MOS transistor 24, which is a charging switch, is on, and is discharged when the MOS transistor 25, which is a discharging switch, is on. The MOS transistors 24 and 25 are turned on/off complementarily. The comparator 27 outputs a clock signal CLK1 which is a comparison result of the charging voltage of the capacitor 26 and the divided voltage V _B of the input voltage V _IN . The MOS transistors Q7 and 25 (also the MOS transistor Q9 in the step-up/step-down mode), which are discharging switches, switch from the off state to the on state in synchronization with the falling edge of the clock signal CLK1, and after a certain period of time, return to the off state again.

The slope of the charging voltage of the capacitor 26 is proportional to each of the input voltage V _IN and the resistance value of the external resistor R _C , and the divided voltage V _B of the input voltage V _IN , which is compared with the charging voltage of the capacitor 26 in the comparator 27, is the input voltage. Proportional to V _IN . Therefore, the cycle of the clock signal CLK1 does not change even if the input voltage V _IN changes, and is inversely proportional to the resistance value of the external resistor R _C. On the other hand, the slope of the ramp voltage V _R is proportional to the input voltage V _IN and the resistance value of the external resistor R _C. Therefore, unless the phase-compensated error signal V _C fluctuates, the on-duty time (on-time in one cycle) of the MOS transistor Q1 is inversely proportional to the input voltage V _IN and the resistance value of the external resistor R _C.

That is, when the resistance value of the external resistor R _C changes, only the frequencies of the clock signal CLK1 and the ramp voltage V _R change, and the feedforward control of the slope of the ramp voltage V _R when the input voltage V _IN changes. the contents of inclination of the feed-forward control of the lamp voltage V _R in the case of switching the contents and buck mode and the buck-boost mode is the same as in the first embodiment.

FIG. 12 is a diagram showing another configuration example of the ramp circuit 13 and the oscillator 15 in the second embodiment. In FIG. 12, the same parts as those in FIG. 11 are designated by the same reference numerals.

When using the lamp circuit 13 and the oscillator 15 shown in FIG. 12, an external pin P7 is further provided in the main integrated circuit package MP1. The external pin P7 is an input terminal for the external clock signal CLK2.

The ramp circuit 13 and the oscillator 15 shown in FIG. 12 are different from the ramp circuit 13 and the oscillator 15 shown in FIG. 11 in that the duty conversion circuit 31, the level shifter 32, the low-pass filter 33, the voltage/current conversion circuit 34, the resistor 35, the switch 36, and 37 and a counter 38 are added.

First, the case where the external clock signal CLK2 is supplied to the external pin P7 will be described. The duty conversion circuit 31 converts the external clock signal CLK2 into an on-duty first pulse signal proportional to the frequency of the external clock signal CLK2. The level shifter 32 converts the first pulse signal into a second pulse signal having a peak value level proportional to the divided voltage V _B of the input voltage V _IN . The low pass filter 33 converts the second pulse signal into a DC voltage V _A. As a result, the DC voltage V _A is proportional to the frequency of the external clock signal CLK2 and the input voltage V _IN . The voltage-current conversion circuit 34 converts the DC voltage V _A into a current I1′ at a conversion rate according to the resistance value of the resistor 35.

The counter 38 sets the selection signal SEL1 to a high level after counting a predetermined number by the external clock signal CLK2. The switch 36 selects the voltage-current conversion circuit 34 as the connection destination of the current mirror circuit 23 by the high-level selection signal SEL1. The switch 37 selects the DC voltage _VA as a voltage to be supplied to the non-inverting input terminal of the comparator 27 by the high-level selection signal SEL1. In this case, the frequency of the clock signal CLK1 and the lamp voltage V _R becomes a frequency corresponding to the frequency of the external clock signal CLK2 rather than the resistance of the external resistor R _C. The contents of the feedforward control of the slope of the lamp voltage V _R when the input voltage V _IN fluctuates and the contents of the feedforward control of the slope of the lamp voltage V _R when switching between the step-down mode and the buck-boost mode. 11 is the same as the case of the ramp circuit 13 and the oscillator 15 shown in FIG.

Next, a case where the external clock signal CLK2 is not supplied to the external pin P7 will be described. In this case, since the counter 38 does not count a predetermined number, the selection signal SEL1 goes low. The switch 36 selects the voltage-current conversion circuit 22 as a connection destination of the current mirror circuit 23 by the low-level selection signal SEL1. The switch 37 selects the divided voltage V _B of the input voltage V _IN as the voltage supplied to the non-inverting input terminal of the comparator 27 by the low-level selection signal SEL1. Therefore, when the external clock signal CLK2 is not supplied to the external pin P7, the ramp circuit 13 and the oscillator 15 shown in FIG. 12 are equivalent to the ramp circuit 13 and the oscillator 15 shown in FIG.

In the ramp circuit 13 and the oscillator 15 shown in FIG. 11 or the ramp circuit 13 and the oscillator 15 shown in FIG. 12, the frequency of the clock signal CLK1 may be spread spectrum as a measure against noise. In this case, it is preferable to change the above-mentioned first predetermined multiple and second predetermined multiple, which are the current mirror ratio of the current mirror circuit 23, without changing the ratio of the second predetermined multiple to the first predetermined multiple. As a specific circuit configuration, a plurality of current I2 output transistors are provided, the number of current I2 output transistors actually used to output the current I2 is switched by a switch, a plurality of current I3 output transistors are provided, and a current I2 output transistor is provided. A configuration in which the number of current I3 output transistors actually used to output is switched by a switch can be mentioned.

<Third Embodiment>
The switching regulator according to the third embodiment is an example of the switching regulator 101 according to the first embodiment shown in FIG. In the switching regulator according to the third embodiment, the fixed duty circuit 3 and the oscillator 15 have the configuration shown in FIG.

The fixed duty circuit 3 and the oscillator 15 shown in FIG. 13 include a resistor 41, MOS transistors 42, 43, and 45, a capacitor 44, resistors 46 to 50, comparators 51 to 54, and a charge/discharge control unit (not shown). ) And.

A resistor 41, a MOS transistor 42 that is a NDMOS transistor for withstanding voltage countermeasures, a MOS transistor 43 that is a charging switch, and a capacitor 44 are sequentially connected in series from the application end of the internal power supply voltage V _DD toward the ground end. A MOS transistor 45, which is a discharge switch, is connected in parallel with the capacitor 45. For example, a constant voltage generated by using the input voltage V _IN in the main integrated circuit package MP1, the input voltage V _IN itself, a divided voltage of the input voltage V _IN , or the like can be used as the internal power supply voltage V _DD .

The resistors 46 to 50 divide the internal power supply voltage V _DD to generate the reference voltage V _FREQ and the voltages V1 to V3. The voltage V1 is 0.7 times the reference voltage V _FREQ , the voltage V2 is 0.5 times the reference voltage V _FREQ , and the voltage V3 is 0.3 times the reference voltage V _FREQ .

A charge/discharge control unit (not shown) controls on/off of the MOS transistors Q6 to Q9 in synchronization with the clock signal CLK1 output from the comparator 51.

The comparator 51 compares the reference voltage V _FREQ with the charging voltage V _CRG of the capacitor 44, which is the ramp voltage, and generates the clock signal CLK1. The comparator 52 compares the voltage V1 with the charging voltage V _CRG of the capacitor 44, which is the lamp voltage, and generates the pulse signal S2_0.7 in which the on-duty is fixed at 0.7. The comparator 53 compares the voltage V2 with the charging voltage V _CRG of the capacitor 44, which is the lamp voltage, and generates the pulse signal S2_0.5 whose on-duty is fixed to 0.5. The comparator 54 compares the voltage V3 with the charging voltage V _CRG of the capacitor 44, which is the lamp voltage, and generates the pulse signal S2_0.3 with the on-duty fixed to 0.3.

The clock signal CLK1 which is the output signal of the oscillator 15 and the pulse signals S2_0.7, S2_0.5 and S2_0.3 whose on-duty is fixed which are the output signals of the fixed duty circuit 3 are shown in the time chart of FIG. So that they have the same frequency. As a result, the frequency of the step-down control signal becomes equal to the frequency of the step-up control signal.

In the switching regulator according to the third embodiment, relatively high level noise is generated at the frequency of the step-down control signal and its multiples and at the frequency of the step-up control signal and its multiples. However, since the frequency of the step-down control signal and the frequency of the step-up control signal are equal as described above, it is possible to reduce the noise frequency component of a relatively high level. This makes it easy to suppress the noise level in a specific frequency band (for example, a broadcast frequency band of radio broadcasting when a switching regulator is mounted on a vehicle).

In the fixed duty circuit 3 and the oscillator 15 shown in FIG. 13, the fixed value D′ of the on-duty set by the fixed duty circuit 3 has three types of 0.7, 0.5, and 0.3. This is just an example. The configurations of the voltage dividing circuit formed by the resistors 46 to 50 and the comparators 51 to 54 may be appropriately changed according to the desired fixed value D'.

Further, the fixed duty circuit 3 and the oscillator 15 shown in FIG. 13 are not limited to the main integrated circuit package that feed-forward controls the slope of the lamp voltage V _R when the input voltage V _IN fluctuates, and the boost control signal is turned on. It can be applied to all main integrated circuit packages that can be used for a step-up/down type switching regulator that fixes the duty. The main integrated circuit package to which the fixed duty circuit 3 and the oscillator 15 shown in FIG. 13 are applied is configured to use a slope voltage having a constant slope or a slope voltage reflecting the information of the inductor L1 instead of the ramp voltage V _R , for example. be able to.

Further, in the switching regulator 102 according to the second embodiment having the ramp circuit 13 and the oscillator 15 shown in FIG. 11 or 12, the comparator for inputting the charging voltage of the capacitor C26 shown in FIG. 11 or 12 has the clock signal CLK1. Is only the comparator 27 for generating. In the configuration shown in FIG. 11, similarly to the configuration shown in FIG. 13, a circuit for _dividing the internal power supply voltage V _DD (the divided voltage V _B of the input voltage V _IN ) and a comparator for generating the pulse signal S2 are added. Thus, the same effect as the configuration shown in FIG. 13 can be obtained. In the configuration shown in FIG. 12, as in the configuration shown in FIG. 13, a circuit for dividing each of the internal power supply voltage V _DD (the divided voltage V _B of the input voltage V _IN , the DC voltage _VA ) and the pulse signal S2 are generated. The effect similar to that of the configuration shown in FIG. 13 can be obtained by adding the comparator.

<Fourth Embodiment>
FIG. 15 is a diagram showing an example of the overall configuration of the fourth embodiment of the switching regulator. The switching regulator 103 shown in FIG. 15 has a configuration in which a determination circuit 61 is added to the switching regulator 101 described above.

The main integrated circuit package MP1 may be used as one component of the step-up/step-down switching regulator 103 as shown in FIG. 15, or may be used as one component of the step-down switching regulator 103′ as shown in FIG. ..

The determination circuit 61 is stored in the main integrated circuit package MP1 and is provided between the AND gate 2 and the fifth external pin P5. The determination circuit 61 determines the impedance of the external component connected to the external pin P5 and determines whether the external component is the MOS transistor Q3 based on the impedance determination result.

FIG. 17 is a diagram showing a configuration example of the determination circuit 61. The determination circuit 61 of the configuration example shown in FIG. 17 includes a mask signal generation circuit 63, MOS transistors 64 to 66, a constant current source 67, a resistor 68, comparators 69 and 70, reference voltage sources 71 and 72, And a NOT gate 73.

The mask signal generation circuit 63 starts the activation of the main integrated circuit package MP1, that is, from the time when the main integrated circuit package MP1 is switched from the disabled state to the enabled state until a predetermined time elapses (hereinafter, referred to as a mask period). ), the high-level mask signal M1 is output, and after the mask period elapses, the low-level mask signal M1 is output. After the mask period has elapsed, the step-down control circuit 1 starts generating the gate signal G1 and the gate signal G2.

The MOS transistor 64 is controlled by the inverted signal of the mask signal M1 output from the NOT gate 73. The MOS transistor 64 is turned off during the mask period. As a result, the output level of the output stage inverter (the inverter formed by the MOS transistors 2A and 2B) of the AND gate 2 becomes indefinite during the mask period.

The MOS transistor 65 is provided between the application end of the internal power supply voltage V _DD and the constant current source 67, and is controlled by the mask signal M1. The MOS transistor 65 is turned on during the mask period. As a result, the constant current source 67 supplies a constant current to the connection point N1 between the AND gate 2 and the external pin P5 during the mask period.

The MOS transistor 66 is provided between the connection point N1 and one end of the resistor 68, and is controlled by the mask signal M1. The other end of the resistor 68 is grounded. The MOS transistor 66 is turned on during the mask period. Accordingly, the potential of the connection point N1 in the mask period is determined by the constant current value of the constant current source 67, the resistance value of the resistor 68, and the impedance of the external component connected to the external pin P5.

When the external pin P5 is pulled down by the external resistor 62 (a resistor having a low resistance value) as shown in FIG. 16, a low impedance external component is connected to the external pin P5, so that the resistor 68 is provided during the mask period. The current flowing through it becomes small. Therefore, the potential of the connection point N1 in the mask period is low.

If the external pin P5 is pulled up by an external resistor, a constant current flows through the resistor 68 during the mask period. Therefore, the potential of the connection point N1 becomes high during the mask period.

When the gate of the MOS transistor Q3 is connected to the external pin P5 as shown in FIG. 15, a high-impedance external component is connected to the external pin P5, so that the current flowing through the resistor 68 is large during the mask period. Become. Therefore, the potential of the connection point N1 in the mask period becomes an intermediate potential higher than the low potential and lower than the high potential.

The comparator 69 compares the potential of the connection point N1 with the first reference voltage V _REF1 output from the reference voltage source 71 during the mask period. The first reference voltage V _REF1 is set to a value capable of determining whether or not the potential of the connection point N1 is the above-mentioned low potential.

The comparator 70 compares the potential of the connection point N1 with the second reference voltage V _REF2 output from the reference voltage source 72 during the mask period. The second reference voltage V _REF2 is set to a value capable of determining whether or not the potential of the connection point N1 is the high potential.

The output signal J1 of the comparator 69 and the output signal J2 of the comparator 70 are signals indicating the determination result regarding the external component.

When both the output signal J1 of the comparator 69 and the output signal J2 of the comparator 70 are high level, it indicates that the pull-up resistor is connected. When the output signal J1 of the comparator 69 is high level and the output signal J2 of the comparator 70 is low level, it indicates that the MOS transistor Q3 is connected. When both the output signal J1 of the comparator 69 and the output signal J2 of the comparator 70 are low level, it indicates that the pull-down resistor is connected.

In this embodiment, a pull-down resistor is connected to the external pin P5 when the main integrated circuit package MP1 is used as one component of the step-down switching regulator, and an external pin P5 is operated when the main integrated circuit package MP1 is operated in the test mode. Arrange to connect a pull-up resistor to. Such an agreement may be specified in a specification or a manual of the main integrated circuit package MP1. The test mode may not be provided. When the test mode is not provided, the comparator 70 and the reference voltage source 72 are unnecessary.

There is no particular limitation on how to use the determination result of the determination circuit 61, but for example, the following usage forms are possible.

When both the output signal J1 of the comparator 69 and the output signal J2 of the comparator 70 are low level, the power supply to the AND gate 2 and the fixed duty circuit 3 is stopped. As a result, it is possible to save power when the main integrated circuit package MP1 is used as one component of the step-down switching regulator.

On the other hand, when the output signal J1 of the comparator 69 and the output signal J2 of the comparator 70 are both high level, or when the output signal J1 of the comparator 69 is high level and the output signal J2 of the comparator 70 is low level, The power supply to the AND gate 2 and the fixed duty circuit 3 is not stopped.

When the output signal J1 of the comparator 69 is high level and the output signal J2 of the comparator 70 is low level, the step-down control is performed when the input voltage V _IN is less than the first threshold value when the main integrated circuit package MP1 is started. The operation of the circuit 1 may be prohibited, and the operations of the AND gate 2 and the fixed duty circuit 3 may be prohibited when the input voltage V _IN is greater than the first threshold and less than the second threshold.

Since the output capacitor C1 is not charged when the main integrated circuit package MP1 is activated, the output current of the step-up/down type switching regulator may become excessive when the main integrated circuit package MP1 is activated in the step-up/down mode. For this reason, when the main integrated circuit package MP1 is used as one component of the step-up/down type switching regulator, the operation prohibition of the step-down control circuit 1, the AND gate 2, and the fixed duty circuit 3 described above is executed to perform main operation in the step-down mode. It is desirable to activate the integrated circuit package MP1.

The determination circuit 61 shown in FIG. 15 is not limited to the main integrated circuit package that feed-forward controls the slope of the lamp voltage V _R when the input voltage V _IN fluctuates, and fixes the on-duty of the boosting control signal. It can be applied to all main integrated circuit packages that can be used in a step-up/down type switching regulator. The main integrated circuit package for the application of the decision circuit 61 shown in FIG. 15 can be configured to use a slope voltage reflecting the information of the slope voltage or inductor L1 having a constant slope in place of example the lamp voltage V _R.

<Fifth Embodiment>
FIG. 18 is a diagram showing an example of the overall configuration of the fifth embodiment of the switching regulator. The switching regulator 104 shown in FIG. 18 has a configuration in which an additional function unit 81, external pins 82 and 83, and a signal processing unit 84 are added to the above-described switching regulator 101.

The additional function part 81 and the external pin 82 are provided in the main integrated circuit package MP1. The additional function unit 81 and the external pin 82 are connected to each other in the main integrated circuit package MP1.

The external pin 83 and the signal processing unit 84 are provided in the sub integrated circuit package SP1. The external pin 83 and the signal processing unit 84 are connected to each other in the sub integrated circuit package SP1.

In the switching regulator 104, the external pin 82 and the external pin 83 are connected. The additional function unit 81 implements the additional function using a signal output from the external pin 82 to the signal processing unit 84 or a signal supplied from the signal processing unit 84 to the external pin 82.

FIG. 19 is a diagram showing a configuration example of the additional function unit 81 and the signal processing unit 84. In the configuration example shown in FIG. 19, the additional function unit 81 includes a light load mode control unit 81A and a switch 81B, and the signal processing unit 84 includes a NOT gate 84A and an AND gate 84B.

The light load mode control unit 81A has a reverse current detection unit that detects a reverse current (current flowing from the external pin P4 to the external pin P2) flowing in the MOS transistor Q2. As the reverse current detector, for example, a comparator in which the first input terminal is connected to the source of the MOS transistor Q2 and the second input terminal is connected to the drain of the MOS transistor Q2 can be used.

When the reverse current flowing through the MOS transistor Q2 is detected, the light load mode control unit 81A determines that the light load mode is set.

When the light load mode control unit 81A determines that the light load mode is set, the light load mode control unit 81A controls the step-down control circuit 1 to stop the switching operation of the MOS transistors Q1 and Q2 and turn off both the MOS transistors Q1 and Q2. ..

Further, when the light load mode control unit 81A determines that the light load mode is set, the light load mode control unit 81A controls the switch 81B so that the switch 81B selects the ground potential, and sets the external pin P5 to the low level. As a result, the MOS transistor Q3 is turned off.

Further, when the light load mode control unit 81A determines that the light load mode is set, the light load mode control unit 81A sets the control signal S4 to be sent to the external pin 82 to the high level. In this case, the signal supplied to the gate of the MOS transistor Q4 by the NOT gate 84A and the AND gate 84 becomes low level, and the MOS transistor Q4 is turned off.

Only the signal S3 can turn on/off the MOS transistors Q3 and Q4 complementarily, but by introducing the control signal S4, all the MOS transistors Q1 to Q4 can be turned off in the light load mode as described above. Thereby, power saving in the light load mode can be achieved. When the output voltage V _OUT becomes smaller than a predetermined value when all the MOS transistors Q1 to Q4 are turned off by the control of the light load mode control unit 81A, the light load mode control unit 81A determines that the light load mode is in the light load mode. The control opposite to the case of the judgment is performed and the control in the light load mode is released.

If the external pin P5 is set to a low level in the light load mode without introducing the control signal S4, the MOS transistors Q1 to Q3 can be turned off, but the MOS transistor Q4 will be turned on. In the mode, there arises a problem that the current flows backward through the route of the output voltage V _OUT application terminal→MOS transistor Q4→MOS transistor Q1 body diode→input voltage V _IN application terminal.

Further, the control signal S4 becomes low level when not in the light load mode. Therefore, when the function of turning off all the MOS transistors Q1 to Q4 in the light load mode is not used, the external pins 82 and 83 may be grounded.

FIG. 20 is a diagram showing another configuration example of the additional function unit 81 and the signal processing unit 84. In the configuration example shown in FIG. 20, the additional function unit 81 is configured by a constant current source 81B, a comparator 81C, and a reference voltage source 81D, and the signal processing unit 84 is configured by a bipolar transistor 84C.

The constant current output from the constant current source 81B is supplied to the bipolar transistor 84C via the external pins 82 and 83. Since the collector and base of the npn type bipolar transistor 84C are connected to the external pin 82 and the emitter of the bipolar transistor 84C is grounded, the base-emitter voltage of the bipolar transistor 84C is applied to the external pins 82 and 83.

The base-emitter voltage of the bipolar transistor 84C has a negative temperature characteristic. Therefore, as shown in FIG. 20, if the inverting input terminal of the comparator 81C is connected to the external pin 82 and the reference voltage output from the reference voltage source 81D is supplied to the non-inverting input terminal of the comparator 81C, the bipolar transistor 84C will be generated. The output signal of the comparator 81C becomes high level when in the overheated state, and becomes the low level when the bipolar transistor 84C is not in the overheated state. When the output signal of the comparator 81C is at the high level, the main integrated circuit package MP1 performs the thermal shutdown operation (stop switching control). As a result, the overheated state of the bipolar transistor 84C, that is, the overheated state of the sub integrated circuit package SP1 is eliminated. It is desirable that the bipolar transistor 84C be arranged in the vicinity of the MOS transistor Q4 that is likely to be overheated in the sub integrated circuit package SP1. When the main integrated circuit package MP1 of this embodiment is used as one component of the step-down switching regulator 104 as in the case shown in FIG. 16, the operation of the additional function unit 81 becomes unnecessary. Therefore, for example, the determination circuit 61 mounted in the main integrated circuit package MP1 in the fourth embodiment may be adopted in this embodiment as well, and the determination result of the determination circuit 61 may be used as follows. If the determination result of the determination circuit 61 indicates that the MOS transistor Q3 is connected to the external pin P5, the additional function unit 81 is operated. On the other hand, if the determination result of the determination circuit 61 indicates that the MOS transistor Q3 is not connected to the external pin P5, the operation of the additional function unit 81 is stopped. As a specific circuit configuration example, a switch is provided between the application end of the internal power supply voltage V _DD and the constant current source 81B, and the switch is switched on/off according to the determination result of the determination circuit 61. be able to.

FIG. 21 is a diagram showing an arrangement example of external pins in the fifth embodiment.

In the main integrated circuit package MP1, the grounded external pin P2 is arranged between the external pin P5 and the external pin 82. As a result, the signal output from the external pin 82 or the signal input to the external pin 82 is less likely to be affected by the signal S3 that is a high frequency signal. Therefore, the reliability of the additional function is improved. Similarly, in the main integrated circuit package MP1, the grounded external pin P2 is arranged between the external pin P4 and the external pin 82. As a result, the signal output from the external pin 82 or the signal input to the external pin 82 is less likely to be affected by the switch voltage V _SW1 which is a high frequency voltage. Therefore, the reliability of the additional function is improved.

Although not described in each of the above-described embodiments, a normal gate driver is provided in the preceding stage of the gates of the MOS transistors Q1 to Q4. An external pin 85 is provided in the sub integrated circuit package SP1, and the ground terminal of the gate driver for the MOS transistor Q3 and the ground terminal of the gate driver for the MOS transistor Q4 in the sub integrated circuit package SP1 are connected to the external pin 85. An external pin 86 is provided in the main integrated circuit package MP1, and the ground terminal of the gate driver for the MOS transistor Q1 and the ground terminal of the gate driver for the MOS transistor Q2 in the main integrated circuit package MP1 are connected to the external pin 86.

The external pins 85 and 86 are connected to a common ground, and the grounds of the external pins 85 and 86 and the ground of the external pin P14 are separated. As a result, the ground level of each gate driver is made uniform, and it is possible to prevent the ground potential of each gate driver from varying due to the current flowing through the MOS transistor Q3. Therefore, the reliability of the switching control of the MOS transistors Q1 to Q4 is improved.

The power supply voltage terminal of the MOS transistor Q3 gate driver and the power supply voltage terminal of the MOS transistor Q4 gate driver are connected to the external pin P12 in the sub integrated circuit package SP1. That is, the output voltage V _OUT becomes the power supply voltage of the gate driver for the MOS transistor Q3 and the gate driver for the MOS transistor Q4. As a result, it is not necessary to provide an external pin for inputting a power supply voltage in the sub integrated circuit package SP1, and the number of external pins in the sub integrated circuit package SP1 can be reduced.

The additional function unit 81 shown in FIG. 18 is not limited to the main integrated circuit package that feedforward controls the slope of the lamp voltage V _R when the input voltage V _IN fluctuates, and the on-duty of the boosting control signal is fixed. The present invention can be applied to all main integrated circuit packages that can be used in a step-up/down type switching regulator. The main integrated circuit package to which the additional function unit 81 shown in FIG. 18 is applied can be configured to use a slope voltage having a constant slope or a slope voltage reflecting information of the inductor L1 instead of the ramp voltage V _R , for example. ..

<Use>
Next, an application example of each switching regulator described above will be described. FIG. 22 is an external view showing a configuration example of a vehicle equipped with an in-vehicle device. The vehicle X of the present configuration example includes a battery (not shown), a primary switching regulator (not shown) that receives a DC voltage supplied from the battery, and a secondary switching regulator (that receives a DC voltage output from the primary switching regulator). (Not shown) and in-vehicle devices X11 to X17 are mounted. Each switching regulator described above can be applied to, for example, a primary switching regulator.

Each of the vehicle-mounted devices X11 to X17 uses either the output voltage of the primary switching regulator or the output voltage of the secondary switching regulator as the power supply voltage.

The vehicle-mounted device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, and the like).

The vehicle-mounted device X12 is a lamp control unit for performing lighting control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

The vehicle-mounted device X13 is a transmission control unit that performs control related to the transmission.

The in-vehicle device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power Steering] control, electronic suspension control, etc.).

The vehicle-mounted device X15 is a security control unit that performs drive control such as door lock and crime prevention alarm.

The in-vehicle device X16 is an electronic device incorporated in the vehicle X at the factory shipment stage as a standard equipment item or a manufacturer option item such as a wiper, an electric door mirror, a power window, an electric sunroof, an electric seat, and an air conditioner.

The vehicle-mounted device X17 is an electronic device such as a vehicle-mounted A/V [audio/visual] device, a car navigation system, and an ETC [Electronic Toll Collection System], which is arbitrarily mounted on the vehicle X by the user.

<Points to note>
In addition to the above-described embodiment, the configuration of the present invention can be modified in various ways without departing from the spirit of the invention. For example, although the power saving control and the overheat protection function in the light load mode are given as examples of the additional functions in the fifth embodiment, other functions may be used. As described above, the above-described embodiments are to be considered as illustrative in all points and not restrictive, and the technical scope of the present invention is not the description of the above-described embodiments but the claims. It is to be understood that it is indicated by the scope and includes all modifications that come within the meaning and range of equivalency of the claims.

INDUSTRIAL APPLICABILITY The present invention can be applied to a step-up/down type switching regulator used in all fields (home appliance field, automobile field, industrial machine field, etc.).

1 Step-down control circuit 2 AND gate 3 Fixed duty circuit 4, 73 NOT gate 11 Error amplifier 12, 71, 72, 81D Reference voltage source 13 Lamp circuit 14, 27, 51-54, 69, 70, 81C Comparator 15 Oscillator 16 Timing control circuit 21 Voltage dividing circuit 22, 34 Voltage/current conversion circuit 23 Current mirror circuit 31 Duty conversion circuit 32 Level shifter 33 Low pass filter 36, 37, 81B switch 38 Counter 61 Judgment circuit 63 Mask signal generation circuit 67, 81B Constant current source 81 Additional function unit 81A Light load mode control unit 84 Signal processing unit 84A NOT gate 84B AND gate 84C Bipolar transistor 101 to 104 Switching regulator C1 Output capacitor C2 to C5, 26, 44 Capacitor L1 Inductor MP1 Main integrated circuit package P1 to P7, P11 ~ P14, 82, 83, 85, 86 External pins Q1 to Q11, 24, 25, 42, 43, 45, 64-66, 2A, 2B MOS transistor R0 Output resistance R1, R2 Voltage dividing resistance R3, R4, 35, 41, 46 to 50, 68 Resistance _RC , 62 External resistance SP1 Sub integrated circuit package X Vehicle X11 to X17 In-vehicle equipment

Claims (12)

A switching regulator that generates an output voltage from an input voltage,
A first switch having a first end connected to the input voltage application end;
A second switch having a first end connected to a second end of the first switch and a second end connected to an application end of a predetermined voltage lower than the input voltage;
An inductor having a first end connected to a connection node of the first switch and the second switch;
A third switch having a first end connected to the second end of the inductor and a second end connected to the application end of the predetermined voltage;
A fourth switch having a first end connected to a connection node of the inductor and the third switch, and a second end connected to an application end of the output voltage;
A first control circuit that generates a step-down control signal for turning on/off the first switch and the second switch in a complementary manner according to the output voltage;
In the buck-boost mode, the on-duty D (0≦D≦1) of the third switch is fixed to a fixed value D′ (0<D′<1) to turn on the third switch and the fourth switch complementarily. A second control circuit for generating a boosting control signal for turning on/off,
Have
The first control circuit includes a ramp voltage generation unit that generates a ramp voltage having a slope according to the input voltage, and generates the step-down control signal according to the ramp voltage .
The switching regulator, wherein the ramp voltage generation unit generates the ramp voltage having a slope according to the fixed value D′ in the buck-boost mode . The first control circuit is
An error amplifier that generates an error signal according to the difference between the voltage corresponding to the output voltage and the reference voltage,
A comparator that generates a reset signal that is a comparison signal by comparing the ramp voltage and the error signal;
An oscillator that generates a set signal that is a clock signal of a predetermined frequency,
A timing control circuit for generating the step-down control signal according to the set signal and the reset signal,
The switching regulator according to claim 1 , further comprising: The switching regulator according to claim 2 , wherein the comparator applies an offset according to a current flowing through the inductor to one of the lamp voltage and the error signal. Wherein the predetermined frequency is not dependent on the input voltage,
The switching regulator according to claim 2 or claim 3 frequency of the lamp voltage is equal to the predetermined frequency. The first control circuit has a detection unit that detects whether or not an external clock signal is supplied to the external clock signal input terminal,
When it is detected that the external clock signal is supplied to the external clock signal input terminal by the detection unit, the oscillator according to claim 4 for varying the predetermined frequency according to the frequency of the external clock signal Switching regulator. A switching regulator that generates an output voltage from an input voltage,
A first switch having a first end connected to the input voltage application end;
A second switch having a first end connected to a second end of the first switch and a second end connected to an application end of a predetermined voltage lower than the input voltage;
An inductor having a first end connected to a connection node of the first switch and the second switch;
A third switch having a first end connected to the second end of the inductor and a second end connected to the application end of the predetermined voltage;
A fourth switch having a first end connected to a connection node of the inductor and the third switch, and a second end connected to an application end of the output voltage;
A first control circuit that generates a step-down control signal for turning on/off the first switch and the second switch in a complementary manner according to the output voltage;
In the step-up/down mode, the on-duty D (0≦D≦1) of the third switch is fixed to a fixed value D′ (0<D′<1) to turn on the third switch and the fourth switch complementarily. A second control circuit for generating a boosting control signal for turning on/off,
Have
The first control circuit is
A ramp voltage generation unit that generates a ramp voltage having a slope according to the input voltage,
An error amplifier that generates an error signal according to the difference between the voltage corresponding to the output voltage and the reference voltage,
A comparator that generates a reset signal that is a comparison signal by comparing the ramp voltage and the error signal;
An oscillator that generates a set signal that is a clock signal of a predetermined frequency,
A timing control circuit for generating the step-down control signal according to the set signal and the reset signal, and generating the step-down control signal according to the lamp voltage,
The predetermined frequency does not depend on the input voltage,
The frequency of the lamp voltage is the same as the predetermined frequency,
The first control circuit has a detection unit that detects whether or not an external clock signal is supplied to the external clock signal input terminal,
When it is detected that the external clock signal is supplied to the external clock signal input terminal by the detection unit, wherein the oscillator is characterized by varying the predetermined frequency according to the frequency of the external clock signal Switching regulator. The ramp voltage generation unit,
A current generation unit that generates a current according to the input voltage,
A capacitor for charging the output current of the current generator,
The switching regulator according to claim 1, further comprising: The switching regulator according to claim 7, wherein the lamp voltage generation unit further includes a charging switch that connects/disconnects a current path from the output end of the current generation unit to the capacitor. 9. The switching regulator according to claim 7, wherein the ramp voltage generation unit includes a reset unit that discharges the capacitor and resets a charging voltage of the capacitor. A first external pin to which an input voltage is applied,
A second external pin to which a predetermined voltage lower than the input voltage is applied;
A third external pin to which a feedback voltage based on the output voltage is applied,
A first switch having a first end connected to the first external pin;
A second switch having a first end connected to the second end of the first switch and a second end connected to the second external pin;
A fourth external pin connected to a connection node between the first switch and the second switch;
A first control circuit that generates a step-down control signal for complementarily turning on/off the first switch and the second switch according to the feedback voltage;
A second control circuit that generates a pulse signal in which the on-duty D (0≦D≦1) is fixed to a fixed value D′ (0<D′<1) in the buck-boost mode;
A fifth external pin for outputting the pulse signal to the outside in the buck-boost mode;
Have
The first control circuit includes a ramp voltage generation unit that generates a ramp voltage having a slope according to the input voltage, and generates the step-down control signal according to the ramp voltage .
The buck-boost mode is configured by connecting a first end of an inductor to the fourth pin, and connecting a first end of a third switch and a first end of a fourth switch to a second end of the inductor, In a buck-boost mode of a switching regulator that converts the input voltage to the output voltage,
The integrated circuit package , wherein the pulse signal is a boosting control signal for complementarily turning on/off the third switch and the fourth switch . An integrated circuit package according to claim 10,
The inductor having a first end connected to the fourth external pin;
A switching regulator having: A switching regulator according to any one of claims 1 to 9 and 11 ,
A battery that supplies power to the switching regulator,
A vehicle having:

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