JP6138448B2 - Power supply device and electronic device using the same - Google Patents

Description

  The present invention relates to a current mode control type power supply apparatus.

  FIG. 15 is a diagram illustrating a first conventional example of a power supply device. The power supply apparatus 100 according to the conventional example monitors the high level potential of the switch voltage Vsw appearing at one end of the inductor 103 as the voltage signal VswH, detects the magnitude of the inductor current IL flowing through the upper transistor 101, and displays the detection result. Accordingly, by performing switching control of the upper transistor 101 and the lower transistor 102, the output voltage Vo is generated from the input voltage Vi.

  FIG. 16 is a diagram illustrating a second conventional example of a power supply device. The power supply apparatus 200 of the conventional example monitors the voltage ΔV across the sense resistor 208 to detect the magnitude of the inductor current IL flowing through the sense resistor 208, and the upper transistor 101 and the lower transistor 102 according to the detection result. In this way, the output voltage Vo is generated from the input voltage Vi.

  As an example of the related art related to the above, Patent Document 1 can be cited.

US Patent Application Publication No. 2011/0148379

  However, in the power supply device 100 of the first conventional example, the voltage signal VswH based on the input voltage Vi higher than the power supply voltage Vcc is directly input to the control unit 107 that operates by receiving the supply of the power supply voltage Vcc. Therefore, the level shifter 110 for converting the Vi-reference voltage signal VswH into the Vcc-reference voltage signal VswH ′ is necessary (see FIG. 17).

  On the other hand, in the power supply device 200 of the second conventional example, although the problem of the first conventional example can be solved, the inductor according to the output characteristics of the amplifier 209 provided to amplify the minute voltage ΔV (several mV). There is a problem that the waveform of the current IL and the waveform of the amplified signal DET do not coincide with each other and the stability of the current mode control is lowered (see FIG. 18).

  In view of the above problems found by the inventor of the present application, the present invention provides a power supply device capable of improving the stability of current mode control while suppressing an increase in circuit scale, and an electronic apparatus using the same. The purpose is to provide.

  In order to achieve the above object, a power supply device according to the present invention includes an output stage for switching an inductor current to generate an output voltage from an input voltage, and an error signal corresponding to an error between the output voltage and its target value. An error amplifier circuit for generating the output stage, and a switch control circuit for controlling the driving of the output stage so that the error signal is reduced. The switch control circuit amplifies the detection signal corresponding to the inductor current. An amplifier that generates an amplification detection signal, a ramp signal generation unit that generates a ramp signal having an amplitude larger than the amplification detection signal, and an addition unit that generates a reference signal by adding the amplification detection signal and the ramp signal together A comparator that generates a comparison signal by comparing the error signal and the reference signal, and a switch control signal that is generated according to the clock signal and the comparison signal A logic unit, which is a driver for controlling the driving of the output stage in response to said switch control signal, the arrangement comprising (a first configuration).

  In the power supply device having the first configuration, the ramp signal generation unit may have a configuration (second configuration) in which the rising slope of the ramp signal is increased as the input voltage is higher.

  In the power supply device having the first or second configuration, the ramp signal generation unit may be configured to bias the ramp signal to a signal value higher than zero (third configuration).

  Further, the power supply device having any one of the first to third configurations may be configured to further include an oscillation circuit that generates the clock signal (fourth configuration).

  In the power supply device having the fourth configuration, the oscillation circuit may be configured to variably control the oscillation frequency of the clock signal so as to suppress fluctuations in the output voltage (fifth configuration).

  In the power supply device having any one of the first to fifth configurations, the error amplification circuit includes an operational amplifier having a non-inverting input terminal connected to a reference voltage application terminal, an output voltage application terminal, and the operational amplifier. A configuration including a resistor connected between the inverting input terminal and a capacitor connected between the inverting input terminal and the output terminal of the operational amplifier may be employed (sixth configuration).

  In the power supply device having any one of the first to fifth configurations, the error amplification circuit includes a current amplifier having a non-inverting input terminal connected to a reference voltage application terminal, and the output voltage divided by the current amplifier. A configuration (seventh configuration) including a voltage dividing circuit that outputs to the inverting input terminal of the amplifier and a capacitor connected between the output terminal of the current amplifier and the ground terminal may be employed.

  In the power supply device having any one of the first to seventh configurations, the detection signal may be configured to be detected using a sense resistor or an inductor resistance (eighth configuration).

  In the power supply device having any one of the first to eighth configurations, the output stage may be configured to be a step-down type, a step-up type, or a step-up / step-down type (ninth configuration).

  In the power supply device having any one of the first to ninth configurations, the error amplification circuit and the switch control circuit are integrated in a semiconductor device, and the output stage is externally attached to the semiconductor device. (10th configuration).

  In addition, the power supply device having any one of the first to tenth configurations includes a plurality of sets of the output stage and the switch control circuit, and each set of switch control circuits has an output stage corresponding to each in a different phase. It is preferable to adopt a configuration (eleventh configuration) for performing the drive control.

  In addition, the power supply device having the eleventh configuration further includes a current balancing circuit that corrects the error signal so that the inductor currents flowing through the output stages of the sets coincide with each other to generate an error signal for each set. (Twelfth configuration) is preferable.

  In addition, an electronic apparatus according to the present invention includes a power supply device having any one of the first to twelfth configurations and a load that operates upon receiving an output voltage from the power supply device (a thirteenth configuration). It is said that.

  Note that in the electronic device having the thirteenth configuration, the load may be a calculation processing device or a memory (fourteenth configuration).

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the power supply device which can improve stability of electric current mode control, suppressing an increase in a circuit scale, and an electronic device using the same.

The figure which shows 1st Embodiment of the power supply device X Timing chart for explaining output operation of power supply device X The figure which shows the example of 1 structure of the ramp signal production | generation part 15 and the addition part 16. Timing chart for explaining generation operation of reference signal V12 Timing chart for explaining output stabilization operation at the time of sudden change of input The figure which shows the example of 1 structure of the current amplifier 14 The figure which shows the 1st structural example of the error amplifier circuit 30. The figure which shows the 2nd structural example of the error amplifier circuit 30. The figure which shows the example of 1 structure of the oscillation circuit 40 Timing chart for explaining frequency variable operation during sudden output change The figure which shows the example of 1 structure of the current balance circuit 50 The figure which shows 2nd Embodiment of the power supply device X The figure which shows 3rd Embodiment of the power supply device X External view showing a configuration example of a desktop PC The figure which shows the 1st prior art example of a power supply device The figure which shows the 2nd prior art example of a power supply device Timing chart for explaining the first problem Timing chart for explaining the second problem

<First Embodiment>
FIG. 1 is a diagram illustrating a first embodiment of a power supply device X. The power supply device X of this configuration example includes a semiconductor device 1 and various discrete components attached to the semiconductor device 1 (N-channel MOS [metal oxide semiconductor] field effect transistors N11 and N12, N-channel MOS field effect transistors N21 and N21). N22, inductors L1 and L2, sense resistors R1 and R2, and a capacitor Co).

  The drain of the transistor N11 is connected to the application terminal for the input voltage Vi. The source of the transistor N11 and the drain of the transistor N12 are both connected to the first end of the inductor L1. The source of the transistor N12 is connected to the ground terminal. The gates of the transistors N11 and N12 are connected to the application terminals of the gate signals G11 and G12, respectively. The second end of the inductor L1 is connected to the application end of the output voltage Vo via the sense resistor R1. These discrete components (N11, N12, L1, and R1) form a step-down output stage OS1 that switches the inductor current IL1 to generate the output voltage Vo from the input voltage Vi.

  The drain of the transistor N21 is connected to the application terminal for the input voltage Vi. The source of the transistor N21 and the drain of the transistor N22 are both connected to the first end of the inductor L2. The source of the transistor N22 is connected to the ground terminal. The gates of the transistors N21 and N22 are connected to the application terminals of the gate signals G21 and G22, respectively. The second end of the inductor L2 is connected to the application end of the output voltage Vo via the sense resistor R2. These discrete components (N21, N22, L2, and R2) form a step-down output stage OS2 that switches the inductor current IL2 to generate the output voltage Vo from the input voltage Vi.

  An output smoothing capacitor Co is connected in parallel with the load Z between the application terminal of the output voltage Vo and the ground terminal.

  The semiconductor device 1 is a monolithic semiconductor integrated circuit device (so-called multi-phase type switching regulator IC) in which switch control circuits 10 and 20, an error amplifier circuit 30, and an oscillation circuit 40 are integrated.

  The switch control circuit 10 generates the gate signals G11 and G12 according to the error signal Vcomp generated so that the output voltage Vo and the internal reference voltage (corresponding to the target value) are equal, thereby controlling the drive of the output stage OS1. The circuit block includes a driver 11, an RS flip-flop 12, a comparator 13, a current amplifier (gm amplifier) 14, a ramp signal generation unit 15, and an addition unit 16.

  The driver 11 performs drive control of the output stage OS1 by generating gate signals G11 and G12 according to the switch control signal S12. More specifically, when the switch control signal S12 is at a high level, the driver 11 turns on the upper transistor N11 and turns off the lower transistor N12. When the level is low, the gate signals G11 and G12 are generated so that the upper transistor N11 is turned off and the lower transistor N12 is turned off.

  The RS flip-flop 12 corresponds to a logic unit that generates the switch control signal S12 according to the clock signal CLK1 and the comparison signal S11. More specifically, the RS flip-flop 12 sets the switch control signal S12 to a high level triggered by the rising edge of the clock signal CLK1 input to the set end (S), and is input to the reset end (R). The switch control signal S12 is reset to a low level using the rising edge of the comparison signal S11 as a trigger.

  The comparator 13 compares the error signal Vcomp applied to the inverting input terminal (−) and the reference signal V12 applied to the non-inverting input terminal (+) to generate a comparison signal S11. Therefore, the comparison signal S11 becomes a low level when the reference signal V12 is lower than the error signal Vcomp, and conversely, becomes a high level when the reference signal V12 is higher than the error signal Vcomp.

  The current amplifier 14 amplifies the voltage ΔV1 across the sense resistor R1 (corresponding to a detection signal corresponding to the inductor current IL1) to generate a current signal I1 (corresponding to an amplified detection signal). Thus, if the configuration using the sense resistor R1 as a means for detecting the inductor current IL1, unlike the configuration using the on-resistance of the transistor N11 (FIG. 15), the input voltage Vi and the power supply voltage Vcc Even if they are different, a level shifter is not required.

  The ramp signal generation unit 15 generates a ramp signal V11 having a sawtooth waveform according to the switch control signal S12.

  The adder 16 adds the current signal I1 (more precisely, the voltage signal V10 obtained by performing I / V conversion of the current signal I1) and the ramp signal V11 to generate the reference signal V12.

  The switch control circuit 20 generates the gate signals G21 and G22 according to the error signal Vcomp generated so that the output voltage Vo is equal to the internal reference voltage (corresponding to the target value), thereby controlling the drive of the output stage OS2. The circuit block includes a driver 21, an RS flip-flop 22, a comparator 23, a current amplifier (gm amplifier) 24, a ramp signal generation unit 25, and an addition unit 26.

  The driver 21 performs drive control of the output stage OS2 by generating gate signals G21 and G22 according to the switch control signal S22. More specifically, when the switch control signal S22 is at a high level, the driver 21 reversely switches the switch control signal S22 so that the upper transistor N21 is turned on and the lower transistor N22 is turned off. When the level is low, the gate signals G21 and G22 are generated so that the upper transistor N21 is turned off and the lower transistor N22 is turned off.

  The RS flip-flop 22 corresponds to a logic unit that generates the switch control signal S22 according to the clock signal CLK2 and the comparison signal S21. More specifically, the RS flip-flop 22 sets the switch control signal S22 to a high level triggered by the rising edge of the clock signal CLK2 input to the set end (S), and is input to the reset end (R). The switch control signal S22 is reset to a low level using the rising edge of the comparison signal S21 as a trigger.

  The comparator 23 compares the error signal Vcomp applied to the inverting input terminal (−) and the reference signal V22 applied to the non-inverting input terminal (+) to generate a comparison signal S21. Therefore, the comparison signal S21 is at a low level when the reference signal V22 is lower than the error signal Vcomp, and conversely, is at a high level when the reference signal V22 is higher than the error signal Vcomp.

  The current amplifier 24 amplifies the voltage ΔV2 across the sense resistor R2 (corresponding to a detection signal corresponding to the inductor current IL2) to generate a current signal I2 (corresponding to an amplified detection signal).

  The ramp signal generator 25 generates a ramp signal V21 having a sawtooth waveform in response to the switch control signal S22.

  The adder 26 adds the current signal I2 (more precisely, the voltage signal V20 obtained by performing I / V conversion of the current signal I2) and the ramp signal V21 to generate the reference signal V22.

  The error amplifier circuit 30 generates an error signal Vcomp corresponding to the error between the output voltage Vo and its target value.

  The oscillation circuit 40 generates clock signals CLK1 and CLK2 having different phases. The oscillation circuit 40 has a function of variably controlling the oscillation frequencies of the clock signals CLK1 and CLK2 so as to suppress fluctuations in the output voltage Vo.

  FIG. 2 is a timing chart for explaining the output operation of the power supply device X. In order from the top, the output current Io, the output voltage Vo, the clock signals CLK1 and CLK2, the error signal Vcomp, the reference signal V12 (solid line), and V22. (Broken line) and switch control signals S12 and S22 are depicted.

  The power supply device X of the first embodiment has two sets of output stages OS1 and OS2 and switch control circuits 10 and 20, and the switch control circuits 10 and 20 of each set are different from each other as shown in FIG. The drive control of the output stages OS1 and OS2 corresponding to each is performed by the phase. The output stages OS1 and OS2 of each set are connected in parallel to the load Z, and a desired output voltage Vout is generated from the input voltage Vin by adding the outputs.

  Thus, since the multi-phase type power supply device X can output a large current to the load Z, the load Z (CPU [central processing unit], GPU [graphics processing unit], or a large current consumption) , Memory, etc.).

  In FIG. 2, the oscillation frequency of the clock signals CLK1 and CLK2 is increased by the oscillation circuit 40 when the output voltage Vo suddenly decreases due to the sudden increase in the output current Io. With such a configuration, it is possible to suppress fluctuations in the output voltage Vo.

  FIG. 3 is a diagram illustrating a configuration example of the ramp signal generation unit 15 and the addition unit 16. The ramp signal generation unit 15 of this configuration example includes a charging current generation circuit 151, a capacitor 152, a constant voltage source 153, switches 154 and 155, and an inverter 156.

  The charging current generation circuit 151 is a circuit block that generates the charging current Ia of the capacitor 152, and includes resistors a1 to a3, a constant current source a4, a pnp bipolar transistor a5, an npn bipolar transistor a6, and a P channel type. MOS field effect transistors a7 and a8.

  The resistors a1 and a2 are connected in series between the application terminal of the input voltage Vi and the ground terminal. The emitter of the transistor a5 is connected to the base of the transistor a6. The collector of the transistor a5 is connected to the ground terminal. The base of the transistor a5 is connected to a connection node of the resistors a1 and a2 (an application end of the divided voltage Va (= α × Vi, where α is a voltage dividing ratio)). The constant current source a4 is connected between the application terminal of the power supply voltage Vcc and the base of the transistor a6. The emitter of the transistor a6 is connected to the ground terminal via the resistor a3. The collector of the transistor a6 is connected to the drain of the transistor a7. The sources of the transistors a7 and a8 are both connected to the application terminal for the power supply voltage Vcc. The gates of the transistors a7 and a8 are both connected to the drain of the transistor a7. The drain of the transistor a8 corresponds to the output terminal of the charging current Ia.

  The divided voltage Va generated by the voltage dividing circuit (a1 and a2) is applied to the resistor a3 via the emitter followers (a4 to a6). As a result, a variable current Ib (= Va / Ra3) corresponding to the divided voltage Va (and thus the input voltage Vi) flows through the resistor a3 (resistance value: Ra3). The variable current Ib is mirrored by the current mirror (a7 and a8), thereby generating a charging current Ia (= β × Ib, where β is a mirror ratio). Therefore, the current value of the charging current Ia changes in proportion to the input voltage Vi. In other words, the rising slope of the ramp signal V11 increases as the input voltage Vi increases.

  The capacitor 152 is a capacitive element that is charged by the charging current Ia, and the charging voltage is output as the ramp signal V11 from the first end.

  The constant voltage source 153 (electromotive voltage: VB) is connected between the second end of the capacitor 152 and the ground end.

  The switch 154 is connected between the output terminal of the charging current generation circuit 151 and the first terminal of the capacitor 152, and is turned on / off according to the switch control signal S12. More specifically, the switch 154 is turned on when the switch control signal S12 is at a high level, and is turned off when the switch control signal S12 is at a low level.

  The switch 155 is connected between both ends of the capacitor 152, and is turned on / off according to the inverting switch control signal S12B. More specifically, the switch 155 is turned on when the inverting switch control signal S12B is at a high level, and turned off when the inverting switch control signal S12B is at a low level.

  The inverter 156 logically inverts the switch control signal S12 to generate an inverting switch control signal S12B.

  In addition, the adding unit 16 of this configuration example includes a buffer 161 and a resistor 162. The input end of the buffer 161 is connected to the output end of the ramp signal generation unit 15. The output terminal of the buffer 161 is connected to the output terminal of the current amplifier 14 and the non-inverting input terminal (+) of the comparator 13 through the resistor 162. The first power supply terminal of the buffer 161 is connected to the application terminal for the power supply voltage Vcc. The second power supply terminal of the buffer 161 is connected to the ground terminal.

  The current signal I1 generated by the current amplifier 14 flows into the second power supply terminal of the buffer 161 via the resistor 162. Accordingly, a voltage signal V10 (= I1 × R162) corresponding to the current signal I1 is generated between both ends of the resistor 162 (resistance value: R162), and this voltage signal V10 is added to the ramp signal V11 to be the reference signal V12. Is generated.

  FIG. 4 is a timing chart for explaining the generation operation of the reference signal V12 (addition operation of the voltage signal V10 and the ramp signal V11). In order from the top, the switch control signal S12, the inductor current IL1, the voltage signal V10, the ramp The signal V11 and the reference signal V12 are depicted.

  When the switch control signal S12 is raised to a high level, the inductor current IL1 gradually increases, and the voltage signal V10 also increases accordingly. At this time, in the ramp signal generation unit 15, the switch 154 is turned on and the switch 155 is turned off. As a result, the charging operation of the capacitor 152 by the charging current Ia is started, and the ramp signal V11 starts to rise. Then, in the adder 16, the voltage signal V10 and the ramp signal V11 are added to generate the reference signal V12.

  In the generation operation of the reference signal V12, the amplitude B of the ramp signal V11 is set larger than the amplitude A of the voltage signal V10 so that the ramp signal V11 is more dominant than the voltage signal V10. By adopting such a configuration, stable current mode control can be performed even if the waveform mismatch between the inductor current IL1 and the current signal I1 (and thus the voltage signal V10) occurs due to the output characteristics of the current amplifier 14. It can be realized. In addition, since the ramp signal V11 having a larger amplitude than the voltage signal V10 becomes dominant, it is less susceptible to noise.

  On the other hand, when the reference signal V12 exceeds the error signal Vcomp and the switch control signal S12 falls to the low level, the inductor current IL1 gradually decreases, and the voltage signal V10 also decreases accordingly. At this time, in the ramp signal generation unit 15, the switch 154 is turned off and the switch 155 is turned on. As a result, the capacitor 152 is discharged, and the ramp signal V11 sharply decreases to the predetermined bias value VB. As described above, since the ramp signal V11 is always biased higher than zero, even if the current signal I1 is drawn into the current amplifier 14, the reference signal V12 does not stick to zero. It becomes possible to further improve the stability of the current mode control.

  Note that the configurations of the ramp signal generation unit 25 and the addition unit 26 are the same as those described above, and a duplicate description is omitted.

  FIG. 5 is a timing chart for explaining the stabilization operation of the output voltage Vo when the input voltage Vi is suddenly changed. From the top, the input voltage Vi, the error signal Vcomp, the reference signal V12 (solid line), and V22 (broken line) are shown. ), The switch control signals S12 and S22 and the output voltage Vo are depicted.

  As shown in this figure, the rising slopes of the reference signals V12 and V22 (that is, the rising slopes of the ramp signals V11 and V21) are proportional to the input voltage Vi. Therefore, when the input voltage Vi increases, the reference signals V12 and V22 are increased. Exceeds the error signal Vcomp at an earlier timing. For example, when the input voltage Vi increases, the high level period of the switch control signals S12 and S22 is shortened, and the output voltage Vo can be suppressed low. On the contrary, if the input voltage Vi decreases, the high level period of the switch control signals S12 and S22 becomes longer, and the output voltage Vo is sufficiently increased. In this way, by making the rising slopes of the ramp signals V11 and V21 proportional to the input voltage Vi, it is possible to suppress fluctuations in the output voltage Vo even when a sudden fluctuation in the input voltage Vi occurs. .

  FIG. 6 is a diagram illustrating a configuration example of the current amplifier 14. The current amplifier 14 of this configuration example includes an operational amplifier 141, an N-channel MOS field effect transistor 142, a resistor 143 (resistance value: Rx), and a current mirror 144.

  The non-inverting input terminal (+) of the operational amplifier 141 is connected to the first terminal (inductor L1 side) of the sense resistor R1. The inverting input terminal (−) of the operational amplifier 141 is connected to the source of the transistor 142 and the first terminal of the resistor 143. The second end of the resistor 143 is connected to the second end (the load Z side) of the sense resistor R1. The output terminal of the operational amplifier 141 is connected to the gate of the transistor 142. The drain of the transistor 142 is connected to the input terminal of the current mirror 144. The output end of the current mirror 144 corresponds to the output end of the current signal I1.

  The operational amplifier 141 controls the conductivity of the transistor 142 so that the voltage ΔV1 across the sense resistor R1 (= IL1 × R1) matches the voltage Vx across the resistor 143 (= Ix × Rx). That is, the current Ix flowing through the resistor 143 has a current value (= IL1 × (R1 / Rx)) corresponding to the inductor current IL1 flowing through the sense resistor R1. The current Ix is mirrored by the current mirror 144 to generate a current signal I1 (= γ × Ix, where γ is a mirror ratio).

  Since the configuration of the current amplifier 24 is the same as described above, a duplicate description is omitted.

  FIG. 7 is a diagram illustrating a first configuration example of the error amplifier circuit 30. The error amplifier circuit 30 of the first configuration example includes an operational amplifier 31, a resistor 32, and a capacitor 33. The operational amplifier 31 is integrated in the semiconductor device 1, and the resistor 32 and the capacitor 33 are externally attached to the semiconductor device 1.

  A non-inverting input terminal (+) of the operational amplifier 31 is connected to an application terminal for a predetermined reference voltage Vref. The resistor 32 is connected between the application terminal of the output voltage Vo and the inverting input terminal (−) of the operational amplifier 31. The capacitor 33 is connected between the inverting input terminal (−) and the output terminal of the operational amplifier 31. That is, the operational amplifier 31, the resistor 32, and the capacitor 33 form an integrating circuit. A phase compensation circuit (a series circuit of a resistor and a capacitor) may be connected to the resistor 32 and the capacitor 33 in parallel with each other.

  In the error amplifier circuit 30 of the first configuration example, as a factor affecting the output characteristics, the manufacturing variation of the resistor 32 and the capacitor 33 that are external discrete components is more than the manufacturing variation of the operational amplifier 31 (about ± 10%). (About ± 1%) is dominant. Therefore, in the case of the error amplifier circuit 30, the output characteristics (frequency characteristics) are unlikely to vary, so that highly accurate output feedback control can be realized.

  FIG. 8 is a diagram illustrating a second configuration example of the error amplifier circuit 30. The error amplifier circuit 30 of the second configuration example includes a current amplifier (gm amplifier) 34, resistors 35 and 36, a capacitor 37, and a phase compensation circuit 38. The current amplifier 34 is integrated in the semiconductor device 1, and the other circuit elements 35 to 38 are all externally attached to the semiconductor device 1.

  A non-inverting input terminal (+) of the current amplifier 34 is connected to an application terminal for a predetermined reference voltage Vref. The resistor 35 is connected between the application terminal of the output voltage Vo and the inverting input terminal (−) of the current amplifier 34. The resistor 36 is connected between the inverting input terminal (−) of the current amplifier 34 and the ground terminal. That is, the resistors 35 and 36 form a voltage dividing circuit that divides the output voltage Vo and outputs the divided voltage to the inverting input terminal (−) of the current amplifier 34. A capacitor may be connected to the resistor 35 in parallel. Both the capacitor 37 and the phase compensation circuit 38 (series circuit of a resistor and a capacitor) are connected between the output terminal of the operational amplifier 31 and the ground terminal.

  Thus, as the error amplifying circuit 30, not only the integrating circuit type of FIG. 7 but also a more general gm amplifier type can be used.

  FIG. 9 is a diagram illustrating a configuration example of the oscillation circuit 40. The oscillation circuit 40 of this configuration example includes an oscillator 41, a constant current source 42, a low-pass filter 43, a constant voltage source 44, a current amplifier 45, and a current mirror 46.

  The oscillator 41 variably controls the oscillation frequency of the clock signals CLK1 and CLK2 according to the bias current IB. More specifically, the oscillator 41 increases the oscillation frequency of the clock signals CLK1 and CLK2 as the bias current IB increases. The bias current IB is a total current of the fixed bias current IBx and the variable bias current IBy.

  The constant current source 42 generates a constant reference bias current IBx.

  The low-pass filter 43 performs low-pass filter processing (smoothing processing) on the output voltage Vo to generate the output voltage Vo1.

  The constant voltage source 44 adds the constant offset voltage Vofs to the output voltage Vo to generate the output voltage Vo2.

  The current amplifier 45 generates a variable bias current IBz corresponding to the difference between the output voltage Vo1 applied to the non-inverting input terminal (+) and Vo2 applied to the inverting input terminal (−). More specifically, the current amplifier 45 increases the variable bias current IBz as the output voltage Vo1 is higher than the output voltage Vo2.

  The current mirror 46 mirrors the variable bias current IBz to generate the variable bias current IBy.

  FIG. 10 is a timing chart for explaining the frequency variable operation when the output voltage Vo suddenly changes. From the top, the output voltage Vo, the output voltage Vo1, the output voltage Vo2, the bias current IB, and the clock signal CLK1 and CLK2 is depicted.

  When the output voltage Vo is kept constant, the output voltage Vo2 is maintained in a state exceeding the output voltage Vo1, so that the variable bias current IBy becomes zero, and the bias current IB matches the fixed bias current IBx. At this time, the oscillation frequencies of the clock signals CLK1 and CLK2 are normal values.

  On the other hand, when the output voltage Vo suddenly decreases, the output voltage Vo2 temporarily falls below the output voltage Vo1, so that the variable bias current IBy is generated and the bias current IB is increased. As a result, the oscillation frequency of the clock signals CLK1 and CLK2 can be increased from the normal value, so that fluctuations in the output voltage Vo can be suppressed.

  Next, the current balancing circuit 50 that is desirably added to the multi-phase power supply device X will be described in detail with reference to FIG.

  FIG. 11 is a diagram illustrating a configuration example of the current balancing circuit 50. The current balancing circuit 50 of the present configuration example corrects the error signal Vcomp so that the inductor currents IL1 and IL2 flowing in the output stages OS1 and OS2 of each set coincide with each other, and generates the error signals Vcomp1 and Vcomp2 for each set. The circuit block to be generated includes resistors 51 and 52 (resistance values: R51 and R52) and current mirrors 53 to 56.

  The current amplifier 14 includes a path for outputting the current signal I1 to the current balancing circuit 50, in addition to the path for outputting the current signal I1 (∝IL1) to the adder 16. Similarly, the current amplifier 24 includes a path for outputting the current signal I2 to the current balancing circuit 50, in addition to the path for outputting the current signal I2 (∝IL2) to the adder 26.

  The first end of the resistor 51 is connected to the application end of the error signal Vcomp. The second end of the resistor 51 is connected to the inverting input terminal (−) of the comparator 13 as an application terminal for the error signal Vcomp1. The error signal Vcomp1 is a voltage signal obtained by correcting the error signal Vcomp in accordance with the balanced current IBAL1 flowing through the resistor 51. For example, when the direction from the first end to the second end of the resistor 51 is defined as the positive direction of the balanced current IBAL1, it can be calculated using an arithmetic expression Vcomp1 = Vcomp−IBAL1 × R51.

  The first end of the resistor 52 is connected to the application end of the error signal Vcomp. The second end of the resistor 52 is connected to the inverting input terminal (−) of the comparator 23 as an application terminal for the error signal Vcomp2. The error signal Vcomp2 is a voltage signal obtained by correcting the error signal Vcomp in accordance with the balanced current IBAL2 flowing through the resistor 52. For example, when the direction from the first end to the second end of the resistor 52 is defined as the positive direction of the balanced current IBAL2, it can be calculated using an arithmetic expression Vcomp2 = Vcomp−IBAL2 × R52.

  The current mirrors 53 to 56 are appropriately combined so as to generate a balanced current IBAL1 and IBAL2 by performing a difference calculation between the current signal I1 and the current signal I2. More specifically, by combining a current mirror 53 that draws the current signal I1 from the node P toward the ground terminal and a current mirror 54 that feeds the current signal I2 from the power supply terminal to the node P, the balanced current IBAL1 (= I1− I2) has been generated. Further, a balanced current IBAL2 (= I2−I1) is generated by combining the current mirror 56 that draws the current signal I2 from the node Q toward the ground terminal and the current mirror 55 that flows the current signal I1 from the power supply terminal to the node Q. ing.

  Here, when I1> I2 (IL1> IL2), IBAL1> 0 and IBAL2 <0, and Vcomp> Vcomp1 and Vcomp <Vcomp2. That is, the phase error signal Vcomp1 in which a relatively large inductor current IL1 flows is pulled down, and the phase error signal Vcomp2 in which a relatively small inductor current IL2 flows is pulled up. As a result, feedback control operates so as to decrease the inductor current IL1 and increase the inductor current IL2.

  Conversely, when I1 <I2 (IL1 <IL2), IBAL1 <0 and IBAL2> 0, and Vcomp <Vcomp1 and Vcomp> Vcomp2. That is, the phase error signal Vcomp2 in which the relatively large inductor current IL2 flows is lowered, and the phase error signal Vcomp1 in which the relatively small inductor current IL1 flows is increased. As a result, feedback control works so as to decrease the inductor current IL2 and increase the inductor current IL1.

  Therefore, the power supply device X finally reaches a current equilibrium state in which the inductor currents IL1 and IL2 coincide with each other.

  For example, when a 10 A output current Io is supplied to the load Z, if 5 A inductor currents IL1 and IL2 flow evenly through the output stages OS1 and OS2, respectively, discrete components that form the output stages OS1 and OS2 are used. It is sufficient to select parts corresponding to the current output of 5A. However, for example, if an inductor current IL1 of 8A flows through the output stage OS1 and only a 2A inductor current IL2 flows through the output stage OS2, a bias of the inductor currents IL1 and IL2 is taken into consideration. In addition, it is necessary to select parts corresponding to a current output of a maximum of 8 A, resulting in unnecessary cost increase. In addition, if a part that only supports a current output of 5 A is selected to avoid an increase in cost, there is a risk of serious accidents (such as damage to discrete parts, smoke or ignition).

  On the other hand, in the power supply device X including the current balancing circuit 50, the inductor currents IL1 and IL2 can be made to coincide with each other, and thus the above-described problem can be solved. In particular, when an arithmetic processing unit such as a CPU or GPU is connected as the load Z, a large current (about 100 A) is instantaneously consumed, so that balanced control of the inductor currents IL1 and IL2 is very important. .

Second Embodiment
FIG. 12 is a diagram illustrating a second embodiment of the power supply device X. As illustrated in FIG. The power supply device X of the second embodiment is configured to use inductor resistances DCR1 and DCR2 as means for detecting the inductor currents IL1 and IL2. When this configuration is adopted, a resistor R11 and a capacitor C1, and a resistor R21 and a capacitor C2 are connected in parallel with the inductors L1 and L2, respectively, and the voltage across the capacitors C1 and C2 is changed to current amplifiers 14 and 24. You can enter them respectively. Further, as means for canceling the temperature characteristics of the inductors L1 and L2, resistors R12 and R22 (eg, a thermistor) may be connected in parallel with the capacitors C1 and C2.

<Third Embodiment>
FIG. 13 is a diagram illustrating a third embodiment of the power supply device X. As illustrated in FIG. The power supply device X of the third configuration example is a single phase type in which the output stage OS2 and the switch control circuit 20 are omitted. Thus, the various configurations described above can be applied not only to the multi-phase type but also to the single-phase type.

<Application example to desktop PC>
FIG. 14 is an external view showing a configuration example of a desktop personal computer Y on which the power supply device X is mounted. The desktop personal computer Y of this configuration example includes a main body case Y10, a liquid crystal monitor Y20, a keyboard Y30, and a mouse Y40.

  The main body case Y10 houses a central processing unit Y11, a memory Y12, an optical drive Y13, a hard disk drive Y14, and the like.

  The central processing unit Y11 comprehensively controls the operation of the desktop personal computer Y by executing an operating system and various application programs stored in the hard disk drive Y14.

  The memory Y12 is used as a work area of the central processing unit Y11 (for example, an area for storing task data when executing a program).

  The optical drive Y13 reads / writes the optical disk. Examples of the optical disc include a CD [compact disc], a DVD [digital versatile disc], and a BD [Blu-ray disc].

  The hard disk drive Y14 is one of large-capacity auxiliary storage devices that store programs and data in a nonvolatile manner using a magnetic disk sealed in a housing.

  The liquid crystal monitor Y20 outputs an image based on an instruction from the central processing unit Y11.

  The keyboard Y30 and the mouse Y40 are one of human interface devices that accept user operations.

  In the desktop personal computer Y having the above-described configuration, the above-described power supply device X can be suitably used as power supply means to the load Z (central processing unit Y11, memory Y12, etc.) with large current consumption.

<Other variations>
In the above description, the desktop PC Y is given as an example of the application of the present invention. However, the application of the present invention is not limited to this, and can be applied to various electronic devices (notebook computers, game machines, etc.). It can be widely applied.

  Various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment.

  For example, in the above-described embodiment, the configuration using the N-channel MOS field effect transistors N11 and N21 as the upper transistor included in the output stage has been described as an example. However, the configuration of the present invention is limited to this. A P channel type MOS field effect transistor may be used instead.

  In the above embodiment, the configuration using the step-down output stage has been described as an example. However, the configuration of the present invention is not limited to this, and the step-up output stage or the step-up / step-down output stage is not limited thereto. An output stage may be used.

  As described above, the above embodiments are examples in all respects and should not be considered to be restrictive, and the technical scope of the present invention is not the description of the above embodiments, but the claims. It is to be understood that all changes that come within the scope of the claims, are equivalent in meaning to the claims, and fall within the scope of the claims.

  The power supply apparatus according to the present invention is provided as a single-phase or multi-phase DC / DC converter (external FET type), for example, a power supply apparatus such as a CPU and a GPU mounted in a personal computer or a game machine. Or, it can be used as a power supply device for a memory.

1 Semiconductor device (Multi-phase switching regulator IC)
10, 20 Switch control circuit 11, 21 Driver 12, 22 RS flip-flop 13, 23 Comparator 14, 24 Current amplifier 15, 25 Ramp signal generator 16, 26 Adder 30 Error amplifier 31 Operational amplifier 32 Resistor 33 Capacitor 34 Current amplifier 35, 36 Resistance 37 Capacitor 38 Phase compensation circuit 40 Oscillation circuit 41 Oscillator 42 Constant current source 43 Low pass filter 44 Constant voltage source 45 Current amplifier 46 Current mirror 50 Current balancing circuit 51, 52 Resistance 53 to 56 Current mirror 141 Operational amplifier 142 N channel Type MOS field effect transistor 143 resistance 144 current mirror 151 charging current generation circuit 152 capacitor 153 constant voltage source 154, 155 switch 156 inverter 161 buffer 1 62 resistor N11, N12, N21, N22 N-channel MOS field effect transistor L1, L2 inductor R1, R2 sense resistor R11, R12, R21, R22 resistor DCR1, DCR2 inductor resistor Co, C1, C2 capacitor OS1, OS2 output stage a1 A3 resistance a4 constant current source a5 pnp bipolar transistor a6 npn bipolar transistor a7, a8 P-channel MOS field effect transistor X power supply Y desktop PC Y10 main unit case Y11 central processing unit Y12 memory Y13 optical drive Y14 hard disk drive Y20 LCD monitor Y30 Keyboard Y40 Mouse Z Load

Claims (13)

An output stage for switching the inductor current to generate an output voltage from the input voltage;
An error amplifying circuit that generates an error signal according to an error between the output voltage and the target value;
A switch control circuit for controlling the driving of the output stage so that the error signal is small;
An oscillation circuit for generating a clock signal;
A power supply device comprising:
The switch control circuit includes:
An amplifier for amplifying a detection signal corresponding to the inductor current to generate an amplified detection signal;
A ramp signal generator for generating a ramp signal having a larger amplitude than the amplified detection signal;
An adder for adding the amplified detection signal and the ramp signal to generate a reference signal;
A comparator that compares the error signal with the reference signal to generate a comparison signal;
A logic unit that generates a switch control signal according to the clock signal and the comparison signal;
A driver for controlling the driving of the output stage according to the switch control signal;
Including
The power supply device, wherein the oscillation circuit variably controls an oscillation frequency of the clock signal so as to suppress fluctuations in the output voltage. A plurality of sets of the output stage and the switch control circuit;
The power supply apparatus according to claim 1, wherein each set of switch control circuits performs drive control of an output stage corresponding to each of the phases in different phases.   3. The power supply apparatus according to claim 2, further comprising a current balancing circuit that corrects the error signal so that inductor currents flowing through the output stages of the sets coincide with each other to generate an error signal for each set. . An output stage for switching the inductor current to generate an output voltage from the input voltage;
An error amplifying circuit that generates an error signal according to an error between the output voltage and the target value;
A switch control circuit for controlling the driving of the output stage so that the error signal is small;
A power supply device comprising:
The switch control circuit includes:
An amplifier for amplifying a detection signal corresponding to the inductor current to generate an amplified detection signal;
A ramp signal generator for generating a ramp signal having a larger amplitude than the amplified detection signal;
An adder for adding the amplified detection signal and the ramp signal to generate a reference signal;
A comparator that compares the error signal with the reference signal to generate a comparison signal;
A logic unit for generating a switch control signal according to the clock signal and the comparison signal;
A driver for controlling the driving of the output stage according to the switch control signal;
Including
The power supply device has a plurality of sets of the output stage and the switch control circuit,
Each set of switch control circuits performs drive control of the output stage corresponding to each with different phases.
The power supply apparatus further includes a current balancing circuit that corrects the error signal so that inductor currents flowing through the output stages of the sets coincide with each other to generate an error signal for each set.   5. The power supply device according to claim 1, wherein the ramp signal generation unit increases the ramp-up slope of the ramp signal as the input voltage increases.   The power supply apparatus according to claim 1, wherein the ramp signal generation unit biases the ramp signal to a signal value higher than zero. The error amplification circuit includes:
An operational amplifier having a non-inverting input terminal connected to a reference voltage application terminal;
A resistor connected between an application terminal of the output voltage and an inverting input terminal of the operational amplifier;
A capacitor connected between an inverting input terminal and an output terminal of the operational amplifier;
The power supply apparatus according to any one of claims 1 to 6, wherein the power supply apparatus includes: The error amplification circuit includes:
A gm amplifier having a non-inverting input terminal connected to a reference voltage application terminal;
A voltage dividing circuit that divides the output voltage and outputs the divided voltage to the inverting input terminal of the gm amplifier;
A capacitor connected between an output terminal and a ground terminal of the gm amplifier;
The power supply apparatus according to any one of claims 1 to 6, wherein the power supply apparatus includes:   The power supply device according to any one of claims 1 to 8, wherein the detection signal is detected using a sense resistor or an inductor resistor.   The power supply apparatus according to any one of claims 1 to 9, wherein the output stage is a step-down type, a step-up type, or a step-up / step-down type.   11. The error amplifier circuit and the switch control circuit are integrated in a semiconductor device, and the output stage is externally attached to the semiconductor device. The power supply device according to item. The power supply device according to any one of claims 1 to 11,
A load that operates by receiving supply of an output voltage from the power supply device;
An electronic device comprising:   The electronic device according to claim 12, wherein the load is an arithmetic processing unit or a memory.