JP6738455B2 - Electronic parts - Google Patents

Description

The present invention relates to a semiconductor light emitting device (light emitting diode, laser diode, etc.) using a group III nitride semiconductor.

Conventionally, in a group III nitride semiconductor light emitting device having a light emitting layer (active layer) sandwiched between an n-type layer and a p-type layer, a buffer is provided as a base layer of the light emitting layer for the purpose of preventing lattice defects from occurring in the light emitting layer. It is known to arrange layers.
For example, Patent Document 1 discloses disposing a superlattice layer having an InGaN layer and a GaN layer between an n-type clad layer and an MQW active layer stacked thereon.

JP 2007-227671A

The above superlattice layer may not be able to sufficiently relax the lattice depending on the peak emission wavelength of the light emitting layer. For example, it is not possible to reduce the occurrence of lattice defects in a light emitting layer having a peak emission wavelength of 500 nm or more, and a method for such a light emitting layer is not yet established.
Therefore, an object of the present invention is to provide a semiconductor light emitting device capable of reducing lattice defects in a light emitting layer which emits light having a peak emission wavelength of 500 nm or more.

Another object of the present invention is to provide a semiconductor light emitting device capable of suppressing a decrease in luminance in a long wavelength region by reducing lattice defects in the light emitting layer.

One embodiment is a group III nitride semiconductor having a laminated structure, which is composed of a group III nitride semiconductor and has at least an n-type layer, a p-type layer, and a light emitting layer sandwiched between the n-type layer and the p-type layer. A main emitting layer having a layer, wherein the emitting layer emits light having a peak emission wavelength of 500 nm or more, and has a In _x Ga _1-x N (x=0.18 to 0.23) layer. Provided is a semiconductor light emitting device including a stress relaxation layer having an In _y Ga _1-y N (y=0.06 to 0.16) layer.

According to this structure, the stress relaxation layer having an In composition ratio (y) relatively close to the In composition ratio (x) of the main light emitting layer constitutes a part of the light emitting layer together with the main light emitting layer. Thus, when the light emitting layer is crystal-grown from the n-type layer or the p-type layer side, the stress relaxation layer is first grown, and then the main light emitting layer is grown, whereby the lattice size at the start of growth of the main light emitting layer is increased. The change in can be moderated. Therefore, the introduction of lattice defects into the main light emitting layer can be reduced. As a result, this semiconductor light emitting device can efficiently generate light having a peak emission wavelength of 500 nm or more in the main light emitting layer. Due to this improvement in light emission efficiency, it is possible to suppress a decrease in luminance in a long wavelength region (for example, a wavelength region of 525 nm or more).

In the semiconductor light emitting device, the stress relaxation layer includes a plurality of the In _y Ga _1-y N layers, and the plurality of In _y Ga _1-y N layers are closer to the main light emitting layer in the In composition ratio (y. ) May be laminated in the order of increasing.
According to this structure, the In composition ratio (y) of the stress relaxation layer can be gradually brought close to the In composition ratio (x) of the main light emitting layer. This makes it possible to reduce the difference in lattice size between the main light emitting layer and the stress relaxation layer, so that the introduction of lattice defects into the main light emitting layer can be further reduced.

The In composition ratio (y) of the plurality of In _y Ga _1-y N layers may be increased at a constant rate (for example, 0.1 step, 0.2 step, etc.) or may be random. It may increase in proportion (for example, 0.1→0.2→0.4).
In the semiconductor light emitting device, the main light emitting layer and the stress relaxation layer may be laminated so as to be in contact with each other.

According to this structure, since the main light emitting layer and the stress relaxation layer are integrated into one laminated structure, it is possible to reduce variations in the lattice size in the portion of the light emitting layer where the laminated structure is formed.
In the semiconductor light emitting device, it is preferable that the light emitting layer has a multiple quantum well structure in which quantum well layers made of InGaN and barrier layers made of GaN are alternately laminated at a predetermined cycle. In this case, it is preferable that the quantum well layer has a thickness of 3 nm±10%. With this configuration, the luminous efficiency of the semiconductor light emitting device can be further improved.

The semiconductor light emitting device further includes an intermediate buffer layer disposed on the side opposite to the main light emitting layer with respect to the stress relaxation layer and having a superlattice structure in which InGaN layers and GaN layers are alternately laminated at a predetermined cycle. It is preferable. In this case, the InGaN layer preferably _includes a layer represented by _{In z Ga 1-z N (} z = 0.01~0.05).
According to this configuration, when the light emitting layer is crystal-grown from the n-type layer or p-type layer side, the intermediate buffer layer is grown prior to the growth of the light emitting layer, so that the growth of the light emitting layer (stress relaxation layer) is started. The change in the lattice size over time can be made gradual. Therefore, the introduction of lattice defects into the stress relaxation layer can be reduced.

In the semiconductor light emitting device, the light emitting layer may generate light having a peak emission wavelength of 500 nm to 550 nm.
According to this structure, it is possible to provide a semiconductor light emitting device having a light emitting layer that efficiently emits green light.
In the semiconductor light emitting device, the light emitting layer may have a total thickness of 60 nm to 140 nm.

According to this structure, the luminous efficiency of the semiconductor light emitting element can be improved while keeping the total thickness of the light emitting layer within a general range.
The semiconductor light emitting device may further include a sapphire substrate, and the light emitting layer may be a layer in which the stress relaxation layer and the main light emitting layer are crystal-grown on a main surface of the sapphire substrate in this order.

According to this structure, the group III nitride semiconductor layer having the light emitting layer with improved light emitting efficiency can be formed on the sapphire substrate. Further, since it is not necessary to use a special substrate and an inexpensive sapphire substrate is sufficient, the manufacturing cost can be reduced.

FIG. 1 is a schematic cross-sectional view for explaining the structure of a light emitting diode according to an embodiment of the present invention. FIG. 2 is a diagram showing a specific structure of the light emitting layer and a relationship between the depth of the group III nitride semiconductor layer and the In composition. FIG. 3 is a schematic diagram for explaining the structure of a processing apparatus for growing each layer constituting the group III nitride semiconductor layer. FIG. 4 is a time chart showing the relationship between the growth time of the light emitting layer and the substrate temperature. FIG. 5 is a graph showing the relationship between the dominant wavelength and the back surface luminance of the wafer having the group III nitride semiconductor layer. FIG. 6 is a diagram showing a PL spectrum of a wafer having the group III nitride semiconductor layer. FIG. 7 is a diagram showing an EL spectrum (1 mA) of a diode package having a structure similar to that of the light emitting diode. FIG. 8 is a diagram showing an EL spectrum (20 mA) of a diode package having the same structure as the light emitting diode. FIG. 9 is a diagram showing an EL spectrum (120 mA) of a diode package having a structure similar to that of the light emitting diode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view for explaining the structure of a light emitting diode according to an embodiment of the present invention.
A light emitting diode 1 as an example of a semiconductor light emitting device of the present invention has a device body formed by growing a group III nitride semiconductor layer 3 having a group III nitride semiconductor laminated structure on a sapphire substrate 2. There is.

The group III nitride semiconductor layer 3 includes, in order from the sapphire substrate 2 side, an n-type low temperature GaN buffer layer 31, an n-type GaN contact layer 32, an intermediate buffer layer 33, a light emitting layer 34, which is an example of the n-type layer of the present invention. In addition, it has a laminated structure in which a p-type AlGaN electron blocking layer 35 and a p-type GaN contact layer 36 are laminated as an example of the p-type layer of the present invention.
In the group III nitride semiconductor layer 3, the recess 4 is formed by selectively removing (eg, etching) from the p-type GaN contact layer 36 to a depth at which the n-type GaN contact layer 32 is exposed so that the cross section has a substantially rectangular shape. Are formed. The n-type GaN contact layer 32 has a lead-out portion 5 that is drawn out from one side of the group III nitride semiconductor layer 3 in the lateral direction along the surface of the sapphire substrate 2.

A p-type electrode (anode electrode) 6 is joined to the surface of the p-type GaN contact layer 36, and an n-type electrode (cathode electrode) 7 is joined to the lead portion 5 of the n-type GaN contact layer 32. ing. Thus, the light emitting diode structure is formed.
The sapphire substrate 2 is joined to a support substrate (wiring substrate) 8. Wirings 9 and 10 are formed on the surface of the support substrate 8. The p-type electrode 6 and the wiring 9 are connected by the bonding wire 11, and the n-type electrode 7 and the wiring 10 are connected by the bonding wire 12.

Although not shown, the package of the light emitting diode 1 (diode package) is configured by sealing the structure of the light emitting diode 1 and the bonding wires 11 and 12 with a transparent resin such as epoxy resin. There is.
The sapphire substrate 2 is a substrate made of a sapphire single crystal having a polar plane (c-plane in this embodiment) as a main surface. Specifically, the main surface of the sapphire substrate 2 is a surface having an off angle of 0.3° or more from the plane orientation of the polar surface, and more preferably an off angle of 0.3° or more in the m-axis direction.

Therefore, the growth main surface (surface 3a) of the group III nitride semiconductor layer 3 crystal-grown on the sapphire substrate 2 is the same surface as the main surface of the sapphire substrate 2, that is, the polar surface (c-plane in this embodiment). ).
In addition, the thickness of the sapphire substrate 2 is preferably 600 μm or more, specifically, 650 μm to 1000 μm. In the light emitting diode 1, instead of the sapphire substrate 2, for example, a hexagonal crystal substrate such as a GaN substrate, a ZnO substrate, an AlN substrate, or a SiC substrate can be used.

The n-type low temperature GaN buffer layer 31 is made of, for example, an undoped (undoped with dopant) GaN layer crystal-grown at a wafer temperature of 400° C. to 700° C. The layer thickness is preferably several tens of nm.
The n-type GaN contact layer 32 is, for example, an n-type GaN layer to which silicon is added as an n-type dopant. The layer thickness is preferably 3 μm or more, specifically 3 μm to 7 μm. The doping concentration of silicon is, for example, about 1×10 ¹⁸ cm ⁻³ .

The intermediate buffer layer 33 has, for example, a superlattice structure in which a silicon-doped InGaN layer (for example, about 4 nm thickness) and a GaN layer (for example, about 2 nm thickness) are alternately laminated for a predetermined period (for example, about 5 periods). There is. Further, in this embodiment, the InGaN layer is a layer represented by In _z Ga _1-z N (z=0.01 to 0.05), and the GaN layer is a layer containing no In at all. The GaN layer may contain a small amount of In in a range smaller than the In composition ratio (z) of the InGaN layer of the intermediate buffer layer 33.

The light emitting layer 34 has, for example, a multiple quantum well (MQW) structure in which a silicon-doped InGaN layer 14 (quantum well layer) and a GaN layer 13 (barrier layer) are alternately laminated for a predetermined period. There is.
Further, the light emitting layer 34 has a GaN final barrier layer 15 (for example, about 10 nm thick) between the p-type AlGaN electron blocking layer 35 and the multiple quantum well structure including the InGaN layer 14 and the GaN layer 13. The GaN final barrier layer 15 is formed of, for example, an undoped (undoped with dopant) GaN layer.

The p-type AlGaN electron blocking layer 35 is, for example, an AlGaN layer to which magnesium is added as a p-type dopant. The layer thickness is preferably 3 nm or more, specifically 5 nm to 30 nm. The doping concentration of magnesium is, for example, about 3×10 ¹⁹ cm ⁻³ .
The p-type GaN contact layer 36 is made of, for example, a GaN layer to which magnesium as a p-type dopant is added at a high concentration. The layer thickness is preferably 0.1 μm or more, specifically 0.2 μm to 0.5 μm. The doping concentration of magnesium is, for example, about 10 ²⁰ cm ⁻³ . The surface of the p-type GaN contact layer 36 forms the surface 3a of the group III nitride semiconductor layer 3, and the surface 3a is a mirror surface. The surface 3a is a light extraction side surface from which the light generated in the light emitting layer 34 is extracted.

The p-type electrode 6 and the n-type electrode 7 are films composed of, for example, a Ti layer and an Al layer. A transparent electrode for anode contact may be formed between the p-type electrode 6 and the p-type GaN contact layer 36 over almost the entire surface 3a of the group III nitride semiconductor layer 3. Such a transparent electrode can be composed of, for example, a transparent thin metal layer composed of a Ni layer and an Au layer, a ZnO layer, or the like.

FIG. 2 is a diagram showing a specific configuration of the light emitting layer 34 and a relationship between the depth of the group III nitride semiconductor layer 3 and the In composition.
The light emitting layer 34 emits light having a peak emission wavelength of 500 nm or more, and preferably emits light having a peak emission wavelength in the range of 500 nm to 550 nm. Here, the peak emission wavelength refers to the wavelength of the light with the highest intensity (main peak) of the light emitted from the light emitting layer 34, and is the wavelength corresponding to the peak value of the spectral distribution of the emitted light. is there.

Therefore, even if the peak of the noise level appears in addition to the maximum peak in the spectral distribution, the peak emission wavelength of the noise level is not included in the “peak emission wavelength” in this embodiment.
The light emitting layer 34 includes a green light emitting layer 16 as an example of the main light emitting layer of the present invention and a blue light emitting layer 17 as an example of the stress relaxation layer of the present invention. Of these two light emitting layers 16 and 17, it is the green light emitting layer 16 that mainly generates the light emitted from the light emitting layer 34, and emits light having a peak emission wavelength of 500 nm or more (specifically, 500 nm to 550 nm). generate.

On the other hand, the blue light emitting layer 17 generates light having a peak emission wavelength of 410 nm to 490 nm, but its intensity is weak and has a noise level with respect to the entire light emitted from the light emitting layer 34. Therefore, the light emission characteristics of the light emitting diode 1 are hardly affected by the light generated in the blue light emitting layer 17.
In this embodiment, the green light emitting layer 16 and the blue light emitting layer 17 are arranged on the side where the green light emitting layer 16 is close to the surface 3a (surface on the light extraction side) of the group III nitride semiconductor layer 3, and the blue light emitting layer 17 is green. The light emitting layer 16 is arranged on the side opposite to the surface 3a (the side close to the sapphire substrate 2), and they are laminated so as to be in contact with each other.

As described above, each of the green light emitting layer 16 and the blue light emitting layer 17 has a multiple quantum well structure in which InGaN layers 14 (g, b) and GaN layers 13 (g, b) are alternately laminated for a predetermined period. There is. For example, in the green light emitting layer 16 and the blue light emitting layer 17, the InGaN layer 14(g,b) and the GaN layer 13(g,b) may be laminated in the same cycle.
In this embodiment, the InGaN layer 14 (g) and the GaN layer 13 (g) are stacked in four cycles (4 pairs) in the green light emitting layer 16. Also, in the blue light emitting layer 17, the InGaN layer 14(b) and the GaN layer 13(b) are stacked for four periods (4 pairs).

Also, the green emitting layer 16, a layer InGaN layer 14 (g) is represented by _{In x Ga 1-x N (} x = 0.18~0.23), GaN layer 13 (g) is the In It is a layer that does not contain at all. In this embodiment, the plurality of InGaN layers 14 (g) have a constant In composition ratio (x) in the stacking direction of the group III nitride semiconductor layers 3.
For example, as shown in the right side of FIG. 2, the In composition ratios (x) of the four InGaN layers 14 (g) are all 0.2 (20%). The plurality of InGaN layers 14(g) may be stacked in the order in which the In composition ratio (x) changes in the stacking direction of the group III nitride semiconductor layer 3. For example, the In composition ratio (x) may be increased in order of increasing distance from the blue light emitting layer 17, or may be stacked in order of decreasing.

On the other hand, in the blue light emitting layer 17, the InGaN layer 14(b) is a layer represented by In _y Ga _1-y N (y=0.06 to 0.16), and the GaN layer 13(b) contains In. It is a layer that does not contain at all. In this embodiment, the plurality of InGaN layers 14(b) are stacked in the stacking direction of the group III nitride semiconductor layers 3 in the order in which the In composition ratio (y) increases toward the green light emitting layer 16.

For example, as shown on the right side of FIG. 2, the In composition ratios (y) of the four InGaN layers 14 (b) are 0.8 (8%) and 0.11 (11) in order toward the green light emitting layer 16. %), 0.14 (14%), and 0.17 (17%), increasing at a constant rate (in this embodiment, in 0.3 increments). Further, in this embodiment, the In composition ratio difference (xy) between the InGaN layer 14(g) of the green light emitting layer 16 and the InGaN layer 14(b) of the blue light emitting layer 17 which are adjacent to each other is equal to a plurality of InGaN layers. It has the same value as the constant increase rate of the In composition ratio (y) of the layer 14(b).

That is, in this embodiment, the In composition ratio (xy) is 0.2-0.17=0.3, which is the same value as the above-mentioned constant increase ratio 0.3. .. Thereby, the change in the lattice size in the light emitting layer 34 can be moderated even at the boundary between the blue light emitting layer 17 and the green light emitting layer 16.
Regarding the thickness of the light emitting layer 34, the total thickness (total thickness) of the light emitting layer 34 including the green light emitting layer 16 and the blue light emitting layer 17 is, for example, 60 nm to 150 nm. Regarding the thickness of each layer 16 and 17, in the green light emitting layer 16, the InGaN layer (quantum well layer) 14(g) is about 3 nm±10% (that is, 2.7 nm to 3.3 nm) thick, and the GaN layer ( The barrier layer) 13(g) has a thickness of about 14 nm.

In the blue light emitting layer 17, the InGaN layer (quantum well layer) 14(b) has a thickness of about 3±10% nm, and the GaN layer (barrier layer) 13(b) has a thickness of about 14 nm. In addition, in the green light emitting layer 16 and the blue light emitting layer 17, the plurality of InGaN layers 14 (g, b) and the GaN layers 13 (g, b) may have a constant thickness, or a group III nitride. It may change in the stacking direction of the semiconductor layers 3. In this embodiment, the InGaN layers 14 (g, b) and the GaN layers 13 (g, b) have a constant thickness.

FIG. 3 is a schematic diagram for explaining the configuration of a processing apparatus for growing each layer forming the group III nitride semiconductor layer 3. FIG. 4 is a time chart showing the relationship between the growth time of the light emitting layer 34 and the substrate temperature.
As shown in FIG. 3, a susceptor 22 containing a heater 21 is arranged in the processing chamber 20 of the processing apparatus. The susceptor 22 is coupled to a rotary shaft 23, and the rotary shaft 23 is rotated by a rotary drive mechanism 24 arranged outside the processing chamber 20.

As a result, by holding the wafer 25 to be processed on the susceptor 22, the wafer 25 can be heated to a predetermined temperature and rotated in the processing chamber 20. The wafer 25 is a sapphire single crystal wafer that constitutes the sapphire substrate 2 described above.
An exhaust pipe 26 is connected to the processing chamber 20. The exhaust pipe 26 is connected to an exhaust facility such as a rotary pump. As a result, the pressure in the processing chamber 20 is set to 1/10 atmospheric pressure to normal pressure (preferably about 1/5 atmospheric pressure), and the atmosphere in the processing chamber 20 is constantly exhausted.

On the other hand, in the processing chamber 20, a raw material gas supply passage 40 for supplying the raw material gas toward the surface of the wafer 25 held by the susceptor 22 is introduced. In the source gas supply passage 40, a nitrogen source pipe 41 for supplying ammonia as a nitrogen source gas, a gallium source pipe 42 for supplying trimethylgallium (TMG) as a gallium source gas, and trimethylaluminum as an aluminum source gas. Aluminum raw material pipe 43 for supplying (TMAl), indium raw material pipe 44 for supplying trimethylindium (TMIn) as an indium raw material gas, and ethylcyclopentadienyl magnesium (EtCp ₂ Mg) as a magnesium raw material gas. A magnesium raw material pipe 45 and a silicon raw material pipe 46 for supplying silane (SiH ₄ ) as a raw material gas for silicon are connected.

Valves 51 to 56 are provided in the raw material pipes 41 to 46, respectively. Each source gas is supplied together with a carrier gas composed of hydrogen, nitrogen, or both.
Then, in order to grow the group III nitride semiconductor layer 3 on the sapphire substrate 2 by crystal growth, for example, a sapphire single crystal wafer whose main surface is the c-plane is held as the wafer 25 on the susceptor 22. In this state, the valves 52 to 56 are closed and the nitrogen source valve 51 is opened to supply the carrier gas and the ammonia gas (nitrogen source gas) into the processing chamber 20.

Further, the heater 21 is energized to raise the wafer temperature (substrate temperature) to 1000° C. to 1100° C. (for example, about 1050° C.). As a result, the group III nitride semiconductor can be grown without causing the surface of the wafer 25 to be rough.
Next, after setting the wafer temperature to 400° C. to 700° C., the nitrogen raw material valve 51 and the gallium raw material valve 52 are opened. As a result, ammonia and trimethylgallium are supplied from the source gas supply passage 40 together with the carrier gas. As a result, the low temperature GaN buffer layer 31 made of an undoped GaN layer grows on the surface of the wafer 25.

Next, after waiting until the wafer temperature reaches 1000° C. to 1100° C., the nitrogen source valve 51, the gallium source valve 52, and the silicon source valve 56 are opened. As a result, ammonia, trimethylgallium, and silane are supplied from the source gas supply passage 40 together with the carrier gas. As a result, the n-type GaN contact layer 32 made of a GaN layer doped with silicon grows on the surface of the wafer 25.

The next step is a step of forming the intermediate buffer layer 33. Specifically, the aluminum material valve 53 and the silicon material valve 56 are closed, and the superlattice structure is grown. The growth of the superlattice structure is performed by opening the nitrogen source valve 51, the gallium source valve 52, and the indium source valve 54 to supply ammonia, trimethylgallium, and trimethylindium to the wafer 25, and growing the InGaN layer. The process of growing the undoped GaN layer by alternately closing the valve 54 and opening the nitrogen source valve 51 and the gallium source valve 52 to supply ammonia and trimethylgallium to the wafer 25 can be performed. it can.

For example, a GaN layer is formed first, and then an InGaN layer is formed thereon. This is repeated 5 times. When forming the intermediate buffer layer 33, the temperature of the wafer 25 is preferably set to, for example, 740° C. to 850° C. (for example, about 780° C.).
The next step is a step of forming the light emitting layer 34. As shown in FIG. 4, the process of forming the light emitting layer 34 includes a blue light emitting layer 17 (having In _y Ga _1-y N (y=0.06 to 0.16) 14(b) at a relatively high temperature. A green color having a In _x Ga _1-x N (x=0.18 to 0.23) layer 14(g) at a first step of forming a stress relaxation layer) and at a temperature relatively lower than the first step. A second step of forming the light emitting layer 16 (main light emitting layer). Further, subsequent to the second step, the step of forming the GaN final barrier layer 15 is performed.

Specifically, in the step of forming the blue light emitting layer 17, the nitrogen source valve 51, the gallium source valve 52, and the indium source valve 54 are opened to supply ammonia, trimethylgallium, and trimethylindium to the wafer 25, and thereby the InGaN layer ( The step of growing the quantum well layer) 14(b), the indium raw material valve 54 is closed, the nitrogen raw material valve 51 and the gallium raw material valve 52 are opened, and ammonia and trimethylgallium are supplied to the wafer 25. This can be performed by alternately performing the step of growing the GaN layer (barrier layer) 13(b).

For example, the GaN layer 13(b) is formed first, and then the InGaN layer 14(b) is formed thereon. This is repeated four times for the same time. When the blue light emitting layer 17 is formed, the temperature of the wafer 25 is preferably set to 770° C. to 830° C., for example. More preferably, as indicated by the solid line of "new structure" in FIG. 4, it is preferable that the wafer temperature be controlled to decrease with the lapse of growth time.

For example, in this embodiment, the wafer temperature is gradually reduced from about 820° C. to about 780° C. By gradually decreasing the temperature of the wafer 25, the plurality of InGaN layers 14(b) in the blue light emitting layer 17 can be stacked in the order in which the In composition ratio (y) increases as the green light emitting layer 16 is closer to the InGaN layer 14(b).
Next, in the step of forming the green light emitting layer 16, similar to the step of forming the blue light emitting layer 17, the step of growing the InGaN layer (quantum well layer) 14 (g) and the undoped GaN layer (barrier layer) 13 are performed. This can be performed by alternately performing the step of growing (g). For example, the GaN layer 13(g) is first formed on the InGaN layer 14(b) formed last in the step of forming the blue light emitting layer 17, and the InGaN layer 14(g) is formed thereon.

After repeating this four times for the same time, the GaN final barrier layer 15 is finally formed on the InGaN layer 14(g). When the green light emitting layer 16 and the GaN final barrier layer 15 are formed, the temperature of the wafer 25 is preferably 700° C. to 770° C., for example.
More preferably, as indicated by the solid line of "new structure" in FIG. 4, the wafer temperature is preferably controlled to be constant even after the growth time has elapsed. For example, in this embodiment, the wafer temperature is controlled to about 760°C. By controlling the constant temperature of the wafer 25, a plurality of InGaN layers 14 (g) in the green light emitting layer 16 can be stacked with a constant In composition ratio (x) in the stacking direction of the group III nitride semiconductor layer 3. ..

The flow rates of the source gases in the step of forming the blue light emitting layer 17 and the step of forming the green light emitting layer 16 may be the same as each other. That is, the boundary between the blue light emitting layer 17 and the green light emitting layer 16 can be easily set by controlling the wafer temperature up and down while the flow rate of the source gas is kept constant. Further, in the blue light emitting layer 17, the In composition ratio (y) of the plurality of InGaN layers 14(b) can be easily changed.

Next, the p-type AlGaN electron blocking layer 35 is formed. That is, the nitrogen raw material valve 51, the gallium raw material valve 52, the aluminum raw material valve 53, and the magnesium raw material valve 55 are opened, and the other valves 54 and 56 are closed.
As a result, ammonia, trimethylgallium, trimethylaluminum, and ethylcyclopentadienylmagnesium are supplied toward the wafer 25, and the p-type AlGaN electron blocking layer 35 formed of an AlGaN layer doped with magnesium is formed. .. When the p-type AlGaN electron blocking layer 35 is formed, the temperature of the wafer 25 is preferably 900° C. to 1100° C. (for example, 970° C.).

Next, the p-type GaN contact layer 36 is formed. That is, the nitrogen source valve 51, the gallium source valve 52, and the magnesium source valve 55 are opened, and the other valves 53, 54, 56 are closed.
As a result, ammonia, trimethylgallium, and ethylcyclopentadienylmagnesium are supplied toward the wafer 25, and the p-type GaN contact layer 36 formed of a GaN layer doped with magnesium is formed. When forming the p-type GaN contact layer 36, the temperature of the wafer 25 is preferably 9000° C. to 1100° C. (for example, 950° C.).

When the group III nitride semiconductor layer 3 is grown on the wafer 25 in this manner, the wafer 25 is transferred to an etching apparatus and the n-type GaN contact layer 32 is exposed by plasma etching, for example, as shown in FIG. The concave portion 4 for forming the concave portion is formed.
The recess 4 may be formed so as to surround the intermediate buffer layer 33, the light emitting layer 34, the p-type AlGaN electron blocking layer 35, and the p-type GaN contact layer 36 in an island shape, whereby the intermediate buffer layer 33, the light emitting layer. 34, the p-type AlGaN electron blocking layer 35, and the p-type GaN contact layer 36 may be shaped into a mesa.

Next, the p-type electrode 6 and the n-type electrode 7 are formed by resistance heating or a metal vapor deposition device using an electron beam. As a result, the structure of the light emitting diode 1 shown in FIG. 1 can be obtained.
After such a wafer process, an individual element is cut out by cleaving the wafer 25, the individual element is connected to a lead electrode by die bonding and wire bonding, and then sealed in a transparent resin such as an epoxy resin. .. Thus, the package of the light emitting diode 1 is manufactured.

As described above, according to the light emitting diode 1, the blue light emitting layer 17 having the In composition ratio (y) relatively close to the In composition ratio (x) of the green light emitting layer 16 as the main light emitting layer of the light emitting layer 34 is provided. A part of the light emitting layer 34 is configured together with the green light emitting layer 16.
Thus, when the light emitting layer 34 is crystal-grown on the sapphire substrate 2, the blue light emitting layer 17 is first grown, and then the green light emitting layer 16 is grown, so that the lattice size at the start of growth of the green light emitting layer 16 is controlled. Changes can be moderated. Therefore, the introduction of lattice defects into the green light emitting layer 16 can be reduced.

As a result, the light emitting diode 1 can efficiently generate light having a peak emission wavelength of 500 nm or more in the green light emitting layer 16. Due to this improvement in light emission efficiency, it is possible to suppress a decrease in luminance in a long wavelength region (for example, a wavelength region of 525 nm or more).
Further, in this embodiment, in the blue light emitting layer 17, the In composition ratio (y) increases as the plurality of InGaN layers 14 (b) are closer to the green light emitting layer 16 in the stacking direction of the group III nitride semiconductor layers 3. They are stacked in the following order.

Therefore, the In composition ratio (y) of the InGaN layer 14(b) can be gradually brought close to the In composition ratio (x) of the InGaN layer 14(g) of the green light emitting layer 16. As a result, the difference in lattice size at the boundary between the blue light emitting layer 17 and the green light emitting layer 16 can be reduced, so that the introduction of lattice defects into the green light emitting layer 16 can be further reduced.
Further, in this embodiment, the blue light emitting layer 17 and the green light emitting layer 16 are laminated so as to be in contact with each other, and a Group III nitride semiconductor different from the layers 16 and 17 is provided at the boundary between the layers 16 and 17. Is not interposed.

That is, since the blue light emitting layer 17 and the green light emitting layer 16 are integrated into one laminated structure, it is possible to reduce the variation in the lattice size in the portion of the light emitting layer 34 where the laminated structure is formed. Specifically, the In composition ratio of the laminated structure is 0.06 which is the lower limit of the In composition ratio (y) of the blue light emitting layer 17 to 0 which is the upper limit of the In composition ratio (x) of the green light emitting layer 16. It can be distributed in the range of up to 0.23.

Further, in this embodiment, the intermediate buffer layer 33 having an InGaN layer represented by In _z Ga _1-z N (z=0.01 to 0.05) is formed as a base layer of the light emitting layer 34. Therefore, when the light emitting layer 34 is crystal-grown on the sapphire substrate 2, by growing the intermediate buffer layer 33 prior to the growth of the light emitting layer 34, the lattice size at the start of the growth of the light emitting layer 34 (blue light emitting layer 17). The change in can be moderated. Therefore, the introduction of lattice defects into the blue light emitting layer 17 can be reduced.

Further, in this embodiment, the light emitting layer 34 additionally includes the blue light emitting layer 17 different from the green light emitting layer 16 as the main light emitting layer, but the total thickness of the light emitting layer 34 is 60 nm to 150 nm. It is suppressed. That is, the luminous efficiency of the light emitting diode 1 can be improved while keeping the total thickness of the light emitting layer 34 within a general range.
Furthermore, according to this embodiment, the group III nitride semiconductor layer 3 having the light emitting layer 34 with improved light emitting efficiency as described above can be formed on the sapphire substrate 2. Since it is not necessary to use a special substrate and an inexpensive sapphire substrate is sufficient, the manufacturing cost can be reduced.

Although one embodiment of the present invention has been described above, the present invention can be implemented in other forms.
For example, in the above-described embodiment, the light emitting diode having the group III nitride semiconductor laminated structure having the c-plane, which is a polar plane, as the growth main surface is taken as an example. A diode structure may be formed with a Group III nitride semiconductor laminated structure having a main surface. Furthermore, the light emission efficiency can be improved not only in the polar plane or the non-polar plane but also in the case where the diode structure is formed by the group III nitride semiconductor laminated structure having the semipolar plane as the growth main surface.

Further, in the above-described embodiment, a light emitting diode in which the In composition ratio (y) of the plurality of InGaN layers 14(b) of the blue light emitting layer 17 increases in order toward the green light emitting layer 16 at a constant rate is taken as an example. However, the In composition ratio (y) may be increased at a random ratio (for example, 0.1→0.2→0.4).
Further, in the above-described embodiment, an example in which the present invention is applied to a light emitting diode has been described, but the present invention can also be applied to other types of light emitting elements such as a nitride semiconductor laser element.

In addition, various design changes can be made within the scope of the matters described in the claims.

Next, some characteristics of the light emitting diode according to the present invention were confirmed by performing the following examples.
(1) Backside Luminance A specific experiment was conducted in order to demonstrate the suppression of luminance reduction in the long wavelength region according to the present invention. First, a sample 1 (new structure) in which the group III nitride semiconductor layer 3 was formed on the c-plane of the sapphire single crystal wafer 25 according to the above-described embodiment was produced.

In the blue light emitting layer 17, the InGaN layer 14(b) and the GaN layer 13(b) are 4 pairs, and the In composition ratio (y) is 0.8, 0.11, 0.14, and 0.17 in this order. Increased. Further, in the green light emitting layer 16, the InGaN layer 14 (g) and the GaN layer 13 (g) were 4 pairs, and the In composition ratio (x) was constant at 0.20.
On the other hand, Group III nitriding was performed on the c-plane of the sapphire single crystal wafer 25 by the same method as in Sample 1 except that the light emitting layer 34 was composed only of the green light emitting layer 16 of Sample 1 (InGaN/GaN=8 pairs). A sample 2 (comparative structure) in which the semiconductor layer 3 was formed was produced. Then, the backside brightness of these samples 1 and 2 was measured using a backside prober. Results are shown in FIG.

According to FIG. 5, in the sample 2 (comparative structure) in which the light emitting layer 34 is composed only of the green light emitting layer 16, the back surface luminance at 515 nm is relatively good, but the back surface luminance decreases from that wavelength to 535 nm. The rate was high, and the brightness decreased from about 2.0 to 0.8.
On the other hand, in the sample 1 (new structure) in which the blue light emitting layer 17 is adopted as a part of the light emitting layer 34, in the short wavelength region (515 nm to 525 nm) of the green light wavelength region (500 nm to 550 nm). Although the back surface luminance of No. 2 is inferior to that of Sample 2, the lowering rate of back surface luminance is lower than that of Sample 2.

As a result, in the long wavelength region (525 nm to 540 nm), excellent back surface luminance could be exhibited as compared with Sample 2. In particular, at 540 nm, it was possible to develop a luminance equivalent to that of Sample 2 at 535 nm.
(2) PL spectrum Next, in order to confirm whether a peak emission wavelength of 500 nm or more can be obtained by the light emitting layer of the present invention, the sample 1 (new structure) prepared in (1) was subjected to PL (Photo Luminescence) intensity was measured. For the PL intensity, the PL distribution of Sample 1 was measured to calculate the spectral distribution, and the integrated value obtained by integrating the emission wavelengths of 400 to 600 nm of the spectrum was obtained. The obtained PL integrated intensity spectrum is shown in FIG.

According to FIG. 6, the light with the highest intensity appears near 525 nm (≧500 nm), which shows that the light emitting layer of the present invention can generate green light of 500 nm or more.
In the PL spectrum of FIG. 6, peaks near 415 nm, 440 nm, and 475 nm are lower than the main peak, but these peaks are caused by light emitted from the blue light emitting layer 17. Is considered to be. Since these peaks are noise level peaks, they do not affect the light emission characteristics of the light emitting diode.
(3) EL spectrum Further, in order to confirm that the peak considered to be caused by the blue light emitting layer 17 shown in (2) does not affect the light emitting characteristics of the light emitting diode 1, the following experiment is conducted. It was Specifically, a p-type electrode 6 and an n-type electrode 7 were formed on the sample 1 (new structure) manufactured in (1), and the diode package was further sealed with a transparent resin.

The EL (Electro Luminescence) intensity of the obtained diode package was measured. The EL intensity was obtained by performing EL measurement of the diode package at room temperature for injection currents of 1 mA, 20 mA, and 120 mA to calculate the spectral distribution, and to obtain an integral value obtained by integrating the emission wavelengths of 400 nm to 600 nm of the spectrum. The obtained EL integrated intensity spectra are shown in FIGS. 7 to 9, respectively.

According to FIGS. 7 to 9, almost no peak appeared in the spectrum in the wavelength range of blue light (410 nm to 490 nm) regardless of the magnitude of the injected current. That is, it was found that the light generated in the blue light emitting layer 17 hardly contributes to the light emission of the light emitting diode 1.
In other words, from the results of FIGS. 6 to 9, the green light generated in the InGaN layer 14(g) of the green light emitting layer 16 contributes to the emission wavelength of the light extracted to the outside, while the InGaN of the blue light emitting layer 17 is formed. It was found that the blue light generated in the layer 14(b) does not contribute to the emission wavelength of the light extracted to the outside.

Examples of features extracted from this specification and the drawings are shown below.
[Item 1] A group III nitride semiconductor layer having a laminated structure, which is composed of a group III nitride semiconductor and has at least an n-type layer, a p-type layer, and a light-emitting layer sandwiched between the n-type layer and the p-type layer. And a main light emitting layer having an In _x Ga _1-x N (x=0.18 to 0.23) layer, wherein the light emitting layer emits light having a peak light emission wavelength of 500 nm or more; _A semiconductor light emitting device, comprising: a stress relaxation layer having a _y Ga _1-y N (y=0.06 to 0.16) layer.

According to this structure, the stress relaxation layer having an In composition ratio (y) relatively close to the In composition ratio (x) of the main light emitting layer constitutes a part of the light emitting layer together with the main light emitting layer. Thus, when the light emitting layer is crystal-grown from the n-type layer or the p-type layer side, the stress relaxation layer is first grown, and then the main light emitting layer is grown, whereby the lattice size at the start of growth of the main light emitting layer is increased. The change in can be moderated. Therefore, the introduction of lattice defects into the main light emitting layer can be reduced. As a result, this semiconductor light emitting device can efficiently generate light having a peak emission wavelength of 500 nm or more in the main light emitting layer. This improvement in light emission efficiency can suppress a decrease in luminance in a long wavelength region (for example, a wavelength region of 525 nm or more).

[Claim 2] The stress relaxing layer comprises a plurality of the _In y _{Ga 1-y} N layer, said plurality of _In y _{Ga 1-y} N layer is closer to the main light-emitting layer In composition ratio (y) is Item 2. The semiconductor light emitting device according to item 1, which is stacked in order of increasing size.
According to this structure, the In composition ratio (y) of the stress relaxation layer can be gradually brought close to the In composition ratio (x) of the main light emitting layer. This makes it possible to reduce the difference in lattice size between the main light emitting layer and the stress relaxation layer, so that the introduction of lattice defects into the main light emitting layer can be further reduced.

The In composition ratio (y) of the plurality of In _y Ga _1-y N layers may be increased at a constant rate (for example, 0.1 step, 0.2 step, etc.) or may be random. It may increase in proportion (for example, 0.1→0.2→0.4).
[Item 3] The semiconductor light-emitting device according to item 1 or 2, wherein the main light emitting layer and the stress relaxation layer are laminated so as to be in contact with each other.

According to this structure, since the main light emitting layer and the stress relaxation layer are integrated into one laminated structure, it is possible to reduce variations in the lattice size in the portion of the light emitting layer where the laminated structure is formed.
[Item 4] The light emitting layer has a multiple quantum well structure in which a quantum well layer made of InGaN and a barrier layer made of GaN are alternately laminated at a predetermined cycle. The semiconductor light emitting device according to.

[Item 5] The semiconductor light-emitting device according to item 4, wherein the quantum well layer has a thickness of 3 nm±10%. With this configuration, the luminous efficiency of the semiconductor light emitting device can be further improved.
[Item 6] The semiconductor light emitting element is arranged on the side opposite to the main light emitting layer with respect to the stress relaxation layer, and has an intermediate buffer having a superlattice structure in which InGaN layers and GaN layers are alternately laminated at a predetermined cycle. Item 6. The semiconductor light-emitting device according to any one of items 1 to 5, further including a layer.

[Item 7] The semiconductor light-emitting device according to item 6, wherein the InGaN layer includes a layer represented by In _z Ga _1-z N (z=0.01 to 0.05).
According to this configuration, when the light emitting layer is crystal-grown from the n-type layer or p-type layer side, the intermediate buffer layer is grown prior to the growth of the light emitting layer, so that the growth of the light emitting layer (stress relaxation layer) is started. The change in the lattice size over time can be made gradual. Therefore, the introduction of lattice defects into the stress relaxation layer can be reduced.

[Item 8] The semiconductor light-emitting device according to any one of Items 1 to 7, wherein the light-emitting layer emits light having a peak emission wavelength of 500 nm to 550 nm. According to this structure, it is possible to provide a semiconductor light emitting device having a light emitting layer that efficiently emits green light.
[Item 9] The semiconductor light-emitting device according to any one of items 1 to 8, wherein the light emitting layer has a total thickness of 60 nm to 150 nm. According to this structure, the luminous efficiency of the semiconductor light emitting element can be improved while keeping the total thickness of the light emitting layer within a general range.

[Item 10] The semiconductor light emitting device further includes a sapphire substrate, and the light emitting layer is a layer in which the stress relaxation layer and the main light emitting layer are crystal-grown on a main surface of the sapphire substrate in this order. Item 10. The semiconductor light emitting device according to any one of items 1 to 9.
According to this structure, the group III nitride semiconductor layer having the light emitting layer with improved light emitting efficiency can be formed on the sapphire substrate. Further, since it is not necessary to use a special substrate and an inexpensive sapphire substrate is sufficient, the manufacturing cost can be reduced.

1 Light Emitting Diode 2 Sapphire Substrate 3 Group III Nitride Semiconductor Layer 13(g,b) GaN Layer 14(g,b) InGaN Layer 16 Green Light Emitting Layer 17 Blue Light Emitting Layer 31 n-Type Low Temperature GaN Buffer Layer 32 n-type GaN Contact Layer 33 Intermediate buffer layer 34 Light emitting layer 35 p-type AlGaN electron blocking layer 36 p-type GaN contact layer

Claims (21)

A first conductivity type first semiconductor layer containing GaN;
A light emitting layer formed on the first semiconductor layer;
A second semiconductor layer of a second conductivity type formed on the light emitting layer,
The light emitting layer includes a blue light emitting layer and a green light emitting layer stacked on the blue light emitting layer,
The blue light-emitting layer is a light-emitting layer that emits light having a peak emission wavelength of 410 nm to 490 nm, which is the wavelength of the highest intensity light emitted.
The green light emitting layer is a light emitting layer that emits light having a peak emission wavelength of 500 nm to 550 nm, which is the wavelength of the highest intensity light emitted.
The blue light emitting layer has a multiple quantum well structure in which a GaN layer as a first layer and an InGaN layer as a second layer are alternately laminated for a predetermined period,
The green light emitting layer has a multiple quantum well structure in which a GaN layer that is a third layer and an InGaN layer that is a fourth layer are alternately laminated in the same period as the predetermined period,
The In composition ratio (y) of the InGaN layer that is the second layer of the blue light emitting layer is represented by In _y Ga _1-y N,
When In the composition ratio of (x) of the InGaN layer and the a fourth layer of the green light-emitting _layer, as shown in In _{x Ga 1-x} N, have a relationship of (x)> (y),
The semiconductor light emitting element, wherein the plurality of second layers in the blue light emitting portion are stacked in an order in which the In composition ratio increases at a constant rate as the green light emitting portion is approached . The plurality of second layers in the blue light emitting portion are laminated with a constant thickness,
The semiconductor light emitting device according to claim 1, wherein the plurality of fourth layers in the green light emitting unit are stacked with a constant thickness. The increase ratio of the In composition ratio of the second layer and the fourth layer adjacent to each other between the blue light emitting unit and the green light emitting unit is the same value as the increase ratio of the In composition ratios of the plurality of second layers. The semiconductor light emitting device according to claim 1 , wherein Further comprising a buffer layer Ru GaN Tona of undoped,
Wherein the first semiconductor layer is formed on the buffer layer, a semiconductor light-emitting device according to any one of claims 1-3. A fifth layer containing GaN and a sixth layer containing InGaN are alternately laminated to each other, further including an intermediate buffer layer formed on the first semiconductor layer;
The light-emitting layer, wherein formed on the intermediate buffer layer, a semiconductor light-emitting device according to any one of claims 1-4. The semiconductor light emitting device according to claim 5 , wherein the sixth layer of the intermediate buffer layer has an In composition ratio less than the In composition ratio of the second layer of the blue light emitting unit. The semiconductor light emitting device according to claim 5 or 6 , wherein the sixth layer of the intermediate buffer layer has an In composition ratio of 0.01 to 0.05. Include GaN of undoped, interposed between the light emitting layer and the second semiconductor layer, further comprising a final barrier layer in contact with the fourth layer of the green light emitting unit, one of the claims 1 to 7 one A semiconductor light-emitting device according to item. 9. The semiconductor light emitting device according to claim 8 , comprising AlGaN, and a second conductivity type electron blocking layer interposed between the second semiconductor layer and the final barrier layer. The blue light emitting unit, said first layer comprising a GaN of undoped, and has the second layer comprising InGaN which impurities are added, according to any one of claims 1-9 Semiconductor light emitting device. The green light emitting unit, said third layer comprising GaN of the undoped, and has the fourth layer including an InGaN doped with an impurity, according to any one of claims 1-10 Semiconductor light emitting device. Wherein the plurality of the fourth layer of the green light-emitting portion, wherein are formed a plurality of the same thickness as the second layer according to the blue light-emitting portion, a semiconductor according to any one of claims 1 to 11 Light emitting element. Said second semiconductor layer has a light extraction surface, the semiconductor light-emitting device according to any one of claims 1 to 12. The first semiconductor layer has a light emitting layer outer lead portions led out in the region, the semiconductor light-emitting device according to any one of claims 1 to 13. A first electrode joined to the lead portion of the first semiconductor layer;
The semiconductor light emitting device according to claim 14 , further comprising a second electrode bonded to a surface of the second semiconductor layer. The first electrode is composed of a Ti layer and an Al layer,
The semiconductor light emitting device according to claim 15 , wherein the second electrode is composed of a Ti layer and an Al layer. Further comprising a transparent electrode which is interposed between the second electrode and the second semiconductor layer, a semiconductor light emitting device according to claim 15 or 16. The light emitting layer has a total thickness of 60 nm to 150 nm, the semiconductor light-emitting device according to any one of claims 1 to 17. Further including a transparent substrate,
Wherein the first semiconductor layer, the are formed on a transparent substrate, a semiconductor light-emitting device according to any one of claims 1 to 18. The transparent substrate is composed of a hexagonal substrate and includes a main surface having an off angle of 0.3° or more in the m-axis direction from the plane orientation of the polar plane,
20. The semiconductor light emitting device according to claim 19 , wherein the first semiconductor layer is formed on the main surface of the transparent substrate. The semiconductor light emitting device according to claim 20 , wherein the transparent substrate is a sapphire substrate, a GaN substrate, a ZnO substrate, an AlN substrate, or a SiC substrate.

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