JP2014187159A - Semiconductor light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element which can reduce lattice defects in a light-emitting layer which generates ling having a peak emission wavelength of 500 nm and over.SOLUTION: A light-emitting diode which is composed of a group III nitride semiconductor and includes a group III nitride semiconductor layer 3 of a laminated structure having an n-type GaN contact layer 32, an intermediate buffer layer 33, a light-emitting layer 34, a p-type AlGaN electronic stopping layer 35 and a p-type GaN contact layer 36, in which a green light-emitting layer 16 having an InGaN(x=0.18-0.23) layer 14(g) and a blue light-emitting layer 17 having an InGaN(y=0.06-0.16) layer 14(b) are formed in the light-emitting layer 34.

Description

  The present invention relates to a semiconductor light emitting device (light emitting diode, laser diode, etc.) using a group III nitride semiconductor.

Conventionally, in a group III nitride semiconductor light-emitting device having a light-emitting layer (active layer) sandwiched between an n-type layer and a p-type layer, a buffer is provided on the base layer of the light-emitting layer for the purpose of preventing the occurrence of lattice defects in the light-emitting layer. It is known to arrange the layers.
For example, Patent Document 1 discloses disposing a superlattice layer having an InGaN layer and a GaN layer between an n-type cladding layer and an MQW active layer laminated thereon.

JP 2007-227671 A

The superlattice layer may not be sufficiently relaxed depending on the peak emission wavelength of the light emitting layer. For example, the generation of lattice defects in a light emitting layer having a peak emission wavelength of 500 nm or more cannot be reduced, and a method for such a light emitting layer has not been established yet.
Accordingly, an object of the present invention is to provide a semiconductor light emitting device capable of reducing lattice defects in a light emitting layer that generates light having a peak emission wavelength of 500 nm or more.

  Another object of the present invention is to provide a semiconductor light emitting device capable of suppressing a decrease in luminance in a long wavelength region by reducing lattice defects in the light emitting layer.

In order to achieve the above object, the invention according to claim 1 is made of a group III nitride semiconductor, at least an n-type layer, a p-type layer, and a light emitting layer sandwiched between the n-type layer and the p-type layer And the light emitting layer emits light having a peak emission wavelength of 500 nm or more, and In _x Ga _1-x N (x = 0.18 to 0). .23) a semiconductor light emitting device including a main light emitting layer having a layer and a stress relaxation layer having an In _y Ga _1-y N (y = 0.06 to 0.16) layer.

  According to this configuration, the stress relaxation layer having an In composition ratio (y) that is relatively approximate to the In composition ratio (x) of the main light emitting layer constitutes a part of the light emitting layer together with the main light emitting layer. Accordingly, when the light emitting layer is crystal-grown from the n-type layer or the p-type layer side, the stress relaxation layer is first grown, and then the main light emitting layer is grown. Can be moderated. Therefore, introduction of lattice defects into the main light emitting layer can be reduced. As a result, this semiconductor light emitting device can efficiently generate light having a peak emission wavelength of 500 nm or more in the main light emitting layer. By improving the light emission efficiency, for example, it is possible to suppress a decrease in luminance in a long wavelength region (for example, a wavelength region of 525 nm or more).

According to a second aspect of the present invention, the stress relaxation layer includes a plurality of the In _y Ga _1-y N layers, and the plurality of In _y Ga _1-y N layers are closer to the main light emitting layer. The semiconductor light-emitting element according to claim 1, wherein the semiconductor light-emitting elements are stacked in the order of increasing ratio (y).
According to this configuration, the In composition ratio (y) of the stress relaxation layer can be gradually brought closer to the In composition ratio (x) of the main light emitting layer. Thereby, since the difference in the lattice size between the main light emitting layer and the stress relaxation layer can be reduced, the introduction of lattice defects into the main light emitting layer can be further reduced.

The In composition ratio (y) of the plurality of In _y Ga _1-y N layers may be increased at a constant rate (for example, 0.1 increments, 0.2 increments, etc.) or randomly. The ratio may be increased (for example, 0.1 → 0.2 → 0.4, etc.).
The invention according to claim 3 is the semiconductor light emitting element according to claim 1 or 2, wherein the main light emitting layer and the stress relaxation layer are laminated so as to be in contact with each other.

According to this configuration, since the main light emitting layer and the stress relaxation layer are integrated into one laminated structure, it is possible to reduce the variation in the lattice size in the portion where the laminated structure of the light emitting layer is formed.
Preferably, the light emitting layer has a multiple quantum well structure in which quantum well layers made of InGaN and barrier layers made of GaN are alternately stacked at a predetermined period. . In this case, as in the invention described in claim 5, the quantum well layer preferably has a thickness of 3 nm ± 10%.

With this configuration, the light emission efficiency of the semiconductor light emitting element can be further improved.
As in the invention described in claim 6, the semiconductor light emitting element is disposed on the opposite side of the main light emitting layer with respect to the stress relaxation layer, and an InGaN layer and a GaN layer are alternately stacked at a predetermined period. It is preferable to further include an intermediate buffer layer having a superlattice structure. In this case, the InGaN layer preferably includes a layer represented by In _z Ga _1-z N (z = 0.01 to 0.05).

According to this configuration, when the light emitting layer is crystal-grown from the n-type layer or the p-type layer side, the growth of the light emitting layer (stress relaxation layer) is started by growing the intermediate buffer layer prior to the growth of the light emitting layer. The change in the lattice size at the time can be moderated. Therefore, introduction of lattice defects into the stress relaxation layer can be reduced.
The invention according to claim 8 is the semiconductor light emitting element according to any one of claims 1 to 7, wherein the light emitting layer emits light having a peak emission wavelength in a range of 500 nm to 550 nm. .

According to this configuration, a semiconductor light emitting element having a light emitting layer that efficiently generates green light can be provided.
The invention according to claim 9 is the semiconductor light emitting element according to claim 1, wherein the light emitting layer has a total thickness of 60 nm to 140 nm.
According to this configuration, it is possible to improve the light emission efficiency of the semiconductor light emitting element while keeping the total thickness of the light emitting layer within a general range.

The invention according to claim 10 further includes a sapphire substrate, and the light emitting layer is a layer in which the stress relaxation layer and the main light emitting layer are grown in this order on the main surface of the sapphire substrate. The semiconductor light-emitting device according to any one of Items 1 to 9.
According to this configuration, the group III nitride semiconductor layer having the light emitting layer with improved light emission efficiency can be formed on the sapphire substrate. Further, it is not necessary to use a special substrate, and an inexpensive sapphire substrate is sufficient, so that the manufacturing cost can be reduced.

FIG. 1 is a schematic cross-sectional view for explaining the structure of a light emitting diode according to an embodiment of the present invention. FIG. 2 is a diagram showing a specific configuration of the light emitting layer and a relationship between the depth of the group III nitride semiconductor layer and the In composition. FIG. 3 is a schematic diagram for explaining a configuration of a processing apparatus for growing each layer constituting the group III nitride semiconductor layer. FIG. 4 is a time chart showing the relationship between the growth time of the light emitting layer and the substrate temperature. FIG. 5 is a graph showing the relationship between the dominant wavelength and the back surface luminance of the wafer having the group III nitride semiconductor layer. FIG. 6 is a diagram showing a PL spectrum of a wafer having the group III nitride semiconductor layer. FIG. 7 is a diagram showing an EL spectrum (1 mA) of a diode package having the same structure as that of the light emitting diode. FIG. 8 is a diagram showing an EL spectrum (20 mA) of a diode package having the same structure as that of the light emitting diode. FIG. 9 is a diagram showing an EL spectrum (120 mA) of a diode package having the same structure as that of the light emitting diode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view for explaining the structure of a light emitting diode according to an embodiment of the present invention.
A light-emitting diode 1 as an example of a semiconductor light-emitting device of the present invention has a device body configured by growing a group III nitride semiconductor layer 3 having a group III nitride semiconductor multilayer structure on a sapphire substrate 2. Yes.

  The group III nitride semiconductor layer 3 includes, in order from the sapphire substrate 2 side, an n-type low-temperature GaN buffer layer 31 and an n-type GaN contact layer 32 as an example of the n-type layer of the present invention, an intermediate buffer layer 33, a light emitting layer 34, In addition, the p-type AlGaN electron blocking layer 35 and the p-type GaN contact layer 36 are stacked as an example of the p-type layer of the present invention. The III-nitride semiconductor layer 3 is selectively removed (for example, etched) from the p-type GaN contact layer 36 to a depth at which the n-type GaN contact layer 32 is exposed so that the cross section is substantially rectangular. Is formed. The n-type GaN contact layer 32 has a lead portion 5 drawn from one side of the group III nitride semiconductor layer 3 in the lateral direction along the surface of the sapphire substrate 2.

A p-type electrode (anode electrode) 6 is joined to the surface of the p-type GaN contact layer 36, and an n-type electrode (cathode electrode) 7 is joined to the lead portion 5 of the n-type GaN contact layer 32. ing. Thus, a light emitting diode structure is formed.
The sapphire substrate 2 is bonded to a support substrate (wiring substrate) 8. Wirings 9 and 10 are formed on the surface of the support substrate 8. The p-type electrode 6 and the wiring 9 are connected by a bonding wire 11, and the n-type electrode 7 and the wiring 10 are connected by a bonding wire 12. Further, although not shown, the structure of the light emitting diode 1 and the bonding wires 11 and 12 are sealed with a transparent resin such as an epoxy resin, thereby forming a package of the light emitting diode 1 (diode package). Yes.

  The sapphire substrate 2 is a substrate made of a sapphire single crystal whose main surface is a polar plane (c-plane in this embodiment). Specifically, the main surface of the sapphire substrate 2 is a surface having an off angle of 0.3 ° or more from the plane orientation of the polar surface, more preferably an off angle of 0.3 ° or more in the m-axis direction. Therefore, the growth main surface (surface 3a) of the group III nitride semiconductor layer 3 grown on the sapphire substrate 2 is the same as the main surface of the sapphire substrate 2, that is, a polar surface (c-plane in this embodiment). ). The thickness of the sapphire substrate 2 is preferably 600 μm or more, specifically, 650 μm to 1000 μm. In the light emitting diode 1, instead of the sapphire substrate 2, a hexagonal substrate such as a GaN substrate, a ZnO substrate, an AlN substrate, or a SiC substrate can be used.

The n-type low-temperature GaN buffer layer 31 is composed of, for example, an undoped (undoped dopant) GaN layer grown at a wafer temperature of 400 ° C. to 700 ° C. The layer thickness is preferably several tens of nm.
The n-type GaN contact layer 32 is made of, for example, an n-type GaN layer to which silicon is added as an n-type dopant. The layer thickness is preferably 3 μm or more, specifically 3 μm to 7 μm. The doping concentration of silicon is, for example, about 1 × 10 ¹⁸ cm ⁻³ .

The intermediate buffer layer 33 has a superlattice structure in which, for example, an InGaN layer doped with silicon (for example, about 4 nm thick) and a GaN layer (for example, about 2 nm thick) are alternately stacked in a predetermined cycle (for example, about 5 cycles). Yes. Furthermore, in this embodiment, the InGaN layer is a layer represented by In _z Ga _1-z N (z = 0.01 to 0.05), and the GaN layer is a layer that does not contain In at all. The GaN layer may contain some In in a range smaller than the In composition ratio (z) of the InGaN layer of the intermediate buffer layer 33.

  The light emitting layer 34 has, for example, a multiple quantum well (MQW) structure in which an InGaN layer 14 (quantum well layer) doped with silicon and a GaN layer 13 (barrier layer) are alternately stacked in a predetermined cycle. Yes. Further, the light emitting layer 34 has a GaN final barrier layer 15 (for example, about 10 nm thick) between the multiple quantum well structure composed of the InGaN layer 14 and the GaN layer 13 and the p-type AlGaN electron blocking layer 35. The GaN final barrier layer 15 is made of, for example, an undoped (undoped dopant) GaN layer.

The p-type AlGaN electron blocking layer 35 is made of, for example, an AlGaN layer to which magnesium as a p-type dopant is added. The layer thickness is preferably 3 nm or more, specifically 5 nm to 30 nm. The doping concentration of magnesium is, for example, about 3 × 10 ¹⁹ cm ⁻³ .
The p-type GaN contact layer 36 is made of, for example, a GaN layer to which magnesium as a p-type dopant is added at a high concentration. The layer thickness is preferably 0.1 μm or more, specifically 0.2 μm to 0.5 μm. The doping concentration of magnesium is, for example, about 10 ²⁰ cm ⁻³ . The surface of the p-type GaN contact layer 36 forms the surface 3a of the group III nitride semiconductor layer 3, and this surface 3a is a mirror surface. The surface 3a is a light extraction side surface from which light generated in the light emitting layer 34 is extracted.

  The p-type electrode 6 and the n-type electrode 7 are films composed of, for example, a Ti layer and an Al layer. A transparent electrode for anode contact may be formed between the p-type electrode 6 and the p-type GaN contact layer 36 over almost the entire surface 3 a of the group III nitride semiconductor layer 3. Such a transparent electrode can be composed of, for example, a transparent thin metal layer composed of a Ni layer and an Au layer, a ZnO layer, or the like.

FIG. 2 is a diagram showing a specific configuration of the light emitting layer 34 and a relationship between the depth of the group III nitride semiconductor layer 3 and the In composition.
The light emitting layer 34 generates light having a peak emission wavelength of 500 nm or more, and preferably generates light having a peak emission wavelength in the range of 500 nm to 550 nm. Here, the peak emission wavelength refers to the wavelength of the light having the highest intensity (main peak) among the light emitted from the light emitting layer 34, and is a wavelength corresponding to the peak value of the spectrum distribution of the emitted light. is there. Therefore, even if the peak of the noise level appears in addition to the maximum peak in the spectrum distribution, the peak emission wavelength of the noise level is not included in the “peak emission wavelength” in this embodiment.

  The light emitting layer 34 includes a green light emitting layer 16 as an example of the main light emitting layer of the present invention and a blue light emitting layer 17 as an example of the stress relaxation layer of the present invention. Of these two light emitting layers 16 and 17, the green light emitting layer 16 mainly generates light emitted from the light emitting layer 34, and emits light having a peak light emission wavelength of 500 nm or more (specifically, 500 nm to 550 nm). generate. On the other hand, the blue light emitting layer 17 generates light having a peak light emission wavelength of 410 nm to 490 nm, but its intensity is weak and is a noise level with respect to the entire light emitted from the light emitting layer 34. Therefore, the light emission characteristics of the light emitting diode 1 are hardly affected by the light generated in the blue light emitting layer 17.

In this embodiment, the green light emitting layer 16 and the blue light emitting layer 17 are arranged on the side close to the surface 3a (light extraction side surface) of the group III nitride semiconductor layer 3, and the blue light emitting layer 17 is green. It arrange | positions on the opposite side (side near the sapphire substrate 2) with respect to the light emitting layer 16, and these are laminated | stacked so that these may mutually contact.
As described above, each of the green light emitting layer 16 and the blue light emitting layer 17 has a multiple quantum well structure in which InGaN layers 14 (g, b) and GaN layers 13 (g, b) are alternately stacked at a predetermined period. Yes. For example, in the green light emitting layer 16 and the blue light emitting layer 17, the InGaN layer 14 (g, b) and the GaN layer 13 (g, b) may be laminated at the same period. In this embodiment, in the green light emitting layer 16, the InGaN layer 14 (g) and the GaN layer 13 (g) are laminated in four periods (4 pairs). Also in the blue light emitting layer 17, the InGaN layer 14 (b) and the GaN layer 13 (b) are laminated in four periods (four pairs).

Also, the green emitting layer 16, a layer InGaN layer 14 (g) is represented by _{In x Ga 1-x N (} x = 0.18~0.23), GaN layer 13 (g) is the In It is a layer that does not contain at all. In this embodiment, the plurality of InGaN layers 14 (g) have a constant In composition ratio (x) in the stacking direction of the group III nitride semiconductor layer 3. For example, as shown on the right side of FIG. 2, the In composition ratios (x) of the four InGaN layers 14 (g) are all 0.2 (20%). The plurality of InGaN layers 14 (g) may be stacked in the order in which the In composition ratio (x) changes in the stacking direction of the group III nitride semiconductor layer 3. For example, the layers may be stacked in the order in which the In composition ratio (x) increases or decreases with increasing distance from the blue light-emitting layer 17.

On the other hand, in the blue light-emitting layer 17, the InGaN layer 14 (b) is a layer represented by In _y Ga _1-y N (y = 0.06 to 0.16), and the GaN layer 13 (b) It is a layer that does not contain at all. In this embodiment, the plurality of InGaN layers 14 (b) are stacked in the order in which the In composition ratio (y) increases as the green light emitting layer 16 is closer in the stacking direction of the group III nitride semiconductor layer 3. For example, as shown on the right side of FIG. 2, the In composition ratios (y) of the four InGaN layers 14 (b) are 0.8 (8%) and 0.11 (11) in order toward the green light emitting layer 16. %), 0.14 (14%), and 0.17 (17%), which increase at a constant rate (in this embodiment, in increments of 0.3). Furthermore, in this embodiment, the difference (xy) in the In composition ratio between the InGaN layer 14 (g) of the green light emitting layer 16 and the InGaN layer 14 (b) of the blue light emitting layer 17 adjacent to each other is determined by a plurality of InGaN. It is the same value as the constant increase rate of the In composition ratio (y) of the layer 14 (b). That is, in this embodiment, the In composition ratio (xy) is 0.2−0.17 = 0.3, and this value is the same value as the above-described constant increase ratio 0.3. . Thereby, the change in the lattice size in the light emitting layer 34 can be moderated even at the boundary between the blue light emitting layer 17 and the green light emitting layer 16.

Regarding the thickness of the light emitting layer 34, the total thickness (total thickness) of the light emitting layer 34 including the green light emitting layer 16 and the blue light emitting layer 17 is, for example, 60 nm to 150 nm.
Regarding the thickness of each layer 16, 17, the green light emitting layer 16 has an InGaN layer (quantum well layer) 14 (g) of about 3 nm ± 10% (that is, 2.7 nm to 3.3 nm), and a GaN layer ( (Barrier layer) 13 (g) is about 14 nm thick. In the blue light emitting layer 17, the InGaN layer (quantum well layer) 14 (b) has a thickness of about 3 ± 10% nm, and the GaN layer (barrier layer) 13 (b) has a thickness of about 14 nm. In addition, in both the green light emitting layer 16 and the blue light emitting layer 17, the plurality of InGaN layers 14 (g, b) and the GaN layer 13 (g, b) may have a constant thickness with each other, or a group III nitride It may change in the stacking direction of the semiconductor layer 3. In this embodiment, the thickness of the plurality of InGaN layers 14 (g, b) and the GaN layer 13 (g, b) is constant.

FIG. 3 is a schematic diagram for explaining a configuration of a processing apparatus for growing each layer constituting the group III nitride semiconductor layer 3. FIG. 4 is a time chart showing the relationship between the growth time of the light emitting layer 34 and the substrate temperature.
As shown in FIG. 3, a susceptor 22 having a heater 21 is disposed in a processing chamber 20 of the processing apparatus. The susceptor 22 is coupled to a rotation shaft 23, and the rotation shaft 23 is rotated by a rotation drive mechanism 24 disposed outside the processing chamber 20. Thus, by holding the wafer 25 to be processed on the susceptor 22, the temperature of the wafer 25 can be raised to a predetermined temperature in the processing chamber 20 and can be rotated. The wafer 25 is a sapphire single crystal wafer constituting the sapphire substrate 2 described above.

An exhaust pipe 26 is connected to the processing chamber 20. The exhaust pipe 26 is connected to exhaust equipment such as a rotary pump. As a result, the pressure in the processing chamber 20 is set to 1/10 atm to normal pressure (preferably about 1/5 atm), and the atmosphere in the processing chamber 20 is always exhausted.
On the other hand, a raw material gas supply path 40 for supplying a raw material gas toward the surface of the wafer 25 held by the susceptor 22 is introduced into the processing chamber 20. The source gas supply path 40 includes a nitrogen source pipe 41 for supplying ammonia as a nitrogen source gas, a gallium source pipe 42 for supplying trimethylgallium (TMG) as a gallium source gas, and trimethylaluminum as an aluminum source gas. An aluminum source pipe 43 for supplying (TMAl), an indium source pipe 44 for supplying trimethylindium (TMIn) as an indium source gas, and ethylcyclopentadienylmagnesium (EtCp ₂ Mg) as a magnesium source gas are supplied. A magnesium raw material pipe 45 and a silicon raw material pipe 46 for supplying silane (SiH ₄ ) as a silicon raw material gas are connected. Valves 51 to 56 are interposed in these raw material pipes 41 to 46, respectively. Each source gas is supplied together with a carrier gas composed of hydrogen, nitrogen, or both.

  In order to grow the group III nitride semiconductor layer 3 on the sapphire substrate 2, for example, a sapphire single crystal wafer having a c-plane as a main surface is held on the susceptor 22 as a wafer 25. In this state, the valves 52 to 56 are closed, the nitrogen material valve 51 is opened, and the carrier gas and ammonia gas (nitrogen material gas) are supplied into the processing chamber 20. Furthermore, the heater 21 is energized, and the wafer temperature (substrate temperature) is raised to 1000 ° C. to 1100 ° C. (for example, about 1050 ° C.). As a result, the group III nitride semiconductor can be grown without causing the surface of the wafer 25 to become rough.

Next, after setting the wafer temperature to be 400 ° C. to 700 ° C., the nitrogen material valve 51 and the gallium material valve 52 are opened. Thus, ammonia and trimethylgallium are supplied from the source gas supply path 40 together with the carrier gas. As a result, a low temperature GaN buffer layer 31 made of an undoped GaN layer grows on the surface of the wafer 25.
Next, after waiting until the wafer temperature reaches 1000 ° C. to 1100 ° C., the nitrogen material valve 51, the gallium material valve 52, and the silicon material valve 56 are opened. As a result, ammonia, trimethylgallium and silane are supplied from the source gas supply path 40 together with the carrier gas. As a result, an n-type GaN contact layer 32 made of a GaN layer doped with silicon grows on the surface of the wafer 25.

  The next step is a step of forming the intermediate buffer layer 33. Specifically, the aluminum material valve 53 and the silicon material valve 56 are closed, and the superlattice structure is grown. The growth of the superlattice structure includes the steps of growing an InGaN layer by opening the nitrogen source valve 51, the gallium source valve 52 and the indium source valve 54 and supplying ammonia, trimethylgallium and trimethylindium to the wafer 25, The step of growing the undoped GaN layer is performed alternately by closing the valve 54 and opening the nitrogen source valve 51 and the gallium source valve 52 to supply ammonia and trimethylgallium to the wafer 25. it can. For example, a GaN layer is formed first, and an InGaN layer is formed thereon. Repeat this 5 times. When the intermediate buffer layer 33 is formed, the temperature of the wafer 25 is preferably 740 ° C. to 850 ° C. (for example, about 780 ° C.).

The next step is a step of forming the light emitting layer 34. As shown in FIG. 4, the process of the light emitting layer 34 is a blue light emitting layer 17 (including In _y Ga _1-y N (y = 0.06 to 0.16) 14 (b) at a relatively high temperature. A first step of forming a stress relaxation layer) and a green color having an In _x Ga _1-x N (x = 0.18 to 0.23) layer 14 (g) at a temperature relatively lower than that of the first step. A second step of forming the light emitting layer 16 (main light emitting layer). Further, following the second step, a step of forming the GaN final barrier layer 15 is performed.

  Specifically, the blue light emitting layer 17 is formed by opening the nitrogen source valve 51, the gallium source valve 52, and the indium source valve 54 to supply ammonia, trimethylgallium, and trimethylindium to the wafer 25, whereby the InGaN layer ( (Quantum well layer) 14 (b), the indium source valve 54 is closed, the nitrogen source valve 51 and the gallium source valve 52 are opened, and ammonia and trimethylgallium are supplied to the wafer 25. The step of growing the GaN layer (barrier layer) 13 (b) can be performed alternately. For example, the GaN layer 13 (b) is formed first, and the InGaN layer 14 (b) is formed thereon. This is repeated four times at the same time. When the blue light emitting layer 17 is formed, the temperature of the wafer 25 is preferably 770 ° C. to 830 ° C., for example. More preferably, as indicated by the solid line of the “new structure” in FIG. 4, it is preferable that the wafer temperature be controlled so as to decrease as the growth time elapses. For example, in this embodiment, the wafer temperature is gradually reduced from a wafer temperature of about 820 ° C. to a wafer temperature of about 780 ° C. By the step-down temperature of the wafer 25, the plurality of InGaN layers 14 (b) in the blue light emitting layer 17 can be stacked in the order in which the In composition ratio (y) increases as the green light emitting layer 16 is closer.

  Next, the green light emitting layer 16 forming step is similar to the blue light emitting layer 17 forming step, in which an InGaN layer (quantum well layer) 14 (g) is grown and an additive-free GaN layer (barrier layer) 13. The step of growing (g) can be performed alternately. For example, the GaN layer 13 (g) is formed first on the InGaN layer 14 (b) formed last in the blue light emitting layer 17 formation step, and the InGaN layer 14 (g) is formed thereon. This is repeated four times for the same time, and finally, the GaN final barrier layer 15 is formed on the InGaN layer 14 (g). When the green light emitting layer 16 and the GaN final barrier layer 15 are formed, the temperature of the wafer 25 is preferably set to 700 ° C. to 770 ° C., for example. More preferably, as shown by the solid line of “new structure” in FIG. 4, it is preferable that the wafer temperature is controlled to be constant even when the growth time has elapsed. For example, in this embodiment, the wafer temperature is controlled to about 760 ° C. By controlling the temperature of the wafer 25 at a constant temperature, a plurality of InGaN layers 14 (g) can be stacked in the green light emitting layer 16 at a constant In composition ratio (x) in the stacking direction of the group III nitride semiconductor layer 3. .

  The flow rates of the source gases in the blue light emitting layer 17 forming process and the green light emitting layer 16 forming process may be the same. That is, the boundary between the blue light emitting layer 17 and the green light emitting layer 16 can be easily set by controlling the wafer temperature up and down while keeping the flow rate of the source gas constant. Further, in the blue light emitting layer 17, the In composition ratio (y) of the plurality of InGaN layers 14 (b) can be easily changed.

  Next, the p-type AlGaN electron blocking layer 35 is formed. That is, the nitrogen material valve 51, the gallium material valve 52, the aluminum material valve 53, and the magnesium material valve 55 are opened, and the other valves 54 and 56 are closed. As a result, ammonia, trimethylgallium, trimethylaluminum, and ethylcyclopentadienylmagnesium are supplied toward the wafer 25, and a p-type AlGaN electron blocking layer 35 made of an AlGaN layer doped with magnesium is formed. . When the p-type AlGaN electron blocking layer 35 is formed, the temperature of the wafer 25 is preferably set to 900 ° C. to 1100 ° C. (for example, 970 ° C.).

  Next, the p-type GaN contact layer 36 is formed. That is, the nitrogen material valve 51, the gallium material valve 52, and the magnesium material valve 55 are opened, and the other valves 53, 54, and 56 are closed. As a result, ammonia, trimethylgallium and ethylcyclopentadienylmagnesium are supplied toward the wafer 25, and a p-type GaN contact layer 36 composed of a GaN layer doped with magnesium is formed. When forming the p-type GaN contact layer 36, the temperature of the wafer 25 is preferably 9000 ° C. to 1100 ° C. (for example, 950 ° C.).

  When the group III nitride semiconductor layer 3 is thus grown on the wafer 25, the wafer 25 is transferred to an etching apparatus, and the n-type GaN contact layer 32 is exposed by plasma etching, for example, as shown in FIG. A recess 4 is formed for the purpose. The recess 4 may be formed so as to surround the intermediate buffer layer 33, the light emitting layer 34, the p-type AlGaN electron blocking layer 35, and the p-type GaN contact layer 36 in an island shape, whereby the intermediate buffer layer 33, the light emitting layer 34, the p-type AlGaN electron blocking layer 35 and the p-type GaN contact layer 36 may be shaped into a mesa shape.

Next, the p-type electrode 6 and the n-type electrode 7 are formed by a metal vapor deposition apparatus using resistance heating or an electron beam. Thereby, the light emitting diode 1 structure shown in FIG. 1 can be obtained.
After such a wafer process, individual elements are cut out by cleaving the wafer 25, and the individual elements are connected to lead electrodes by die bonding and wire bonding, and then sealed in a transparent resin such as an epoxy resin. . Thus, a package of the light emitting diode 1 is manufactured.

As described above, according to the light emitting diode 1, the blue light emitting layer 17 having an In composition ratio (y) that is relatively approximate to the In composition ratio (x) of the green light emitting layer 16 as the main light emitting layer of the light emitting layer 34. A part of the light emitting layer 34 is formed together with the green light emitting layer 16.
Thus, when the light emitting layer 34 is crystal-grown on the sapphire substrate 2, the blue light emitting layer 17 is first grown, and then the green light emitting layer 16 is grown, whereby the lattice size at the start of the growth of the green light emitting layer 16 is increased. Change can be moderated. Therefore, introduction of lattice defects into the green light emitting layer 16 can be reduced. As a result, the light emitting diode 1 can efficiently generate light having a peak emission wavelength of 500 nm or more in the green light emitting layer 16. By improving the light emission efficiency, for example, it is possible to suppress a decrease in luminance in a long wavelength region (for example, a wavelength region of 525 nm or more).

  In this embodiment, in the blue light emitting layer 17, the In composition ratio (y) increases as the plurality of InGaN layers 14 (b) are closer to the green light emitting layer 16 in the stacking direction of the group III nitride semiconductor layer 3. Are stacked in the order Therefore, the In composition ratio (y) of the InGaN layer 14 (b) can be gradually brought closer to the In composition ratio (x) of the InGaN layer 14 (g) of the green light emitting layer 16. Thereby, since the difference in lattice size at the boundary between the blue light emitting layer 17 and the green light emitting layer 16 can be reduced, the introduction of lattice defects into the green light emitting layer 16 can be further reduced.

  In this embodiment, the blue light-emitting layer 17 and the green light-emitting layer 16 are stacked so as to be in contact with each other, and a group III nitride semiconductor different from the layers 16 and 17 is formed at the boundary between the layers 16 and 17. There is no intervening layer. That is, since the blue light emitting layer 17 and the green light emitting layer 16 are integrated into one laminated structure, the variation in the lattice size in the portion where the laminated structure of the light emitting layer 34 is formed can be reduced. Specifically, the In composition ratio in the stacked structure is from 0.06, which is the lower limit of the In composition ratio (y) of the blue light emitting layer 17, to 0, which is the upper limit of the In composition ratio (x) of the green light emitting layer 16. .23 can be distributed within the range.

In this embodiment, an intermediate buffer layer 33 having an InGaN layer represented by In _z Ga _1-z N (z = 0.01 to 0.05) is formed as a base layer of the light emitting layer 34. Therefore, when the light emitting layer 34 is crystal-grown on the sapphire substrate 2, the growth of the light emitting layer 34 (blue light emitting layer 17) is started by growing the intermediate buffer layer 33 prior to the growth of the light emitting layer 34. Can be moderated. Therefore, introduction of lattice defects into the blue light emitting layer 17 can be reduced.

In this embodiment, the light emitting layer 34 additionally includes a blue light emitting layer 17 different from the green light emitting layer 16 as the main light emitting layer, but the total thickness of the light emitting layer 34 is 60 nm to 150 nm. It is suppressed. That is, the light emission efficiency of the light emitting diode 1 can be improved while keeping the total thickness of the light emitting layer 34 within a general range.
Furthermore, according to this embodiment, the group III nitride semiconductor layer 3 having the light emitting layer 34 with improved light emission efficiency can be formed on the sapphire substrate 2 as described above. It is not necessary to use a special substrate, and an inexpensive sapphire substrate is sufficient, so that the manufacturing cost can be reduced.

As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the above-described embodiment, the light emitting diode having a group III nitride semiconductor multilayer structure in which the c-plane which is the polar plane is the growth main surface is taken as an example, but the m-plane and the a-plane which are nonpolar planes are grown. The diode structure may be formed of a group III nitride semiconductor multilayer structure as the main surface. Furthermore, not only a polar surface and a nonpolar surface, but also when a diode structure is formed with a group III nitride semiconductor multilayer structure having a semipolar surface as a growth main surface, the light emission efficiency can be improved.

Further, in the above-described embodiment, the light emitting diode in which the In composition ratio (y) of the plurality of InGaN layers 14 (b) of the blue light emitting layer 17 increases in order toward the green light emitting layer 16 is taken as an example. However, the In composition ratio (y) may be increased at a random ratio (for example, 0.1 → 0.2 → 0.4, etc.).
In the above-described embodiment, an example in which the present invention is applied to a light-emitting diode has been described. However, the present invention can also be applied to other types of light-emitting elements such as a nitride semiconductor laser element.

  In addition, various design changes can be made within the scope of matters described in the claims.

Next, several characteristics of the light emitting diode according to the present invention were confirmed by carrying out the following examples.
(1) Back surface brightness In order to demonstrate the suppression of the decrease in brightness in the long wavelength region according to the present invention, a specific experiment was conducted. First, Sample 1 (new structure) in which the group III nitride semiconductor layer 3 was formed on the c-plane of the sapphire single crystal wafer 25 according to the above-described embodiment was produced. In the blue light emitting layer 17, the InGaN layer 14 (b) and the GaN layer 13 (b) are 4 pairs, and the In composition ratio (y) is in the order of 0.8, 0.11, 0.14, and 0.17. Increased. In the green light emitting layer 16, the InGaN layer 14 (g) and the GaN layer 13 (g) were 4 pairs, and the In composition ratio (x) was constant at 0.20. On the other hand, the group III nitride is formed on the c-plane of the sapphire single crystal wafer 25 in the same manner as in the sample 1 except that the light emitting layer 34 is composed of only the green light emitting layer 16 of the sample 1 (InGaN / GaN = 8 pairs). Sample 2 (comparative structure) in which the physical semiconductor layer 3 was formed was produced. And the back surface brightness | luminance of these samples 1 and 2 was measured using the back surface prober. The results are shown in FIG.

According to FIG. 5, in the sample 2 (comparative structure) in which the light emitting layer 34 is composed of only the green light emitting layer 16, the back surface luminance at 515 nm is relatively good, but the back surface luminance from the wavelength to 535 nm is reduced. The rate was high and the brightness decreased from about 2.0 to 0.8. On the other hand, in the sample 1 (new structure) in which the blue light-emitting layer 17 is adopted as a part of the light-emitting layer 34, in the short wavelength region (515 nm to 525 nm) of the green light wavelength region (500 nm to 550 nm). Although the back surface brightness is inferior to that of sample 2, the reduction rate of the back surface brightness is lower than that of sample 2. As a result, in the long wavelength region (525 nm to 540 nm), it was possible to express the back surface luminance superior to that of the sample 2. In particular, at 540 nm, the luminance equivalent to that at 535 nm of Sample 2 could be expressed.
(2) PL spectrum Next, in order to confirm whether or not the peak emission wavelength of 500 nm or more can be obtained by the light emitting layer of the present invention, the sample 1 (new structure) prepared in (1) was subjected to PL (Photo) at room temperature. Luminescence) intensity was measured. For the PL intensity, the PL distribution of sample 1 was measured to calculate the spectrum distribution, and an integral value obtained by integrating the emission wavelength of the spectrum from 400 nm to 600 nm was obtained. The spectrum of the obtained PL integral intensity is shown in FIG.

According to FIG. 6, the light with the highest intensity appears in the vicinity of 525 nm (≧ 500 nm), which indicates that the light emitting layer of the present invention can generate green light of 500 nm or more. In the PL spectrum of FIG. 6, peaks lower than the main peak appear near 415 nm, 440 nm, and 475 nm, respectively. These peaks are caused by light generated from the blue light emitting layer 17. It is thought that. Since these peaks are noise level peaks, they do not affect the light emission characteristics of the light emitting diode.
(3) EL spectrum Further, in order to confirm that the peak considered to be caused by the blue light emitting layer 17 shown in (2) does not affect the light emission characteristics of the light emitting diode 1, the following experiment was conducted. It was.

Specifically, a p-type electrode 6 and an n-type electrode 7 were formed on the sample 1 (new structure) produced in (1), and a diode package sealed with a transparent resin was produced.
About the obtained diode package, EL (Electro Luminescence) intensity was measured. The EL intensity was obtained by performing EL measurement of the diode package at room temperature for each injection current of 1 mA, 20 mA, and 120 mA to calculate a spectrum distribution, and obtaining an integrated value obtained by integrating the emission wavelength of the spectrum from 400 nm to 600 nm. The obtained spectrum of EL integrated intensity is shown in FIGS.

  According to FIGS. 7 to 9, almost no peak appeared in the spectrum in the wavelength range of blue light (410 nm to 490 nm) regardless of the magnitude of the injection current. That is, it was found that the light generated in the blue light emitting layer 17 hardly contributes to the light emission of the light emitting diode 1.

DESCRIPTION OF SYMBOLS 1 Light emitting diode 2 Sapphire base 3 Group III nitride semiconductor layer 13 (g, b) GaN layer 14 (g, b) InGaN layer 16 Green light emitting layer 17 Blue light emitting layer 31 n-type low-temperature GaN buffer layer 32 n-type GaN contact Layer 33 intermediate buffer layer 34 light emitting layer 35 p-type AlGaN electron blocking layer 36 p-type GaN contact layer

Claims (10)

A group III nitride semiconductor layer comprising a group III nitride semiconductor, comprising at least an n-type layer, a p-type layer, and a light-emitting layer sandwiched between the n-type layer and the p-type layer,
The light emitting layer emits light having a peak emission wavelength of 500 nm or more, and includes a main light emitting layer having an In _x Ga _1-x N (x = 0.18 to 0.23) layer, and In _y Ga _{1. A} semiconductor light emitting device including a stress relaxation layer having a -yN (y = 0.06 to 0.16) layer. The stress relaxation layer includes a plurality of the In _y Ga _1-y N layers,
2. The semiconductor light emitting element according to claim 1, wherein the plurality of In _y Ga _1-y N layers are stacked in an order in which an In composition ratio (y) increases as the main light emitting layer is closer.   The semiconductor light emitting element according to claim 1, wherein the main light emitting layer and the stress relaxation layer are laminated so as to be in contact with each other.   The said light emitting layer has the multiple quantum well structure which laminated | stacked the quantum well layer which consists of InGaN, and the barrier layer which consists of GaN alternately with the predetermined period. Semiconductor light emitting device.   The semiconductor light emitting device according to claim 4, wherein the quantum well layer has a thickness of 3 nm ± 10%.   The semiconductor light emitting device further includes an intermediate buffer layer disposed on a side opposite to the main light emitting layer with respect to the stress relaxation layer and having a superlattice structure in which InGaN layers and GaN layers are alternately stacked at a predetermined period. The semiconductor light-emitting device according to claim 1. The semiconductor light emitting device according to claim 6, wherein the InGaN layer includes a layer represented by In _z Ga _1-z N (z = 0.01 to 0.05).   The said light emitting layer is a semiconductor light emitting element as described in any one of Claims 1-7 which generate | occur | produces the light of the range whose peak light emission wavelengths are 500 nm-550 nm.   The semiconductor light emitting element according to any one of claims 1 to 8, wherein the light emitting layer has a total thickness of 60 nm to 150 nm. The semiconductor light emitting device further includes a sapphire substrate,
10. The semiconductor light emitting element according to claim 1, wherein the light emitting layer is a layer in which the stress relaxation layer and the main light emitting layer are grown in this order on the main surface of the sapphire substrate. .

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