JP6737306B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6737306B2
JP6737306B2 JP2018121620A JP2018121620A JP6737306B2 JP 6737306 B2 JP6737306 B2 JP 6737306B2 JP 2018121620 A JP2018121620 A JP 2018121620A JP 2018121620 A JP2018121620 A JP 2018121620A JP 6737306 B2 JP6737306 B2 JP 6737306B2
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semiconductor element
semiconductor device
semiconductor
hole
insulating sheet
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JP2018148238A (en
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直輝 池田
直輝 池田
浩公 秦
浩公 秦
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

本発明は、例えば大電流のスイッチングに用いられる半導体装置に関する。 The present invention relates to a semiconductor device used for switching a large current, for example.

特許文献１には、チップと、チップを覆う樹脂を備えた半導体装置が開示されている。 Patent Document 1 discloses a semiconductor device including a chip and a resin covering the chip.

特開平０５−０８２６７２号公報Japanese Patent Laid-Open No. 05-082672

複数の半導体素子を搭載する半導体装置では、複数の半導体素子のそれぞれから発生する熱が干渉し、半導体装置の温度が高くなる問題があった。その結果半導体素子が劣化する問題があった。 In a semiconductor device including a plurality of semiconductor elements, there is a problem that heat generated from each of the plurality of semiconductor elements interferes with each other and the temperature of the semiconductor device increases. As a result, there is a problem that the semiconductor element deteriorates.

半導体素子の温度上昇を抑制するために、半導体素子間の距離を大きくすると半導体装置が大型化してしまう問題があった。 If the distance between the semiconductor elements is increased in order to suppress the temperature rise of the semiconductor elements, there is a problem that the semiconductor device becomes larger.

本発明は、上述のような課題を解決するためになされたもので、小型化に好適な、良好な放熱性を有する半導体装置を提供することを目的とする。 The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device suitable for miniaturization and having good heat dissipation.

本願の発明に係る半導体装置は、第１半導体素子と、第２半導体素子と、該第１半導体素子と該第２半導体素子を覆うモールド樹脂と、該第１半導体素子の裏面側に設けられた第１絶縁シートと、該第２半導体素子の裏面側に設けられた第２絶縁シートと、該第１絶縁シートと該第２絶縁シートが対向しつつ接触しない部分を残しつつ、該第１絶縁シートと該第２絶縁シートの端部だけを接続する接続部と、を備えたことを特徴とする。
A semiconductor device according to the invention of the present application is provided on a first semiconductor element, a second semiconductor element, a mold resin that covers the first semiconductor element and the second semiconductor element, and a back surface side of the first semiconductor element. The first insulating sheet, the second insulating sheet provided on the back surface side of the second semiconductor element, and the first insulating sheet while leaving a portion where the first insulating sheet and the second insulating sheet face each other but do not contact each other. It is characterized by comprising a sheet and a connecting portion for connecting only an end portion of the second insulating sheet.

本発明によれば、新しい放熱経路を提供したり、半導体素子間の熱の往来を抑制したりすることで、小型化に好適な、良好な放熱性を有する半導体装置を提供することができる。 According to the present invention, it is possible to provide a semiconductor device having a good heat dissipation property, which is suitable for miniaturization, by providing a new heat dissipation path and suppressing the heat transfer between the semiconductor elements.

実施の形態１に係る半導体装置の断面図である。FIG. 3 is a sectional view of the semiconductor device according to the first embodiment. 半導体素子と第１貫通穴の位置関係を示す平面図である。It is a top view which shows the positional relationship of a semiconductor element and a 1st through-hole. 半導体装置の斜視図である。It is a perspective view of a semiconductor device. ヒートシンクに固定された半導体装置の断面図である。It is sectional drawing of the semiconductor device fixed to the heat sink. 比較例の半導体装置の放熱経路を示す図である。It is a figure which shows the heat dissipation path|route of the semiconductor device of a comparative example. 実施の形態１に係る半導体装置の放熱経路を示す図である。FIG. 3 is a diagram showing a heat dissipation path of the semiconductor device according to the first embodiment. 実施の形態２に係る半導体装置の断面図である。FIG. 6 is a cross-sectional view of the semiconductor device according to the second embodiment. 実施の形態３に係る半導体装置の断面図である。FIG. 9 is a cross-sectional view of the semiconductor device according to the third embodiment. 実施の形態４に係る半導体装置の断面図である。FIG. 11 is a cross-sectional view of the semiconductor device according to the fourth embodiment. 実施の形態５に係る半導体装置の断面図である。FIG. 13 is a cross-sectional view of the semiconductor device according to the fifth embodiment. 実施の形態６に係る半導体装置の断面図である。FIG. 13 is a cross-sectional view of the semiconductor device according to the sixth embodiment. 実施の形態７に係る半導体装置の断面図である。FIG. 14 is a cross-sectional view of the semiconductor device according to the seventh embodiment. 実施の形態８に係る半導体装置の斜視図である。FIG. 11 is a perspective view of a semiconductor device according to an eighth embodiment. 変形例に係る半導体装置の斜視図である。It is a perspective view of the semiconductor device concerning a modification.

本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。 A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置１０の断面図である。半導体装置１０は、半導体素子１２、１４を備えている。半導体素子１２は例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）などの大電流をスイッチングするスイッチング素子である。半導体素子１４は例えば還流ダイオード（Free Wheeling Diode）である。 Embodiment 1.
FIG. 1 is a sectional view of a semiconductor device 10 according to the first embodiment of the present invention. The semiconductor device 10 includes semiconductor elements 12 and 14. The semiconductor element 12 is a switching element such as an IGBT (Insulated Gate Bipolar Transistor) that switches a large current. The semiconductor element 14 is, for example, a free wheeling diode.

半導体素子１２の裏面のコレクタと半導体素子１４の裏面のカソードは、はんだによってフレーム１６に固定されている。半導体素子１２、１４の熱抵抗を下げるために、フレーム１６は例えば銅または銅合金で形成されている。フレーム１６にはめっき処理を施してもよい。 The collector on the back surface of the semiconductor element 12 and the cathode on the back surface of the semiconductor element 14 are fixed to the frame 16 by soldering. In order to reduce the thermal resistance of the semiconductor elements 12 and 14, the frame 16 is made of, for example, copper or a copper alloy. The frame 16 may be plated.

半導体素子１２、１４の裏面に接するフレーム１６には、絶縁シート１８が接している。絶縁シート１８には金属箔２０が接している。金属箔２０の材料は例えば銅である。半導体素子１２の上面のエミッタと半導体素子１４の上面のアノードはワイヤ２２ａで接続されている。半導体素子１４のアノードはワイヤ２２ｂにより、フレーム１６とは別のフレームに接続されている。ワイヤ２２ａ、２２ｂは例えば太線アルミワイヤである。 An insulating sheet 18 is in contact with the frame 16 in contact with the back surfaces of the semiconductor elements 12 and 14. The metal foil 20 is in contact with the insulating sheet 18. The material of the metal foil 20 is, for example, copper. The emitter on the upper surface of the semiconductor element 12 and the anode on the upper surface of the semiconductor element 14 are connected by a wire 22a. The anode of the semiconductor element 14 is connected to a frame different from the frame 16 by the wire 22b. The wires 22a and 22b are thick aluminum wires, for example.

半導体素子１２、１４はモールド樹脂２４で覆われている。フレーム１６の一部と金属箔２０の裏面はモールド樹脂２４の外に露出している。モールド樹脂２４の中から外にリード端子２６が伸びている。モールド樹脂２４の中のリード端子２６には、樹脂ペースト等で制御ＩＣ２８が固定されている。制御ＩＣ２８はワイヤ２２ｃで半導体素子１２のゲートに接続されている。ワイヤ２２ｃは例えば細線金ワイヤである。制御ＩＣ２８は、半導体素子１２のゲートに半導体素子１２のオンオフを切り替える制御信号を伝送する。このように、半導体装置１０は、トランスファーモールド型のパワーモジュールを構成している。 The semiconductor elements 12 and 14 are covered with a mold resin 24. Part of the frame 16 and the back surface of the metal foil 20 are exposed to the outside of the mold resin 24. A lead terminal 26 extends from the inside of the molding resin 24 to the outside. A control IC 28 is fixed to the lead terminal 26 in the molding resin 24 with a resin paste or the like. The control IC 28 is connected to the gate of the semiconductor element 12 by the wire 22c. The wire 22c is, for example, a thin gold wire. The control IC 28 transmits a control signal for switching on/off of the semiconductor element 12 to the gate of the semiconductor element 12. Thus, the semiconductor device 10 constitutes a transfer mold type power module.

モールド樹脂２４の上には金属板３２が設けられている。金属板３２の材料は、放熱性の良い材料であれば特に限定されないが、例えば銅である。金属板３２は、複数の半導体素子の上に位置している。そして、モールド樹脂２４の厚み方向に、金属板３２とモールド樹脂２４を貫く第１貫通穴３４が設けられている。本発明の実施の形態１では、第１貫通穴３４は、金属板３２とモールド樹脂２４に加えて、絶縁シート１８と金属箔２０を貫いている。 A metal plate 32 is provided on the mold resin 24. The material of the metal plate 32 is not particularly limited as long as it has a good heat dissipation property, but is, for example, copper. The metal plate 32 is located on the plurality of semiconductor elements. A first through hole 34 that penetrates the metal plate 32 and the mold resin 24 is provided in the thickness direction of the mold resin 24. In the first embodiment of the present invention, the first through hole 34 penetrates the insulating sheet 18 and the metal foil 20 in addition to the metal plate 32 and the mold resin 24.

図２は、半導体素子と第１貫通穴の位置関係を示す平面図である。モールド樹脂の中には、半導体素子１２、１４に加えて半導体素子４０、４２がある。半導体素子４０、４２は、それぞれＩＧＢＴと還流ダイオードである。半導体素子４０のコレクタと半導体素子４２のカソードがフレーム１７に固定されている。半導体素子４０のエミッタと半導体素子４２のアノードがワイヤ接続されている。したがって、半導体装置１０は、２つのアームを有するレグを構成している。 FIG. 2 is a plan view showing the positional relationship between the semiconductor element and the first through hole. In the mold resin, in addition to the semiconductor elements 12 and 14, there are semiconductor elements 40 and 42. The semiconductor elements 40 and 42 are an IGBT and a free wheeling diode, respectively. The collector of the semiconductor element 40 and the cathode of the semiconductor element 42 are fixed to the frame 17. The emitter of the semiconductor element 40 and the anode of the semiconductor element 42 are wire-connected. Therefore, the semiconductor device 10 constitutes a leg having two arms.

第１貫通穴３４は、平面視で、複数の半導体素子の間に設けられている。具体的には、第１貫通穴３４は、半導体素子１２と半導体素子４０の間に設けられている。ところで、金属板３２は、モールド樹脂２４の中で特に高温になりやすい場所の上に設ける。特に高温になりやすい場所とは、本発明の実施の形態１では、半導体素子１２と半導体素子４０の間である。したがって、金属板３２は、少なくとも半導体素子１２と半導体素子４０の間の直上に設ける。しかし、金属板３２は放熱性を高める機能を有するので、半導体素子間の上だけでなく、半導体素子が形成された領域全体の上に設けることが好ましい。具体的には、半導体素子１２、１４、４０、４２が形成された領域全体の上に金属板３２を設けることが好ましい。 The first through hole 34 is provided between the plurality of semiconductor elements in plan view. Specifically, the first through hole 34 is provided between the semiconductor element 12 and the semiconductor element 40. By the way, the metal plate 32 is provided on a portion of the mold resin 24 where the temperature is particularly high. In the first embodiment of the present invention, the particularly high temperature place is between the semiconductor element 12 and the semiconductor element 40. Therefore, the metal plate 32 is provided at least directly between the semiconductor element 12 and the semiconductor element 40. However, since the metal plate 32 has a function of improving heat dissipation, it is preferable to provide the metal plate 32 not only between the semiconductor elements but also over the entire region where the semiconductor elements are formed. Specifically, it is preferable to provide the metal plate 32 over the entire region where the semiconductor elements 12, 14, 40, 42 are formed.

図３は、半導体装置の斜視図である。第１貫通穴３４はモールド樹脂２４のほぼ中央に設けられている。図４は、ヒートシンクに固定された半導体装置の断面図である。ヒートシンク５０は、平坦部５０ａと平坦部５０ａに接続されたフィン部分５０ｂを備えている。ヒートシンク５０にはねじ穴５０ｃが設けられている。半導体装置は、このねじ穴５０ｃに挿入されたねじ５２によってヒートシンク５０に固定されている。ねじ５２の頭部は金属板３２と接触している。ねじ５２の軸部（ねじ山が刻まれた部分）は第１貫通穴３４を通りねじ穴５０ｃに螺合されている。 FIG. 3 is a perspective view of the semiconductor device. The first through hole 34 is provided substantially in the center of the mold resin 24. FIG. 4 is a cross-sectional view of the semiconductor device fixed to the heat sink. The heat sink 50 includes a flat portion 50a and a fin portion 50b connected to the flat portion 50a. The heat sink 50 is provided with a screw hole 50c. The semiconductor device is fixed to the heat sink 50 by the screws 52 inserted in the screw holes 50c. The head of the screw 52 is in contact with the metal plate 32. The shaft portion of the screw 52 (the portion on which the thread is engraved) passes through the first through hole 34 and is screwed into the screw hole 50c.

半導体装置１０がヒートシンク５０にねじ止めされた状態では、半導体装置の裏面に露出した金属箔２０が、金属箔２０とヒートシンク５０の間に設けられたグリスを介してヒートシンク５０に接する。 When the semiconductor device 10 is screwed to the heat sink 50, the metal foil 20 exposed on the back surface of the semiconductor device contacts the heat sink 50 via the grease provided between the metal foil 20 and the heat sink 50.

ここで、本発明の実施の形態１に係る半導体装置の特徴の理解を容易にするために、比較例について説明する。図５は、比較例の半導体装置の放熱経路を示す図である。比較例の半導体装置は、図１の半導体装置とほぼ同じであるが、第１貫通穴３４がない点で図１の半導体装置と異なる。比較例の半導体装置の放熱経路としては、半導体素子から、フレーム、絶縁シート、金属箔、及びグリスを経由してヒートシンクに至る第１経路と、半導体素子からモールド樹脂を介して金属板に至る第２経路がある。 Here, a comparative example will be described in order to facilitate understanding of the features of the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a diagram showing a heat dissipation path of the semiconductor device of the comparative example. The semiconductor device of the comparative example is almost the same as the semiconductor device of FIG. 1, but is different from the semiconductor device of FIG. 1 in that the first through hole 34 is not provided. As the heat dissipation path of the semiconductor device of the comparative example, the first path from the semiconductor element to the heat sink via the frame, the insulating sheet, the metal foil, and the grease, and the first path from the semiconductor element to the metal plate via the mold resin. There are two routes.

図６は、本発明の実施の形態１に係る半導体装置の放熱経路を示す図である。本発明の実施の形態１に係る半導体装置の放熱経路としては、前述の第１経路と第２経路に加えて、半導体素子から、モールド樹脂２４、金属板３２及びねじ５２を経由してヒートシンク５０に至る第３経路がある。したがって、従って比較例の半導体装置にはない第３経路により半導体装置の放熱性を高めることができる。第３経路は半導体装置に第１貫通穴３４を開けて簡単に形成できるので、半導体装置を大型化する必要はない。よって、実施の形態１の半導体装置は小型化に好適である。 FIG. 6 is a diagram showing heat dissipation paths of the semiconductor device according to the first embodiment of the present invention. As the heat dissipation path of the semiconductor device according to the first embodiment of the present invention, in addition to the first path and the second path described above, the heat sink 50 from the semiconductor element via the mold resin 24, the metal plate 32 and the screw 52. There is a third route to. Therefore, the heat dissipation of the semiconductor device can be improved by the third path which is not provided in the semiconductor device of the comparative example. Since the third path can be easily formed by opening the first through hole 34 in the semiconductor device, it is not necessary to upsize the semiconductor device. Therefore, the semiconductor device of the first embodiment is suitable for downsizing.

第１貫通穴３４は、第１貫通穴がない場合に、複数の半導体素子の熱干渉によって温度が最大となる場所に形成することが好ましい。温度が最大となる場所に第１貫通穴を形成することでこの位置での放熱を促進できる。本発明の実施の形態１では、半導体素子１２と半導体素子４０の間の位置が、熱干渉によって温度が最大になる場所であるので、半導体素子１２と半導体素子４０の間に第１貫通穴を形成した。 It is preferable that the first through hole 34 is formed at a position where the temperature becomes maximum due to thermal interference of the plurality of semiconductor elements when the first through hole is not provided. By forming the first through hole at a position where the temperature is maximum, heat dissipation at this position can be promoted. In the first embodiment of the present invention, since the position between the semiconductor element 12 and the semiconductor element 40 is the location where the temperature is maximized due to thermal interference, the first through hole is formed between the semiconductor element 12 and the semiconductor element 40. Formed.

第１貫通穴３４の位置は変更可能である。第１貫通穴３４は必ずしも温度が最大となる場所に形成しなくてもよい。例えば複数の半導体素子が設けられた領域全体が高温になる場合は、複数の半導体素子が設けられた、ある程度広がりのある領域のどこかに第１貫通穴３４を設ければ、十分に放熱性を高めることができる。なお、第１貫通穴３４を設ける際には、ワイヤを切断したり、半導体素子にダメージを与えたりしないよう注意する必要がある。 The position of the first through hole 34 can be changed. The first through hole 34 does not necessarily have to be formed in a place where the temperature becomes maximum. For example, when the entire region where a plurality of semiconductor elements are provided has a high temperature, providing the first through hole 34 somewhere in the region where a plurality of semiconductor elements is provided and has a certain degree of spread provides sufficient heat dissipation. Can be increased. When providing the first through hole 34, it is necessary to take care not to cut the wire or damage the semiconductor element.

金属箔２０は省略しても良い。その場合、絶縁シート１８とヒートシンク５０の間にグリスを設ける。絶縁シート１８を省略して、半導体素子の裏面をモールド樹脂２４で覆ってもよい。そのような構造はフルモールド構造と呼ばれている。 The metal foil 20 may be omitted. In that case, grease is provided between the insulating sheet 18 and the heat sink 50. The insulating sheet 18 may be omitted and the back surface of the semiconductor element may be covered with the molding resin 24. Such a structure is called a full mold structure.

第１貫通穴３４は複数設けてもよい。第１貫通穴３４を複数設けると第３経路の数を増やすことができるので、更なる放熱性の向上が可能となる。第１貫通穴にねじを通さず、第１貫通穴を半導体素子の空冷に用いることも有効である。これらの変形は以下の実施の形態に係る半導体装置に適宜応用できる。なお、以下の実施の形態に係る半導体装置は、実施の形態１との共通点が多いので実施の形態１との相違点を中心に説明する。 A plurality of first through holes 34 may be provided. By providing a plurality of the first through holes 34, the number of the third paths can be increased, so that the heat dissipation can be further improved. It is also effective to use the first through hole for air cooling of the semiconductor element without passing the screw through the first through hole. These modifications can be appropriately applied to the semiconductor devices according to the following embodiments. Note that the semiconductor device according to the following embodiments has many common points with the first embodiment, and therefore the differences from the first embodiment will be mainly described.

実施の形態２．
図７は、実施の形態２に係る半導体装置の断面図である。モールド樹脂２４に、モールド樹脂２４を厚み方向に貫通する第２貫通穴６０が複数形成されている。第２貫通穴６０は、半導体素子、ワイヤ、及びフレームの絶縁を確保できる位置に形成する。第２貫通穴６０は必ずしも金属板３２を貫通する必要はなく、半導体装置の任意の位置に形成する。半導体装置を空冷する場合、第２貫通穴６０を空気が通ることができ、対流による放熱が可能となる。また、水冷の場合、第２貫通穴６０に水（冷媒）を通すことにより放熱性を高めることができる。 Embodiment 2.
FIG. 7 is a cross-sectional view of the semiconductor device according to the second embodiment. A plurality of second through holes 60 that penetrate the mold resin 24 in the thickness direction are formed in the mold resin 24. The second through hole 60 is formed at a position where insulation of the semiconductor element, the wire, and the frame can be secured. The second through hole 60 does not necessarily have to penetrate the metal plate 32 and is formed at an arbitrary position in the semiconductor device. When air-cooling the semiconductor device, air can pass through the second through holes 60, and heat can be released by convection. In the case of water cooling, heat dissipation can be improved by passing water (refrigerant) through the second through hole 60.

実施の形態３.
図８は、実施の形態３に係る半導体装置の断面図である。第２貫通穴６２の開口幅はモールド樹脂２４の上面側と下面側で異なっている。本発明の実施の形態３に係る半導体装置では、半導体装置の上方から下方へ空気が流れることを想定し、第２貫通穴６２の開口幅をモールド樹脂２４の上面側でモールド樹脂２４の下面側より大きくした。これにより、第２貫通穴６２に空気が流入しやすくなり、半導体装置の熱を対流により放熱することができる。 Embodiment 3.
FIG. 8 is a sectional view of the semiconductor device according to the third embodiment. The opening width of the second through hole 62 differs between the upper surface side and the lower surface side of the mold resin 24. In the semiconductor device according to the third embodiment of the present invention, assuming that air flows downward from above the semiconductor device, the opening width of the second through hole 62 is set to the upper surface side of the mold resin 24 and the lower surface side of the mold resin 24. Made bigger. This facilitates the inflow of air into the second through holes 62, and the heat of the semiconductor device can be radiated by convection.

実施の形態４．
図９は、実施の形態４に係る半導体装置の断面図である。ヒートシンク５０に、第２貫通穴６０に通じる貫通穴５０ｄが形成されている。これにより、貫通穴５０ｄと第２貫通穴６０の一方から他方へ空気が流れるので、半導体装置の熱を対流により放熱することができる。 Fourth Embodiment
FIG. 9 is a sectional view of the semiconductor device according to the fourth embodiment. A through hole 50d communicating with the second through hole 60 is formed in the heat sink 50. As a result, air flows from one of the through hole 50d and the second through hole 60 to the other, so that the heat of the semiconductor device can be radiated by convection.

実施の形態５．
図１０は、実施の形態５に係る半導体装置の断面図である。半導体素子１２の直上のモールド樹脂２４を横方向に貫く第１横方向貫通穴７０が形成されている。第１横方向貫通穴７０の他にも、モールド樹脂２４を横方向に貫く横方向貫通穴が形成されている。 Embodiment 5.
FIG. 10 is a sectional view of the semiconductor device according to the fifth embodiment. A first lateral through hole 70 is formed to laterally penetrate the mold resin 24 immediately above the semiconductor element 12. In addition to the first lateral through holes 70, lateral through holes penetrating the mold resin 24 in the lateral direction are formed.

第１横方向貫通穴７０は半導体素子１２のすぐ近くの穴であるため、第１横方向貫通穴７０に空気が流入することで、対流によって半導体装置の放熱性を高めることができる。他の横方向貫通穴にも空気が流入することで半導体装置の放熱性が高まる。また、水冷の場合、これらの穴に水を通すことにより放熱性を高めることができる。なお、第１横方向貫通穴７０は、複数の半導体素子のいずれか１つの半導体素子の直上のモールド樹脂２４を横方向に貫くものであればよい。半導体素子のすぐ近くに横方向貫通穴を形成することで、放熱性を十分に高めることができる。 Since the first lateral through hole 70 is a hole in the immediate vicinity of the semiconductor element 12, the air flowing into the first lateral through hole 70 can enhance the heat dissipation of the semiconductor device by convection. Air also flows into the other lateral through holes, so that the heat dissipation of the semiconductor device is improved. In the case of water cooling, heat dissipation can be improved by passing water through these holes. Note that the first lateral through hole 70 may be any hole that laterally penetrates the molding resin 24 immediately above any one of the plurality of semiconductor elements. By forming the lateral through hole in the immediate vicinity of the semiconductor element, heat dissipation can be sufficiently enhanced.

実施の形態６．
図１１は、実施の形態６に係る半導体装置の断面図である。本発明の実施の形態６に係る半導体装置は、半導体素子の裏面側には絶縁シートがなく、半導体素子の全方位にモールド樹脂があるものである。つまり、モールド樹脂２４は、複数の半導体素子の下面を覆っている。半導体素子１２の直下のモールド樹脂２４を横方向に貫く第２横方向貫通穴７２が形成されている。第２横方向貫通穴は半導体素子１２のすぐ近くにあるので、第２横方向貫通穴７２に空気が流入することで、対流によって半導体装置の放熱性を高めることができる。また、水冷の場合、穴に水を通すことにより放熱性を高めることができる。 Sixth Embodiment
FIG. 11 is a sectional view of the semiconductor device according to the sixth embodiment. In the semiconductor device according to the sixth embodiment of the present invention, there is no insulating sheet on the back surface side of the semiconductor element, and the molding resin is provided in all directions of the semiconductor element. That is, the mold resin 24 covers the lower surfaces of the plurality of semiconductor elements. A second lateral penetrating hole 72 is formed to laterally penetrate the mold resin 24 immediately below the semiconductor element 12. Since the second lateral through hole is in the immediate vicinity of the semiconductor element 12, the air flowing into the second lateral through hole 72 can enhance the heat dissipation of the semiconductor device by convection. In the case of water cooling, heat dissipation can be improved by passing water through the holes.

第２横方向貫通穴は、複数の半導体素子のいずれか１つの半導体素子の直下のモールド樹脂２４を横方向に貫くものであればよい。よって、半導体素子１２の直下以外の位置に第２横方向貫通穴を形成してもよい。なお、第１横方向貫通穴７０と第２横方向貫通穴７２は半導体素子、ワイヤ及びフレームがない部分に設ける。 The second lateral through-hole may be any hole as long as it laterally penetrates through the molding resin 24 immediately below any one of the plurality of semiconductor elements. Therefore, the second lateral through hole may be formed at a position other than directly below the semiconductor element 12. The first lateral through-holes 70 and the second lateral through-holes 72 are provided in the portions where there are no semiconductor elements, wires or frames.

実施の形態７．
図１２は、実施の形態７に係る半導体装置の断面図である。金属箔２０の上に複数の絶縁シート１８が設けられている。複数の絶縁シート１８のそれぞれに半導体素子８０が設けられている。半導体素子８０は、モールド樹脂２４に覆われている。図１２には６つの半導体素子８０が示されているが、その中の1つを第１半導体素子８０ａとし、第１半導体素子８０ａの隣の半導体素子を第２半導体素子８０ｂとする。半導体素子の間のモールド樹脂には凹部２４ａが形成されている。例えば、第１半導体素子８０ａと第２半導体素子８０ｂの間のモールド樹脂２４には、凹部２４ａが形成されている。 Embodiment 7.
FIG. 12 is a sectional view of the semiconductor device according to the seventh embodiment. A plurality of insulating sheets 18 are provided on the metal foil 20. The semiconductor element 80 is provided on each of the plurality of insulating sheets 18. The semiconductor element 80 is covered with the mold resin 24. Although six semiconductor elements 80 are shown in FIG. 12, one of them is referred to as a first semiconductor element 80a, and a semiconductor element adjacent to the first semiconductor element 80a is referred to as a second semiconductor element 80b. A recess 24a is formed in the mold resin between the semiconductor elements. For example, a recess 24a is formed in the mold resin 24 between the first semiconductor element 80a and the second semiconductor element 80b.

図１２では半導体素子８０の電気的接続に関する要素は省略したが、凹部２４ａは、そのような電気的接続を阻害しないように設ける。凹部２４ａを設けることで、半導体素子同士の熱干渉が軽減される。つまり、ある半導体素子で発生した熱が他の半導体素子へ熱伝導する経路を凹部２４ａで遮断することで、半導体素子間の熱干渉を防ぐことができる。凹部２４ａの形状は、図１２に示す切り込みに限定されず、例えばＵ字溝などでもよい。 Although the elements relating to the electrical connection of the semiconductor element 80 are omitted in FIG. 12, the recess 24a is provided so as not to obstruct such electrical connection. By providing the recess 24a, thermal interference between semiconductor elements is reduced. That is, by blocking the path through which the heat generated in one semiconductor element is conducted to another semiconductor element by the recess 24a, it is possible to prevent thermal interference between the semiconductor elements. The shape of the recess 24a is not limited to the notch shown in FIG. 12, and may be, for example, a U-shaped groove.

実施の形態８．
図１３は、実施の形態８に係る半導体装置の斜視図である。モールド樹脂２４によって第１半導体素子９０ａと第２半導体素子９０ｂが覆われている。第１半導体素子９０ａは、第１コレクタと第１エミッタと第１ゲートを有するスイッチング素子であり、第２半導体素子９０ｂは、第２コレクタと第２エミッタと第２ゲートを有するスイッチング素子である。モールド樹脂２４の中で第１エミッタと第２コレクタが接続されている。 Eighth embodiment.
FIG. 13 is a perspective view of the semiconductor device according to the eighth embodiment. The mold resin 24 covers the first semiconductor element 90a and the second semiconductor element 90b. The first semiconductor element 90a is a switching element having a first collector, a first emitter and a first gate, and the second semiconductor element 90b is a switching element having a second collector, a second emitter and a second gate. In the mold resin 24, the first emitter and the second collector are connected.

第１半導体素子９０ａの裏面側に第１絶縁シート１８ａが設けられている。第２半導体素子９０ｂの裏面側に第１絶縁シート１８ａと接触しない第２絶縁シート１８ｂが設けられている。 The first insulating sheet 18a is provided on the back surface side of the first semiconductor element 90a. A second insulating sheet 18b that does not contact the first insulating sheet 18a is provided on the back surface side of the second semiconductor element 90b.

実施の形態８に係る半導体装置は、Ｐ側の半導体素子として機能する第１半導体素子９０ａとＮ側の半導体素子として機能する第２半導体素子９０ｂを有するモータ駆動用インバータ装置を構成している。そして、第１半導体素子９０ａの絶縁に用いられる第１絶縁シート１８ａと第２半導体素子９０ｂの絶縁に用いられる第２絶縁シート１８ｂを分割することで、第１半導体素子９０ａと第２半導体素子９０ｂの間の熱干渉を抑制することができる。 The semiconductor device according to the eighth embodiment constitutes a motor drive inverter device having a first semiconductor element 90a that functions as a P-side semiconductor element and a second semiconductor element 90b that functions as an N-side semiconductor element. Then, by dividing the first insulating sheet 18a used for insulating the first semiconductor element 90a and the second insulating sheet 18b used for insulating the second semiconductor element 90b, the first semiconductor element 90a and the second semiconductor element 90b are divided. It is possible to suppress thermal interference between the two.

本発明の実施の形態８に係る半導体装置は様々な変形が可能である。例えば、第１半導体素子はコレクタとエミッタとゲートを有するスイッチング素子とし、第２半導体素子はゲートに接続された制御ＩＣとしてもよい。この場合、制御ＩＣとゲートがワイヤ接続される。こうすると、所謂パワーチップである第１半導体素子直下の絶縁シート(第１絶縁シート１８ａ)と、制御ＩＣ直下の絶縁シート（第２絶縁シート１８ｂ）が分割されることになる。これにより、パワーチップと制御ＩＣの熱干渉を抑制することができる。 The semiconductor device according to the eighth embodiment of the present invention can be variously modified. For example, the first semiconductor element may be a switching element having a collector, an emitter, and a gate, and the second semiconductor element may be a control IC connected to the gate. In this case, the control IC and the gate are wire-connected. By doing so, the insulating sheet (first insulating sheet 18a) immediately below the first semiconductor element, which is a so-called power chip, and the insulating sheet (second insulating sheet 18b) immediately below the control IC are divided. Thereby, thermal interference between the power chip and the control IC can be suppressed.

図１４は、別の変形例に係る半導体装置の斜視図である。第１絶縁シート１８ａ及び第２絶縁シート１８ｂと同じ材料で形成された接続部１８ｃが設けられている。接続部１８ｃは、第１絶縁シート１８ａと第２絶縁シート１８ｂが対向しつつ接触しない部分を残しつつ、第１絶縁シート１８ａと第２絶縁シート１８ｂを接続するものである。言い換えれば、接続部１８ｃは、第１絶縁シート１８ａと第２絶縁シート１８ｂの端部を接続する。これにより、熱干渉抑制の効果を享受しつつ、絶縁シートの位置ズレを防止できる。 FIG. 14 is a perspective view of a semiconductor device according to another modification. A connecting portion 18c made of the same material as the first insulating sheet 18a and the second insulating sheet 18b is provided. The connecting portion 18c connects the first insulating sheet 18a and the second insulating sheet 18b while leaving a portion where the first insulating sheet 18a and the second insulating sheet 18b face each other and are not in contact with each other. In other words, the connecting portion 18c connects the ends of the first insulating sheet 18a and the second insulating sheet 18b. This makes it possible to prevent the positional displacement of the insulating sheet while enjoying the effect of suppressing thermal interference.

ここまでに説明した各実施の形態に係る半導体装置の特徴は適宜に組み合わせて用いてもよい。 The features of the semiconductor device according to each of the embodiments described so far may be appropriately combined and used.

１０ 半導体装置、 １２,１４,４０,４２ 半導体素子、 １６,１７ フレーム、 １８,１８ａ,１８ｂ 絶縁シート、 １８ｃ 接続部、 ２０ 金属箔、 ２４ モールド樹脂、 ３２ 金属板、 ３４ 第１貫通穴、 ５０ ヒートシンク、 ５０ｃ ねじ穴、 ５０ｄ 貫通穴、 ６０,６２ 第２貫通穴、 ７０ 第１横方向貫通穴、 ７２ 第２横方向貫通穴 10 semiconductor device, 12, 14, 40, 42 semiconductor element, 16, 17 frame, 18, 18a, 18b insulating sheet, 18c connection part, 20 metal foil, 24 mold resin, 32 metal plate, 34 first through hole, 50 Heat sink, 50c screw hole, 50d through hole, 60,62 second through hole, 70 first lateral through hole, 72 second lateral through hole

Claims (1)

第１半導体素子と、 A first semiconductor element;
第２半導体素子と、 A second semiconductor element,
前記第１半導体素子と前記第２半導体素子を覆うモールド樹脂と、 A mold resin covering the first semiconductor element and the second semiconductor element,
前記第１半導体素子の裏面側に設けられた第１絶縁シートと、 A first insulating sheet provided on the back surface side of the first semiconductor element;
前記第２半導体素子の裏面側に設けられた第２絶縁シートと、 A second insulating sheet provided on the back surface side of the second semiconductor element;
前記第１絶縁シートと前記第２絶縁シートが対向しつつ接触しない部分を残しつつ、前記第１絶縁シートと前記第２絶縁シートの端部だけを接続する接続部と、を備えたことを特徴とする半導体装置。 A connecting portion that connects only the end portions of the first insulating sheet and the second insulating sheet while leaving a portion where the first insulating sheet and the second insulating sheet face each other but do not contact each other. Semiconductor device.
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