JP6734750B2 - High frequency package - Google Patents

High frequency package Download PDF

Info

Publication number
JP6734750B2
JP6734750B2 JP2016200369A JP2016200369A JP6734750B2 JP 6734750 B2 JP6734750 B2 JP 6734750B2 JP 2016200369 A JP2016200369 A JP 2016200369A JP 2016200369 A JP2016200369 A JP 2016200369A JP 6734750 B2 JP6734750 B2 JP 6734750B2
Authority
JP
Japan
Prior art keywords
diagonal
high frequency
dielectric layers
connection point
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016200369A
Other languages
Japanese (ja)
Other versions
JP2018064005A (en
Inventor
勝章 杉野
勝章 杉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP2016200369A priority Critical patent/JP6734750B2/en
Publication of JP2018064005A publication Critical patent/JP2018064005A/en
Application granted granted Critical
Publication of JP6734750B2 publication Critical patent/JP6734750B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Waveguide Connection Structure (AREA)

Description

本発明は、高周波信号を伝送可能な高周波パッケージに関し、特に、電子部品が載置され、伝送線路を経由して高周波信号を伝送可能に構成された高周波パッケージに関するものである。 The present invention relates to a high frequency package capable of transmitting a high frequency signal, and more particularly, to a high frequency package configured to have an electronic component mounted thereon and capable of transmitting a high frequency signal via a transmission line.

従来から、複数の誘電体層を含む積層基板上に半導体チップ等の電子部品を載置し、電子部品と外部基板の間で伝送される高周波信号の伝送線路を構成した高周波パッケージが用いられている。高周波信号の伝送特性が良好な高周波パッケージを実現するには、配線構造の設計が重要になる。すなわち、信号配線間の容量結合やインダクタンス成分の影響をできるだけ抑制するとともに、入出力部における反射損失を低減するためにインピーダンス整合を考慮した設計が求められる。この種の高周波パッケージにおける一般的な伝送線路としては、例えば、電子部品の端子から、上層の誘電体層に形成された信号配線と、積層方向に延びる複数のビア導体と、下層の誘電体層に形成された信号配線をそれぞれ経由して、外部端子まで電気的に接続される配線構造が知られている(例えば、特許文献1〜4参照)。このうち、特許文献1、2、4に示される複数のビア導体は、各々の誘電体層を貫く個々のビア導体が積層方向に沿って直線状に延びる構造であるに対し、特許文献3に示される複数のビア導体は、断面で見たときに全体が斜め方向に延びる構造となっている。 Conventionally, a high-frequency package has been used in which electronic components such as semiconductor chips are placed on a laminated substrate including a plurality of dielectric layers, and a transmission line of a high-frequency signal transmitted between the electronic components and an external substrate is configured. There is. The design of the wiring structure is important to realize a high-frequency package with good high-frequency signal transmission characteristics. That is, it is required to design in consideration of impedance matching in order to suppress the influence of capacitive coupling between signal lines and the inductance component as much as possible and to reduce the reflection loss in the input/output section. A general transmission line in this type of high-frequency package is, for example, a signal wiring formed from an electronic component terminal to an upper dielectric layer, a plurality of via conductors extending in the stacking direction, and a lower dielectric layer. There is known a wiring structure in which an external terminal is electrically connected via each of the signal wirings formed in (1) to (4). Among them, the plurality of via conductors shown in Patent Documents 1, 2, and 4 have a structure in which individual via conductors penetrating each dielectric layer extend linearly along the stacking direction, while in Patent Document 3, The plurality of via conductors shown have a structure in which the whole extends obliquely when viewed in cross section.

特許第4413234号公報Japanese Patent No. 4413234 特開2007−53411号公報JP, 2007-53411, A 特開平6−21253号公報JP-A-6-21253 特開2014−154593号公報JP, 2014-154593, A

上記従来の配線構造は、上層及び下層のうち、コプレナー線路構造以外のグランド導体除去領域内の信号配線の長さを短縮することで、この部分のインダクタンス成分の影響の軽減を図っている。これに加えて、上記特許文献3の配線構造は、複数のビア導体には不連続な接続箇所が存在しないため、多重反射による影響を抑制する効果がある。しかしながら、特許文献3の配線構造においては、複数のビア導体の全体が斜め方向に延伸されるので、その周囲を取り囲むグランドビア導体との距離が一定に保たれず、この部分でインピーダンス整合を確保することが難しくなる。よって、上記従来の配線構造を採用したとしても、多重反射による影響の抑制と良好なインピーダンス整合とを両立して良好な高周波特性を実現することは困難であった。 In the above-mentioned conventional wiring structure, by shortening the length of the signal wiring in the ground conductor removal region other than the coplanar line structure in the upper layer and the lower layer, the influence of the inductance component in this portion is reduced. In addition to this, the wiring structure of Patent Document 3 has an effect of suppressing the influence of multiple reflection because there are no discontinuous connection points in the plurality of via conductors. However, in the wiring structure of Patent Document 3, since the entire plurality of via conductors are obliquely extended, the distance from the surrounding ground via conductor cannot be kept constant, and impedance matching is ensured at this portion. Becomes difficult to do. Therefore, even if the above-mentioned conventional wiring structure is adopted, it is difficult to realize good high frequency characteristics by achieving both suppression of the influence of multiple reflection and good impedance matching.

本発明は上記の課題を解決するためになされたものであり、多重反射による影響の抑制と良好なインピーダンス整合とを両立し、高周波信号の良好な伝送特性を実現可能な高周波パッケージを提供するものである。 The present invention has been made to solve the above problems, and provides a high-frequency package that achieves both good suppression of the effects of multiple reflections and good impedance matching, and good transmission characteristics of high-frequency signals. Is.

上記課題を解決するために、本発明の高周波パッケージは、積層された複数の誘電体層を含む積層基板に電子部品を載置可能な高周波パッケージであって、平面視において、前記電子部品の端子と接続される端子パッドから、前記複数の誘電体層のうち第1の誘電体層に形成された第1の接続点まで第1の方向に延びる第1の信号配線と、平面視において、前記複数の誘電体層のうち第2の誘電体層に形成された第2の接続点から、外部接続用のパッドまで前記第1の方向に延びる第2の信号配線と、前記複数の誘電体層を積層方向に貫き、前記第1の接続点と前記第2の接続点との間を電気的に接続する複数のビア導体と、前記複数の誘電体層の各々には、平面視において前記複数のビア導体が配置される領域を取り囲むように形成されるグランド導体とを備えて構成される。前記複数のビア導体は、前記第1の誘電体層よりも下方の誘電体層に形成された上端部から、前記第2の誘電体層よりも上方の誘電体層に形成された下端部までを、前記積層方向に沿って直線状に延びる直線ビア部と、前記第1の接続点から前記直線ビア部の前記上端部までを斜め方向に延びる第1の斜めビア部と、前記第2の接続点から前記直線ビア部の前記下端部までを斜め方向に延びる第2の斜めビア部とを含み、前記積層基板の一方の表面に前記第1の信号配線が形成されるとともに、前記積層基板の他方の表面に前記第2の信号配線が形成され、平面視で前記第1の方向に沿って、前記第1の接続点、前記直線ビア部、前記第2の接続点が順次ずれた位置に配置されることを特徴としている。
In order to solve the above problems, a high-frequency package of the present invention is a high-frequency package capable of mounting an electronic component on a laminated substrate including a plurality of laminated dielectric layers, and has a terminal of the electronic component in plan view. A first signal line extending in a first direction from a terminal pad connected to the first pad to a first connection point formed on the first dielectric layer of the plurality of dielectric layers; A second signal line extending in the first direction from a second connection point formed on a second dielectric layer of the plurality of dielectric layers to a pad for external connection; and the plurality of dielectric layers A plurality of via conductors that penetrate through the stack in the stacking direction and electrically connect between the first connection point and the second connection point, and the plurality of dielectric layers each include the plurality of via conductors in plan view. And a ground conductor formed so as to surround a region in which the via conductor is arranged. The plurality of via conductors extend from an upper end portion formed in a dielectric layer below the first dielectric layer to a lower end portion formed in a dielectric layer above the second dielectric layer. A linear via portion extending linearly along the stacking direction, a first diagonal via portion extending diagonally from the first connection point to the upper end portion of the linear via portion, and the second A second diagonal via portion extending diagonally from a connection point to the lower end portion of the linear via portion , wherein the first signal wiring is formed on one surface of the laminated substrate, and the laminated substrate. A position where the second signal wiring is formed on the other surface of the first connection point, and the first connection point, the linear via portion, and the second connection point are sequentially displaced along the first direction in a plan view. It is characterized by being placed in.

本発明の高周波パッケージによれば、第1の信号配線と、複数のビア導体と、第2の信号配線とを含む伝送線路を経由して高周波信号が伝送され、このうちの複数のビア導体は、第1の信号配線側の第1の接続点から第2の信号配線側の第2の接続点に至るまで、第1の斜めビア部と直線ビア部と第2の斜めビア部とを連結した構造を有する。この場合、平面視で第1の方向に沿って、第1の接続点、直線ビア部、第2の接続点の各位置を順次ずらした配置とすることで、第1及び第2の信号配線のグランド導体除去領域内の信号配線の長さを短縮してインダクタンス成分を低減することができる。そして、本発明の配線構造により、積層方向に隣接するビア導体同士の不連続な接続箇所に起因する多重反射を抑制できるとともに、複数のビア導体の全体を斜め方向に配置する場合に比べて第1及び第2の斜めビア部の長さを短縮し、インピーダンスを整合させることができるので良好なインピーダンス整合を確保しやすくなる。 According to the high frequency package of the present invention, a high frequency signal is transmitted via the transmission line including the first signal wiring, the plurality of via conductors, and the second signal wiring, and the plurality of via conductors are Connecting the first diagonal via portion, the linear via portion, and the second diagonal via portion from the first connection point on the first signal wiring side to the second connection point on the second signal wiring side. It has a structure. In this case, the positions of the first connection point, the linear via portion, and the second connection point are sequentially shifted along the first direction in a plan view, whereby the first and second signal wirings are arranged. The inductance component can be reduced by shortening the length of the signal wiring in the ground conductor removal region. With the wiring structure of the present invention, it is possible to suppress multiple reflection due to discontinuous connection points between via conductors that are adjacent to each other in the stacking direction, and in comparison with the case where the entire plurality of via conductors are arranged diagonally. Since the lengths of the first and second diagonal via portions can be shortened and the impedances can be matched, it is easy to ensure good impedance matching.

本発明において、第1及び第2の斜めビア部の各々は、複数の誘電体層のうちの2層又は3層の誘電体層を貫くビア部とすることができる。この場合、第1及び第2の斜めビア部の各々が形成される部分は、複数の誘電体層の全体の厚さに対して15%から30%までの範囲の厚さを有することが望ましい。第1及び第2の斜めビア部の各々が形成される部分の厚さが薄すぎると、インダクタンス成分の影響によりインピーダンスを整合することができなくなる。また、第1及び第2の斜めビア部の形成部分の厚さが厚すぎると、斜めビア部のインピーダンスが低くなりインピーダンス整合に支障を来す。 In the present invention, each of the first and second diagonal via portions can be a via portion that penetrates two or three dielectric layers of the plurality of dielectric layers. In this case, the portion where each of the first and second diagonal via portions is formed preferably has a thickness in the range of 15% to 30% with respect to the total thickness of the plurality of dielectric layers. .. If the thickness of the portion where each of the first and second diagonal via portions is formed is too thin, the impedance cannot be matched due to the influence of the inductance component. Further, if the thickness of the formation portion of the first and second diagonal via portions is too large, the impedance of the diagonal via portions becomes low, which impedes impedance matching.

本発明において、第1及び第2の斜めビア部のビア径は、平面視で直線ビア部のビア径と比べて同一又は僅かに大きく設定することができる。ここで、「僅かに大きい」とは直線ビア部のビア径に対して、第1及び第2の斜めビア部のビア径が数%(0.1〜15%)大きいことを示す。この場合、直線ビア部と第1及び第2の斜めビアの各々は、所望の特性インピーダンスとなるように、それぞれのビア径を設定することが望ましい。高周波パッケージの伝送線路の特性インピーダンスを、例えば50Ωで設計する場合、直線ビア部に対し第1及び第2の斜めビアのそれぞれのビア径を適切に調整することで対応可能である。 In the present invention, the via diameters of the first and second oblique via portions can be set to be the same or slightly larger than the via diameter of the linear via portion in plan view. Here, "slightly large" means that the via diameters of the first and second oblique via portions are several percent (0.1 to 15%) larger than the via diameter of the linear via portion. In this case, it is desirable to set the via diameter of each of the straight via portion and each of the first and second diagonal vias so as to have a desired characteristic impedance. When the characteristic impedance of the transmission line of the high frequency package is designed to be, for example, 50Ω, it can be dealt with by appropriately adjusting the via diameters of the first and second diagonal vias with respect to the straight via portion.

本発明によれば、高周波パッケージにおける高周波信号の伝送線路として、上下の信号配線の間を接続する複数のビア導体を、第1の斜めビア部、直線ビア部、第2の斜めビア部を連結し、かつ平面視で第1の方向に沿う所定の配置順を規定することで、上下の信号配線のグランド導体除去領域内の信号配線の長さを短縮してインダクタンス成分を低減しつつ、複数のビア導体の不連続な接続箇所からの多重反射を抑制し、さらに積層方向の中央の直線ビア部によりインピーダンス整合の確保を容易化することができる。よって、これらが相まって、高周波パッケージにおける高周波信号の伝送特性の向上が可能となる。 According to the present invention, as a high-frequency signal transmission line in a high-frequency package, a plurality of via conductors connecting upper and lower signal wirings are connected to a first diagonal via portion, a straight via portion, and a second diagonal via portion. In addition, by defining the predetermined arrangement order along the first direction in plan view, the length of the signal wiring in the ground conductor removal region of the upper and lower signal wirings is shortened to reduce the inductance component, and It is possible to suppress the multiple reflection from the discontinuous connection portion of the via conductor, and it is possible to easily secure the impedance matching by the linear via portion at the center in the stacking direction. Therefore, by combining these, it is possible to improve the transmission characteristics of the high frequency signal in the high frequency package.

本実施形態の高周波パッケージ1の部分的な領域の断面図である。It is sectional drawing of the partial area|region of the high frequency package 1 of this embodiment. 図1に示す高周波パッケージ1の領域を誘電体層L(1)の上方から見た平面図である。FIG. 2 is a plan view of a region of the high frequency package 1 shown in FIG. 1 viewed from above a dielectric layer L(1). 図1の配線構造に関し、斜めビア部21、22の各々の形成部分が全体の15〜30%の範囲の厚さとなる変形例である。This is a modification example of the wiring structure of FIG. 1 in which each of the formation portions of the diagonal via portions 21 and 22 has a thickness in the range of 15 to 30% of the whole. 従来の配線構造を有する比較例に関する模式的な断面図である。It is a typical sectional view regarding a comparative example having a conventional wiring structure. 比較例(図4)のSパラメータの検証結果を示す図である。It is a figure which shows the verification result of the S parameter of a comparative example (FIG. 4). 本実施形態(図1)のSパラメータの検証結果を示す図である。It is a figure which shows the verification result of the S parameter of this embodiment (FIG. 1). 比較例(図4)のインピーダンスの検証結果を示す図である。It is a figure which shows the verification result of the impedance of a comparative example (FIG. 4). 本実施形態(図1)のインピーダンスの検証結果を示す図である。It is a figure which shows the verification result of the impedance of this embodiment (FIG. 1).

以下、本発明の好適な実施形態について、図面を参照しながら説明する。ただし、以下に述べる実施形態は本発明を適用した形態の一例であって、本発明が本実施形態の内容により限定されることはない。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. However, the embodiment described below is an example of a mode to which the present invention is applied, and the present invention is not limited by the contents of the present embodiment.

図1及び図2を参照して、本実施形態の高周波パッケージの構造の概要について説明する。図1は、本実施形態の高周波パッケージ1の部分的な領域の断面図を示し、図2は、図1に示す高周波パッケージ1を誘電体層L(1)の上方から見た平面図を示している。本実施形態の高周波パッケージ1には、図1及び図2には示されない領域(図1の右側)に半導体チップ等の電子部品(不図示)が載置され、その電子部品の複数の端子と外部回路との間の電気的接続のために本発明の配線構造が形成されている。図1及び図2では、電子部品の端子に接続される1個の端子パッド(不図示)から高周波パッケージ1の底面の1個の外部接続用のパッド(不図示)に至る1つの伝送線路に適用される配線構造が例示される。 The outline of the structure of the high-frequency package of the present embodiment will be described with reference to FIGS. 1 and 2. 1 shows a cross-sectional view of a partial region of the high frequency package 1 of the present embodiment, and FIG. 2 shows a plan view of the high frequency package 1 shown in FIG. 1 as seen from above the dielectric layer L(1). ing. In the high frequency package 1 of the present embodiment, an electronic component (not shown) such as a semiconductor chip is placed in a region (right side of FIG. 1) not shown in FIGS. 1 and 2, and a plurality of terminals of the electronic component are arranged. The wiring structure of the present invention is formed for electrical connection with an external circuit. In FIGS. 1 and 2, one transmission line from one terminal pad (not shown) connected to the terminal of the electronic component to one external connection pad (not shown) on the bottom surface of the high-frequency package 1 is provided. An applied wiring structure is illustrated.

図1に示す高周波パッケージ1の積層基板は、全部で複数の誘電体層Lが積層された構造を有している。このうち、上層から順に番号を付した11層の誘電体層L(1)〜L(11)は、本発明の配線構造の形成領域に含まれる複数の誘電体層に相当する。図1には示されないが、高周波パッケージ1に載置された電子部品を取り囲むように壁状の2層の誘電体層Lを、11層の誘電体層L(1)〜L(11)の上部に形成してもよい。各々の誘電体層Lは、それぞれに必要な電気的特性に応じた厚さに形成され、その表面には各々に固有の導体パターンが形成されている。例えば、複数の誘電体層Lからなる積層基板は、比較的高い誘電率を有する高温焼成の多層セラミックにより形成される。 The laminated substrate of the high frequency package 1 shown in FIG. 1 has a structure in which a plurality of dielectric layers L are laminated in total. Among these, eleven dielectric layers L(1) to L(11) numbered in order from the top layer correspond to a plurality of dielectric layers included in the formation region of the wiring structure of the present invention. Although not shown in FIG. 1, two wall-shaped dielectric layers L are provided to surround the electronic components mounted on the high-frequency package 1, and the eleven dielectric layers L(1) to L(11) are provided. It may be formed on the upper part. Each dielectric layer L is formed to have a thickness according to the required electrical characteristics, and a conductor pattern unique to each is formed on the surface thereof. For example, a laminated substrate including a plurality of dielectric layers L is formed of a high temperature fired multilayer ceramic having a relatively high dielectric constant.

本発明に係る配線構造の形成領域のうち、最上層の誘電体層L(1)(本発明の第1の誘電体層)の表面には、前述の1個の端子パッドから延伸される信号配線10(本発明の第1の信号配線)が形成されている。また、最下層の誘電体層L(11)(本発明の第2の誘電体層)の裏面には、外部接続用の1個のパッドに延伸される信号配線11(本発明の第2の信号配線)が形成されている。図1の下部には、便宜上、紙面横方向をX方向(本発明の第1の方向)と定め、複数の誘電体層Lの積層方向をZ方向と定め、X方向及びZ方向をそれぞれ矢印にて示している。なお、X方向の+(プラス)側の方向を左方向、及び、X方向の−(マイナス)側の方向を右方向とする。また、Z方向の+(プラス)側の方向を上方向、及び、Z方向の−(マイナス)側の方向を下方向とする。同様に、図2の下部には、平面視でX方向に直交する方向(図1の紙面垂直方向)をY方向と定め、X方向及びY方向をそれぞれ矢印にて示している。よって、上下の各信号配線10、11は、いずれもX方向に延びる伝送線路である。 In the formation area of the wiring structure according to the present invention, on the surface of the uppermost dielectric layer L(1) (first dielectric layer of the present invention), a signal extended from the above-mentioned one terminal pad is provided. The wiring 10 (first signal wiring of the present invention) is formed. Further, on the back surface of the lowermost dielectric layer L(11) (the second dielectric layer of the present invention), the signal wiring 11 extending to one pad for external connection (the second dielectric layer of the present invention). Signal wiring) is formed. In the lower part of FIG. 1, for convenience, the lateral direction of the drawing is defined as the X direction (first direction of the present invention), the stacking direction of the plurality of dielectric layers L is defined as the Z direction, and the X direction and the Z direction are indicated by arrows. It is shown in. It should be noted that the + (plus) side direction of the X direction is the left direction, and the-(minus) side direction of the X direction is the right direction. Further, the + (plus) side direction of the Z direction is the upward direction, and the − (minus) side direction of the Z direction is the downward direction. Similarly, in the lower part of FIG. 2, the direction orthogonal to the X direction in plan view (the direction perpendicular to the paper surface of FIG. 1) is defined as the Y direction, and the X direction and the Y direction are indicated by arrows. Therefore, each of the upper and lower signal wirings 10 and 11 is a transmission line extending in the X direction.

上下の信号配線10、11は、誘電体層L(1)〜L(11)をZ方向に貫く複数のビア導体を介して電気的に接続されており、信号配線10から信号配線11への信号伝送が可能となっている。図1に示すように、これら複数のビア導体からなるビア部は、Z方向の中央の5層の誘電体層L(4)〜L(8)を貫いてZ方向に沿って直線状に延びる直線ビア部20と、上部の3層の誘電体層L(1)〜L(3)を貫いて斜め方向に延びる斜めビア部21と、下部の3層の誘電体層L(9)〜L(11)を貫いて斜め方向に延びる斜めビア部22とに区分される。なお、複数のビア導体の個数については特に制約されないが、例えば、11層の誘電体層L(1)〜L(11)の各1層に1つのビア導体を形成し、上下に隣接するビア導体同士を接続導体を介して接続する場合は、11個のビア導体が多段接続される構造になる。 The upper and lower signal wirings 10 and 11 are electrically connected to each other through a plurality of via conductors that penetrate the dielectric layers L(1) to L(11) in the Z direction, and the signal wiring 10 to the signal wiring 11 are connected to each other. Signal transmission is possible. As shown in FIG. 1, the via portion formed of the plurality of via conductors extends linearly along the Z direction through the five dielectric layers L(4) to L(8) at the center in the Z direction. The linear via part 20, the oblique via part 21 extending obliquely through the upper three dielectric layers L(1) to L(3), and the lower three dielectric layers L(9) to L(L). It is divided into diagonal via portions 22 that extend diagonally through (11). Although the number of the plurality of via conductors is not particularly limited, for example, one via conductor is formed in each of the eleven dielectric layers L(1) to L(11), and the vias vertically adjacent to each other are formed. When the conductors are connected to each other via the connection conductor, eleven via conductors are connected in multiple stages.

図1には、4つの接続点N1、N2、N3、N4が示されている。すなわち、上部から順に、接続点N1(本発明の第1の接続点)を介して信号配線10と斜めビア部21の上端部が接続され、接続点N2を介して斜めビア部21の下端部と直線ビア部20の上端部が接続され、接続点N3を介して直線ビア部20の下端部と斜めビア部22の上端部が接続され、接続点N4(本発明の第2の接続点)を介して斜めビア部22の下端部と信号配線11が接続される。ここで、各接続点N1〜N4のX方向の位置に着目すると、図1に示すように、1対の接続点N2、N3はX方向の中央に位置し、そこを基準として、接続点N1が右側に距離X1だけ離れ、接続点N4が左側に同様の距離X1だけ離れている。また、図1の例では、上下1対の斜めビア部21、22は、いずれもZ方向及びX方向で長さが等しく、XZ面内において同じ角度で延伸している。 In FIG. 1, four connection points N1, N2, N3, N4 are shown. That is, from the top, the signal wiring 10 and the upper end of the diagonal via part 21 are sequentially connected via the connection point N1 (first connection point of the present invention), and the lower end of the diagonal via part 21 is connected via the connection point N2. And the upper end of the linear via part 20 are connected, the lower end of the linear via part 20 and the upper end of the oblique via part 22 are connected via a connection point N3, and a connection point N4 (the second connection point of the present invention) The lower end portion of the diagonal via portion 22 and the signal wiring 11 are connected via the. Here, focusing on the positions of the connection points N1 to N4 in the X direction, the pair of connection points N2 and N3 are located at the center in the X direction as shown in FIG. Are separated by a distance X1 on the right side, and the connection point N4 is separated by a similar distance X1 on the left side. In the example of FIG. 1, the pair of upper and lower diagonal via portions 21 and 22 have the same length in the Z direction and the X direction, and extend at the same angle in the XZ plane.

なお、図1の構造には制約されず、1対の斜めビア部21、22は、互いにX方向の距離及び延伸方向の角度が異なっていてもよい。ただし、平面視でX方向に沿って、端子パッド、接続点N1、接続点N2及びN3(直線ビア部20の平面視の位置)、接続点N4、外部接続用のパッドの順で位置が順次ずれる配置にする必要がある。かかる配置を逸脱すると、信号配線10、11の一方又は両方が長くなり過ぎたり、高周波信号の伝送方向が途中でX方向に反転するなどの不具合を招くことになる。また、直線ビア部20に関しては、Z方向に正確に平行な場合に限らず、インピーダンス整合が確保できる範囲内で、概ねZ方向に平行であればよい。 Note that the pair of diagonal via portions 21 and 22 may be different from each other in the distance in the X direction and the angle in the stretching direction without being limited to the structure of FIG. 1. However, the positions of the terminal pad, the connection point N1, the connection points N2 and N3 (the position of the linear via portion 20 in plan view), the connection point N4, and the pad for external connection are sequentially arranged in this order along the X direction in a plan view. It is necessary to shift it. If the arrangement deviates from this, one or both of the signal wirings 10 and 11 may become too long, or the transmission direction of the high-frequency signal may be inverted in the X direction. Further, the linear via portion 20 is not limited to being exactly parallel to the Z direction, but may be substantially parallel to the Z direction as long as impedance matching can be ensured.

また、図1において、上層側の信号配線10と下層側の信号配線11は、それぞれの全体がX方向に直線状に延伸されているが、各信号配線10、11は部分的にX方向に延びる線路部分を含んでいればよい。例えば、上層側の信号配線10の接続点N1と電子部品用の端子パッドとのそれぞれの位置がY方向に若干ずれた配置である場合や、下層側の信号配線11の接続点N4と外部接続用のパッドのそれぞれの位置がY方向に若干ずれた配置である場合が想定される。 Further, in FIG. 1, the signal wiring 10 on the upper layer side and the signal wiring 11 on the lower layer side are entirely extended linearly in the X direction, but the signal wirings 10 and 11 are partially extended in the X direction. It suffices if it includes an extended line portion. For example, when the positions of the connection point N1 of the signal wiring 10 on the upper layer side and the terminal pads for electronic parts are slightly displaced in the Y direction, or when the connection point N4 of the signal wiring 11 on the lower layer side and the external connection are externally connected. It is assumed that the positions of the pads for use are slightly displaced in the Y direction.

また、各々の誘電体層Lの周囲には、共通のグランドと電気的に接続されたグランド導体12が形成されている。図2に示すように、グランド導体12の中央には、直径Dの円形のグランド導体除去領域13が設けられ、グランド導体除去領域13の内部だけグランド導体12が除去されている。11層の誘電体層L(1)〜L(11)には、平面視で重なる配置でグランド導体12及びグランド導体除去領域13が形成されている。 Around each dielectric layer L, a ground conductor 12 electrically connected to a common ground is formed. As shown in FIG. 2, a circular ground conductor removal region 13 having a diameter D is provided in the center of the ground conductor 12, and the ground conductor 12 is removed only inside the ground conductor removal region 13. On the eleven dielectric layers L(1) to L(11), the ground conductor 12 and the ground conductor removal region 13 are formed so as to overlap each other in a plan view.

さらに、図2に示すように、各々の誘電体層Lには、グランド導体12のうち円形のグランド導体除去領域13を取り囲むように配置されたグランド用の複数(図2では、10個)のビア導体からなるグランドビア導体群23が形成されている。図1に示すように、グランドビア導体群23の各々のビア導体は、各層の誘電体層Lの同じ位置に配置され、それぞれZ方向に貫いて多段に接続されている。平面視において、前述の直線ビア部20及び斜めビア部21、22は、円形のグランド導体除去領域13の範囲内に位置しているため、その周囲をグランド導体12が取り囲む配置となっている。 Further, as shown in FIG. 2, each of the dielectric layers L includes a plurality of ground conductors (10 in FIG. 2) arranged so as to surround the circular ground conductor removal region 13 of the ground conductor 12. A ground via conductor group 23 composed of via conductors is formed. As shown in FIG. 1, the respective via conductors of the ground via conductor group 23 are arranged at the same position of the dielectric layers L of the respective layers, and are penetrated in the Z direction and connected in multiple stages. When seen in a plan view, the linear via portion 20 and the diagonal via portions 21 and 22 described above are located within the circular ground conductor removal region 13, so that the ground conductor 12 surrounds the periphery thereof.

なお、図2では、グランド導体12に配置されたグランドビア導体群23は、いずれも円形のグランド導体除去領域13の近傍に配置されているが、グランド導体12の全体にわたって分布するグランドビア導体群23を配置することで、高周波パッケージ1のグランドを強化してもよい。 In FIG. 2, the ground via conductor groups 23 arranged in the ground conductor 12 are all arranged in the vicinity of the circular ground conductor removal region 13, but the ground via conductor groups distributed over the entire ground conductor 12 are arranged. By arranging 23, the ground of the high frequency package 1 may be strengthened.

図1及び図2に示す配線構造の寸法例としては、例えば、グランド導体除去領域13の直径Dとして、D=1.25mmとし、接続点N1、N4の各々をグランド導体除去領域13の外周から0.15mm内側の位置に設定し、直線ビア部20及び斜めビア部21、22の各ビア径を0.11mm程度に設定することができる。 As an example of dimensions of the wiring structure shown in FIG. 1 and FIG. 2, for example, the diameter D of the ground conductor removal region 13 is D=1.25 mm, and each of the connection points N1 and N4 is separated from the outer periphery of the ground conductor removal region 13. The via diameter of each of the linear via portion 20 and the diagonal via portions 21 and 22 can be set to about 0.11 mm by setting the inside diameter of 0.15 mm.

図1及び図2に示す配線構造を用いて高周波信号を伝送する場合、電子部品の端子から出力される高周波信号は、上層側の信号配線10から、斜めビア部21、直線ビア部20、斜めビア部22の順に経由した後、下層側の信号配線11に伝送されて外部接続用のパッドに達する。ここで、上下の信号配線10、11に着目すると、グランド導体12に対向する部分はコプレーナ線路構造としてインピーダンス整合を確保しやすいのに対し、グランド導体除去領域13に対向する部分はインダクタンス成分の影響でインピーダンスの不整合を生じやすい。そのため、上下の信号配線10、11のうちグランド導体除去領域13に対向する部分をできるだけ短くすることが望ましい。仮に、複数のビア導体の全てがZ方向に沿う直線状である場合は、信号配線10、11をグランド導体除去領域13の中心まで延伸する必要がある。しかし、本実施形態では、上下1対の斜めビア部21、22を設けたことにより、信号配線10、11の長さを、グランド導体除去領域13の中心から距離X1だけ短く構成することが可能となり、その分だけ信号配線10、11のインダクタンス成分を低減することができる。 When a high-frequency signal is transmitted using the wiring structure shown in FIGS. 1 and 2, the high-frequency signal output from the terminal of the electronic component is transmitted from the signal wiring 10 on the upper layer side to the diagonal via portion 21, the straight via portion 20, and the diagonal via portion 20. After passing through the via portion 22 in this order, the signal is transmitted to the signal wiring 11 on the lower layer side and reaches the pad for external connection. Here, paying attention to the upper and lower signal wirings 10 and 11, the portion facing the ground conductor 12 is easy to ensure impedance matching as a coplanar line structure, while the portion facing the ground conductor removal region 13 is affected by the inductance component. It is easy to cause impedance mismatch. Therefore, it is desirable to shorten the portions of the upper and lower signal wirings 10 and 11 facing the ground conductor removal region 13 as short as possible. If all of the plurality of via conductors are linear along the Z direction, it is necessary to extend the signal wirings 10 and 11 to the center of the ground conductor removal region 13. However, in the present embodiment, by providing the pair of upper and lower diagonal via portions 21 and 22, the length of the signal wirings 10 and 11 can be configured to be shorter than the center of the ground conductor removal region 13 by the distance X1. Therefore, the inductance component of the signal wirings 10 and 11 can be reduced accordingly.

また、直線ビア部20及び斜めビア部21、22に着目すると、直線ビア部20が対称的な配置で各層のグランド導体12及びグランドビア導体群23に囲まれているのに対し、斜めビア部21、22は各層のグランド導体12及びグランドビア導体群23とは非対称な位置に配置されている。よって、直線ビア部20に比べると、斜めビア部21、22のインピーダンスの整合を確保しにくい。そのため、本実施形態では、斜めビア部21、22のXY面内の断面積を適切に設定することで、斜めビア部21、22のインピーダンス整合を確保している Further, focusing on the linear via portion 20 and the diagonal via portions 21 and 22, while the linear via portion 20 is surrounded by the ground conductors 12 and the ground via conductor groups 23 of the respective layers in a symmetrical arrangement, the diagonal via portions are inclined. Reference numerals 21 and 22 are arranged asymmetrically with respect to the ground conductor 12 and the ground via conductor group 23 of each layer. Therefore, as compared with the straight via portion 20, it is difficult to ensure the impedance matching of the diagonal via portions 21 and 22. Therefore, in this embodiment, the impedance matching of the diagonal via portions 21 and 22 is ensured by appropriately setting the cross-sectional area of the diagonal via portions 21 and 22 in the XY plane.

さらに、従来の複数のビア導体の構造としては、例えば特許文献3に開示されるように複数のビア導体の全体が斜め方向に配置される構造や、例えば特許文献1、4に開示されるように複数のビア導体のうち上下に隣接するビア導体がX方向の異なる位置で接続導体を介して接続される構造が知られている。しかし、特許文献3の構造によれば、図1の直線ビア部20に相当する部分がなく斜め方向に長い距離を延伸されるため、ビア導体の位置によりインピーダンスが異なるので、インピーダンス整合が難しくなる。また、特許文献1、4の構造によれば、複数のビア導体がX方向に不連続に接続される箇所からの多重反射が避けらない。これに対し、本実施形態の構造によれば、前述したように斜めビア部21、22の長さが限られるので、全体的にインピーダンス整合が確保しやすいとともに、接続点N1、N2、N3、N4を含めてX方向に不連続となる接続箇所がないため前述の多重反射を回避することができる。本実施形態の配線構造に基づく具体的な高周波特性及びインピーダンス特性については後述する。 Further, as a conventional structure of a plurality of via conductors, for example, a structure in which all of the plurality of via conductors are obliquely arranged as disclosed in Patent Document 3 or disclosed in Patent Documents 1 and 4, for example. There is known a structure in which vertically adjacent via conductors among a plurality of via conductors are connected via connection conductors at different positions in the X direction. However, according to the structure of Patent Document 3, since there is no portion corresponding to the linear via portion 20 of FIG. 1 and a long distance is extended in an oblique direction, the impedance varies depending on the position of the via conductor, which makes impedance matching difficult. .. Further, according to the structures of Patent Documents 1 and 4, multiple reflection from a location where a plurality of via conductors are discontinuously connected in the X direction cannot be avoided. On the other hand, according to the structure of the present embodiment, since the length of the oblique via portions 21 and 22 is limited as described above, it is easy to ensure impedance matching as a whole, and the connection points N1, N2, N3, Since there are no connection points discontinuous in the X direction including N4, the above-mentioned multiple reflection can be avoided. Specific high-frequency characteristics and impedance characteristics based on the wiring structure of this embodiment will be described later.

なお、図1及び図2に示す配線構造は一例であって、かかる構造に限定されることなく、本発明を適用することができる。例えば、図1では、11層の誘電体層L(1)〜L(11)のうち、直線ビア部20が5層分の範囲に形成され、斜めビア部21、22の各々が3層分の範囲に形成されるが、それぞれが貫く範囲の積層数を変更してもよい。本実施形態の配線構造に基づく高周波特性を考慮すると、全体の厚さに対し、斜めビア部21、22の各々を15〜30%の範囲の厚さを有する部分に形成し、直線ビア部20を残余の部分に形成することが望ましい。 Note that the wiring structures shown in FIGS. 1 and 2 are examples, and the present invention can be applied without being limited to such structures. For example, in FIG. 1, of the eleven dielectric layers L(1) to L(11), the linear via portions 20 are formed in a range of five layers, and each of the oblique via portions 21 and 22 corresponds to three layers. However, the number of stacked layers may be changed. Considering the high frequency characteristics based on the wiring structure of the present embodiment, each of the oblique via portions 21 and 22 is formed in a portion having a thickness in the range of 15 to 30% with respect to the total thickness, and the linear via portion 20 is formed. Is preferably formed in the remaining portion.

図3は、図1の配線構造に関し、斜めビア部21、22の各々の形成部分が前述のように全体の15〜30%の範囲の厚さとなる一変形例を示している。なお、図3では、図1の配線構造のうち、11層の誘電体層L(1)〜L(11)、信号配線10、11、直線ビア部20及び斜めビア部21、22以外の構成要素については図1と相違がないので図示を省略している。具体的には、直線ビア部20が7層の誘電体層L(3)〜L(9)を貫き、上部の斜めビア部21が2層の誘電体層L(1)、L(2)を貫き、下部の斜めビア部22が2層の誘電体層L(10)、L(11)を貫く構造となっている。 FIG. 3 shows a modification of the wiring structure shown in FIG. 1, in which each of the formation portions of the diagonal via portions 21 and 22 has a thickness in the range of 15 to 30% of the whole as described above. Note that, in FIG. 3, in the wiring structure of FIG. 1, a configuration other than the eleven dielectric layers L(1) to L(11), the signal wirings 10 and 11, the straight via portion 20, and the diagonal via portions 21 and 22 is provided. The elements are not shown because they are the same as those in FIG. Specifically, the linear via portion 20 penetrates the seven dielectric layers L(3) to L(9), and the upper oblique via portion 21 has two dielectric layers L(1) and L(2). And the lower diagonal via portion 22 penetrates the two dielectric layers L(10) and L(11).

しかし、図1の配線構造を例にとると、斜めビア部21、22の各々が貫く範囲の積層数は1層又は4層以上に設定するのは、いずれも前述の15〜30%の範囲を逸脱するので、良好な高周波特性の観点からは好ましくない。図1の配線構造の場合には、斜めビア部21、22の形成範囲が15〜30%の範囲となる条件は、積層数が2層(図3)又は3層(図1)に限られる。ただし、全体の誘電体層Lの積層数や各誘電体層Lの厚さを変更すれば、1層又は4層以上の積層数としても前述の条件を満たす場合がある。この条件に関し、斜めビア部21、22の各々を形成する範囲が相対的に短すぎると、インダクタンス成分の影響によりインピーダンスを整合することができなくなる。一方、斜めビア部21、22の各々を形成する範囲が相対的に長すぎると、直線ビア部20を形成する範囲が短くなり、いずれの場合も高周波特性の劣化を招く。 However, taking the wiring structure of FIG. 1 as an example, the number of stacked layers in the range where each of the diagonal via portions 21 and 22 penetrates is set to one layer or four layers or more in each of the above 15 to 30% range. Therefore, it is not preferable from the viewpoint of good high frequency characteristics. In the case of the wiring structure of FIG. 1, the condition that the formation range of the oblique via portions 21 and 22 is in the range of 15 to 30% is limited to the number of laminated layers being 2 layers (FIG. 3) or 3 layers (FIG. 1). .. However, if the number of laminated dielectric layers L or the thickness of each dielectric layer L is changed, the above-described condition may be satisfied even if the number of laminated layers is one or four or more. With respect to this condition, if the range in which each of the diagonal via portions 21 and 22 is formed is relatively short, the impedance cannot be matched due to the influence of the inductance component. On the other hand, when the range in which each of the oblique via portions 21 and 22 is formed is relatively long, the range in which the linear via portion 20 is formed becomes short, and in either case, high frequency characteristics are deteriorated.

また、上下の斜めビア部21、22の断面形状と方向性は互いに異なっていてもよいが、図1及び図2における接続点N1〜N4のX方向の位置については制約がある。図1の例では、信号配線10の端部(右端)から、前述したように+(プラス)X方向に沿って、接続点N1の位置、接続点N2、N3の位置、接続点N4の位置、信号配線11の端部(左端)のように順次ずれた配置となる。この例では、接続点N1の位置が接続点N2、N3の位置より左側にある配置(接続点N1から接続点N2まで−(マイナス)X方向に信号配線10が延びる)、あるいは接続点N4の位置が接続点N2、N3の位置より右側にある配置(接続点N3から接続点N4まで−(マイナス)X方向に信号配線11が延びる)は、信号配線10、11の長さが長くなるので好ましくない。また、接続点N1、N4の位置が接続点N2、N3に対して同じ側にある配置(接続点N1から接続点N2まで+(プラス)X方向に信号配線10が延び、接続点N3から接続点N4まで−(マイナス)X方向に信号配線11が延びる)も、信号配線10、11の伝送方向の観点から好ましくない。 Further, although the cross-sectional shapes and the directivities of the upper and lower diagonal via portions 21 and 22 may be different from each other, there are restrictions on the positions in the X direction of the connection points N1 to N4 in FIGS. 1 and 2. In the example of FIG. 1, the position of the connection point N1, the positions of the connection points N2 and N3, and the position of the connection point N4 are measured along the + (plus) X direction from the end (right end) of the signal line 10 as described above. , The signal wiring 11 is arranged in such a manner that it is sequentially displaced like the end (left end). In this example, the position of the connection point N1 is located on the left side of the positions of the connection points N2 and N3 (the signal wiring 10 extends in the −(minus) X direction from the connection point N1 to the connection point N2) or the connection point N4. In the arrangement in which the position is on the right side of the positions of the connection points N2 and N3 (the signal wiring 11 extends in the −(minus) X direction from the connection point N3 to the connection point N4), the length of the signal wirings 10 and 11 becomes long. Not preferable. Further, the arrangement is such that the positions of the connection points N1 and N4 are on the same side as the connection points N2 and N3 (the signal wiring 10 extends in the + (plus) X direction from the connection point N1 to the connection point N2 and is connected from the connection point N3. The signal wiring 11 extending in the −(minus)X direction up to the point N4) is also not preferable from the viewpoint of the transmission direction of the signal wirings 10 and 11.

また、図1及び図2では、1系統の伝送線路を構成する配線構造を示したが、複数の伝送線路を構成する場合は、高周波パッケージ1内に、図1及び図2の構造を並列に複数個形成すればよい。例えば、差動伝送線路を構成する場合、図1及び図2の構造を対称的に配置し、それぞれを経由する2系統の伝送線路を構成すればよい。 1 and 2, the wiring structure that constitutes one transmission line is shown. However, when a plurality of transmission lines are configured, the structures of FIGS. 1 and 2 are arranged in parallel in the high frequency package 1. It is only necessary to form a plurality. For example, in the case of configuring a differential transmission line, the structures of FIGS. 1 and 2 may be symmetrically arranged and two types of transmission lines may be configured to pass through the structures.

次に、図4〜図8を参照して、本実施形態の高周波パッケージ1の電気的特性について説明する。以下では、本実施形態の配線構造の電気的特性との対比のための比較例として、複数のビア導体の全体が斜め方向に延伸される従来の配線構造を想定する。図4は、特許文献3の配線構造を有する比較例に関し、11層の誘電体層L(1)〜L(11)を貫く全てのビア導体からなる斜めビア部30を介して上下の信号配線10、11が電気的に接続される構造の模式的な断面図を示している。なお、図4では、図1の配線構造のうち、11層の誘電体層L(1)〜L(11)、信号配線10、11以外の構成要素は図1と相違がないので図示を省略している。 Next, the electrical characteristics of the high frequency package 1 of the present embodiment will be described with reference to FIGS. In the following, as a comparative example for comparison with the electrical characteristics of the wiring structure of the present embodiment, a conventional wiring structure in which a plurality of via conductors are entirely extended in an oblique direction is assumed. FIG. 4 relates to a comparative example having the wiring structure of Patent Document 3, and relates to upper and lower signal wirings via diagonal via portions 30 formed of all via conductors penetrating eleven dielectric layers L(1) to L(11). The schematic sectional drawing of the structure where 10 and 11 is electrically connected is shown. 4, the components other than the eleven dielectric layers L(1) to L(11) and the signal wirings 10 and 11 in the wiring structure of FIG. 1 are not different from those of FIG. doing.

図5は、比較例(図4)のSパラメータの検証結果を示しており、図6は、本実施形態(図1)のSパラメータの検証結果を示している。図5及び図6では、周波数40GHz以下の範囲で、電子部品の端子から、それぞれの配線構造を経由して外部接続用のパッドに至る伝送線路に対し、シミュレーションによりSパラメータの周波数特性を検証したものである。Sパラメータとしては、反射特性を表すS11、S22及び透過特性を表すS21が含まれるが、高周波特性の良否は主にSパラメータS11、S22に基づいて判断することができる。なお、図5で用いた斜めビア部30と図6で用いた直線ビア部20及び斜めビア部21、22とは、いずれもビア径がXY面内で0.11mmに設定されるものとする。 FIG. 5 shows the verification result of the S parameter of the comparative example (FIG. 4), and FIG. 6 shows the verification result of the S parameter of the present embodiment (FIG. 1). In FIGS. 5 and 6, the frequency characteristic of the S parameter was verified by simulation for the transmission line from the terminal of the electronic component to the pad for external connection via each wiring structure in the frequency range of 40 GHz or less. It is a thing. The S parameters include S11 and S22 indicating the reflection characteristics and S21 indicating the transmission characteristics, and the quality of the high frequency characteristics can be determined mainly based on the S parameters S11 and S22. The diagonal via portion 30 used in FIG. 5 and the linear via portion 20 and the diagonal via portions 21 and 22 used in FIG. 6 have a via diameter set to 0.11 mm in the XY plane. ..

まず、図5に示す比較例においては、特に20GHzを超えるような高周波帯域において反射損失(S11、S22)の劣化が顕著であり、高周波信号の伝送特性としては不十分であることがわかる。これに対し、図6に示す本実施形態においては、広い周波数範囲にわたって反射損失を抑制でき、図5に比べて高周波信号の伝送特性を改善することができる。これは、上述したように、直線ビア部20及び斜めビア部21、22を連結した構造により、多重反射を回避しつつ、斜めビア部21、22を短縮してインピーダンス不整合の影響を抑制することの効果によるものである。 First, in the comparative example shown in FIG. 5, it can be seen that the deterioration of the reflection loss (S11, S22) is remarkable particularly in the high frequency band exceeding 20 GHz, which is insufficient as the transmission characteristic of the high frequency signal. On the other hand, in the present embodiment shown in FIG. 6, the reflection loss can be suppressed over a wide frequency range, and the transmission characteristic of the high frequency signal can be improved as compared with FIG. This is because the structure in which the straight via portion 20 and the diagonal via portions 21 and 22 are connected to each other as described above avoids multiple reflection, and shortens the diagonal via portions 21 and 22 to suppress the influence of impedance mismatch. This is due to the effect of that.

次に、図7は、比較例(図4)のインピーダンスの検証結果を示しており、図8は、本実施形態(図1)のインピーダンスの検証結果を示している。図7及び図8では、図5及び図6の場合と同様の条件で、シミュレーションにより信号配線とビア導体の各位置のインピーダンス特性を検証したものである。なお、図7及び図8においては、電子部品用の端子パッド側からパルス信号を入力し、信号配線とビア導体の各位置から端子側への反射信号に基づいて計算したインピーダンスを示している。また、図7には、パルス信号の入力位置からの距離に対応する時間領域の区分として、a部(信号配線10の領域)、b部(信号配線10近傍の斜めビア部30の領域)、c部(斜めビア部30の中央領域)、d部(信号配線11近傍の斜めビア部30の領域)、e部(信号配線11の領域)をそれぞれ示している。 Next, FIG. 7 shows the impedance verification result of the comparative example (FIG. 4), and FIG. 8 shows the impedance verification result of the present embodiment (FIG. 1). 7 and 8, the impedance characteristics at each position of the signal wiring and the via conductor are verified by simulation under the same conditions as in the cases of FIGS. 5 and 6. 7 and 8, the pulse signal is input from the terminal pad side for the electronic component, and the impedance calculated based on the reflection signal from each position of the signal wiring and the via conductor to the terminal side is shown. In addition, in FIG. 7, as a time region section corresponding to the distance from the input position of the pulse signal, a portion (region of the signal wiring 10), b portion (region of the oblique via portion 30 near the signal wiring 10), The section c (the central area of the oblique via section 30), the section d (the area of the oblique via section 30 near the signal wiring 11), and the section e (the area of the signal wiring 11) are shown.

一般的には、伝送線路の特性インピーダンスを50Ωとして設計することが前提であり、この場合は時間範囲の全体にわたって50Ωを保つことが理想的である。図7及び図8のいずれの特性においても、時間範囲の特定部分でインピーダンスの変動が増加しているが、これは主に入力部から接続点N1〜N4などの接合箇所までの距離を反映している。しかし、図7に示す比較例に比べ、図8に示す本実施形態においては、インピーダンスの変動幅が相対的に小さくなっており、前述のSパラメータの検証結果と相まって、本実施形態の配線構造の採用により高周波特性の向上に有効であることが確認された。 In general, it is premised that the characteristic impedance of the transmission line is designed to be 50Ω, and in this case it is ideal to keep 50Ω over the entire time range. In both the characteristics of FIG. 7 and FIG. 8, the impedance variation increases in a specific part of the time range, but this mainly reflects the distance from the input part to the connection points such as the connection points N1 to N4. ing. However, as compared with the comparative example shown in FIG. 7, in the present embodiment shown in FIG. 8, the fluctuation range of the impedance is relatively small, and in combination with the above-described S parameter verification result, the wiring structure of the present embodiment is obtained. It was confirmed that the adoption of is effective in improving the high frequency characteristics.

なお、本実施形態の高周波パッケージ1の電気的特性に関し、図6及び図8では、前述のように直線ビア部20及び斜めビア部21、22のXY面内でのビア径がXY面内で0.11mmに設定される例を示したが、斜めビア部21、22のビア径を直線ビア部20に比べて若干増加させてもよい。斜めビア21、22のビア径を増加させることにより、インダクタンス成分が減少し、容量成分が増加することにより、インピーダンスを低くすることが可能となる。この場合、直線ビア部20及び斜めビア部21、22の最適なビア径は、高周波信号の周波数や高周波パッケージ1の製造条件など多様な要素によって定まるので、例えばシミュレーションに基づき適切に調整することが望ましい。また、図1の配線構造のように、11層の誘電体層L(1)〜L(11)のうち、斜めビア部21、22の各々の積層数を3層とする場合が最も良好な高周波特性が得られるが、この点に関しても前述の多様な要素に応じて最適な積層数が変わる可能性がある。 Regarding the electrical characteristics of the high frequency package 1 of this embodiment, in FIGS. 6 and 8, the via diameters in the XY plane of the linear via portion 20 and the diagonal via portions 21 and 22 are in the XY plane as described above. Although the example is set to 0.11 mm, the via diameters of the oblique via portions 21 and 22 may be slightly increased as compared with the straight via portion 20. By increasing the via diameter of the diagonal vias 21 and 22, the inductance component decreases and the capacitance component increases, so that the impedance can be lowered. In this case, since the optimum via diameters of the straight via portion 20 and the diagonal via portions 21 and 22 are determined by various factors such as the frequency of the high frequency signal and the manufacturing conditions of the high frequency package 1, it can be appropriately adjusted based on, for example, a simulation. desirable. Further, as in the wiring structure of FIG. 1, it is most preferable that the number of the laminated layers of the diagonal via portions 21 and 22 is three layers among the eleven dielectric layers L(1) to L(11). Although high frequency characteristics can be obtained, the optimum number of layers may change depending on the various factors mentioned above.

以上、本実施形態に基づき本発明の内容を具体的に説明したが、本発明は上述の実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々の変更を施すことができる。例えば、本実施形態の高周波パッケージ1に載置される電子部品としては、半導体チップを含めた多様な電子部品を用いることができる。また、本実施形態の高周波パッケージ1において、誘電体層Lの積層数や構成材料は多様な選択が可能である。その他の点についても上記実施形態により本発明の内容が限定されるものではなく、本発明の作用効果を得られる限り、上記実施形態に開示した内容には限定されることなく適宜に変更可能である。 Although the content of the present invention has been specifically described based on the present embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. For example, various electronic components including a semiconductor chip can be used as the electronic components mounted on the high frequency package 1 of the present embodiment. Further, in the high frequency package 1 of the present embodiment, the number of layers of the dielectric layers L and the constituent materials can be variously selected. In other respects, the content of the present invention is not limited to the above-described embodiment, and the content disclosed in the above-described embodiment is not limited as long as the effect of the present invention can be obtained, and can be appropriately changed. is there.

1…高周波パッケージ
10、11…信号配線
12…グランド導体
13…グランド導体除去領域
20…直線ビア部
21、22…斜めビア部
23…グランドビア導体群
L…誘電体層
N1、N2、N3、N4…接続点
DESCRIPTION OF SYMBOLS 1... High frequency package 10, 11... Signal wiring 12... Ground conductor 13... Ground conductor removal area 20... Straight via part 21, 22... Oblique via part 23... Ground via conductor group L... Dielectric layers N1, N2, N3, N4 … Junction

Claims (5)

積層された複数の誘電体層を含む積層基板に電子部品を載置可能な高周波パッケージであって、
平面視において、前記電子部品の端子と接続される端子パッドから、前記複数の誘電体層のうち第1の誘電体層に形成された第1の接続点まで第1の方向に延びる第1の信号配線と、
平面視において、前記複数の誘電体層のうち第2の誘電体層に形成された第2の接続点から、外部接続用のパッドまで前記第1の方向に延びる第2の信号配線と、
前記複数の誘電体層を積層方向に貫き、前記第1の接続点と前記第2の接続点との間を電気的に接続する複数のビア導体と、
前記複数の誘電体層の各々に形成され、平面視において前記複数のビア導体が配置される領域を取り囲むグランド導体と、
を備え、
前記複数のビア導体は、
前記第1の誘電体層よりも下方の誘電体層に形成された上端部から、前記第2の誘電体層よりも上方の誘電体層に形成された下端部までを、前記積層方向に沿って直線状に延びる直線ビア部と、
前記第1の接続点から前記直線ビア部の前記上端部までを斜め方向に延びる第1の斜めビア部と、
前記第2の接続点から前記直線ビア部の前記下端部までを斜め方向に延びる第2の斜めビア部と、
を含み、
前記積層基板の一方の表面に前記第1の信号配線が形成されるとともに、前記積層基板の他方の表面に前記第2の信号配線が形成され、
平面視で前記第1の方向に沿って、前記第1の接続点、前記直線ビア部、前記第2の接続点が順次ずれた位置に配置される、
ことを特徴とする高周波パッケージ。
A high frequency package capable of mounting electronic components on a laminated substrate including a plurality of laminated dielectric layers,
In a plan view, a first pad extending in a first direction from a terminal pad connected to a terminal of the electronic component to a first connection point formed on a first dielectric layer of the plurality of dielectric layers. Signal wiring,
A second signal wiring extending in the first direction from a second connection point formed on the second dielectric layer of the plurality of dielectric layers to a pad for external connection in plan view;
A plurality of via conductors that penetrate the plurality of dielectric layers in the stacking direction and electrically connect the first connection point and the second connection point;
A ground conductor formed in each of the plurality of dielectric layers and surrounding a region in which the plurality of via conductors are arranged in a plan view,
Equipped with
The plurality of via conductors are
From the upper end formed in the dielectric layer below the first dielectric layer to the lower end formed in the dielectric layer above the second dielectric layer, along the stacking direction. And a linear via part that extends linearly,
A first diagonal via portion extending diagonally from the first connection point to the upper end portion of the linear via portion;
A second diagonal via portion extending diagonally from the second connection point to the lower end portion of the linear via portion;
Including
The first signal wiring is formed on one surface of the laminated board, and the second signal wiring is formed on the other surface of the laminated board,
The first connection points, the linear via portions, and the second connection points are arranged at positions that are sequentially displaced along the first direction in a plan view.
High frequency package characterized by
前記第1及び第2の斜めビア部の各々は、前記複数の誘電体層のうちの2層又は3層の誘電体層を貫くビア部であることを特徴とする請求項1に記載の高周波パッケージ。 The high frequency wave according to claim 1, wherein each of the first and second diagonal via portions is a via portion that penetrates two or three dielectric layers of the plurality of dielectric layers. package. 前記第1及び第2の斜めビア部の各々が形成される部分は、前記複数の誘電体層の全体の厚さに対して15%から30%までの範囲の厚さを有することを特徴とする請求項1又は2に記載の高周波パッケージ。 A portion in which each of the first and second diagonal via portions is formed has a thickness in a range of 15% to 30% with respect to a total thickness of the plurality of dielectric layers. The high frequency package according to claim 1 or 2. 前記第1及び第2の斜めビア部のビア径は、平面視で前記直線ビア部のビア径と比べて同一又は僅かに大きく設定されていることを特徴とする請求項1に記載の高周波パッケージ。 The high frequency package according to claim 1, wherein the via diameters of the first and second diagonal via portions are set to be the same as or slightly larger than the via diameter of the linear via portion in a plan view. .. 前記直線ビア部と前記第1及び第2の斜めビアの各々は、所望の特性インピーダンスとなるように前記ビア径が設定されていることを特徴とする請求項4に記載の高周波パッケージ。
The high frequency package according to claim 4, wherein the diameter of each of the straight via portion and each of the first and second diagonal vias is set so as to have a desired characteristic impedance.
JP2016200369A 2016-10-11 2016-10-11 High frequency package Active JP6734750B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2016200369A JP6734750B2 (en) 2016-10-11 2016-10-11 High frequency package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016200369A JP6734750B2 (en) 2016-10-11 2016-10-11 High frequency package

Publications (2)

Publication Number Publication Date
JP2018064005A JP2018064005A (en) 2018-04-19
JP6734750B2 true JP6734750B2 (en) 2020-08-05

Family

ID=61966899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016200369A Active JP6734750B2 (en) 2016-10-11 2016-10-11 High frequency package

Country Status (1)

Country Link
JP (1) JP6734750B2 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3100232B2 (en) * 1992-06-29 2000-10-16 新光電気工業株式会社 Signal lines for high-frequency electronic components
JP2004087563A (en) * 2002-08-23 2004-03-18 Nec Engineering Ltd Multilayer board and semiconductor device
JP2005243831A (en) * 2004-02-25 2005-09-08 Ngk Spark Plug Co Ltd Ceramic wiring board, manufacturing method thereof, and component-packaged wiring board using the same
JP2009188362A (en) * 2008-02-08 2009-08-20 Japan Electronic Materials Corp Ceramic laminated substrate and its manufacturing method

Also Published As

Publication number Publication date
JP2018064005A (en) 2018-04-19

Similar Documents

Publication Publication Date Title
US8643168B1 (en) Integrated circuit package with input capacitance compensation
JP6138752B2 (en) Coil component and manufacturing method thereof
JP5329737B2 (en) Multi-layer package, multi-layer ceramic package, and method for realizing high-frequency matching in multi-layer package
US9843085B2 (en) Directional coupler
JP6168943B2 (en) EBG structure, semiconductor device and circuit board
CN103458611B (en) Stacked semiconductor encapsulation, printed wiring board and printed circuit board (PCB)
JP2015056719A (en) Multilayer wiring board
JP2009212400A (en) High-frequency package
US9565750B2 (en) Wiring board for mounting a semiconductor element
US10212807B2 (en) Electrical interface for package and die
JP6320167B2 (en) Wilkinson distributor and high frequency circuit
JP6102770B2 (en) High frequency module
JP6734750B2 (en) High frequency package
JP2014154593A (en) High frequency package
US20120098615A1 (en) Broadband non-coplanar feedthrough
JP6256575B2 (en) High frequency module
JP2010016196A (en) High-frequency package
US8975737B2 (en) Transmission line for electronic circuits
JP4464291B2 (en) High frequency circuit
JP6745743B2 (en) High frequency matching circuit
JP4570607B2 (en) High frequency module package
JP4329702B2 (en) High frequency device equipment
JP2004259960A (en) Wiring board
CN105764252A (en) Wiring board
JP6724648B2 (en) Wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190507

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200217

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200225

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200424

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200616

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200710

R150 Certificate of patent or registration of utility model

Ref document number: 6734750

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250