JP6730567B2 - Plasma processing apparatus, plasma generation method, and self-bias application method - Google Patents

Description

The present invention flop plasma processing apparatus having a power supply circuit for converting the DC power into high frequency power, plasma generating method, and a self-bias applying method.

2. Description of the Related Art In recent years, as a semiconductor device manufacturing line, one device is basically formed on a 0.5 inch size (half inch size) wafer, and therefore, the manufacturing process is configured by a plurality of portable unit processing devices. , A minimal fab system has been proposed that makes it possible to relocate these multiple unit processing devices to a flow ship or a job shop, and to appropriately cope with ultra-small-volume production and high-mix production ( See, for example, Patent Document 1.).

The unit processing device adapted to this minimal fab system has a structure in which it is formed in a substantially rectangular parallelepiped shape having a longitudinal direction in the vertical direction and is shielded from the outside air. A housing having a space is provided, and a wafer processing unit for processing a half-inch size wafer is housed in the housing (see, for example, Patent Document).

International Publication No. 2012/029775

However, the minimal fab system of Patent Document 1 is a method of processing half-inch size wafers one by one in a unit processing apparatus, and as a plasma processing apparatus that performs plasma etching processing on the surface of a half-inch size wafer, No suggestions have been made. The housing of the unit processing apparatus adapted to the minimal fab system has an extremely small internal space. Therefore, for example, in an inductively coupled plasma etcher capable of independently controlling the plasma generation and the ion incident energy to the wafer. , A power supply circuit for driving a wafer processing unit such as a plasma processing apparatus, a power supply circuit used for a plasma generation unit for generating plasma in a chamber, a power supply used for a wafer bias unit for applying a bias to a wafer on a stage The circuit is also required to be downsized.

Further, in order to supply the high frequency power to the plasma generation unit or the wafer bias unit, it is necessary to suppress the reflection of the high frequency power by matching the impedance of the load such as the antenna and the bias unit with the impedance of the power source, for example, 50Ω. Therefore, an impedance matching method is used in which the impedance that changes depending on the plasma state is adjusted using a variable capacitor. In this impedance matching method, a mechanical drive component such as a motor for controlling a variable capacitor and its control circuit are required for each of the plasma generation unit and the wafer bias unit, and can be easily accommodated in the casing of the minimal fab system described above. is not. In addition, in a process method that requires gas replacement at high speed, such as the Bosch process method, a method that achieves impedance matching at high speed is effective.However, the impedance matching method described above achieves impedance matching by mechanical drive of a variable capacitor. Since the adjustment is performed, there is a problem that the time response is poor.

The present invention has been made from the actual situation in the prior art described above, and its object is suitable for minimal fab systems, miniaturization possible flop plasma processing apparatus, a plasma generation method, and to provide a self-biasing method is there.

In order to achieve the above object, the present invention provides an inverter unit that converts DC power into high frequency power and outputs the high frequency power, a transformer unit that transforms the high frequency power output from the inverter unit, and a serial connection to the transformer unit. The inductively coupled plasma generator includes a power supply circuit having the resonance capacitor, and a plasma generation antenna, which is an inductor and is supplied with the high frequency power transformed by the transformer.

According to the present invention having such a configuration, it becomes possible to increase the high frequency current flowing to the load when the inverter unit is switched at the frequency corresponding to the resonance frequency, and when the plasma generation antenna is the load. In this case, the strength of the induction electromagnetic field is increased and plasma can be generated. However, when the plasma is generated or when the state of the plasma changes, the impedance of the load fluctuates and the resonance frequency fluctuates. The deviation from the resonance state before and after can be adjusted by changing the driving frequency, and the resonance state can always be maintained and high-frequency power can be efficiently input. Therefore, high-frequency power can be input without using an impedance matching device for high-frequency power, which is a so-called matcher, which is generally composed of a variable capacitor group and a mechanical drive component for capacitor control. It becomes possible, and is suitable for a power supply circuit of a minimal fab system which is composed of unit processing devices standardized to a predetermined size.

In order to achieve the above-mentioned object, the present invention provides the frequency control, wherein the power supply circuit detects a current value between the inverter unit and the transformer unit, and controls high-frequency power output from the inverter unit. The inductively coupled plasma generator is provided with a section.

The present invention thus configured detects the current value between the inverter unit and the transformer unit and, for example, makes the phase of the voltage and current of the inverter unit equal, that is, the resonance in which the load impedance is a pure resistance component. By controlling the frequency of the high-frequency power output from the inverter unit so that the state is always maintained, it is possible to maintain the resonance state following the fluctuation of the load impedance.

Further, in order to achieve the above-mentioned object, in the present invention, the inverter unit has a plurality of switching elements, and the frequency control unit detects a voltage value of each switching element and a current value of an output current. A phase comparison unit that compares the phase of the detected voltage value and the phase of the current value, and a switching frequency control unit that controls the switching frequency of each switching element based on the phase shift compared by this phase comparison unit, And an inductively coupled plasma generator having a.

The present invention thus configured detects the voltage value of each switching element and the current value of the output current, and compares the phase of the detected voltage value and the phase of the current value in the phase comparison unit. By controlling the switching frequency of each switching element by the frequency control unit so as to eliminate the phase shift, the resonance state can be controlled accurately and at high speed.

In order to achieve the above object, the present invention provides an inverter unit that converts DC power into high frequency power and outputs the high frequency power, a transformer unit for transforming the high frequency power output from the inverter unit, and the transformer unit. Self-bias application including a power supply circuit having a resonance inductor connected in series, a self-bias capacitor to which high-frequency power transformed by the transformer is supplied, and a resonance capacitor connected in parallel to the capacitor The device.
And

According to the present invention thus configured, it becomes possible to increase the high-frequency current flowing to the load when the inverter section is switched at a frequency corresponding to the resonance frequency, and when the self-biasing capacitor is the load, It becomes possible to efficiently apply a high frequency voltage to the wafer. However, when the plasma is generated or when the plasma is changed, the impedance of the load changes, so the resonance frequency changes, but for example, a self-bias capacitor is connected as the load. Therefore, the deviation from the resonance state before and after plasma generation can be adjusted by changing the driving frequency, and the high frequency high voltage can be constantly applied to the wafer. Therefore, high-frequency power can be input without using an impedance matching device for high-frequency power, which is a so-called matcher, which is generally composed of a variable capacitor group and a mechanical drive component for capacitor control. It becomes possible, and is suitable for a power supply circuit of a minimal fab system which is composed of unit processing devices standardized to a predetermined size.

In order to achieve the above-mentioned object, the present invention provides the frequency control, wherein the power supply circuit detects a current value between the inverter unit and the transformer unit, and controls high-frequency power output from the inverter unit. The self-bias applying device is provided with a section.

The present invention thus configured detects the current value between the inverter unit and the transformer unit and, for example, makes the phase of the voltage and current of the inverter unit equal, that is, the resonance in which the load impedance is a pure resistance component. By controlling the frequency of the high-frequency power output from the inverter unit so that the state is always maintained, it is possible to maintain the resonance state following the fluctuation of the load impedance.

Further, in order to achieve the above object, the present invention, the inverter unit has a plurality of switching elements, the frequency control unit detects the voltage value of each switching element and the current value of the output current, A phase comparison unit that compares the phase of the detected voltage value and the phase of the current value, and a switching frequency control unit that controls the switching frequency of each switching element based on the phase shift compared by this phase comparison unit, A self-bias applying device having

The present invention thus configured detects the voltage value of each switching element and the current value of the output current, and compares the phase of the detected voltage value and the phase of the current value in the phase comparison unit. By controlling the switching frequency of each switching element by the frequency control unit so as to eliminate the phase shift, the resonance state can be controlled accurately and at high speed.

In order to achieve the above object, the present invention provides a stage on which a wafer is installed, a chamber that covers the stage, a vacuuming unit that evacuates the chamber, and a position of the chamber that faces the stage. 4. A gas supply unit provided in the gas supply unit, a plasma generation unit having the inductively coupled plasma generation device according to claim 1, and generating a plasma in the etching gas in the gas supply unit. 7. A plasma processing apparatus comprising: the self-bias applying apparatus according to any one of 6 to 6; and a wafer bias section that applies a high-frequency voltage to a wafer placed on the stage to induce a DC self-bias.

According to the present invention thus configured, the wafer is placed on the stage, the chamber is evacuated by the evacuation unit, and then the etching gas is supplied from the gas supply unit to the plasma generation unit to the plasma generation antenna. High frequency power is supplied to generate plasma. Before and after plasma generation, the impedance of the load consisting of the plasma generation antenna and plasma changes, so the resonance frequency fluctuates, and the phase of the output current and voltage of the inverter section of the inductively coupled plasma generator is aligned. By controlling the frequency of the high frequency power as described above, the resonance state can be maintained at high speed without using a variable capacitor. The plasma and radical species generated by the plasma generation unit reach the wafer by diffusion. At the same time, the high frequency voltage output from the self-bias applying device is applied to the wafer. Since the resonance frequency of the wafer bias part changes due to the inflow of plasma from the plasma generation part into the region including the wafer installed on the stage, the phase of the output current and voltage of the inverter part of the self-bias applying device is aligned. By controlling the frequency of the high frequency power in the wafer bias section as described above, the resonance state can be maintained at high speed without using a variable capacitor.

That is, the resonance generated by the plasma generation antenna, the resonance capacitor, and the plasma in the plasma generation unit, and the resonance generated by the resonance inductor, the self-bias capacitor, the resonance capacitor, and the plasma in the wafer bias unit It can be maintained by controlling. Therefore, by controlling so that the phases of the high frequency voltage and the current output from the inverter section become equal, the wafer bias section is connected even when the plasma generation antenna is connected as the supply destination of the high frequency power. Even when the plasma is present, the resonance state before and after the plasma generation can be maintained. Therefore, the resonance state can be maintained without using an impedance matching device of a high frequency power, which is generally called a so-called matcher, so that the size can be reduced and the size is standardized. It is suitable as a control method for a power supply circuit of a minimal fab system composed of a unit processing device. In addition, there is no mechanical drive part that controls the variable capacitor in the matcher, and the resonance state is maintained only by controlling the frequency, so there is also a high speed response in time, and a high-speed response such as the Bosch process. It is also suitable for processes that require quality.

In order to achieve the above object, the present invention provides an inverter unit having a plurality of switching elements for converting DC power into high frequency power and outputting the high frequency power, and a transformer for transforming the high frequency power output from the inverter unit. A plasma generation method using a power supply circuit comprising a transformer unit and an inductor and a capacitor connected in series to the transformer unit, wherein the switching is performed so that phases of high frequency power output from the inverter unit become equal. The plasma generation method was used to control the switching frequency of the device.

In the present invention thus configured, the resonance state can be always maintained by controlling the switching frequency of the switching element so that the phases of the high frequency power output from the inverter unit become equal. On the other hand, since the output power corresponding to the product of the voltage and the current in the same phase is determined by the impedance of the output side circuit including the transformer connected to the inverter and the DC power supply voltage, stable control can be realized.

In order to achieve the above object, the present invention provides an inverter unit having a plurality of switching elements for converting DC power into high frequency power and outputting the high frequency power, and a transformer for transforming the high frequency power output from the inverter unit. A self-bias applying method using a power supply circuit comprising a transformer and an inductor and a capacitor connected in series to the transformer, wherein the high frequency power output from the inverter is equalized in phase. The self-bias application method is used to control the switching frequency of the switching element.

In the present invention thus configured, the resonance state can be always maintained by controlling the switching frequency of the switching element so that the phases of the high frequency power output from the inverter unit become equal. On the other hand, since the output power corresponding to the product of the voltage and the current in the same phase is determined by the impedance of the output side circuit including the transformer connected to the inverter and the DC power supply voltage, stable control can be realized.

According to the present invention, the output of the output destination can be controlled without using a high-frequency power impedance matching device, which is a so-called matcher having a large structure generally composed of a variable capacitor group and a control component group such as a motor and a gear. Since the resonance state can be maintained, it can be miniaturized and can be used for a power supply circuit of a minimal fab system configured by a unit processing device standardized to a predetermined size.

In addition, the above-described effect can save space for two impedance matching devices called matchers in a plasma processing apparatus that requires high-frequency power for each of the plasma generation unit and the wafer bias unit, which are composed of an inductively coupled plasma source. Therefore, it is suitable for the power supply circuit of the minimal fab system.

It is a schematic diagram showing a plasma treatment apparatus concerning one embodiment of the present invention. It is the schematic which shows the power supply circuit which supplies high frequency electric power to the plasma generation part of the said plasma processing apparatus. It is a schematic diagram showing a power supply circuit which supplies high frequency electric power to a wafer bias part of the above-mentioned plasma processing apparatus. It is a control circuit diagram which shows the inverter part of the said plasma processing apparatus. It is an external view showing a housing in which the plasma processing apparatus is housed. It is a schematic diagram showing a layout in the above-mentioned case. 6 is a flowchart showing a frequency control method by a frequency control unit of a power supply circuit that supplies high-frequency power to the wafer bias unit. It is a flowchart which shows the frequency control method by the electric power control part of the said power supply circuit. It is a graph which shows a mode at the time of supplying high frequency electric power to the wafer bias part of the said plasma processing apparatus. It is an electron micrograph which shows the state of the wafer plasma-processed by the said plasma processing apparatus.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram showing a plasma processing apparatus 10 according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing a high frequency power supply circuit 7 for supplying high frequency power to the high frequency antenna 5e installed in the plasma generation unit 11 of the plasma processing apparatus 10. FIG. 3 is a schematic diagram showing a high frequency power supply circuit 9 for supplying high frequency power to the stage 6 installed in the process unit 12 of the plasma processing apparatus 10. FIG. 4 is a circuit diagram showing the high frequency power supply circuits 7 and 9 of the plasma processing apparatus 10. FIG. 5 is an external view showing the housing 2 in which the plasma processing apparatus 10 is housed. FIG. 6 is a schematic diagram showing a layout inside the housing 2.

<Overall structure>
As shown in FIGS. 5 and 6, a plasma processing apparatus 10 according to an embodiment of the present invention is a minimal etching based on a minimal fabrication concept housed in a housing 2 having a standard size. It is a device, and is housed in the minimal fab system processing device 1 as a unit processing device (small device). Here, the minimal fab concept is optimal for the semiconductor manufacturing market of high-mix low-volume production, and can be used for a variety of fabs that are resource-saving, energy-saving, investment-saving, and high-performance, and are described in, for example, JP2012-54414A. To realize a minimal production system that minimizes the production of.

The housing 2 is formed in a substantially rectangular parallelepiped shape having a longitudinal direction in the vertical direction, and has a uniform size of width (x) 0.294 m x depth (y) 0.45 m x height (z) 1.44 m. This is a processing chamber in which the invasion of fine particles and gas molecules into the interior is blocked and the atmosphere is blocked. A wafer processing unit 2 f for processing a wafer W is provided on the upper part 2 a of the apparatus on the upper side of the housing 2. The wafer processing unit 2f accommodates a plasma processing apparatus 10, which is a processing apparatus main body for ion-etching the wafer W. Here, as the plasma etching by the plasma processing apparatus 10, the surface of the wafer W is etched corresponding to the resist pattern stacked on the surface of the wafer W.

A supply unit 3 a for supplying, for example, an etching gas G used for plasma etching in the plasma processing apparatus 10 is housed in the apparatus upper portion 2 a above the plasma processing apparatus 10. The processing device 1 for the minimal fab system is unified to perform each process with power consumption of AC 100V and 10A.

On the lower side of the housing 2, an apparatus lower portion 2b for incorporating a control device or the like for controlling the plasma processing apparatus 10 in the apparatus upper portion 2a is provided. A high pressure cylinder (not shown) filled with an etching gas G used for etching in the plasma processing apparatus 10 is housed in the lower portion 2b of the apparatus. On the back surface of the lower part 2b of the apparatus, there is provided a discharge part 3b which serves as an outlet for discharging a gas such as the etching gas G used after etching in the plasma processing apparatus 10 to the outside of the housing 2. The discharge unit 3b is connected to a tank (not shown) that stores the gas discharged from the discharge unit 3b.

The front side of the device upper part 2a is formed in a concave shape in the upper middle portion of the device upper part 2a of the housing 2 in the vertical direction. An operation panel 2c is attached to the front side of the upper side of the device upper portion 2a. The lower part of the apparatus upper part 2a is a front chamber 2d for loading the wafer W into the housing 2. A substantially circular docking port 2e is provided as a shuttle accommodating portion for installing a minimal shuttle (not shown) as a transport container at a substantially central portion on the upper surface of the front chamber 2d. The docking port 2e is provided with a clamp (not shown) for fixing the minimal shuttle fitted in the docking port 2e.

The front chamber 2d is configured to block each of fine particles and gas molecules entering the housing 2. In the front chamber 2d, a PLAD (Particle Lock Air-tight Docking) as a transfer device for allowing the wafer W accommodated in the minimal shuttle to be taken in and out of the housing 2 without being exposed to the outside air. System 2g is attached. PLAD system 2
In g, the wafer W carried in from the docking port 2e is carried to a predetermined position of the plasma processing apparatus 10, and the wafer W etched by the plasma processing apparatus 10 is carried out to the docking port 2e.

<Plasma processing device>
The plasma processing apparatus 10 is housed in a wafer processing unit 2f on the upper rear side of the front chamber 2d in the housing 2. The wafer W to be etched by the plasma processing apparatus 10 has a circular surface having a predetermined size, for example, a diameter of 12.5 mm (half inch size), and has a disk shape made of single crystal silicon (Si). Has been formed. A predetermined resist pattern is formed in advance on the surface of the wafer W and is in a state before plasma etching. Here, the wafer W is a wafer size that conforms to the minimal fab concept, that is, an extremely small wafer size for manufacturing a semiconductor device in an extremely small unit.

The minimum unit is a semiconductor device in a minimum unit, for example, one semiconductor device of 1 cm ² is manufactured from a wafer W of 0.5 inch size (half inch size), or the size of the device to be manufactured. The number of the minimum units is not limited to one, and if the wafer size is extremely small for manufacturing a semiconductor device in a minimum unit, the number of minimum units may be two or more as long as it can be manufactured from one wafer W.

The plasma processing apparatus 10 is a reactive ion etching apparatus using a so-called high-frequency inverter, that is, a plasma etcher of ICP (Inductively Coupled Plasma). The plasma processing apparatus 10 applies a high frequency power to a high frequency antenna 5e attached to a plasma generation insulating tube 5d described later to generate plasma, thereby generating a large amount of fluorine radicals (F) and electrons and ions in the etching gas G. (SF ²⁺ , Ar ⁺ ) is generated, a high frequency voltage is applied to the stage 6 to generate an ion sheath, and the positive ions (SF ²⁺ , Ar ⁺ ) ionized by the plasma generation unit 11 are applied to the surface of the wafer W. It is hit almost vertically to perform vertical etching. As shown in FIG. 1, the plasma processing apparatus 10 includes a chamber 5 and a stage 6 installed in the chamber 5, and the stage 6 is hermetically covered with the chamber 5.

<Chamber>
The chamber 5 is composed of, for example, a grounded metal vacuum container. The chamber 5 has a cylindrical or rectangular parallelepiped main body portion 5a, is installed with the axial direction of the main body portion 5a along the vertical direction, and the upper end side of the main body portion 5a is closed by a disc-shaped upper plate 5b. It is shaped. A circular opening 5c is formed at the central position of the upper plate 5b, and the lower end side of the plasma generation insulating tube 5d, which is an insulating tube as a plasma generating section, maintains airtightness in the opening 5c. Installed. The plasma generation insulating tube 5d has a cylindrical shape having an outer dimension smaller than the inner dimension of the main body 5a and slightly larger than the outer dimension of the wafer W, and is formed of a circular insulating material tube such as glass or ceramic. .. The lower end side of the plasma generation insulating tube 5d is attached to the opening 5c by adhesion or an O-ring seal.

An etching gas G such as a mixed gas (SF ₆ /Ar) of sulfur hexafluoride (SF ₆ ) and argon (Ar) is supplied from the upper part of the plasma generation insulating tube 5d, and the plasma generation insulating tube 5d is supplied. Plasma P is generated at 5d. As an etching gas G, sulfur hexafluoride or only gas (SF _6), carbon tetrafluoride (CF ₄₎ only a gas, carbon tetrafluoride (CF ₄₎ and argon (Ar) and oxygen (O ₂ ) mixed gas (CF ₄ /Ar/O ₂ ) or the like may be used.

A high frequency antenna 5e, which is a plasma generation antenna corresponding to an inductor, is attached to the plasma generation insulating tube 5d. The high frequency antenna 5e is also a radical generation unit that ionizes the etching gas G inside the plasma generation insulating tube 5d to generate plasma P and generate a large amount of fluorine radicals (F) derived from the plasma P. The high frequency antenna 5e is a power supply target that is an inductive load of the inductively coupled plasma source, and, for example, a conductive copper wire or the like is provided outside the plasma generation insulating tube 5d, in the circumferential direction of several tens to several hundreds of turns. It is configured in a wound coil shape. Antenna terminals 5f and 5g as electrode portions are provided at both ends of the high frequency antenna 5e, that is, at the upper end and the lower end, respectively.

A high-frequency power supply circuit 7, which is a high-frequency power supply device as a first power supply circuit for supplying a high-frequency current to the high-frequency antenna 5e having inductive impedance, is attached between the antenna terminals 5f and 5g. The high frequency power supply circuit 7 applies high frequency power between the antenna terminals 5f and 5g, and induces a plasma P in the etching gas G passing through the inside of the plasma generation insulating tube 5d by an induction electromagnetic field generated by a high frequency current flowing through the high frequency antenna 5e. generate. The plasma generation insulating tube 5d serves as a plasma generation unit 11 that ionizes part of the etching gas G passing through the plasma generation insulating tube 5d to generate plasma P and fluorine radicals (F). Here, the high frequency antenna 5e and the high frequency power supply circuit 7 constitute an inductively coupled plasma generator 10A.

Below the chamber 5, a lid 5h that closes the lower end of the chamber 5 is attached. A vacuum forming device 8 is attached to the lid 5h as a vacuuming unit for vacuuming the inside of the chamber 5. The vacuum forming apparatus 8 is housed in the lower portion 2b of the apparatus, and evacuates the chamber 5 with the wafer W placed on the stage 6 in the chamber 5.

As shown in FIG. 2, the high frequency power supply circuit 7 is a full-bridge type inverter power supply, and is supplied with DC power from a DC power supply 7a as a DC power supply unit for supplying DC power and DC power from the DC power supply 7a. , A power conversion circuit 7c that converts a direct current of the direct current power into a high frequency power of, for example, several hundreds kHz by switching and outputs the high frequency power, and a gate driver circuit 7m for controlling the frequency of the high frequency power output by the power conversion circuit 7c. With. The gate driver circuit 7m is configured to control the gate voltage of each of the switching elements S1 to S4.

The current conversion circuit 7c is provided with a bridge circuit 7g as an inverter power supply unit having a plurality of switching elements S1 to S4, for example, a total of four switching elements including FET elements or IGBT elements. Two switching elements S1 and S2 among these switching elements S1 to S4 are connected in series to form a series circuit 7h, which is connected in parallel to a DC power supply 7a. The other two switching elements S3, S4 are also made into a series circuit 7i connected in series, and the series circuit 7h of the other two switching elements S1, S2 except these two switching elements S3, S4 and the DC power supply 7a. They are connected in parallel to each other. A transformer 7j as a transformer for impedance conversion is connected in series between the switching elements S1 and S2 and between the switching elements S3 and S4 of each series circuit 7h and 7i. The transformer 7j is connected in series with the high frequency antenna 5e. A resonance capacitor C is connected in series between the transformer 7j and the high frequency antenna 5e.

<Stage>
As shown in FIG. 1, the stage 6 is installed vertically below the opening 5 c of the chamber 5 while being housed in the chamber 5 and along the axial direction of the chamber 5 in the vertical direction. The stage 6 is located concentrically with respect to the opening 5c of the chamber 5, and is installed at a position spaced downward from the opening 5c by a predetermined distance. The stage 6 includes a columnar main body 6a, and is installed with the axial direction of the main body 6a along the vertical direction. The upper end surface of the main body portion 6a is closed to form a flat disk-shaped installation surface 6b, and the wafer W is installed on the installation surface 6b. That is, the main body portion 6a is formed to have an outer diameter dimension slightly larger than the outer diameter dimension of the wafer W, and serves as an installation surface 6b having a diameter dimension slightly larger than the outer diameter dimension of the wafer W.

Wafer bias terminals 6c and 6d are connected to the lower surface of the main body 6a of the stage 6 and the lid 5h of the chamber. A high frequency power supply circuit 9 which is a high frequency power supply device is connected between the wafer bias terminals 6c and 6d, and high frequency power is supplied from the high frequency power supply circuit 9 to the wafer bias terminals 6c and 6d. A high frequency power supply circuit 9 applies a high frequency voltage between the wafer W and the chamber 5 in a state where electrons and ions in the plasma P generated by the plasma generation unit 11 are diffused and flown into the wafer W. Since the DC current is suppressed by the included blocking capacitor C1, the wafer W is charged, an ion sheath is generated in the vicinity of the wafer W, and a vertical DC electric field is formed. Therefore, by applying high frequency power to the wafer W by the high frequency power supply circuit 9, the energy of the ions incident on the wafer W is controlled. That is, the stage 6 serves as a process unit 12 as a wafer bias unit that applies a bias to the wafer W placed on the stage 6 by the high frequency power supplied from the high frequency power supply circuit 9. Here, the high-frequency power supply circuit 9 and the wafer bias terminals 6c and 6d constitute a self-bias applying device 10B for generating a DC voltage that is spontaneously generated due to the plasma P.

The high frequency power supply circuit 9 is a high frequency power application device as a second power supply circuit for applying a high frequency voltage between the wafer stage 6c having a capacitive impedance and the chamber 6d. As with the high frequency power supply circuit 7, the high frequency power supply circuit 9 is supplied with a DC power supply 9a as a DC power supply unit for supplying direct current power and a DC power supply from the DC power supply 9a, as shown in FIG. A power conversion circuit 9c for converting and outputting the high frequency power of 100 kHz and a gate driver circuit 9m for controlling the frequency of the high frequency power output by the power conversion circuit 9c are provided. The gate driver circuit 9m is configured to control the gate voltage of each of the switching elements S5 to S8.

The current conversion circuit 9c includes a bridge circuit 9g serving as an inverter unit having a plurality of switching elements S5 to S8, for example, a total of four switching elements including FET elements or IGBT elements. Two switching elements S5 and S6 of these switching elements S5 to S8 are connected in series to form a series circuit 9h, which is connected in parallel to a DC power supply 9a. The other two switching elements S7 and S8 are also made into a series circuit 9i connected in series, and the series circuit 9h of the other two switching elements S5 and S6 excluding these two switching elements S7 and S8 and the DC power source 9a. They are connected in parallel to each other. A transformer 9j as a transformer for transforming high frequency power is connected in series between the switching elements S5 and S6 and between the switching elements S7 and S8 of the series circuits 9h and 9i. The transformer 9j is an output load and is connected in series between the wafer bias terminals 6c and 6d corresponding to a capacitor. A resonance capacitor C2 is connected in parallel between the transformer 9j and the wafer bias terminals 6c and 6d. Between the resonance capacitor C2 and the transformer 9j, a resonance inductor I and a blocking capacitor C1 which is a self-bias inducing capacitor for reducing the direct current of the load to zero are connected in series. Then, the resonance inductor I and the resonance capacitor C2 form an LC resonance circuit.

The high-frequency power supply circuit 7 (9) is controlled by the control circuit shown in FIG. 4 so as to satisfy each resonance condition and power set value described later. The power control unit 7b (9b) monitors the voltage value of the DC power output from the DC power supply 7a (9a) and performs PID (Proportional-Integral-Derivative) control. The power control unit 7b (9b) detects the power value output from the DC power supply 7a (9a) and outputs it as a power signal by a power detection unit 7e (9e) and a power detection unit 7e (9e). And a PID control circuit 7f (9f) as a power control circuit that controls the power value of the DC power output by the DC power supply 7a (9a) based on the power signal output by the DC power supply 7a (9a). The PID control circuit 7f (9f) is input with an output power setting value for setting the power value of the DC power output by the DC power supply 7a (9a).

The frequency control unit 7d (9d) includes an output current of the bridge circuit 7g (9g), that is, a series circuit 7h in which two switching elements S1, S2, S3, S4 (S5, S6, S7, S8) are connected in series. The current value (current signal) between 7i (9h, 9i) and the transformer 7j (9j) is detected, and this current signal and the gate voltage signals of S1 to S4 (S5 to S8) in phase with the output voltage. The phase comparison circuit 7k (9k) to which is input and the gate driver circuit 7m (9m) that generates the gate voltage of each switching element S1 to S4 (S5 to S8) are compared with the phase comparison circuit 7k (9k). And an integrator 7n (9n) that integrates the phase difference and a switching frequency control unit that outputs a clock signal obtained by shifting the frequency of the signal of the integrator 7n (9n) from a predetermined reference voltage that gives an initial frequency. It has a voltage-controlled oscillator (VCO) 7p (9p). The voltage signal output from the voltage controlled oscillator 7p (9p) to the gate driver circuit 7m (9m) is input to the phase comparison circuit 7k (9k) and the voltage corresponding to the phase of the output voltage of the bridge circuit 7g (9g) is input. The phase of the signal is compared with the phase of the current signal of the output current of the bridge circuit 7g (9g), and the phase difference between the high frequency voltage and the current output by the bridge circuit 7g (9g) is calculated every predetermined time. By this control, the phase difference between the high-frequency voltage and the current becomes zero, that is, the impedance of the load connected to the bridge circuit 7g (9g) becomes a pure resistance component, that is, the resonance frequency is maintained. Is automatically adjusted. By operating the bridge circuit 7g (9g) and the frequency controller 7d (9d) at the same time, it is possible to control the output power to be kept constant while maintaining the resonance state.

Next, a plasma etching method using the plasma processing apparatus 10 of the above embodiment will be described.

First, the minimal shuttle containing the wafer W before etching is fitted into the docking port 2e of the front chamber 2d of the housing 2 and installed. In this state, a start switch (not shown) displayed on a predetermined position of the housing 2, for example, the operation panel 2c is pushed. Then, the minimal shuttle installed in the docking port 2e is opened, and the wafer W accommodated in the minimal shuttle is transferred to the predetermined position on the stage 6 of the plasma processing apparatus 10 by the PLAD system 2g and installed. At this time, the stage 6 is in a state in which the stage 6 is taken out from the chamber 5 by, for example, the stage 6 and the chamber 5 being moved up and down relatively.

After that, the chamber 5 of the plasma processing apparatus 10 is sealed by the lid 5h, and the inside of the chamber 5 is evacuated by the vacuum forming apparatus 8 until the inside of the chamber 5 becomes substantially vacuum. In this state, the etching gas G is supplied to the plasma generation insulating pipe 5d connected to the chamber 5, and the pressure inside the plasma generation insulating pipe 5d and the chamber 5 is maintained at a predetermined pressure. After that, each of the high-frequency power supply circuits 7 and 9 is turned on, high-frequency power is supplied to the high-frequency antenna 5e, and a plasma P composed of ions, electrons, and radicals is generated inside the insulating tube 5d for plasma generation, and is transferred to the wafer W. Spread towards. In the high frequency power supply circuit 9 for applying high frequency power to the stage 6, the DC current is suppressed to zero by the blocking capacitor C1 inserted in series, so that the flux of ions and electrons flowing from the plasma P into the wafer W becomes equal. Then, the wafer W is charged. As a result, a potential gradient along the direction toward the wafer W is formed near the wafer W, and a vertical electric field is formed.

As a result, the etching gas G generates plasma P in the etching gas G by the high-frequency power applied to the high-frequency antenna 5e when passing through the place where the high-frequency antenna 5e is attached in the plasma generation insulating tube 5d. Then, the fluorine of SF ₆ forming this etching gas G is radicalized to generate a large amount of fluorine radicals (F). That is, SF ₆ in the etching gas G is separated and a large amount of fluorine radicals (F) are generated.

Further, the high frequency power applied to the stage 6 forms the ion sheath and the electric field E along the vertical direction above the stage 6 as described above. As a result, the positive ions (SF ²⁺ , Ar ⁺ ) of the plasma P that have diffused from the plasma generation insulating tube 5d are accelerated and hit perpendicularly onto the wafer W, and the wafer W is etched. At the same time, the radicalized fluorine radicals (F) diffused from the plasma generation insulating tube 5d chemically react with the wafer W, and the wafer W is etched. Since these two etching processes proceed through the resist pattern provided on the wafer W, the wafer W is plasma-etched according to the resist pattern formed in advance.

That is, the fluorine radicals (F) and ions (SF ²⁺ , Ar ⁺ ) derived from the plasma P are supplied to the wafer W by the high-frequency power applied to the high-frequency antenna 5e, and the wafer W is supplied to the wafer W by the high-frequency power applied to the stage 6. The ion incident energy of is controlled. The etching process by the chemical reaction between these fluorine radicals (F) and Si and the physical etching process by the ions are superposed, so that the etching process of silicon proceeds. Further, when mixed with oxygen (O ₂₎ protective film such as gas (SiO ₂₎ for forming an etching gas G includes a protective film formed on the etching hole, physical etching of the bottom protective film by ions, and fluorine By simultaneously proceeding with the silicon etching process by radicals (F), etching processing with a high aspect ratio is realized.

After that, after the etching of the wafer W is completed, the sealing of the chamber 5 is released, and the stage 6 is taken out of the chamber 5 by moving the stage 6 and the chamber 5 relative to each other, for example. The wafer W placed above is placed on the minimal shuttle by the pullback operation of the PLAD system 2g, and then the minimal shuttle is closed to accommodate the wafer W. Further, by removing the minimal shuttle containing the wafer W from the docking port 2e of the front chamber 2c, the wafer W is unloaded.

Next, resonance control of the high frequency power supply circuit 7 that applies high frequency power to the high frequency antenna 5e of the plasma generation unit 11 of the plasma processing apparatus 10 according to the above-described embodiment will be described.

From the viewpoint of suppressing switching loss, the inverter-type high frequency power supply circuit 7 sets the drive frequency to be output, that is, the frequency of the high frequency power to a relatively low frequency such as 100 kHz to 500 Hz. Since the dielectric magnetic field generated by the high frequency antenna 5e is proportional to dΦ/dt (Φ: interlinking magnetic flux), the plasma generating unit 11 can generate the plasma P at the frequency of the high frequency power to be output. The number of turns of the high frequency antenna 5e is, for example, in the range of about 30 to 300 turns.

The frequency of the high frequency power output from the high frequency power supply circuit 7 can be easily controlled by using the above voltage controlled oscillator 7p as the input clock frequency to the gate driver circuit 7m. Since it is connected to the high frequency antenna 5e via the transformer 7j and the resonance capacitor C that play a role of impedance conversion for operating within the range of the voltage/current capacity of the DC power supplied from the DC power supply 7a, When the inductance of the antenna 5e is L and the capacitance of the resonance capacitor C is C, the maximum frequency f of the output high frequency power is (Equation 1) f=1/2π√(LC).

However, when the plasma P is generated in the plasma generation insulating tube 5d, the impedance of the load changes due to the impedance of the generated plasma P itself. Therefore, by controlling the frequency of the output high-frequency power, it becomes possible to maintain the optimum impedance matching state before and after the plasma P is generated, that is, at all times. Therefore, after the plasma P is generated, the input clock frequency to the gate driver circuit 7m is adjusted, for example, manually or automatically so that the frequency of the output high-frequency power becomes equal to the resonance frequency. Maintain the impedance resonance state.

Next, a self-bias inducing method and resonance control of the high frequency power supply circuit 9 for applying a high frequency voltage to the process unit 12 of the plasma processing apparatus 10 of the above embodiment will be described with reference to FIG.

In the high frequency power supply circuit 9, the stage 6 on which the wafer W is installed is a load, and the stray capacitance (Csub) between the stage 5 and the inner wall of the chamber 5 is the main component of the impedance. It is a value of about 100 pF, which is unique to the configuration of each plasma processing apparatus 10. In order to satisfy the resonance condition of the above formula 1 for a capacitive load of several tens of pF to several hundreds of pF within the frequency range of the high frequency power output by the high frequency power supply circuit 9, for example, a relatively large size of approximately 1 mH to 100 mH is used. Inductance is required. Therefore, a resonance capacitor C2 of about several μF, which is sufficiently larger than the stray capacitance (Csub), is connected in parallel to the stage 6, and the impedance of the load of the high frequency power supply circuit 9 is determined only by the resonance capacitor C2. There is.

Further, the main purpose of applying the high frequency voltage to the stage 6 is to induce DC self-bias due to the behavior of ions and electrons in the plasma P. By inserting a capacitor in series with the load circuit, the DC current becomes zero. It is necessary to configure the circuit so that
The blocking capacitor C1, which is a self-biasing capacitor, is inserted in series. The resonance condition in this case is (Equation 2) f=1/2π√(LCs), where Cs=(C1×C2)/(C1+C2). At this time, the required inductance is 150 μH, which allows a sufficiently small design, and the high frequency power applied to the stage 6 is determined by the current I output from the transformer 9j and the resonance capacitor C2. Here, in the high frequency power supply circuit 9, since the DC current due to the plasma charged particles flowing into the stage 6 from the blocking capacitor C1 becomes zero (0), the DC bias is automatically and spontaneously applied to the stage 6. When applied, the insulator such as an oxide film can be etched.

Next, with reference to FIG. 4, FIG. 7, and FIG. 8, for automatic resonance control and power control of the high-frequency power supply circuits 7 and 9 used in the plasma generation unit 11 and the process unit 12 of the plasma processing apparatus 10 of the above-described embodiment, respectively. And explain. However, in the above-described embodiment, the high-frequency power supply circuits 7 and 9 are equivalent to the DC power supply unit 7a (9a), the gate driver circuit 7m (9m), and the switching elements S1 to S4 (S5 to S8). Therefore, the same control can be applied to each of the high frequency power supply circuits 7 and 9.

Specifically, the high frequency power supply circuit 7 (9) automatically follows so that the output voltage of the high frequency power output from the bridge circuit 7g (9g) and the phase of the output current of this high frequency power become equal. The initial frequency of the high frequency power output from the bridge circuit 7g (9g) before the plasma P is generated in the plasma generation unit 11 is input to the high frequency power supply circuit 7 (9) in advance (step S11). Then, the voltage signal of the gate voltage of each of the switching elements S1 to S4 (S5 to S8) having the same phase as the output voltage of the bridge circuit 7g (9g) and the current signal of the high frequency power output from the bridge circuit 7g (9g). Are input to the phase comparison circuit 7k (9k), the phases of the voltage signal and the current signal are compared, and the gate voltage is calculated from the resonance frequencies of the switching elements S1 to S4 (S5 to S8) of the bridge circuit 7g (9g). The value obtained by converting the deviation of the frequency (gate frequency) into the voltage is output by the phase comparison circuit 7k (9k) (step S12).

Then, voltage control is performed so that the frequency of the gated voltage signal of each of the switching elements S1 to S4 (S5 to S8) becomes equal to the phase of the output current output to the transformer 7j (9j) by the bridge circuit 7g (9g). The clock frequency of the gate voltage of each of the switching elements S1 to S4 (S5 to S8), that is, the switching frequency is controlled by the pattern oscillator 7p (9p) (step S13).

When the plasma P is generated by the plasma generation unit 11, the impedance of each of the plasma generation unit 11 and the process unit 12 varies due to the impedance of the plasma P itself (step S14). Then, whether the phase of the voltage signal of the gate voltage of each switching element S1 to S4 (S5 to S8) is larger than the phase of the current signal of the high frequency power output from the bridge circuit 7g (9g) is the phase comparison circuit 7k (9k). Is determined (step S15).

When the phase of the voltage signal is larger than the phase of the current signal (step S15/YES), the frequency of the gate signal of each of the switching elements S1 to S4 (S5 to S8) is reduced by the voltage controlled oscillator 7p (9p). When the phase of the voltage signal is equal to or less than the phase of the current signal (step S15/NO), the voltage control type oscillator 7p (9p) controls the gate signals of the switching elements S1 to S4 (S5 to S8). The frequency of the gate signal of each of the switching elements S1 to S4 (S5 to S8) in phase with the output voltage of the bridge circuit 7g (9g) is controlled by the bridge circuit 7g (9g) to the transformer 7j ( By repeating the processes of steps S12 to S15 until the phase of the output current to be output to 9j) is equalized, the resonance frequency varying depending on the state of the plasma P is automatically tracked.

Furthermore, when the plasma P is generated by the plasma generation unit 11, the high frequency power supply circuit 7 (9) supplies impedance to the high frequency antenna 5e and the stage 6 because the impedance of the plasma P itself causes the impedance to be changed. The generated high frequency power itself also fluctuates. Therefore, the power control unit 7b (9b) presets the output power set value as the target value, that is, the set power in the PID control circuit 7f (9f) (step S21). Then, the power detector 7e (9e) calculates the power value of the DC power output by the DC power supply 7a (9a) based on the voltage value and the current value output by the DC power supply 7a (9a), and the calculated power A power signal based on the value is output to the PID control circuit 7f (9f) (step S22). Thereafter, the PID control circuit 7f (9f) determines whether or not the power value according to the output power signal, that is, the output power is larger than the set power (step S23).

Then, when the output power is larger than the set power (step S23/YES), the PID control circuit 7f (9f) is controlled to reduce the output power of the DC power supply 7a (9a), and the output power is less than or equal to the set power. In this case (step S23/NO), the PID control circuit 7f (9f) is controlled to increase the output power of the DC power supply 7a (9a) until the output power of the DC power supply 7a (9a) becomes equal to the set power. The processing in steps S21 to S23 is repeated, and stable power supply is performed from the DC power supply 7a (9a).

In the plasma processing apparatus 10 according to the above-described embodiment, for the purpose of optimizing the precision vertical processing having anisotropy and the etching rate at that time, the control of the ion density and the radical density in the plasma generation unit 11 and the wafer W are performed. It is necessary to control the incident energy of the ions with respect to. In particular, when the process of laminating the protective film on the wafer W and the process of ion-etching only the bottom portion of the protective film are simultaneously performed, it is necessary to apply high-frequency power having a higher frequency to the process unit 12. This need is addressed by separating the high frequency power supply circuit 7 that supplies high frequency power to the high frequency antenna 5e of the plasma generation unit 11 and the high frequency power supply circuit 9 that supplies high frequency power to the stage 6 of the process unit 12. Then, the automatic control is applied to each as described above.
Can handle.

The processing apparatus 1 for a minimal fab system has a relatively small housing 2 in which all components including an evacuation system, a gas control system, a plasma source, a bias power supply, an apparatus control interface, a gas cylinder, and an exclusion facility are included. Need to be stowed. Therefore, it is necessary to reduce the size of each of the high frequency power supply circuit 7 for the plasma generation unit 11 and the high frequency power supply circuit 9 for the process unit 12. In the case of using a conventional matcher, these high-frequency power supply circuits 7 and 9 have a large space occupancy in the housing 2, and for the purpose of suppressing power loss in wiring and impedance variation due to wiring as much as possible, Since the matcher needs to be installed close to the load or directly attached to the load, the device design and design restrictions are very large.

Furthermore, in each of the high frequency power supply circuits 7 and 9, it is desired to further reduce heat exhaustion and power consumption, and therefore it is necessary to increase the conversion efficiency from DC power to high frequency power. In particular, when each component is housed in the housing 2, high-frequency noise may occur due to the characteristics of the output high-frequency power, which may cause malfunction or damage of the device. There is a need to. Generally, as a method of suppressing high frequency noise, shielding with a ground metal is effective, but the frequency of the high frequency power to be output is, for example, several M.
In the case of Hz to several tens of MHz, a slight bending of the wiring acts as an inductance, so that the characteristics due to high frequency noise change depending on the assembled state of the device.

In the process unit 12, the relationship between the high frequency power and the current flowing to the grounded chamber 5 is determined according to the stray capacitance (impedance: 1/jωCsub) between the wafer W on the stage 6 and the chamber 5. Therefore, when a predetermined high frequency power is supplied, the higher the frequency of the high frequency power to be output, the larger the current value becomes, and the influence of noise caused by the current flowing through the chamber 5 and the grounded portion and returning to the power source is affected. It gets bigger. Therefore, it is necessary to take measures against noise and adjust wiring every time the device is assembled. On the other hand, in the plasma generation unit 11, since the forward and backward paths of the current are formed only by the high frequency antenna 5e, the influence of noise caused by the current flowing through the grounded portion is not so large. Therefore, by setting the frequency of the high frequency power to about 100 kHz to 500 kHz, it is possible to reduce the influence of noise particularly in the process unit 12.

In order to uniformly plasma-etch the surface of the wafer W, it is necessary to make the flux (flux) and energy of ions incident on the wafer W and the flux of radicals uniform. That is, in addition to the uniformity of the plasma density generated in the plasma generation unit 11, the flux of incident ions, the surface potential of the wafer W placed on the stage 6, and the electron temperature (electron energy distribution) that contributes to the radical generation rate. Function) is important. The penetration distance (skin thickness δ) of the high-frequency electromagnetic field into the plasma P generated by the plasma generation unit 11 is (Equation 3) δ=−C/(ωIm(K _p ^1/2 ), K _P =−ω. It is represented by _ps ² /ω ² (1-iv _m /ω), where K _p is the relative permittivity of the plasma P and is used in the plasma generation unit of a general conventional plasma processing apparatus. Assuming that the frequency is 13.56 MHz, argon gas is used, the pressure is 10 mTorr, and the plasma density is 5×10 ¹⁷ m ⁻³ , δ is about 5 cm, and most of the electromagnetic field is absorbed around the gas supply pipe of the plasma generation unit. Therefore, high-energy electrons are formed in this region, and the electron temperature distribution becomes nonuniform.

Therefore, in the plasma processing apparatus 10 of the above-described embodiment, a matcherless reactive etching apparatus is used, and high-frequency power supply circuits 7 and 9 are used as power supply circuits of the plasma generation unit 11 and the process unit 12 of the plasma processing apparatus 10. There is. These high-frequency power supply circuits 7 and 9 have a configuration in which the frequency of the high-frequency power output from the bridge circuits 7g and 9g is variable, and the load is an LC resonance circuit, so that an optimum impedance (pure load resistance) can be realized. ..

Therefore, even if the reactance component of the load impedance fluctuates due to the generation of the plasma P in the plasma generation unit 11 of the plasma processing apparatus 10 or the fluctuation of the plasma P, the high frequency power supplied to the high frequency antenna 5e and the stage 6 is high. Since the frequency is variable and high-speed adjustment is possible, it is possible to maintain a stable resonance state for the high-frequency power supplied to the high-frequency antenna 5e and the high-frequency power supplied to the stage 6 by using a matcher. It can be realized without using.

On the other hand, as described above, it is possible to correct the reactance component by maintaining the resonance state, but it is theoretically impossible to adjust the frequency with respect to the variation of the resistance component of the load impedance due to the generation or variation of the plasma P. It is possible and requires stable control of output power. Therefore, stable power supply is possible by PID control of the output power of the DC power supply 7a (9a) by the power control unit 7b (9b). From these, by using these high frequency power supply circuits 7 and 9, it is possible to secure a stable resonance state of the high frequency power supplied to the high frequency antenna 5e and the stage 6 without using a matcher composed of a variable capacitor or the like. At the same time, stable output power can be maintained.

Further, as compared with the high frequency power supplied to the plasma processing apparatus for the mega fab that processes a relatively large wafer, for example, 13.56 MHz, the high frequency power supplied to the high frequency antenna 5e of the plasma generation unit 11 and the stage 6 of the process unit 12 The frequency is low, for example, several 100 kHz. Therefore, the change in impedance due to the wiring from each high-frequency power supply circuit 7, 9 to the high-frequency antenna 5e or the stage 6 can be reduced, and noise can be reduced. Therefore, the distance from each of the high-frequency power supply circuits 7 and 9 to the high-frequency antenna 5e or the stage 6 can be flexibly changed. Therefore, it is necessary to accommodate each component in a relatively small housing 6. This is a great advantage in designing the system processing device 1.

Further, each high-frequency power supply circuit 7, 9 is configured to use full-bridge type bridge circuits 7g, 9g, and the frequency of the high-frequency power output from these bridge circuits 7g, 9g is generally about 1 MHz at the maximum. is there. However, since the high-frequency power supply circuits 7 and 9 have a configuration capable of realizing conversion efficiency of 90% or more of DC power to high-frequency power, wiring from the high-frequency power supply circuits 7 and 9 to the high-frequency antenna 5e or the stage 6 is performed. It is possible to suppress power loss in the device and fluctuation of impedance due to wiring.

Further, the frequency of the high-frequency power output from these high-frequency power supply circuits 7 and 9 is lower than that of the power supply circuit using the conventional matcher, and the frequency is low. The permeation distance (skin thickness δ) of the electromagnetic field increases, the electromagnetic field permeates into the inside of the plasma generation unit 11, and electron heating of the central region is also possible, so that the electron temperature or the electron energy distribution function can be made uniform. Become. In particular, since the electron temperature has a great influence on the collision generation process at the time of ion/radical generation and the like, uniform plasma generation and radical generation are possible, and uniform wafer processing is possible.

Further, since the respective matcher-less high-frequency power supply circuits 7 and 9 are provided, the space for installing the matcher, which is conventionally required, is not required even in the case 2 of the processing device 1 for the minimal fab system which is relatively small. Therefore, these spaces can be effectively used. Therefore, the vacuum exhaust system, the gas introduction system, the controller, or the like can be efficiently incorporated in a more appropriate position in the housing 2. That is, by using the high-frequency voltage applying device 7, 9, the space that can be effectively used in the housing 2 can be increased.

Next, regarding the plasma processing apparatus 10 according to the embodiment of the present invention, a high frequency power supply circuit 9 is used to supply high frequency power to the process section 12 to induce self bias, and Example 1 is referred to FIG. 9. And explain. FIG. 9 is a graph showing how the high frequency power supply circuit 9 supplies high frequency power to the process unit 12 of the plasma processing apparatus 10.

Using the high frequency power supply circuit 7, the high frequency power was supplied to the stage 6 of the process unit 12 from the high frequency power supply circuit 9 in a state where the high frequency power was supplied to the plasma generation unit 11 to constantly generate the plasma P in the chamber 5. When the potential of the stage 6 at that time was measured, as shown in FIG. 9, when the high frequency power supply circuit 9 was turned on, at the same time, a high frequency voltage of 300 Vpp was output from the high frequency power supply circuit 9 and a DC voltage of −100 V was simultaneously superimposed. Became. As a result, it was found that direct-current (DC) self-bias was induced at the same time that high-frequency power was applied to the process unit 12.

Next, Example 2 in which the etching process is performed by the plasma processing apparatus 10 according to the embodiment of the present invention will be described with reference to FIG. FIG. 10 is an electron micrograph showing the state of the wafer W that has been plasma-processed by the plasma processing apparatus 10.

A mixed gas of argon (Ar) gas ₆₀ sccm and sulfur hexafluoride (SF ₆ ) gas 3.7 sccm is introduced as an etching gas G into the plasma generation insulating tube 5 d of the plasma generation unit 11 of the plasma processing apparatus 10. Then, the power consumption of the high frequency power supply circuit 7 is 110 W, the power consumption of the high frequency power supply circuit 9 of the process unit 12 is 18.2 W, and the etching time is 10 minutes. Under this condition, when the SEM image of the Si wafer W on which the patterning mask M of SiO ₂ was applied was etched by the plasma processing apparatus 10, the SEM image of the wafer W was confirmed to be 0.1 μm/min as shown in FIG. It was found that a moderate etching rate was obtained, and it was found that appropriate reactive etching was performed.

<Other>
In addition, in the above-described embodiment, the plasma processing apparatus 10 is used to etch the wafer W on which the resist pattern is laminated. However, the present invention is not limited to this, and can be used correspondingly even with a wafer W other than the single crystal silicon structure wafer W in which resist patterns are laminated.

1 Processor for Minimal Fab System (Unit Processor)
2 Housing 2a Device upper part 2b Device lower part 2c Operation panel 2d Front chamber 2e Docking port 2f Wafer processing part 2g PLAD system 3a Supply part 3b Discharge part 5 Chamber 5a Main part 5b Upper plate 5c Opening part 5d Plasma generation insulating tube (gas Supply department)
5e High frequency antenna (plasma generation antenna)
5f, 5g Antenna terminal 5h Lid 6 Stage 6a Main body 6b Installation surface 6c, 6d Wafer bias terminal 7 High frequency power supply circuit (power supply circuit)
7a DC power supply 7b Power control unit 7c Power conversion circuit 7d Frequency control unit 7e Power detection unit 7f PID control circuit 7g Bridge circuit (inverter unit)
7h, 7i Series circuit 7j Transformer 7k Phase comparison circuit (phase comparison unit)
7m Gate driver circuit 7n Integrator 7p Voltage controlled oscillator (switching frequency controller)
8 Vacuum forming device (vacuum drawing unit)
9 High frequency power supply circuit (power supply circuit)
9a DC power supply 9b Power control unit 9c Power conversion circuit 9d Frequency control unit 9e Power detection unit 9f PID control circuit 9g Bridge circuit (inverter unit)
9h, 9i series circuit 9j transformer 9k phase comparison circuit (phase comparison unit)
9m gate driver circuit 9n integrator 9p voltage controlled oscillator (switching frequency controller)
10 plasma processing apparatus 10A inductively coupled plasma generation apparatus 10B self-bias application apparatus 11 plasma generation section 12 process section (wafer bias section)
G etching gas P plasma W wafer S1 to S8 switching element C resonance capacitor C1 blocking capacitor (self-bias capacitor)
C2 Resonant capacitor I Resonant inductor M Patterning mask

Claims (5)

A stage where the wafer is placed,
A chamber that covers this stage,
A vacuuming unit for vacuuming the inside of this chamber,
A gas supply unit provided at a position facing the stage of the chamber;
A plasma generation unit having an inductively coupled plasma generation device for generating plasma in the etching gas in the gas supply unit;
A wafer bias unit that has a self-bias applying device and applies a high-frequency voltage to the wafer placed on the stage to induce a DC self-bias;
The inductively coupled plasma generator,
Plasma generation inverter unit the DC power output from the power supply and outputs the converted high frequency power, plasma generating transformer for transformer high-frequency power output from the plasma generator inverter unit, and a plasma generating A plasma generating power supply circuit having a resonance capacitor serially connected to the transformer,
A plasma generation antenna to which the high frequency power transformed by the plasma generation transformer is supplied, and
The self-bias applying device,
Self-biased inverter unit the DC power output from the power supply and outputs the converted high frequency power, the self-bias transformer for transformer high-frequency power output from the self-biased inverter section, a transformer for the self-bias And a self-bias power supply circuit having a resonance inductor connected in series to the unit, and a self-bias capacitor to which the high-frequency power transformed by the self-bias transformer is supplied.
A resonance capacitor connected in series to the self-bias capacitor and connected in parallel to the self-bias transformer,
The inductively coupled plasma generation device and the self-bias application device,
Resonance between the high frequency power supplied to the plasma generation antenna and the high frequency power supplied to the wafer placed on the stage, with the direct current power output from the power source being equal to a preset predetermined power. A plasma processing apparatus comprising a power control unit for maintaining a state. The plasma processing apparatus according to claim 1,
The plasma generation power source circuit, the detected current value between the plasma generator inverter unit the plasma generating transformer, plasma generating frequencies for controlling the high frequency power output from the plasma generator inverter unit Equipped with a control unit,
The self-bias power supply circuit detects a current value between the self-bias inverter unit and the self-bias transformer unit, and controls a high-frequency power output from the self-bias inverter unit. Ru and a control unit,
A plasma processing apparatus characterized by the above. The plasma processing apparatus according to claim 2,
The plasma generation inverter section and the self-bias inverter section each have a plurality of switching elements,
The plasma generation frequency control unit and the self-bias frequency control unit detect the voltage value of each switching element and the current value of the output current, and compare the detected voltage value phase with the detected current value phase. the plasma processing apparatus characterized by comprising: a phase comparator, and the switching frequency control section for controlling the switching frequency of each switching element based on the phase shift in comparison with the phase comparison unit, respectively. The plasma generation method of the inductively coupled plasma generator of the plasma processing apparatus according to claim 1,
The inductively coupled plasma generator has a plurality of switching elements,
A plasma generation method comprising: controlling a switching frequency of the switching element such that an output voltage of the high frequency power output from the plasma generation inverter unit and an output current of the high frequency power are in phase with each other. The self-bias applying method of the self-bias applying apparatus of the plasma processing apparatus according to claim 1,
The self-bias applying device has a plurality of switching elements,
The output voltage of the high-frequency power output from the self-biased inverter unit, wherein as the phase of the output current of the high-frequency power are equal, the self-bias applying method characterized by controlling the switching frequency of the switching element ..