JP6719027B2 - 巨大ページをサポートするメモリ管理 - Google Patents

巨大ページをサポートするメモリ管理 Download PDF

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Publication number
JP6719027B2
JP6719027B2 JP2019536814A JP2019536814A JP6719027B2 JP 6719027 B2 JP6719027 B2 JP 6719027B2 JP 2019536814 A JP2019536814 A JP 2019536814A JP 2019536814 A JP2019536814 A JP 2019536814A JP 6719027 B2 JP6719027 B2 JP 6719027B2
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page
data
memory
main memory
size
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JP2019532450A (ja
JP2019532450A5 (enExample
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コバーン，ジョエル・ディラン
ボーチャーズ，アルバート
ジョンソン，クリストファー・ライル
スプリンクル，ロバート・エス
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/152—Virtualized environment, e.g. logically partitioned system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/304—In main memory subsystem
    • G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/305—Providing cache or TLB in specific location of a processing system being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/604—Details relating to cache allocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2019536814A 2016-09-22 2017-08-25 巨大ページをサポートするメモリ管理 Active JP6719027B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/273,433 US10108550B2 (en) 2016-09-22 2016-09-22 Memory management supporting huge pages
US15/273,433 2016-09-22
PCT/US2017/048663 WO2018057235A1 (en) 2016-09-22 2017-08-25 Memory management supporting huge pages

Publications (3)

Publication Number Publication Date
JP2019532450A JP2019532450A (ja) 2019-11-07
JP2019532450A5 JP2019532450A5 (enExample) 2020-01-16
JP6719027B2 true JP6719027B2 (ja) 2020-07-08

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JP2019536814A Active JP6719027B2 (ja) 2016-09-22 2017-08-25 巨大ページをサポートするメモリ管理

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US (2) US10108550B2 (enExample)
EP (1) EP3516526B1 (enExample)
JP (1) JP6719027B2 (enExample)
KR (1) KR102273622B1 (enExample)
CN (2) CN109791523B (enExample)
DK (1) DK3516526T3 (enExample)
IE (2) IE87058B1 (enExample)
SG (2) SG10201707699VA (enExample)
WO (1) WO2018057235A1 (enExample)

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US10949356B2 (en) * 2019-06-14 2021-03-16 Intel Corporation Fast page fault handling process implemented on persistent memory
US11392428B2 (en) * 2019-07-17 2022-07-19 Memverge, Inc. Fork handling in application operations mapped to direct access persistent memory
US12086446B2 (en) 2019-10-21 2024-09-10 Intel Corporation Memory and storage pool interfaces
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US11829298B2 (en) 2020-02-28 2023-11-28 Apple Inc. On-demand memory allocation
CN111666230B (zh) * 2020-05-27 2023-08-01 江苏华创微系统有限公司 在组相联tlb中支持巨页的方法
CN111913893A (zh) * 2020-06-22 2020-11-10 成都菁蓉联创科技有限公司 保留内存的映射方法和装置、设备和存储介质
US11567880B2 (en) 2020-08-12 2023-01-31 Microsoft Technology Licensing, Llc Prevention of RAM access pattern attacks via selective data movement
CN114253873A (zh) * 2020-09-22 2022-03-29 华为技术有限公司 内存管理方法、装置、设备和存储介质
CN112148736B (zh) * 2020-09-23 2024-03-12 抖音视界有限公司 缓存数据的方法、设备及存储介质
US20220382478A1 (en) * 2021-06-01 2022-12-01 Samsung Electronics Co., Ltd. Systems, methods, and apparatus for page migration in memory systems
CN113608866B (zh) * 2021-07-13 2024-10-25 阿里巴巴创新公司 内存分配方法及装置
US20220012209A1 (en) * 2021-09-20 2022-01-13 Intel Corporation Apparatus, system and method to sample page table entry metadata between page walks
CN113641464A (zh) * 2021-10-15 2021-11-12 云宏信息科技股份有限公司 Xen平台的内存配置方法、系统及计算机可读存储介质
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CN115794397A (zh) * 2022-11-29 2023-03-14 阿里云计算有限公司 冷热页管理加速设备、方法、mmu、处理器及电子设备
CN120872570A (zh) * 2023-01-20 2025-10-31 华为技术有限公司 内存访问的页错误处理方法及装置
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Also Published As

Publication number Publication date
KR102273622B1 (ko) 2021-07-06
SG10201903332RA (en) 2019-05-30
IE20180302A1 (en) 2018-10-31
JP2019532450A (ja) 2019-11-07
EP3516526B1 (en) 2020-10-14
US10108550B2 (en) 2018-10-23
DK3516526T3 (da) 2020-11-30
CN116701250A (zh) 2023-09-05
US20180365157A1 (en) 2018-12-20
WO2018057235A1 (en) 2018-03-29
KR20190052106A (ko) 2019-05-15
IE20170188A1 (en) 2018-04-04
CN109791523A (zh) 2019-05-21
US10474580B2 (en) 2019-11-12
CN109791523B (zh) 2023-07-14
IE87058B1 (en) 2019-10-16
SG10201707699VA (en) 2018-04-27
US20180081816A1 (en) 2018-03-22
EP3516526A1 (en) 2019-07-31

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