CN109791523B - 支持巨页的内存管理 - Google Patents

支持巨页的内存管理 Download PDF

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Publication number
CN109791523B
CN109791523B CN201780058759.7A CN201780058759A CN109791523B CN 109791523 B CN109791523 B CN 109791523B CN 201780058759 A CN201780058759 A CN 201780058759A CN 109791523 B CN109791523 B CN 109791523B
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page
data
size
main memory
memory
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CN109791523A (zh
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乔尔·迪伦·科伯恩
阿尔贝特·博尔歇斯
克里斯多夫·莱尔·约翰逊
罗伯特·S·斯普林科
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/152—Virtualized environment, e.g. logically partitioned system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/304—In main memory subsystem
    • G06F2212/3042—In main memory subsystem being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/305—Providing cache or TLB in specific location of a processing system being part of a memory device, e.g. cache DRAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/604—Details relating to cache allocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201780058759.7A 2016-09-22 2017-08-25 支持巨页的内存管理 Active CN109791523B (zh)

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Application Number Priority Date Filing Date Title
US15/273,433 2016-09-22
US15/273,433 US10108550B2 (en) 2016-09-22 2016-09-22 Memory management supporting huge pages
PCT/US2017/048663 WO2018057235A1 (en) 2016-09-22 2017-08-25 Memory management supporting huge pages

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EP (1) EP3516526B1 (enExample)
JP (1) JP6719027B2 (enExample)
KR (1) KR102273622B1 (enExample)
CN (2) CN109791523B (enExample)
DK (1) DK3516526T3 (enExample)
IE (2) IE20170188A1 (enExample)
SG (2) SG10201903332RA (enExample)
WO (1) WO2018057235A1 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110427340B (zh) * 2018-04-28 2023-08-04 伊姆西Ip控股有限责任公司 用于文件存储的方法、装置和计算机存储介质
US20190354470A1 (en) * 2018-05-16 2019-11-21 Sap Se Reduced Database Backup Memory Usage
US10956058B2 (en) * 2018-08-03 2021-03-23 Western Digital Technologies, Inc. Tiered storage system with tier configuration by peer storage devices
US10949356B2 (en) * 2019-06-14 2021-03-16 Intel Corporation Fast page fault handling process implemented on persistent memory
US11150962B2 (en) * 2019-07-17 2021-10-19 Memverge, Inc. Applying an allocation policy to capture memory calls using a memory allocation capture library
US12086446B2 (en) 2019-10-21 2024-09-10 Intel Corporation Memory and storage pool interfaces
JP6972202B2 (ja) * 2020-02-14 2021-11-24 株式会社日立製作所 計算機システム及びメモリ管理方法
US11829298B2 (en) 2020-02-28 2023-11-28 Apple Inc. On-demand memory allocation
CN111666230B (zh) * 2020-05-27 2023-08-01 江苏华创微系统有限公司 在组相联tlb中支持巨页的方法
CN111913893A (zh) * 2020-06-22 2020-11-10 成都菁蓉联创科技有限公司 保留内存的映射方法和装置、设备和存储介质
US11567880B2 (en) 2020-08-12 2023-01-31 Microsoft Technology Licensing, Llc Prevention of RAM access pattern attacks via selective data movement
CN114253873A (zh) * 2020-09-22 2022-03-29 华为技术有限公司 内存管理方法、装置、设备和存储介质
CN112148736B (zh) * 2020-09-23 2024-03-12 抖音视界有限公司 缓存数据的方法、设备及存储介质
US20220382478A1 (en) * 2021-06-01 2022-12-01 Samsung Electronics Co., Ltd. Systems, methods, and apparatus for page migration in memory systems
CN113608866B (zh) * 2021-07-13 2024-10-25 阿里巴巴创新公司 内存分配方法及装置
US20220012209A1 (en) * 2021-09-20 2022-01-13 Intel Corporation Apparatus, system and method to sample page table entry metadata between page walks
CN113641464A (zh) * 2021-10-15 2021-11-12 云宏信息科技股份有限公司 Xen平台的内存配置方法、系统及计算机可读存储介质
US12147352B2 (en) * 2022-10-20 2024-11-19 International Business Machines Corporation Dynamic tuning of larger pages during runtime
CN115794397A (zh) * 2022-11-29 2023-03-14 阿里云计算有限公司 冷热页管理加速设备、方法、mmu、处理器及电子设备
CN118377606A (zh) * 2023-01-20 2024-07-23 华为技术有限公司 内存访问的页错误处理方法及装置
US20240256459A1 (en) * 2023-01-26 2024-08-01 Vmware, Inc. System and method for managing a memory hierarchy
US12481588B2 (en) 2023-03-12 2025-11-25 Samsung Electronics Co., Ltd. Systems and methods for memory representation and management
US12423229B2 (en) 2023-03-16 2025-09-23 Samsung Electronics Co., Ltd. Systems and methods for memory representation and tracking
CN119536662A (zh) * 2023-03-31 2025-02-28 华为技术有限公司 冷热数据的迁移方法、处理器、设备和系统

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102473091A (zh) * 2009-07-01 2012-05-23 超威半导体公司 使用聚合的小页面的扩展的页面大小
CN102473138A (zh) * 2009-06-29 2012-05-23 甲骨文美国公司 具有用于页面错误处理的闪存的扩展主存储器层次结构

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5361345A (en) 1991-09-19 1994-11-01 Hewlett-Packard Company Critical line first paging system
US5987561A (en) * 1995-08-31 1999-11-16 Advanced Micro Devices, Inc. Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle
US5960463A (en) * 1996-05-16 1999-09-28 Advanced Micro Devices, Inc. Cache controller with table walk logic tightly coupled to second level access logic
US6112285A (en) 1997-09-23 2000-08-29 Silicon Graphics, Inc. Method, system and computer program product for virtual memory support for managing translation look aside buffers with multiple page size support
US6804729B2 (en) 2002-09-30 2004-10-12 International Business Machines Corporation Migrating a memory page by modifying a page migration state of a state machine associated with a DMA mapper based on a state notification from an operating system kernel
US7447869B2 (en) * 2005-04-07 2008-11-04 Ati Technologies, Inc. Method and apparatus for fragment processing in a virtual memory system
US7519781B1 (en) 2005-12-19 2009-04-14 Nvidia Corporation Physically-based page characterization data
US8543792B1 (en) 2006-09-19 2013-09-24 Nvidia Corporation Memory access techniques including coalesing page table entries
US7917725B2 (en) 2007-09-11 2011-03-29 QNX Software Systems GmbH & Co., KG Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer
JP2009069969A (ja) * 2007-09-11 2009-04-02 Canon Inc 情報処理方法および情報処理装置、プログラム
US9244855B2 (en) * 2007-12-31 2016-01-26 Intel Corporation Method, system, and apparatus for page sizing extension
US8615642B2 (en) 2009-10-14 2013-12-24 International Business Machines Corporation Automatic page promotion and demotion in multiple page size environments
US8533382B2 (en) * 2010-01-06 2013-09-10 Vmware, Inc. Method and system for frequent checkpointing
US9158701B2 (en) 2012-07-03 2015-10-13 International Business Machines Corporation Process-specific views of large frame pages with variable granularity
US10133677B2 (en) 2013-03-14 2018-11-20 Nvidia Corporation Opportunistic migration of memory pages in a unified virtual memory system
US20150058520A1 (en) 2013-08-22 2015-02-26 International Business Machines Corporation Detection of hot pages for partition migration
US9864698B2 (en) 2013-11-04 2018-01-09 International Business Machines Corporation Resolving cache lookup of large pages with variable granularity
US9535831B2 (en) 2014-01-10 2017-01-03 Advanced Micro Devices, Inc. Page migration in a 3D stacked hybrid memory
US9501422B2 (en) 2014-06-11 2016-11-22 Vmware, Inc. Identification of low-activity large memory pages
CN105095099B (zh) 2015-07-21 2017-12-29 浙江大学 一种基于内存页位图变更的大内存页整合方法
US10037173B2 (en) 2016-08-12 2018-07-31 Google Llc Hybrid memory management
US10152427B2 (en) 2016-08-12 2018-12-11 Google Llc Hybrid memory management

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102473138A (zh) * 2009-06-29 2012-05-23 甲骨文美国公司 具有用于页面错误处理的闪存的扩展主存储器层次结构
CN102473091A (zh) * 2009-07-01 2012-05-23 超威半导体公司 使用聚合的小页面的扩展的页面大小

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CN109791523A (zh) 2019-05-21
IE20180302A1 (en) 2018-10-31
WO2018057235A1 (en) 2018-03-29
JP6719027B2 (ja) 2020-07-08
EP3516526B1 (en) 2020-10-14
SG10201903332RA (en) 2019-05-30
CN116701250A (zh) 2023-09-05
EP3516526A1 (en) 2019-07-31
SG10201707699VA (en) 2018-04-27
US10108550B2 (en) 2018-10-23
IE20170188A1 (en) 2018-04-04
KR20190052106A (ko) 2019-05-15
IE87058B1 (en) 2019-10-16
JP2019532450A (ja) 2019-11-07
US20180365157A1 (en) 2018-12-20
US20180081816A1 (en) 2018-03-22
KR102273622B1 (ko) 2021-07-06
DK3516526T3 (da) 2020-11-30
US10474580B2 (en) 2019-11-12

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