JP6718454B2 - 選択的ページミス変換プリフェッチによってプログラムメモリコントローラにおけるページ変換ミスレイテンシを隠すこと - Google Patents

選択的ページミス変換プリフェッチによってプログラムメモリコントローラにおけるページ変換ミスレイテンシを隠すこと Download PDF

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JP6718454B2
JP6718454B2 JP2017533975A JP2017533975A JP6718454B2 JP 6718454 B2 JP6718454 B2 JP 6718454B2 JP 2017533975 A JP2017533975 A JP 2017533975A JP 2017533975 A JP2017533975 A JP 2017533975A JP 6718454 B2 JP6718454 B2 JP 6718454B2
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address
translation
cache
address translation
instruction
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JP2018506776A5 (enExample
JP2018506776A (ja
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ヴェンカタスブラマニアン ラマクリシュナン
ヴェンカタスブラマニアン ラマクリシュナン
オルオロード オルライ
オルオロード オルライ
プラサッド ヘレマガルール ラマプラサッド ビピン
プラサッド ヘレマガルール ラマプラサッド ビピン
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日本テキサス・インスツルメンツ合同会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/654—Look-ahead translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/681—Multi-level TLB, e.g. microTLB and main TLB

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
JP2017533975A 2014-12-22 2015-12-22 選択的ページミス変換プリフェッチによってプログラムメモリコントローラにおけるページ変換ミスレイテンシを隠すこと Active JP6718454B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/579,654 2014-12-22
US14/579,654 US9514059B2 (en) 2014-12-22 2014-12-22 Hiding page translation miss latency in program memory controller by selective page miss translation prefetch
PCT/US2015/067525 WO2016106392A1 (en) 2014-12-22 2015-12-22 Hiding page translation miss latency in program memory controller by selective page miss translation prefetch

Publications (3)

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JP2018506776A JP2018506776A (ja) 2018-03-08
JP2018506776A5 JP2018506776A5 (enExample) 2019-01-31
JP6718454B2 true JP6718454B2 (ja) 2020-07-08

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JP2017533975A Active JP6718454B2 (ja) 2014-12-22 2015-12-22 選択的ページミス変換プリフェッチによってプログラムメモリコントローラにおけるページ変換ミスレイテンシを隠すこと

Country Status (5)

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US (1) US9514059B2 (enExample)
EP (1) EP3238073B1 (enExample)
JP (1) JP6718454B2 (enExample)
CN (1) CN107111550B (enExample)
WO (1) WO2016106392A1 (enExample)

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US9673977B1 (en) 2016-09-15 2017-06-06 ISARA Corporation Refreshing public parameters in lattice-based cryptographic protocols
US10719451B2 (en) 2017-01-13 2020-07-21 Optimum Semiconductor Technologies Inc. Variable translation-lookaside buffer (TLB) indexing
US10565115B2 (en) * 2017-03-30 2020-02-18 Western Digital Technologies, Inc. Calculating the optimal number of LBNS to prefetch per CPU
US10929296B2 (en) * 2017-10-12 2021-02-23 Texas Instruments Incorporated Zero latency prefetching in caches
KR102151180B1 (ko) * 2017-11-20 2020-09-02 삼성전자주식회사 효율적인 가상 캐시 구현을 위한 시스템 및 방법
US10489305B1 (en) * 2018-08-14 2019-11-26 Texas Instruments Incorporated Prefetch kill and revival in an instruction cache
US10642742B2 (en) * 2018-08-14 2020-05-05 Texas Instruments Incorporated Prefetch management in a hierarchical cache system
CN111984318B (zh) 2019-05-22 2025-10-03 德克萨斯仪器股份有限公司 伪先进先出（fifo）标签线替换
US11113208B2 (en) * 2019-05-22 2021-09-07 Texas Instruments Incorporated Pseudo-first in, first out (FIFO) tag line replacement
US10977184B2 (en) * 2019-06-20 2021-04-13 Apical Limited and Arm Limited Managing memory access for convolutional neural networks
US11573802B2 (en) * 2019-10-23 2023-02-07 Texas Instruments Incorporated User mode event handling
US11704253B2 (en) 2021-02-17 2023-07-18 Microsoft Technology Licensing, Llc Performing speculative address translation in processor-based devices

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US5778434A (en) 1995-06-07 1998-07-07 Seiko Epson Corporation System and method for processing multiple requests and out of order returns
JPH1040171A (ja) * 1996-07-24 1998-02-13 Sony Corp アドレス変換装置および方法
US6487640B1 (en) 1999-01-19 2002-11-26 International Business Machines Corporation Memory access request reordering to reduce memory access latency
EP1182569B8 (en) 2000-08-21 2011-07-06 Texas Instruments Incorporated TLB lock and unlock operation
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US9251048B2 (en) * 2012-10-19 2016-02-02 International Business Machines Corporation Memory page management

Also Published As

Publication number Publication date
EP3238073A4 (en) 2017-12-13
CN107111550B (zh) 2020-09-01
CN107111550A (zh) 2017-08-29
JP2018506776A (ja) 2018-03-08
EP3238073A1 (en) 2017-11-01
WO2016106392A1 (en) 2016-06-30
US20160179700A1 (en) 2016-06-23
EP3238073B1 (en) 2019-06-26
US9514059B2 (en) 2016-12-06

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