JP6714841B2 - Method for manufacturing nitride semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a nitride semiconductor device.

Conventionally, it has been known to provide a GaN low temperature growth buffer layer between a GaAs substrate and a GaN layer when a gallium nitride (hereinafter GaN) layer is heterocrystal-grown on a gallium arsenide (hereinafter GaAs) substrate. (For example, refer to Patent Document 1). Further, in order to reduce threading dislocations, it is known to form a low temperature GaN layer having an island-like feature and a high temperature GaN layer on the low temperature GaN layer by HVPE (Hydride Vapor Phase Epitaxy) (for example, Patent Document 1). 2). It is also known to fill the pits after forming an intermediate layer that is a GaN layer having pits (see, for example, Patent Document 3).
[Prior Art Document]
[Patent Document]
[Patent Document 1] JP-A-9-255496 [Patent Document 2] JP-A-2013-241331 [Patent Document 3] JP-A-2007-201424

When homo-epitaxially growing a GaN layer on a GaN substrate, the temperature of the GaN substrate may be set to about 1000°C. However, in this case, nitrogen atoms escape from the surface of the GaN substrate, causing surface roughness of the GaN substrate. Since the crystal quality of the GaN layer depends on the surface state of the underlying GaN substrate, the crystal quality of the GaN layer deteriorates due to the surface roughness of the GaN substrate.

According to a first aspect of the present invention, a method for manufacturing a nitride semiconductor device is provided. The nitride semiconductor device may include a nitride semiconductor substrate and a nitride semiconductor layer provided on the nitride semiconductor substrate. A method for manufacturing a nitride semiconductor device is performed by heating a nitride semiconductor substrate arranged in a film forming chamber to raise the temperature of the nitride semiconductor substrate to a growth temperature, and maintaining the growth temperature after reaching the growth temperature. In the heating step and before the nitride semiconductor substrate reaches the growth temperature after starting the heating of the nitride semiconductor substrate, the introduction of the material gas for forming the nitride semiconductor layer into the film forming chamber is started to And a gas introducing step of continuously introducing the material gas into the film forming chamber even after the semiconductor substrate reaches the growth temperature.

In the gas introduction stage, the material gas is introduced into the film forming chamber using a carrier gas containing no hydrogen from the start of introduction of the material gas to a predetermined switching timing, and after the switching timing, the carrier gas containing hydrogen is introduced. May be used to introduce the material gas into the film forming chamber.

The material gas may include a Group 5 element-containing gas. The flow rate of the group 5 element-containing gas per unit time before the switching timing may be smaller than the flow rate of the group 5 element-containing gas after the switching timing per unit time.

The material gas may include a Group 3 element-containing gas. The flow rate of the group 3 element-containing gas per unit time before the switching timing may be smaller than the flow rate of the group 3 element-containing gas after the switching timing per unit time.

The material gas may include a Group 3 element-containing gas and a Group 5 element-containing gas. The ratio of the flow rate of the group 5 element-containing gas per unit time to the flow rate of the group 3 element-containing gas may be lower after the switching timing than before before the switching timing.

The temperature of the nitride semiconductor substrate at the switching timing is 700° C. or higher and may be lower than the growth temperature.

In the gas introduction step, introduction of the material gas may be started when the temperature of the nitride semiconductor substrate is 500° C. or higher and 900° C. or lower.

The above summary of the invention does not enumerate all necessary features of the invention. Further, a sub-combination of these feature groups can also be an invention.

It is a figure which shows the cross-section outline of the vertical MOSFET 100 in 1st Embodiment. FIG. 6 is a flow chart showing a manufacturing process of the vertical MOSFET 100 in the first embodiment. (A) is a timing chart showing the transition of the temperature of the GaN substrate 10 in steps S10 and S15. (B) is a figure explaining (1) introduction gas according to each timing, (2) state of film-forming chamber, and (3) formed layer. It is a figure showing stage S10 in a manufacturing process. It is a figure showing stage S15 in a manufacturing process. It is a figure showing stage S20 in a manufacturing process. It is a figure which shows step S30 in a manufacturing process. It is a figure which shows step S40 in a manufacturing process. It is a figure which shows step S50 in a manufacturing process.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all of the combinations of features described in the embodiments are essential to the solving means of the invention.

In the present specification, n or p means that electrons or holes are majority carriers, respectively. Regarding + or-marked on the right shoulder of n or p, + means that the carrier concentration is higher than that not described, and-means that the carrier concentration is lower than that not described. To do.

FIG. 1 is a diagram showing an outline of a cross section of the vertical MOSFET 100 in the first embodiment. The vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 of this example has a function of switching between conduction and non-conduction of current.

The vertical MOSFET 100 of this example includes an n ⁺ -type GaN substrate 10 as a nitride semiconductor substrate, a GaN layer 12 as a nitride semiconductor layer, a gate insulating film 32, a gate electrode 34, and a source electrode 44. And a drain electrode 54. An impurity-doped region may be exposed on at least a part of the front surface 14 of the GaN layer 12. In this example, the impurity-doped regions are the p-type well 24, the p ⁺ -type well 26, and the n ⁺ -type well 28 formed in the predetermined depth range from the front surface 14.

The GaN layer 12 of this example is provided on the GaN substrate 10. The GaN layer 12 is epitaxially formed on the GaN substrate 10. In this example, the front surface 14 is the main surface of the GaN layer 12 that is not in contact with the GaN substrate 10, and the back surface 16 is the main surface of the GaN substrate 10 that is not in contact with the GaN layer 12. In this example, “upper” means the direction from the back surface 16 of the GaN substrate 10 toward the front surface 14 of the GaN layer 12. Further, “down” means in the opposite direction to the “up”. "Top" and "bottom" do not necessarily mean vertical to the ground. The terms "above" and "below" are merely expedient expressions that specify relative positional relationships such as layers and films.

The GaN layer 12 has a protective layer 20, an n-type region 22, a p-type well 24, a p ⁺ -type well 26, and an n ⁺ -type well 28. The protective layer 20 of this example is provided directly on the GaN substrate 10. The n-type region 22 of this example is provided directly on the protective layer 20. The protective layer 20 may have the same material and the same composition as the n-type region 22. The protective layer 20 and the n-type region 22 in this example are both n-type GaN layers. Therefore, the lattice constant of the protective layer 20 matches the lattice constant of the lower GaN substrate 10 and the upper n-type region 22.

The protective layer 20 may be formed at a temperature different from that when forming the n-type region 22. Further, the protective layer 20 may be formed by changing the flow rate ratio per unit time for a plurality of gas species as compared with the case of forming the n-type region 22. In this example, the protective layer 20 is formed at a temperature and a flow rate ratio different from those when forming the n-type region 22. The thickness of the protective layer 20 may be 1 nm or more and 200 nm or less. The boundary between the protective layer 20 and the n-type region 22 in the GaN layer 12 may not be clearly distinguished by using an observation means such as TEM (Transmission Electron Microscope).

The protective layer 20 may not have a thickness that can be clearly observed. That is, the thickness of the protective layer 20 may be substantially zero nm. The surface roughness on the upper main surface of the GaN substrate 10 may be improved by causing the source gas and the carrier gas to flow over the GaN substrate 10 under predetermined conditions. The raw material gas and the carrier gas mean the raw material gas and the carrier gas introduced into the film forming chamber at a predetermined flow rate per unit time.

The protective layer 20 of this example may have a function of preventing nitrogen atoms from escaping from the surface of the GaN substrate 10 when the GaN layer 12 is homoepitaxially grown on the GaN substrate 10. By providing the protective layer 20, it is possible to prevent the surface roughness of the GaN substrate 10 while maintaining the lattice matching, so that it is possible to improve the crystal quality of the GaN layer 12 as compared with the case where the protective layer 20 is not provided. .. Further, since the surface roughness of the GaN substrate 10 can be prevented by flowing the material gas for forming the protective layer 20, even if the thickness of the protective layer 20 itself is substantially zero as described above, the crystal quality of the GaN layer 12 is small. Can be improved.

The n-type region 22 of this example functions as a drift layer of the vertical MOSFET 100. The p-type well 24 of this example is formed by ion implantation into the n-type region 22. In the p-type well 24, a portion immediately below the gate insulating film 32 and between the n-type region 22 and the n ⁺ -type well 28 may function as the channel formation region 25.

The p ⁺ type well 26 of this example is formed by ion implantation into the p type well 24. The p ⁺ type well 26 may have a function of reducing the contact resistance with the source electrode 44 and a function of providing a hole extraction path when turned off. Further, the n ⁺ type well 28 of this example is formed by ion implantation into the p type well 24 and the p ⁺ type well 26. The n ⁺ type well 28 functions as a source region.

The n-type impurities for GaN may include one or more elements of Si (silicon), Ge (germanium), and O (oxygen). In this example, Si is used as the n-type impurity. Further, the p-type impurity for GaN may include one or more elements selected from Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc). In this example, Mg is used as the p-type impurity.

The gate insulating film 32 of this example is in direct contact with the uppermost portions of the p-type well 24 and the n-type region 22. The gate electrode 34 of this example is in direct contact with the gate insulating film 32. The source electrode 44 of this example is electrically connected to the n ⁺ type well 28 and the p ⁺ type well 26. Further, the drain electrode 54 of this example is in direct contact with the back surface 16 of the GaN substrate 10.

The gate terminal 30, source terminal 40 and drain terminal 50 are shown with G, D and S circled, respectively. In this example, when the drain electrode 54 has a predetermined high potential and the source electrode 44 has the ground potential, when a potential equal to or higher than the threshold voltage is applied from the gate terminal 30 to the gate electrode 34, the channel formation region is formed. A charge inversion layer is formed at 25, and a current flows from the drain terminal 50 to the source terminal 40. When a potential lower than the threshold voltage is applied to the gate electrode 34, the charge inversion layer in the channel formation region 25 disappears and the current is cut off.

FIG. 2 is a flow chart showing a manufacturing process of the vertical MOSFET 100 in the first embodiment. The manufacturing process of this example is performed in the order of steps S10 to S50. In the manufacturing process of this example, a step of homoepitaxially forming the protective layer 20 (S10), a step of homoepitaxially forming the n-type region 22 (S15), and a step of ion-implanting impurities into the front surface 14 of the GaN layer 12. (S20), providing the cap layer 18 on the front surface 14 of the GaN layer 12 (S30), annealing the GaN layer 12 (S40), and forming the gate insulating film 32 and the like (S50). ..

FIG. 3A is a timing chart showing the transition of the temperature of the GaN substrate 10 in steps S10 and S15. FIG. 3B is a diagram illustrating (1) introduction gas, (2) state of film forming chamber, and (3) formed layer according to each timing. In (a) and (b), the horizontal axis represents time. Further, in (a), the vertical axis represents temperature.

At time t ₀ , the back surface 16 of the GaN substrate 10 is placed on the susceptor in the film formation chamber, and the main surface of the GaN substrate 10 opposite to the back surface 16 may be exposed inside the film formation chamber. The temperature of the GaN substrate 10 may be the room temperature T ₀ of the film forming chamber. T ₀ may be room temperature, for example 15° C.

The heating of the GaN substrate 10 is started from time t ₀ . The heating method may be high frequency heating or lamp heating. Other suitable heating schemes may be used. In this example, the GaN substrate 10 is heated such that the temperature rises linearly with time from time t ₀ to time t ₃ . In this example, the heating stage is from time t ₀ to time t ₄ . The temperature of the GaN substrate 10 is increased from the time t ₀ to the time t _3, and the temperature of the GaN substrate 10 is continuously maintained from the time t ₃ to the time t ₄ .

After the heating of the GaN substrate 10 is started and before the GaN substrate 10 reaches the growth temperature, the introduction of the material gas into the film forming chamber is started. In this example, the material gas is introduced into the film formation chamber at time t ₁ during the temperature rise. In this example, the gas introduction stage is from time t ₁ to time t ₄ . That is, from time t ₁ to time t ₄ , the material gas and the carrier gas are caused to flow into the film formation chamber. Thereby, the GaN layer is formed by the metal organic growth method (MOCVD).

Temperature _{T 1} of the GaN substrate 10 at time _{t 1} is, 400 ° C. or higher, 450 ° C. or higher, 500 ° C. or higher, it may be at 550 ° C. or higher, or 600 ° C. or higher, and, 850 ° C. or less, 900 ° C. or less, 950 ° C. or less Alternatively, it may be 1000° C. or lower. However, the temperature T ₁ is lower than the temperature T ₂ described later. In this example, the temperature T ₁ of the GaN substrate 10 is a temperature of 500° C. or higher and 900° C. or lower. As a result, the protective layer 20 that directly contacts the GaN substrate 10 is formed.

The material gas of this example is a gas that forms the GaN layer 12. The material gas contains trimethylgallium (Ga(CH ₃ ) ₃ ) (hereinafter, TMG) as a group 3 element-containing gas, ammonia (NH ₃ ) as a group 5 element-containing gas, and monosilane (SiH ₄ ). Good. Silicon (Si) of monosilane functions as an n-type impurity in the GaN layer 12.

From time t ₁ to time t ₂ , the material gas is introduced into the film formation chamber using a carrier gas containing no hydrogen (H ₂ ). The time from time t ₁ to time t ₂ may be several minutes. The carrier gas that does not include hydrogen (H ₂ ) may include nitrogen (N ₂ ). In this example, the carrier gas is nitrogen gas. At the gas introduction start temperature T ₁ , hydrogen may chemically react with the GaN substrate 10, so that the hydrogen may etch the GaN substrate 10. Therefore, in this example, nitrogen gas is used as the carrier gas from time t ₁ to time t ₂ . Thereby, the flatness of the upper main surface (the main surface opposite to the back surface 16) of the GaN substrate 10 can be maintained during the formation of the protective layer 20.

Time t ₂ is a gas switching timing determined in advance. In this example, the V/III ratio and the carrier gas are switched at time t ₂ during the temperature rise. As a result, formation of the n-type region 22 is started. Temperature _{T 2} of the GaN substrate 10 at time _{t 2,} 700 ° C. or higher, 750 ° C. or higher, 800 ° C. or higher, may be at 850 ° C. or higher, or 900 ° C. or higher, and, 1100 ° C. or less, 1150 ° C. or less, or 1200 ° C. or less May be The temperature T ₂ is 10° C. or higher, 20° C. or higher, 30° C. or higher, 40° C. or higher, 50° C. or higher, 60° C. or higher, 70° C. or higher, 80° C. or higher, 90 higher than the film formation temperature of the n-type region 22. The temperature may be lower than 100°C or lower than 100°C.

In this example, the V/III ratio means the ratio of the flow rate of the group 5 element-containing gas per unit time to the flow rate of the group 3 element-containing gas introduced into the film forming chamber. The V/III ratio may be lower after time t ₂ than before time t ₂ . In this example, the V/III ratio before time t ₂ is about 1.5 times the V/III ratio after time t ₂ . That is, before time t ₂ , the protective layer 20 can be formed while reducing the escape of nitrogen atoms from the GaN substrate 10 by excessively supplying nitrogen to gallium.

The flow rate per unit time of the Group 5 element-containing gas in before time t ₂ may be less than the flow rate per unit time of the Group 5 element-containing gas in the after time t _2. In this example, the flow rate per unit time ammonia before time t ₂ is about half the flow rate per unit time of ammonia in the after time t _2. Further, the flow rate per unit time of the group III element-containing gas in before time t ₂ may be less than the flow rate per unit of group III element-containing gas time in after time t _2. In this example, the flow rate per unit time TMG before time t ₂ is about half the flow rate per unit time of TMG to definitive after time t _2.

In this example, the growth rate of the protective layer 20 in step S10 is suppressed by suppressing the supply of ammonia and TMG more than in step S20. Since the temperature of the GaN substrate 10 of step S10 is lower than that of step S20, the crystal quality of step S10 is considered to be lower than that of step S20. Therefore, by suppressing the growth rate in step S10, a higher quality epitaxial layer can be formed for the GaN layer 12 as a whole.

The carrier gas introduced into the film formation chamber after the time t ₂ may contain hydrogen. The carrier gas of this example is switched to contain hydrogen but not nitrogen after time t ₂ . The "including hydrogen in after the time t ₂ switched to be free of nitrogen", at time t ₂ just the supply of hydrogen was started, the carrier gas contains still be nitrogen, the time t _{By 3} it means that the nitrogen is reduced to zero. Incidentally, ammonia and TMG raw material gases may also be varied to a predetermined V / III ratio to the time t _3. In one example, the flow rate of ammonia per unit time may be 223000 μmol/min and the flow rate of TMG per unit time may be 110 μmol/min after time t ₂ and before time t ₃ . In this case, the V/III ratio is about 2000.

In this example, the growth temperature means a substantially constant temperature at which the growth of the n-type region 22 proceeds. However, the growth temperature does not mean only a fixed and constant temperature. The growth temperature may have a temperature range that deviates from a predetermined temperature by a predetermined temperature. For example, the growth temperature is in the temperature range of 1100° C.±25° C. In this example, the temperature of the front GaN substrate 10 at time t ₂ is 700° C. or higher, which is lower than the growth temperature. In this example, by starting to flow the film forming gas of the n-type region 22 before reaching the growth temperature, it is possible to continuously shift from the formation of the protective layer 20 to the formation of the n-type region 22.

In this example, the temperature rise of the GaN substrate 10 is stopped at time t ₃ . Time from time t ₂ to time t ₃ may be a few minutes. At time t ₃ , the temperature of GaN substrate 10 may reach temperature T ₃ . The temperature T _{3 in} this example is the growth temperature of the n-type region 22. After reaching the temperature T ₃ , the temperature of the GaN substrate 10 may be maintained at the growth temperature. In addition, even after the temperature of the GaN substrate 10 reaches the growth temperature, the introduction of the material gas into the film forming chamber is continued until time t ₄ . Thereby, from time t ₃ to time t ₄ , the temperature T ₃ may be maintained and the n-type region 22 may be grown. The time from time t ₃ to time t ₄ may be 300 minutes.

In this example, the heating of the GaN substrate 10 is stopped at time t ₄ . In this example, time t ₄ to time t ₅ is the cooling stage. At time t ₅ , the laminated structure of the GaN substrate 10 and the GaN layer 12 that has been lowered to the temperature T ₀ may be taken out of the deposition chamber.

FIG. 4A is a diagram showing step S10 in the manufacturing process. In step S10, the protective layer 20 is epitaxially formed. FIG. 4B is a diagram showing step S15 in the manufacturing process. In step S15, the n-type region 22 is epitaxially formed. Thereby, the protective layer 20 and the n-type region 22 are formed. As described with reference to FIG. 3, step S10 and step S15 are continuously executed with the gas switching (time t ₂ ) sandwiched therebetween.

FIG. 4C is a diagram showing step S20 in the manufacturing process. In step S20, the p-type well 24, the p ⁺ -type well 26, and the n ⁺ -type well 28 are formed. In this example, Mg is ion-implanted into the GaN layer 12 by multi-stage implantation with an acceleration voltage of 20, 40, 70, 110, 150, 200, 250, and 430 (all units are keV) and a dose amount of 6E+12 cm ⁻² . Accordingly, the impurity concentration of the p-type well 24 may be 1E+17 cm ⁻³ after the annealing in step S40. In addition, E means the power of 10. For example, E+17 means 10 ¹⁷ .

Further, in this example, Mg is ion-implanted into the p-type well 24 at an acceleration voltage of 10 keV and a dose amount of 4.5E+13 cm ⁻² . Accordingly, the impurity concentration of the p ⁺ -type well 26 may be 2E+19 cm ⁻³ after the annealing in step S40. Further, in this example, Si is ion-implanted into the p-type well 24 and the p ⁺ -type well 26 by multi-stage implantation with an acceleration voltage of 30, 60, and 80 (all units are keV) and a dose amount of 3E+15 cm ⁻² . Accordingly, the impurity concentration of the n ⁺ type well 28 may be 1E+20 cm ⁻³ after the annealing in step S40.

FIG. 4D is a diagram showing step S30 in the manufacturing process. In paragraph S30, the cap layer 18 is formed. In this example, the laminated structure of the GaN substrate 10, the GaN layer 12, and the cap layer 18 is referred to as a processed laminate 60. In this example, since each well is formed by ion implantation, the crystallinity of the front surface 14 of the GaN layer 12 is disturbed. Therefore, nitrogen atoms are more likely to be decomposed and released from the GaN layer 12 during annealing, as compared with the case where each well is epitaxially formed. The cap layer 18 has a function of reducing decomposition and release of nitrogen atoms from the front surface 14 during annealing.

The cap layer 18 in this example is an AlN (aluminum nitride) film provided in direct contact with the front surface 14 of the GaN layer 12. The AlN film may be formed by a sputtering method using an AlN target. The cap layer 18 may have a thickness of 2 nm or more and 1000 nm or less. The cap layer 18 in this example has a thickness of about 200 nm.

FIG. 4E is a diagram showing step S40 in the manufacturing process. In step S40, the to-be-processed laminated body 60 is arrange|positioned in the annealing device 110, and the to-be-processed laminated body 60 is annealed at the temperature and the pressure which were predetermined. Thereby, the GaN layer 12 is annealed. Argon (Ar) gas may be added to the annealing device 110 in addition to nitrogen gas. The predetermined pressure may be several hundred MPa. Further, the predetermined temperature may be 1200° C. or higher and 1500° C. or lower, and more preferably 1400° C. or higher and 1500° C. or lower. After annealing, the AlN film is removed selectively with respect to the GaN layer 12 using an aqueous potassium hydroxide solution (KOHaq).

FIG. 4F is a diagram showing step S50 in the manufacturing process. In step S50, the gate insulating film 32, the gate electrode 34, the source electrode 44, and the drain electrode 54 are formed by applying known film forming methods and patterning methods. In this example, a SiO ₂ film as the gate insulating film 32 is formed by low pressure chemical vapor deposition (LPCVD). The thickness of the gate insulating film 32 is 100 nm, for example.

After that, polycrystalline silicon is formed as the gate electrode 34 by LPCVD. The polycrystalline silicon may be doped with one or more elements of phosphorus (P) and arsenic (As) during or after the deposition of the polycrystalline silicon. The gate insulating film 32 and the gate electrode 34 are patterned by photolithography and etching.

Then, the source electrode 44 is formed. The source electrode 44 may be a laminated body including a lower Ti (titanium) layer and an upper Al (aluminum) layer. Then, the drain electrode 54 is formed. The drain electrode 54 may be a laminated body having an upper Ti layer and a lower Al layer that are in direct contact with the back surface 16 of the GaN substrate 10. Then, the gate terminal 30, the source terminal 40, and the drain terminal 50 are connected to the gate electrode 34, the source electrode 44, and the drain electrode 54 by wiring. As a result, the vertical MOSFET 100 is completed.

Although the present invention has been described above using the embodiment, the technical scope of the present invention is not limited to the scope described in the above embodiment. It is apparent to those skilled in the art that various modifications and improvements can be added to the above-described embodiment. It is apparent from the description of the scope of claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

The execution order of each process such as operation, procedure, step, and step in the device, system, program, and method shown in the claims, the specification, and the drawings is, in particular, “before” or “prior to”. It should be noted that the output of the previous process can be realized in any order unless the output of the previous process is used in the subsequent process. The operation flow in the claims, the specification, and the drawings is described using “first,” “next,” and the like for convenience, but it is essential that the operations are performed in this order. Not a thing.

10 ···GaN substrate, 12···GaN layer, 14··front surface, 16··back surface, 18··cap layer, 20··protection layer, 22··n type region, 24··p type well , 25 ·· channel forming region, 26 · · p ⁺ type well, 28 · · n ⁺ type well, 30 · · gate terminal, 32 · · gate insulating film, 34 · · gate electrode, 40 · · source terminal, 44 ..Source electrode, 50..drain terminal, 54..drain electrode, 60..processed laminate, 100..vertical MOSFET, 110..annealing device

Claims (6)

A method for manufacturing a nitride semiconductor device having a nitride semiconductor substrate and a nitride semiconductor layer provided on the nitride semiconductor substrate, comprising:
A heating step of heating the nitride semiconductor substrate arranged in the film forming chamber to raise the temperature of the nitride semiconductor substrate to a growth temperature, and maintaining the growth temperature after reaching the growth temperature;
Before starting the heating of the nitride semiconductor substrate and before the nitride semiconductor substrate reaches the growth temperature, the introduction of the material gas for forming the nitride semiconductor layer into the film forming chamber is started, and A gas introduction step of continuing the introduction of the material gas into the film forming chamber even after the nitride semiconductor substrate reaches the growth temperature ,
In the gas introduction step, from the start of introduction of the material gas to a predetermined switching timing, the material gas is introduced into the film forming chamber using a carrier gas containing no hydrogen, and after the switching timing, The material gas is introduced into the film forming chamber using a carrier gas containing hydrogen,
The material gas includes a Group 5 element-containing gas,
The manufacturing method , wherein the flow rate of the group 5 element-containing gas per unit time before the switching timing is smaller than the flow rate of the group 5 element-containing gas after the switching timing per unit time . A method for manufacturing a nitride semiconductor device having a nitride semiconductor substrate and a nitride semiconductor layer provided on the nitride semiconductor substrate, comprising:
A heating step of heating the nitride semiconductor substrate arranged in the film forming chamber to raise the temperature of the nitride semiconductor substrate to a growth temperature, and maintaining the growth temperature after reaching the growth temperature;
Before starting the heating of the nitride semiconductor substrate and before the nitride semiconductor substrate reaches the growth temperature, starting the introduction of the material gas for forming the nitride semiconductor layer into the film forming chamber, A gas introduction step of continuing the introduction of the material gas into the film forming chamber even after the nitride semiconductor substrate reaches the growth temperature;
Equipped with
In the gas introduction step, from the start of introduction of the material gas to a predetermined switching timing, the material gas is introduced into the film forming chamber using a carrier gas containing no hydrogen, and after the switching timing, The material gas is introduced into the film forming chamber using a carrier gas containing hydrogen,
The manufacturing method, wherein the temperature of the nitride semiconductor substrate at the switching timing is 700° C. or higher and lower than the growth temperature. The material gas includes a Group 5 element-containing gas,
The manufacturing method according to claim 2, wherein a flow rate of the group 5 element-containing gas per unit time before the switching timing is smaller than a flow rate of the group 5 element-containing gas after the switching timing per unit time. The material gas includes a Group 3 element-containing gas,
The flow rate per unit of the Group 3 element-containing gas time before from the switching timing, any one of claims 1-3 less than the flow rate per unit time of the Group 3 element-containing gas in the later than the switching timing The manufacturing method according to item . The material gas includes a Group 3 element-containing gas and a Group 5 element-containing gas,
The flow rate ratio per unit time of the Group 5 element-containing gas per group III element units containing gas time to the flow rate, the one than before the switching timing of 4 from lower claim 1 in after the switching timing The method according to item 1. In the gas introducing step, the temperature of the nitride semiconductor substrate 500 ° C. or higher, when it is 900 ° C. or less, the production method according to any one of claims 1 5 for starting the introduction of the material gas.

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