JP2017208428A - Method for manufacturing nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a surface of a GaN substrate is roughened by the coming-off of nitrogen from the GaN substrate surface to worsen the crystal quality of a GaN layer when the GaN layer is homoepitaxially grown on the GaN substrate with a GaN substrate temperature of about 1000°C because of the GaN layer crystal quality depending on the surface condition of its base.SOLUTION: A method for manufacturing a nitride semiconductor device having a nitride semiconductor substrate and a nitride semiconductor layer provided on the nitride semiconductor substrate is provided. The method comprises: a heating step where the nitride semiconductor substrate set in a film-forming chamber is heated to raise a temperature of the nitride semiconductor substrate to a growth temperature, and the nitride semiconductor substrate is kept at the growth temperature after having reached the growth temperature; and a gas introduction step where the introduction of a material gas for forming the nitride semiconductor layer into the film-forming chamber is started before the nitride semiconductor substrate reaches the growth temperature after the start of heating of the nitride semiconductor substrate, and the introduction of the material gas into the film-forming chamber is continued after the nitride semiconductor substrate has reached the growth temperature.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a method for manufacturing a nitride semiconductor device.

Conventionally, when a gallium nitride (hereinafter referred to as GaN) layer is heterocrystal-grown on a gallium arsenide (hereinafter referred to as GaAs) substrate, it is known to provide a GaN low-temperature growth buffer layer between the GaAs substrate and the GaN layer. (For example, refer to Patent Document 1). Furthermore, in order to reduce threading dislocations, it is known to form a low-temperature GaN layer having island-like characteristics and a high-temperature GaN layer on the low-temperature GaN layer by HVPE (Hydride Vapor Phase Epitaxy) (for example, Patent Documents) 2). It is also known to embed the pits after forming an intermediate layer, which is a GaN layer having pits (see, for example, Patent Document 3).
[Prior art documents]
[Patent Literature]
[Patent Document 1] JP-A-9-255596 [Patent Document 2] JP-A-2013-241331 [Patent Document 3] JP-A-2007-201424

  When homoepitaxially growing a GaN layer on a GaN substrate, the temperature of the GaN substrate may be about 1000 ° C. However, in this case, nitrogen atoms escape from the surface of the GaN substrate, resulting in surface roughness of the GaN substrate. Since the crystal quality of the GaN layer depends on the surface state of the underlying GaN substrate, the crystal quality of the GaN layer deteriorates due to surface roughness of the GaN substrate.

  In a first aspect of the present invention, a method for manufacturing a nitride semiconductor device is provided. The nitride semiconductor device may include a nitride semiconductor substrate and a nitride semiconductor layer provided on the nitride semiconductor substrate. A method of manufacturing a nitride semiconductor device includes heating a nitride semiconductor substrate disposed in a film formation chamber to raise the temperature of the nitride semiconductor substrate to a growth temperature, and maintaining the growth temperature after reaching the growth temperature. Before starting the heating step and heating the nitride semiconductor substrate and before the nitride semiconductor substrate reaches the growth temperature, the introduction of the material gas for forming the nitride semiconductor layer into the film formation chamber is started, A gas introduction step of continuing the introduction of the material gas into the film formation chamber even after the semiconductor substrate reaches the growth temperature.

  In the gas introduction stage, the material gas is introduced into the film forming chamber using a carrier gas not containing hydrogen from the start of introduction of the material gas to a predetermined switching timing, and after the switching timing, the carrier gas containing hydrogen May be used to introduce the material gas into the film formation chamber.

  The material gas may include a group 5 element-containing gas. The flow rate per unit time of the Group 5 element-containing gas before the switching timing may be smaller than the flow rate per unit time of the Group 5 element-containing gas after the switching timing.

  The material gas may include a group 3 element-containing gas. The flow rate per unit time of the Group 3 element-containing gas before the switching timing may be smaller than the flow rate per unit time of the Group 3 element-containing gas after the switching timing.

  The material gas may include a group 3 element-containing gas and a group 5 element-containing gas. The ratio of the flow rate per unit time of the Group 5 element-containing gas to the flow rate per unit time of the Group 3 element-containing gas may be lower after the switching timing than before the switching timing.

  The temperature of the nitride semiconductor substrate at the switching timing may be 700 ° C. or higher and lower than the growth temperature.

  In the gas introduction step, the introduction of the material gas may be started when the temperature of the nitride semiconductor substrate is 500 ° C. or higher and 900 ° C. or lower.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

It is a figure which shows the cross-sectional outline | summary of the vertical MOSFET100 in 1st Embodiment. It is a flowchart which shows the manufacturing process of the vertical MOSFET100 in 1st Embodiment. (A) is a timing chart which shows transition of the temperature of the GaN substrate 10 in step S10 and step S15. (B) is a figure explaining (1) introduction gas according to each timing, (2) the state of a film-forming chamber, and (3) the layer formed. It is a figure which shows step S10 in a manufacturing process. It is a figure which shows step S15 in a manufacturing process. It is a figure which shows step S20 in a manufacturing process. It is a figure which shows step S30 in a manufacturing process. It is a figure which shows step S40 in a manufacturing process. It is a figure which shows step S50 in a manufacturing process.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  In this specification, n or p means that an electron or a hole is a majority carrier, respectively. In addition, regarding + or − written on the right shoulder of n or p, + means that the carrier concentration is higher than that in which it is not described, and − means that the carrier concentration is lower than that in which it is not described. To do.

  FIG. 1 is a diagram showing an outline of a cross section of a vertical MOSFET 100 in the first embodiment. A vertical MOSFET (Metal Oxide Field Effect Effect Transistor) 100 of this example has a function of switching between current conduction and non-conduction.

The vertical MOSFET 100 of this example includes an n ⁺ -type GaN substrate 10 as a nitride semiconductor substrate, a GaN layer 12 as a nitride semiconductor layer, a gate insulating film 32, a gate electrode 34, a source electrode 44, And a drain electrode 54. A region doped with impurities may be exposed on at least a part of the front surface 14 of the GaN layer 12. In this example, the impurity-doped regions are the p-type well 24, the p ⁺ -type well 26, and the n ⁺ -type well 28 that are formed in a predetermined depth range from the front surface 14.

  The GaN layer 12 of this example is provided on the GaN substrate 10. The GaN layer 12 is epitaxially formed on the GaN substrate 10. In this example, the front surface 14 is the main surface of the GaN layer 12 that is not in contact with the GaN substrate 10, and the back surface 16 is the main surface of the GaN substrate 10 that is not in contact with the GaN layer 12. In this example, “up” means a direction from the back surface 16 of the GaN substrate 10 toward the front surface 14 of the GaN layer 12. Further, “down” means the direction opposite to “up”. “Up” and “down” do not necessarily mean a vertical direction with respect to the ground. “Upper” and “lower” are merely convenient expressions for specifying a relative positional relationship such as a layer and a film.

The GaN layer 12 includes a protective layer 20, an n-type region 22, a p-type well 24, a p ⁺ -type well 26, and an n ⁺ -type well 28. The protective layer 20 of this example is provided directly on the GaN substrate 10. Further, the n-type region 22 of this example is provided directly on the protective layer 20. Protective layer 20 may have the same material and the same composition as n-type region 22. Both the protective layer 20 and the n-type region 22 in this example are n-type GaN layers. Therefore, the lattice constant of the protective layer 20 matches the lattice constant of the lower GaN substrate 10 and the upper n-type region 22.

  The protective layer 20 may be formed at a temperature different from that when the n-type region 22 is formed. Furthermore, the protective layer 20 may be formed by changing the flow rate ratio per unit time in a plurality of gas types as compared with the formation of the n-type region 22. In this example, the protective layer 20 is formed at a temperature and a flow rate ratio different from those at the time of forming the n-type region 22. The thickness of the protective layer 20 may be 1 nm or more and 200 nm or less. Note that the boundary between the protective layer 20 and the n-type region 22 in the GaN layer 12 may not be clearly distinguishable even by using observation means such as TEM (Transmission Electron Microscope).

  Note that the protective layer 20 may not have a thickness that can be clearly observed. That is, the thickness of the protective layer 20 may be approximately zero nm. The surface roughness of the upper main surface of the GaN substrate 10 may be improved by flowing the source gas and the carrier gas on the GaN substrate 10 under predetermined conditions. Note that the source gas and the carrier gas mean a source gas and a carrier gas introduced into the film forming chamber at a predetermined flow rate per unit time.

  The protective layer 20 of this example may have a function of preventing nitrogen atoms from escaping from the surface of the GaN substrate 10 when the GaN layer 12 is homoepitaxially grown on the GaN substrate 10. By providing the protective layer 20, it is possible to prevent surface roughness of the GaN substrate 10 while maintaining lattice matching. Therefore, the crystal quality of the GaN layer 12 can be improved as compared with the case where the protective layer 20 is not provided. . Further, since the surface roughness of the GaN substrate 10 can be prevented by flowing the material gas for forming the protective layer 20, the crystal quality of the GaN layer 12 can be obtained even when the thickness of the protective layer 20 is substantially zero as described above. Can be improved.

The n-type region 22 in this example functions as a drift layer of the vertical MOSFET 100. The p-type well 24 of this example is formed by ion implantation into the n-type region 22. In the p-type well 24, a portion immediately below the gate insulating film 32 and between the n-type region 22 and the n ⁺ -type well 28 may function as the channel formation region 25.

The p ⁺ type well 26 of this example is formed by ion implantation into the p type well 24. The p ⁺ type well 26 may have a function of reducing a contact resistance with the source electrode 44 and a function of providing a hole extraction path when off. Further, the n ⁺ type well 28 in this example is formed by ion implantation into the p type well 24 and the p ⁺ type well 26. The n ⁺ type well 28 functions as a source region.

  The n-type impurity for GaN may include one or more elements of Si (silicon), Ge (germanium), and O (oxygen). In this example, Si is used as the n-type impurity. The p-type impurity for GaN may contain one or more elements of Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc). In this example, Mg is used as the p-type impurity.

The gate insulating film 32 in this example is in direct contact with the uppermost portions of the p-type well 24 and the n-type region 22. The gate electrode 34 in this example is in direct contact with the gate insulating film 32. The source electrode 44 in this example is electrically connected to the n ⁺ type well 28 and the p ⁺ type well 26. Further, the drain electrode 54 of this example is in direct contact with the back surface 16 of the GaN substrate 10.

  The gate terminal 30, the source terminal 40, and the drain terminal 50 are shown with circles G, D, and S, respectively. In this example, when the drain electrode 54 has a predetermined high potential and the source electrode 44 has a ground potential, if a potential higher than the threshold voltage is applied from the gate terminal 30 to the gate electrode 34, the channel formation region A charge inversion layer is formed at 25, and a current flows from the drain terminal 50 to the source terminal 40. Further, when a potential lower than the threshold voltage is applied to the gate electrode 34, the charge inversion layer in the channel formation region 25 disappears, and the current is cut off.

  FIG. 2 is a flowchart showing manufacturing steps of the vertical MOSFET 100 according to the first embodiment. The manufacturing process of this example is performed in the order of steps S10 to S50. The manufacturing process of this example includes the step of homoepitaxially forming the protective layer 20 (S10), the step of homoepitaxially forming the n-type region 22 (S15), and the step of ion-implanting impurities into the front surface 14 of the GaN layer 12 (S20), the step of providing the cap layer 18 on the front surface 14 of the GaN layer 12 (S30), the step of annealing the GaN layer 12 (S40), and the step of forming the gate insulating film 32 and the like (S50). .

  FIG. 3A is a timing chart showing a change in the temperature of the GaN substrate 10 in steps S10 and S15. FIG. 3B is a diagram for explaining (1) the introduced gas, (2) the state of the film forming chamber, and (3) the layer to be formed according to each timing. In (a) and (b), the horizontal axis indicates time. Moreover, in (a), a vertical axis | shaft shows temperature.

At time t ₀ , the back surface 16 of the GaN substrate 10 is placed on the susceptor in the film forming chamber, and the main surface of the GaN substrate 10 opposite to the back surface 16 may be exposed to the inside of the film forming chamber. The temperature of the GaN substrate 10 may be a room temperature _{T 0} of the deposition chamber. T ₀ may be normal temperature, for example, 15 ° C.

From time _{t 0} to start the heating of the GaN substrate 10. The heating method may be high-frequency heating or lamp heating. Other suitable heating methods may be employed. In this example, as the temperature increases linearly with time from time t ₀ to time t _3, heating the GaN substrate 10. In this example, from time t ₀ to time t ₄ is the heating phase. From time _{t 0} to time _{t 3} by increasing the temperature of the GaN substrate 10 and the time _{t 3} to time _{t 4} maintains the temperature of the GaN substrate 10.

Before starting the heating of the GaN substrate 10 and before the GaN substrate 10 reaches the growth temperature, introduction of a material gas into the film forming chamber is started. In this example, the material gas starts to be introduced into the film formation chamber at time t ₁ during the temperature rise. In this example, from time t ₁ to time t ₄ is a gas introduction stages. That is, from time t ₁ to time t ₄ , the material gas and the carrier gas are flowed into the film formation chamber. Thereby, a GaN layer is formed by metal organic growth (MOCVD).

Temperature _{T 1} of the GaN substrate 10 at time _{t 1} is, 400 ° C. or higher, 450 ° C. or higher, 500 ° C. or higher, may be at 550 ° C. or higher, or 600 ° C. or higher, and, 850 ° C. or less, 900 ° C. or less, 950 ° C. or less Or it may be 1000 degrees C or less. However, the temperature T ₁ is lower than a temperature T ₂ described later. In this example, the temperature T ₁ of the GaN substrate 10 is a temperature of 500 ° C. or higher and 900 ° C. or lower. Thereby, the protective layer 20 in direct contact with the GaN substrate 10 is formed.

The material gas in this example is a gas for forming the GaN layer 12. The material gas includes trimethyl gallium (Ga (CH ₃ ) ₃ ) (hereinafter referred to as TMG) as a Group 3 element-containing gas, ammonia (NH ₃ ) as a Group 5 element-containing gas, and monosilane (SiH ₄ ). It's okay. Monosilane silicon (Si) functions as an n-type impurity in the GaN layer 12.

From time t ₁ to time t ₂ , a material gas is introduced into the film formation chamber using a carrier gas that does not contain hydrogen (H ₂ ). Time from time t ₁ to time t ₂ may be a few minutes. The carrier gas not containing hydrogen (H ₂ ) may contain nitrogen (N ₂ ). In this example, the carrier gas is nitrogen gas. At the gas introduction start temperature T ₁ , hydrogen chemically etches the GaN substrate 10 due to chemical reaction with the GaN substrate 10. Thus, in this example, from time t ₁ to time t _2, the use of nitrogen gas as a carrier gas. Thereby, the flatness of the upper main surface (main surface opposite to the back surface 16) of the GaN substrate 10 can be maintained during the formation of the protective layer 20.

Time t ₂ is a gas switching timing determined in advance. In this example, at time t ₂ is in heated, switches the V / III ratio and a carrier gas. Thereby, formation of the n-type region 22 is started. Temperature _{T 2} of the GaN substrate 10 at time _{t 2,} 700 ° C. or higher, 750 ° C. or higher, 800 ° C. or higher, may be at 850 ° C. or higher, or 900 ° C. or higher, and, 1100 ° C. or less, 1150 ° C. or less, or 1200 ° C. or less It may be. The temperature T ₂ is 10 ° C. or higher, 20 ° C. or higher, 30 ° C. or higher, 40 ° C. or higher, 50 ° C. or higher, 60 ° C. or higher, 70 ° C. or higher, 80 ° C. or higher, 90 ° C. or higher than the film formation temperature of the n-type region 22. It may be a temperature lower than or equal to 100 ° C.

In this example, the V / III ratio means the ratio of the flow rate per unit time of the Group 5 element-containing gas to the flow rate per unit time of the Group 3 element-containing gas introduced into the film forming chamber. The V / III ratio may be lower after time t ₂ than before time t ₂ . In this example, the V / III ratio before time t ₂ is about 1.5 times the V / III ratio after time t ₂ . That is, before time t ₂ , the protective layer 20 can be formed while reducing escape of nitrogen atoms from the GaN substrate 10 by supplying excessive nitrogen to gallium.

The flow rate per unit time of the Group 5 element-containing gas in before time t ₂ may be less than the flow rate per unit time of the Group 5 element-containing gas in the after time t _2. In this example, the flow rate per unit time ammonia before time t ₂ is about half the flow rate per unit time of ammonia in the after time t _2. Further, the flow rate per unit time of the group III element-containing gas in before time t ₂ may be less than the flow rate per unit of group III element-containing gas time in after time t _2. In this example, the flow rate per unit time TMG before time t ₂ is about half the flow rate per unit time of TMG to definitive after time t _2.

  In this example, the growth rate of the protective layer 20 in step S10 is suppressed by suppressing the supply of ammonia and TMG more than in step S20. Since the temperature of the GaN substrate 10 in step S10 is lower than that in step S20, the crystal quality in step S10 is considered to be lower than that in step S20. Therefore, by suppressing the growth rate in step S10, it is possible to form a higher quality epitaxial layer when viewed as the GaN layer 12 as a whole.

Carrier gas introduced into the deposition chamber after the time point t ₂ may contain hydrogen. The carrier gas of the present example, including hydrogen switched so as not to include nitrogen in after the time t _2. “Switching to include hydrogen but not including nitrogen after time t ₂ ” means that the supply of hydrogen was started just at time t ₂ , but the carrier gas still contains nitrogen, and time t 2 It means that nitrogen is reduced so that nitrogen is zero by ₃ . Incidentally, ammonia and TMG raw material gases may also be varied to a predetermined V / III ratio to the time t _3. In one example, the flow rate of ammonia per unit time may be 223000 μmol / min after time t ₂ and by time t ₃ , and the flow rate of TMG per unit time may be 110 μmol / min. In this case, the V / III ratio is about 2000.

In this example, the growth temperature means a substantially constant temperature at which the growth of the n-type region 22 proceeds. However, the growth temperature does not mean only a fixed and constant temperature. The growth temperature may have a temperature range deviated by a predetermined temperature from a predetermined temperature. For example, the growth temperature is in the temperature range of 1100 ° C. ± 25 ° C. In this example, the temperature of the pre-GaN substrate 10 at time _{t 2} is lower than the growth temperature is at 700 ° C. or higher. In this example, by starting to flow the film forming gas in the n-type region 22 before reaching the growth temperature, it is possible to shift from the formation of the protective layer 20 to the formation of the n-type region 22 continuously.

In this example, stop the Atsushi Nobori of the GaN substrate 10 at time _{t 3.} Time from time t ₂ to time t ₃ may be a few minutes. At time _{t 3,} the temperature of the GaN substrate 10 may reach the temperature _{T 3.} The temperature T _{3 in} this example is the growth temperature of the n-type region 22. After reaching the temperature T ₃ may maintain the temperature of the GaN substrate 10 in the growth temperature. Even after the temperature of the GaN substrate 10 has reached the growth temperature, until the time t ₄ is introduced into the deposition chamber of the source gas is continued. Accordingly, from time _{t 3} to time _{t 4,} the n-type region 22 may be grown and maintained in the temperature _{T 3.} Time from time _{t 3} to time _{t 4} can be a 300 minutes.

In this example, stop the heating of the GaN substrate 10 at time _{t 4.} In this example, time _{t 5} from time _{t 4} is cooling phase. At time _{t 5,} may retrieve the laminated structure of GaN substrate 10 and GaN layer 12 was lowered to a temperature _{T 0} from the film forming chamber.

FIG. 4A is a diagram showing step S10 in the manufacturing process. In step S10, the protective layer 20 is formed epitaxially. FIG. 4B is a diagram showing step S15 in the manufacturing process. In step S15, the n-type region 22 is formed epitaxially. Thereby, the protective layer 20 and the n-type region 22 are formed. As described with reference to FIG. 3, step S10 and step S15 are continuously executed with gas switching (time t ₂ ) interposed therebetween.

FIG. 4C is a diagram showing step S20 in the manufacturing process. In step S20, the p-type well 24, the p ⁺ -type well 26, and the n ⁺ -type well 28 are formed. In this example, Mg is ion-implanted into the GaN layer 12 by multistage implantation with acceleration voltages of 20, 40, 70, 110, 150, 200, 250, and 430 (units are all keV) and a dose of 6E + 12 cm ⁻² . Thereby, after the annealing in step S40, the impurity concentration of the p-type well 24 may be 1E + 17 cm ⁻³ . Note that E means 10 tiles. For example, E + 17 means ^{10 17.}

In this example, Mg is ion-implanted into the p-type well 24 at an acceleration voltage of 10 keV and a dose of 4.5E + 13 cm ⁻² . Thereby, after the annealing in step S40, the impurity concentration of the p ⁺ type well 26 may be 2E + 19 cm ⁻³ . Further, in this example, Si is ion-implanted into the p-type well 24 and the p ⁺ -type well 26 by multi-stage implantation with acceleration voltages 30, 60, and 80 (all units are keV) and a dose amount of 3E + 15 cm ⁻² , respectively. Thereby, after the annealing in step S40, the impurity concentration of the n ⁺ -type well 28 may be 1E + 20 cm ⁻³ .

  FIG. 4D is a diagram showing step S30 in the manufacturing process. In the paragraph S30, the cap layer 18 is formed. In this example, the stacked structure of the GaN substrate 10, the GaN layer 12, and the cap layer 18 is referred to as a processing stack 60. In this example, since each well is formed by ion implantation, the crystallinity of the front surface 14 of the GaN layer 12 is disturbed. Therefore, compared with the case where each well is formed epitaxially, nitrogen atoms are easily decomposed and released from the GaN layer 12 during annealing. The cap layer 18 has a function of reducing the decomposition and release of nitrogen atoms from the front surface 14 during annealing.

  The cap layer 18 in this example is an AlN (aluminum nitride) film provided in direct contact with the front surface 14 of the GaN layer 12. The AlN film may be formed by sputtering using an AlN target. The cap layer 18 may have a thickness of 2 nm to 1000 nm. The cap layer 18 of this example has a thickness of about 200 nm.

  FIG. 4E is a diagram showing step S40 in the manufacturing process. In step S40, the stack 60 to be processed is placed in the annealing apparatus 110, and the stack 60 to be processed is annealed at a predetermined temperature and pressure. Thereby, the GaN layer 12 is annealed. Argon (Ar) gas may be added in the annealing apparatus 110 in addition to nitrogen gas. The predetermined pressure may be several hundred MPa. The predetermined temperature may be 1200 ° C. or higher and 1500 ° C. or lower, more preferably 1400 ° C. or higher and 1500 ° C. or lower. After the annealing, the AlN film is selectively removed with respect to the GaN layer 12 using an aqueous potassium hydroxide solution (KOHaq).

FIG. 4F is a diagram illustrating step S50 in the manufacturing process. In step S50, the gate insulating film 32, the gate electrode 34, the source electrode 44, and the drain electrode 54 are formed by applying a known film forming method and patterning method, respectively. In this example, a SiO ₂ film as the gate insulating film 32 is formed by low pressure chemical vapor deposition (LPCVD). The thickness of the gate insulating film 32 is, for example, 100 nm.

  Thereafter, polycrystalline silicon is formed by LPCVD as the gate electrode 34. One or more elements of phosphorus (P) and arsenic (As) may be doped into the polycrystalline silicon during or after the formation of the polycrystalline silicon. The gate insulating film 32 and the gate electrode 34 are patterned by photolithography and etching.

  Thereafter, the source electrode 44 is formed. The source electrode 44 may be a laminate having a lower Ti (titanium) layer and an upper Al (aluminum) layer. Thereafter, the drain electrode 54 is formed. The drain electrode 54 may be a laminate having an upper Ti layer and a lower Al layer that are in direct contact with the back surface 16 of the GaN substrate 10. Thereafter, the gate terminal 30, the source terminal 40, and the drain terminal 50 are connected to the gate electrode 34, the source electrode 44, and the drain electrode 54 by wiring. Thereby, the vertical MOSFET 100 is completed.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the operation flow in the claims, the description, and the drawings is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

10 .. GaN substrate, 12 .. GaN layer, 14 .. front surface, 16 .. back surface, 18 .. cap layer, 20 .. protective layer, 22 .. n-type region, 24 .. p-type well , 25 .. channel forming region, 26... P ⁺ type well, 28... N ⁺ type well, 30... Gate terminal, 32... Gate insulating film, 34. ..Source electrode, 50 ..Drain terminal, 54 ..Drain electrode, 60 ..Layer to be processed, 100 ..Vertical MOSFET, 110 ..Annealing apparatus

Claims (7)

A method for manufacturing a nitride semiconductor device comprising a nitride semiconductor substrate and a nitride semiconductor layer provided on the nitride semiconductor substrate,
Heating the nitride semiconductor substrate disposed in the film formation chamber, heating the nitride semiconductor substrate to a growth temperature, and maintaining the growth temperature after reaching the growth temperature;
Before starting the heating of the nitride semiconductor substrate and before the nitride semiconductor substrate reaches the growth temperature, the introduction of a material gas for forming the nitride semiconductor layer into the film formation chamber is started, A gas introduction step of continuing introduction of the material gas into the film formation chamber even after the nitride semiconductor substrate reaches the growth temperature. In the gas introduction stage, from the start of introduction of the material gas to a predetermined switching timing, the material gas is introduced into the film formation chamber using a carrier gas not containing hydrogen, and after the switching timing, The manufacturing method according to claim 1, wherein the material gas is introduced into the film formation chamber using a carrier gas containing hydrogen. The material gas includes a group 5 element-containing gas,
The manufacturing method according to claim 2, wherein a flow rate per unit time of the Group 5 element-containing gas before the switching timing is less than a flow rate per unit time of the Group 5 element-containing gas after the switching timing. The material gas includes a group 3 element-containing gas,
The flow rate per unit time of the Group 3 element-containing gas before the switching timing is less than the flow rate per unit time of the Group 3 element-containing gas after the switching timing. Method. The material gas includes a group 3 element-containing gas and a group 5 element-containing gas,
The ratio of the flow rate per unit time of the Group 5 element-containing gas to the flow rate per unit time of the Group 3 element-containing gas is lower after the switching timing than before the switching timing. The manufacturing method according to claim 1. The manufacturing method according to claim 2, wherein a temperature of the nitride semiconductor substrate at the switching timing is 700 ° C. or higher and lower than the growth temperature. 7. The manufacturing method according to claim 1, wherein in the gas introduction step, introduction of the material gas is started when the temperature of the nitride semiconductor substrate is 500 ° C. or more and 900 ° C. or less.

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